JP2005346629A - Image processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent manufacturability from being reduced by restrictions on bands of magnetic storage devices, to improve performance of the magnetic storage devices extended by post-installation. <P>SOLUTION: A plurality of HDD units 21 are connected to a switch (switch network) 14 based on PCI Express standards. Alternately, in the case that only one or two HDD units 21 are connected to the switch (switch network) 14 at the beginning, HDD units 21 are additionally connected to the switch (switch network) 14. Each HDD unit 21 performs RAID (redundant arrays of independent/inexpensive disks) operation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus that performs predetermined processing relating to image data.

  As a high-speed serial interface, an interface called PCI Express (registered trademark) corresponding to a successor to the PCI bus system has been proposed (for example, see Non-Patent Document 1).

  FIG. 21 is a block diagram for explaining an example of connection of devices in an existing digital copying machine 200 called a multifunction peripheral. A CPU 203 that centrally controls each unit is connected to a controller 203 configured by an ASIC via a dedicated interface (I / F) 202, and image data and other data are connected to the controller 203 via the dedicated I / F 202. A system memory 204 that stores data, a hard disk (HDD) unit 205 that stores image data and other data, and an image processing unit 206 that performs predetermined image processing on the image data are connected. The controller 203 is connected to a scanner 213, a plotter 214, a communication I / F 215 that communicates with a network, other multifunction devices 216, and the like via a PCI parallel bus 211 and a general-purpose I / F 212. Image processing units 217 and 218 that perform predetermined image processing are connected to the scanner 213 and the plotter 214 via the dedicated I / F 202, respectively.

“Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, conventionally, since the PCI parallel bus 411 is used to transfer a relatively large amount of image data, the image data dominates the band, and a new function such as an image processing function cannot be retrofitted. However, there has been a problem in that the computing ability of image processing units such as the image processing units 406, 417, and 418 cannot be improved. There is also a problem that the performance of the HDD unit 405 cannot be improved due to the limitation of the bandwidth of the HDD unit 405.

  An object of the present invention is to prevent a decrease in productivity due to a band limitation of a magnetic storage device in an image processing apparatus and to improve the performance of the magnetic storage device by adding a retrofit.

  Another object of the present invention is to realize high-speed image processing in an image processing apparatus, or to be able to add image processing different from existing ones later.

  (1) The present invention provides a PCI Express standard bus and switch for transferring data, and a plurality of PCI Express standard endpoints connected to the switch in an image processing apparatus that performs predetermined processing relating to image data. An image processing apparatus.

  (2) According to another aspect of the present invention, in an image processing apparatus that performs predetermined processing relating to image data, a PCI Express standard bus and switch for transferring data, and the PCI Express standard bus connected to the switch. An image processing apparatus comprising a plurality of image processing circuits serving as end points.

  According to the invention of (1), since a plurality of magnetic storage devices serving as PCI Express standard endpoints are provided, the reduction in productivity of the image processing device due to the bandwidth limitation of the magnetic storage device is caused by the RAID operation or the like. Can be resolved. Since the magnetic storage device can be added later, the performance of the magnetic storage device can be improved by retrofitting.

  According to the invention of (2), a plurality of image processing circuits that perform the same kind of image processing are used to achieve high-speed image processing, or an image processing circuit that performs image processing different from existing ones can be retrofitted. Can be expanded.

  The best mode for carrying out the present invention will be described with reference to the drawings.

  In the following, details of PCI Express will be described in the columns [Outline of PCI Express Standard] to [Details of Architecture of PCI Express], and then the digital copier of this embodiment will be described in the [Digital Copier] column. explain.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explain by excerpt. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. A tree structure in which a PCI-X bridge 105b to which PCI-X devices 104c and 104d are connected and a PCI bridge 107 to which a PCI bus slot 106 is connected are connected via a PCI-X bridge 105c ( Tree structure).

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. PCI Express 114b connects the switch 117a to which the PCI Express 114b is connected, and the PCI bridge 119 to which the switch 117b to which the endpoint 115b and the legacy endpoint 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to a desktop / mobile. For example, graphics 125 is connected to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. An x16 PCI Express 126a and an I / O hub 127 having a conversion function are connected by a PCI Express 126b. For example, a memory 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Furthermore, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c. The switch 134 is connected to the mobile dock 135, Gigabit Ethernet (Ethernet is a registered trademark) 136, and an add-in by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects components one-to-one (point-to-point). The transfer rate is, for example, one-way 2.5 Gbps (in the future, 5 Gbps or 10 Gbps is assumed). The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint basically does not request I / O port resources in the BAR (base address register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7 (a), the conventional PCI architecture has a structure in which protocols and signaling are closely related and has no concept of hierarchy. In PCI Express, as shown in FIG. 7 (b), Like general communication protocols and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. Also, it has interface initialization and maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration employs a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the cross-point of the data signal. The system extracts the clock.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting conventional access to PCI Express access is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (NEWCARD), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed in order to avoid overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (mechanism to check the buffer availability on the receiving side before starting data transfer and prevent overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew that is a problem with the parallel bus is greatly reduced.

b. Power Management and Link State In order to keep the power consumption of the link low, a link state of L0 / L0s / L1 / L2 is defined as shown in FIG.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 15, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Digital copier]
Next, the digital copying machine of this embodiment will be described.

  FIG. 16 is a block diagram showing an outline of connection of each device of the digital copying machine 1 according to the present embodiment. The digital copying machine 1 implements the image processing apparatus of the present invention that performs predetermined processing relating to image data, and is a so-called multi-function machine that executes processing such as reading of a document image and image formation on a sheet or the like. To do.

  The digital copying machine 1 uses a PCI Express standard bus system for data transfer. That is, a CPU 11 that centrally controls each unit of the digital copying machine 1 and a system memory 12 that is a work area of the CPU 11 are connected to a root complex 13 of the PCI Express standard. A root complex 13 and a PCI Express standard switch (or switch network) 14 are connected via a PCI Express standard general-purpose bus 15. The PCI Express standard switch (or switch network) 14 is connected to various devices serving as PCI Express standard end points. That is, a hard disk (HDD) unit 21 for storing image data, an image memory unit 22 and a memory unit 23, an image processing unit 24 for performing various image processing, a communication interface (I / F) 25, a scanner 26, a plotter 27, another multifunction device 28, and the like.

  Next, the relationship between the HDD unit 21 as a magnetic storage device and the switch (or a switch network composed of a plurality of switches) 14 will be described with reference to the explanatory diagram of FIG. A plurality of HDD units 21 are connected to a switch (switch network) 14. Alternatively, when only one or two HDD units 21 are initially connected to the switch (switch network) 14, the HDD units 21 are further connected to the switch (switch network) 14. Each HDD unit 21 performs a RAID (Redundant Array of Independent / Inexpensive Disks) operation.

  As described above, by using the PCI Express standard bus system, it is possible to eliminate the decrease in productivity of the digital copying machine 1 due to the bandwidth limitation of the HDD unit 21 by the RAID operation. In this case, since the HDD unit 21 can be added later, the performance of the HDD unit 21 can be improved by retrofitting.

  The relationship between the image processing unit 24, which is an image processing circuit, and the switch (or switch network) 14 will be described with reference to FIG. A plurality of image processing units 24 are connected to the switch (or switch network) 14. Alternatively, when only one or two image processing units 24 are initially connected to the switch (or switch network) 14, the image processing unit 24 is further added to the switch (or switch network) 14. Connecting.

  As a result, the image processing speed can be increased by using a plurality of image processing units 24 that perform the same kind of image processing, or the number of image processing units 24 that perform image processing different from the existing ones can be added later. it can.

  A specific processing example will be described with reference to FIGS. 19 and 20. The example of FIG. 19 is an example in which high-speed image processing is realized by using three image processing units 24 that perform the same kind of image processing. The image data G of the original read by the scanner 26 is processed by the image processing unit 24 and output to the plotter 27. The image data G is divided into three parts A, B, and C according to the main scanning direction. By dividing and processing the divided portions to each image processing unit 24, it is possible to realize high-speed image processing.

  The example of FIG. 20 is an example in which three image processing units 24 that execute different image processes (processes A, B, and C) are used, and image data of a document read by the scanner 26 is processed by processes A, B, and C. Each image processing unit 24 to be executed sequentially performs processing. As a result, even if only two image processing units 24 that execute only the processes A and B are provided at the beginning, the image processing units 24 that execute the process C are additionally installed, and the image is added. Processing C can also be performed on the data.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. (A) is a block diagram showing an existing PCI architecture, and (b) is a block diagram showing a PCI Express architecture. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is explanatory drawing explaining the definition of the link state of L0 / L0s / L1 / L2. It is a time chart which shows the example of control of active state power management. 1 is a block diagram showing an outline of connection of devices of a digital copying machine according to an embodiment of the present invention. It is a block diagram explaining the relationship between a HDD unit and a switch (or switch network). It is a block diagram explaining the relationship between an image processing unit and a switch (or switch network). It is explanatory drawing explaining the operation | movement in the structure of FIG. It is explanatory drawing explaining the operation | movement in the structure of FIG. It is a block diagram which shows the outline | summary of the connection of each apparatus of the conventional digital copying machine.

Explanation of symbols

1 Image Processing Device 14 Switch 15 Bus 21 Magnetic Storage Device 24 Image Processing Circuit

Claims (4)

In an image processing apparatus that performs predetermined processing relating to image data,
PCI Express standard buses and switches that transfer data,
A plurality of magnetic storage devices connected to the switch and serving as endpoints of the PCI Express standard;
An image processing apparatus comprising: In an image processing apparatus that performs predetermined processing relating to image data,
PCI Express standard buses and switches that transfer data,
A plurality of image processing circuits connected to the switch and serving as endpoints of the PCI Express standard;
An image processing apparatus comprising:   The image processing apparatus according to claim 2, wherein each of the image processing circuits executes the same kind of image processing. The image processing apparatus according to claim 2, wherein each of the image processing circuits executes different kinds of image processing.

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