JP4603336B2 - Data transfer system, image forming system, and data transfer method - Google Patents

Description

  The present invention relates to a data transfer system, and more particularly to an image forming system such as a multifunction peripheral (MFP) that handles various image data and performs various processes, and a data transfer method.

  Generally, in a device / system that handles image data and other data, a PCI bus is used as an interface between devices. However, the parallel PCI bus has problems such as racing and skew, and the transfer rate has been low for use in high-speed and high-quality image equipment. The use of a high-speed serial interface is being considered in place of the system interface. Conventionally, there are standards such as IEEE1394 and USB as a widely used serial interface, but there are problems such as insufficient transfer rate and difficulty in securing a scalable bus width compared to PCI. . For this reason, the use of an interface called PCI Express (registered trademark) corresponding to a successor standard of the PCI bus system is being studied as another high-speed serial interface.

  Although details will be described later, this PCI Express system is schematically configured as a data communication network having a tree structure (tree structure) as shown in FIG.

  An example of this is simplified and shown in FIG. That is, the PCI Express system 200 sets a plurality of end nodes (end points) A, B, C, D,... Via the switches SW1, SW2, SW3,. Connected to a tree structure. Here, each of the switches SW1, SW2, SW3,... Has one upstream port (route node side) and a plurality of downstream ports (end node side), and other than the switches SW1, SW2, SW3,. Each of the devices A, B, C, D,... Has only one port, and the communication path between each device is uniquely determined by a tree structure.

  The connection lines between nodes and switches are connected in advance according to the speed required for data transfer. At this time, each connection line has a different performance (for example, a bus width). The number of lanes shown is x8, x4.x2, etc.). Further, the switches SW1, SW2, SW3,... Can adjust the transfer speed when a plurality of data transfers are processed in parallel (when contention occurs) by setting priority to each port. it can.

“Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, when such a PCI Express system is simply used, the communication path is fixed, so when multiple independent data transfers are processed in parallel, contention of the data transfer path occurs and transfer efficiency decreases. There is an inconvenience.

  For example, in the example shown in FIG. 23, when a route 202 from the root node 201 to the end node A and a route 203 from the end node C to the end node B are to be processed at the same time, two types of data transfer are attempted. As shown in an enlarged view in FIG. 23, the downstream port competes with the switch SW2 in the switch SW1. Therefore, when the packet of the route 202 and the packet of the route 203 are alternately output, the transfer rate is reduced to half and the transfer efficiency is lowered. In addition, it is possible to give priority to one path 202 or 203 by arbitration of the switch SW1, but the transfer efficiency of the other path 203 or 202 is further reduced.

  In order to prevent the competition shown in FIG. 23 from occurring, for example, as shown in FIG. 24, the connections of the end nodes A, B, C, and D to the switches SW2 and SW2 may be changed in advance. In another parallel processing operation, when the processing of the route 202 and the processing of the route 204 from the end node C to the end node D have to be processed at the same time, the same contention as in FIG. The rate will drop and it will not be an essential improvement.

  Such a decrease in the data transfer rate is the same not only when the data transfer path competes but also in the case of a data transfer path that passes through more switches than necessary.

  An object of the present invention is to improve data transfer efficiency by avoiding data transfer path contention when a plurality of independent data transfers are processed in parallel or a data transfer path that passes through more than necessary switches. It is.

The invention of claim 1 wherein is a communication channel of the send and receive independently as a data communications network according to a tree structure is established Lud over data transfer system, a first device located downstream in the tree structure upstream A plurality of endpoints including a first endpoint that can communicate with a first switch located on the side and a second endpoint that can communicate with a second switch located on the upstream side, and The second device located on the downstream side has a third endpoint capable of communicating with the first switch located on the upstream side and a fourth endpoint capable of communicating with the second switch located on the upstream side. And the first device performs independent data transfer to each of the first switch and the second switch. In the operation mode, the first endpoint that arbitrates an endpoint to be used among the plurality of endpoints of the first device so as to use the first endpoint and the second endpoint. An arbiter, and the second device is configured to operate the third endpoint and the fourth endpoint in an operation mode in which independent data transfer is performed for each of the first switch and the second switch. A second arbiter that adjusts an endpoint to be used among the plurality of endpoints of the second device so as to use the endpoint .

The invention according to claim 2 is the data transfer system according to claim 1, wherein the data transfer system is a PCI Express system.

According to a third aspect of the present invention, in the data transfer system according to the first or second aspect , the first device and the second device are devices involved in image formation.

According to a fourth aspect of the present invention, in the image forming system according to the third aspect , at least an image input device, an image output device, an image processing device, and a storage device are used as the first device or the second device . Including devices.

The invention of claim 5, wherein the communication channel transmission received independently by a data communications network according to a tree structure is established, first a first device located on the downstream side in the prior SL tree structure is located on the upstream side and having a plurality of endpoints, including a second endpoint capable of communicating with a second switch located on the first endpoint and the upstream capable of communicating with the switch, a position on the downstream side of the tree 2 A plurality of endpoints including a third endpoint capable of communicating with the first switch located upstream and a fourth endpoint capable of communicating with the second switch located upstream. having a data transfer method utilizing a data transfer system, the first device, each of the first switch and the second switch The end to be used among the plurality of end points of the first device so that the first end point and the second end point are used in the case of the operation mode in which independent data transfer is performed. When the second device is in an operation mode in which the second device performs independent data transfer to each of the first switch and the second switch, the third endpoint and the fourth device The end point to be used is arbitrated among the plurality of end points of the second device so as to use the end point .

The invention according to claim 6 is the data transfer method according to claim 5 , wherein the data transfer system is a PCI Express system.

According to the present invention, the first device to have multiple endpoints comprising a first switch and the second endpoint can communicate with the first endpoint of the possible communication and a second switch Rutotomoni, The second device has a plurality of endpoints including a third endpoint that can communicate with the first switch and a fourth endpoint that can communicate with the second switch, the first switch and the second The first device uses the first endpoint and the second endpoint, and the second device uses the third endpoint and the fourth endpoint in an operation mode that performs independent data transfer to each of the switches. to use the endpoint, by adjusting the end point used, it is possible to dynamically change the tree structure, therefore, a plurality of Germany Even when parallel data transfers are processed in parallel, it is possible to avoid data transfer path contention by securing independent data transfer paths, or to avoid data transfer paths that require more than a multi-stage switch. Improvements can be made.

  The best mode for carrying out the present invention will be described with reference to the drawings.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. The switch 117a connected by the PCI Express 114b is connected by the PCI Express 114c, and the PCI bridge 119 to which the switch 117b to which the end point 115b and the legacy end point 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected is a PCI. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Furthermore, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c. The switch 134 is connected to the mobile dock 135, Gigabit Ethernet (Ethernet is a registered trademark) 136, and an add-in by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects components one-to-one (point-to-point). The transfer rate is, for example, 2.5 Gbps in one direction. The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint basically does not request I / O port resources in the BAR (base address register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 117
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and has no concept of hierarchy. In PCI Express, as shown in FIG. 7B, Like general communication protocols and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration uses a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the crosspoint of the data signal. The clock is extracted.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting the conventional access to the access by PCI Express is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (Express Cards), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed to avoid the overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (a mechanism that confirms the buffer availability on the receiving side before starting data transfer and prevents overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power management and link state As shown in Table 1, a link state of L0 / L0s / L1 / L2 is defined in order to keep the power consumption of the link low.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 14, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Data transfer system; Image forming system]
The data transfer system according to the present embodiment uses the PCI Express system as described above, particularly with the tree structure improved.

  FIG. 15 is a principle schematic diagram showing an example of a tree structure in the data transfer system of the present embodiment. According to the specifications of the PCI Express system described above, each device located on the downstream side (terminal side) of the tree structure is configured to have one endpoint, but in this embodiment, each device A, B, C, D,..., A4, B1,..., B4, C1,..., C4, D1,. Arbiters 2A and 2B that connect to the downstream ports of 1A, 1B, 1C, and 1D and mediate the endpoints to be used according to the operation mode of the image forming system to each device A, B, C, D,. , 2C, 2D,...

  Therefore, in the tree structure of the image forming system according to the present embodiment, the root complex 3 that manages the whole is used as the apex, the most upstream switch 4 included in the root complex 3, and the plurality of switches 1A, A plurality of devices A, B, C, D,... Are connected downstream through 1B, 1C, 1D,..., But each device A, B, C, D,. For example, the device A has four data transfer paths connected to the downstream ports of the switches 1A, 1B, 1C, and 1D by the end points A1, A2, A3, and A4. Similarly, the device B has four data transfer paths connected to the downstream ports of the switches 1A, 1B, 1C, and 1D by the end points B1, B2, B3, and B4. Each having four data transfer paths connected to the downstream ports of the switches 1A, 1B, 1C, and 1D by the respective endpoints C1, C2, C3, and C4. In the device D, each endpoint D1 , D2, D3, D4 have four data transfer paths connected to the downstream ports of the switches 1A, 1B, 1C, 1D.

  In the present embodiment, the data transfer width between the switch 4 and the switches 1A to 1D is the x4 link width, and the data transfer between each switch 1A to 1D and each end point of each device A to D is performed. The width is x1 link width.

  In such a configuration, in the operation mode in which a plurality of independent data transfers are processed in parallel in the data transfer system, the devices A to D are configured so that no conflict occurs in the data transfer path passing through the switch 1. The arbiters 2A to 2D adjust the end points to be used.

  For example, in the case where the image data from the device A is processed by the device B and transferred to the device C in parallel with the data transfer processing for outputting the image data from the device A by the device D at the same time, the arbiter 2A uses endpoint A1 for switch 1A in device A, endpoint A3 for switch 1C, arbiter 2B uses endpoints B1 and B2 for switches 1A and 1B in device B, and arbiter 2C uses endpoint B1 for switch 1B Using C2, arbiter 2D arbitrates each endpoint to use endpoint D3 for switch 1C.

  Thus, device A (endpoint A1) -switch 1A-device B (endpoints B1, B2) -switch 1B-device C (endpoint C2) x1 link path 7 and device A (endpoint A3)- The path 1 of the x1 link of the switch 1C-device D (endpoint D3) is secured.

  In this way, by adjusting the endpoints used for each of the devices A to D according to the operation mode, the tree structure can be dynamically changed, and thus a plurality of independent data transfers are processed in parallel. Even in this case, by securing independent data transfer paths, contention of data transfer paths can be avoided and data transfer efficiency can be improved.

  A preferred example of the data transfer system as in this embodiment is an image forming system as shown in FIG. In the image forming system, for example, device A is an image input device using a scanner engine or the like that photoelectrically converts and reads a document image, and device B is an image processing device that performs various image processing such as scaling and rotation on image data. Device, device C is a memory for storing image data, a storage device such as an HDD, and device D is an image output device by a printer engine or the like that prints out paper on the basis of image data or the like, and includes at least these devices It is said that. In the image forming system, the root complex 3 is configured as a controller and connected to the host CPU 5 and the memory 6.

  In such a configuration, for example, the image data read by the device A is printed out by the device D in parallel with the data transfer processing in which the image data read by the device A is processed by the device B and stored in the device C. When data transfer processing is performed simultaneously, the arbiter 2A uses the endpoint A1 for the switch 1A and the endpoint A3 for the switch 1C in the device A, and the arbiter 2B uses the endpoints B1 and B2 for the switches 1A and 1B in the device B. In use, arbiter 2C uses endpoint C2 for switch 1B, and arbiter 2D arbitrates each endpoint to use endpoint D3 for switch 1C.

  Thus, device A (endpoint A1) -switch 1A-device B (endpoints B1, B2) -switch 1B-device C (endpoint C2) x1 link path 7 and device A (endpoint A3)- The path 1 of the x1 link of the switch 1C-device D (endpoint D3) is secured. Therefore, the image processing of the read image data to the data transfer for memory storage can be performed between the devices A, B, and C by the x1 link, and at the same time, the data transfer between the devices A, B, and C is disturbed between the devices A and D. Therefore, it is possible to transfer data for copying that makes full use of the x1 link.

  In this way, by adjusting the endpoints used for each of the devices A to D according to the operation mode, the tree structure can be dynamically changed, and thus a plurality of independent data transfers are processed in parallel. Even in this case, by securing independent data transfer paths, contention of data transfer paths can be avoided and data transfer efficiency can be improved.

[Manage routing information]
By the way, the arbitration of the end points A1 to A4,..., D1 to D4 by the arbiters 2A to 2D of each of the devices A to D (determination of the end points used when accessing other devices) is performed by the host CPU 5 Is executed by referring to the path information written and set in each of the devices A to D. Setting of such path information is mainly performed according to the data transfer program installed in the host CPU 5. Executed.

  Therefore, an example of such a route information management method will be described. In this example, the premise is that each of the devices A to D has not only information on the device function that it has, but also information on the endpoint (for example, the number of endpoints ... 4 in the illustrated example, the number of lanes for each endpoint) (X1 in the illustrated example, connection destination, for example, the downstream port of the switch 1A in the case of the end point A1) is held in the memory area so as to be accessible from the host CPU 5 (information holding means).

  Under such a premise, the host CPU 5 executes processing control according to a data transfer program, that is, a flowchart schematically shown in FIG. That is, the host CPU 5 determines a path between devices that is optimal in the tree structure based on the device connection status in the system, information on each device function acquired from each device, and information on the endpoint. And setting means for writing and setting the path information determined for each device, and the arbiter 2 of each device refers to the path information set by the setting means and is used for accessing other devices. It is configured to arbitrate points.

  First, the connection states of the devices A to D in the data transfer system (image forming system) are confirmed (step S1), and the connected devices A to D are accessed to check the connection states of the devices A to D. Information on functions and information on endpoints are acquired (S2). Also, information on the operation mode to be performed is acquired, and the route between the devices A to D that is optimal in the tree structure is determined based on the device connection state, device function information, and information on the endpoint (S3). Here, “optimum path between devices” means that a switch is selected (no overlap occurs between a plurality of paths) so as not to cause a competition between a plurality of paths. For example, FIG. Routes 7 and 8 as shown in FIG. The process of step S3 is executed as a determination unit and a determination function.

  The path information for each device A to D determined in step S3 is written and set in the corresponding device A to D (S4). The processing in step S4 is executed as setting means and a setting function.

  After this, the arbitration of the end points A1 to A4,..., D1 to D4 by the arbiters 2A to 2D of the devices A to D refers to the path information written and set in the devices A to D by the host CPU 5. It is executed by doing. For example, arbitration is performed by the arbiter 2A to use the end points A1 and A3.

  On the other hand, another example of such a route information management method will be described. In this example, as a premise, for each of the devices A to D, not only the information on the device function of each but also the information on the endpoint (for example, the number of endpoints ... 4 in the illustrated example, the number of lanes for each endpoint) In the illustrated example, x1, connection destination, for example, the downstream port of the switch 1A in the case of the endpoint A1, etc.) are directly managed by the host CPU 5 (information management means). That is, the host CPU 5 that manages the system includes information management means that manages information related to device functions and endpoints of each device, device connection status in the system, and device functions that are managed by the information management means. A determination means for determining an optimum route between devices in the tree structure based on the information on the endpoint and the information on the endpoint, and a setting means for writing and setting the route information determined for each device. The arbiter 2 is configured to arbitrate an endpoint to be used when accessing another device with reference to the path information set by the setting means.

  Under such a premise, the host CPU 5 executes processing control according to the data transfer program and according to the flowchart schematically shown in FIG. First, the connection status of the devices A to D in the data transfer system (image forming system) is confirmed (step S11), and information about the functions of the managed devices A to D and information about the endpoints are acquired. (S12) and also obtains information about the operation mode to be performed, and determines the route between the devices A to D that is optimal in the tree structure based on the device connection status, device function information, and information on the endpoint. (S13). The process of step S13 is executed as a determination unit and a determination function. The path information for each of the devices A to D determined in step S13 is written and set in the corresponding devices A to D (S14). The processing in step S14 is executed as setting means and a setting function.

  After this, the arbitration of the end points A1 to A4,..., D1 to D4 by the arbiters 2A to 2D of the devices A to D refers to the path information written and set in the devices A to D by the host CPU 5. It is executed by doing. For example, arbitration is performed by the arbiter 2A to use the end points A1 and A3.

  Next, an example of timing control in such a route information management method will be described with reference to a schematic flowchart shown in FIG. First, when the system is activated (Y in S21), path information is written and set to each of the devices A to D (S22). Here, “when the system starts up” means to include a point in time from when the system is started up, and is not limited to the point in time of starting up. In addition, a default value that is a preset standard specification is used as the path information writing setting at the time of activation. The processes of Y and S22 in step S21 are executed as setting means and setting functions.

  After this, the arbitration of the end points A1 to A4,..., D1 to D4 by the arbiters 2A to 2D of the devices A to D is performed by the route information (default) written and set in each of the devices A to D by the host CPU 5. Value).

  Thereafter, it is monitored whether or not the operation mode is changed during the activation of the system (S23). When the operation mode is changed (Y in S23) and the host CPU 5 directly receives information related to the change in the operation mode (Y in S24), the host CPU 5 relates to the changed operation mode. Based on the information, and the device connection state (acquired from each device or managed by the host CPU 5), device function information, and information on the endpoint, the route between the devices A to D that is optimal in the tree structure is re-established. Determine (S25). The process of step S25 is executed as redetermination means and redetermination function. The path information for each of the devices A to D determined in step S25 is written and set in the corresponding devices A to D (S26). The processing in step S26 is executed as setting means and a setting function.

  After this, the arbitration of the end points A1 to A4,..., D1 to D4 by the arbiters 2A to 2D of the devices A to D refers to the path information written and set in the devices A to D by the host CPU 5. It is executed by doing.

  On the other hand, when the devices A to D receive information regarding the change of the operation mode (N in S24), these devices A to D request the host CPU 5 to re-determine the route information (Message Transaction). ) Is issued (S27). The processing in step S27 is executed as a function of the transaction issuing means by the device. With the issuance of this message transaction, the host CPU 5 receives the information regarding the change of the operation mode by receiving the notification of the information regarding the change of the operation mode stored in the message transaction packet (S28). After receiving the information regarding this operation mode, the processing from step S25 is similarly performed.

  Instead of the processing in step S28, the information regarding the change of the operation mode may be received by referring to the information regarding the change of the operation mode recorded in the device by receiving the message transaction packet.

  Next, another example of timing control in such a route information management method will be described with reference to a schematic flowchart shown in FIG. First, as in the case described with reference to FIG. 19, when the system is activated (Y in S21), path information (default value) is written and set to each of the devices A to D (S22).

  After this, the arbitration of the end points A1 to A4,..., D1 to D4 by the arbiters 2A to 2D of the devices A to D is performed by the route information (default) written and set in each of the devices A to D by the host CPU 5. Value).

  Thereafter, the timer is started from the time of starting the system (S31), and it is monitored whether a certain time has passed (S32), and every time the certain time has passed (Y of S32), the operation at that time The route between the devices A to D that is optimal in the tree structure based on the information on the mode, the device connection state (obtained from each device or managed by the host CPU 5), device function information, and information on the endpoint Is re-determined (S33). The processing in step S33 is executed as redetermination means and redetermination function. The path information for each device A to D determined in step S33 is written and set in the corresponding device A to D (S34). The processing in step S34 is executed as setting means and a setting function.

  After this, the arbitration of the end points A1 to A4,..., D1 to D4 by the arbiters 2A to 2D of the devices A to D refers to the path information written and set in the devices A to D by the host CPU 5. It is executed by doing.

[Discussion about effects]
First, consider the effect of switch output port contention. When a conflict occurs in the output port in the PCI Express switch, the data transfer rate is lowered. FIG. 21 shows that under the condition where there is one output port for four input ports in a PCI Express switch, four different types of traffic are started at the same time, and data transfer is completed in order according to the transfer rate. It is the graph which showed the characteristic in the case of going. In the figure, the horizontal axis represents the transfer time, the vertical axis represents the data transfer amount (integrated value) of each port, and the slope of each graph represents the transfer rate. Note that the payload size (meaning the size of the data portion other than the header information out of the total packet data size) is a measurement example under the condition that all four types are fixed to 64 bytes. The data transfer algorithm is a weighted round robin (WRR) in the PCI Express standard, and shows an example of characteristics when data transfer is set at a ratio of 1: 2: 4: 8 for four types. When the data transfer of one traffic class is completed, the algorithm is to transfer data while changing the ratio, such as 8: 4: 2 and further 8: 4 for the remaining traffic classes.

  In FIG. 21, it can be seen that, from the left side, four transfers are in conflict, three transfers are in conflict, two transfers are in conflict, and there is no conflict. Here, it can be seen that as the number of competing traffics decreases, the slope of each graph, that is, the transfer rate becomes steep, and the data transfer rate improves. In this regard, according to the present embodiment as described above, with respect to the plurality of end points A1 to A4, B1 to B4, C1 to C4, and D1 to D4, there is no competition in the data transfer path passing through the switch. Since the end point to be used is adjusted according to the operation mode, it can be seen that the data transfer rate can be improved.

  Next, consider the effect of the number of switch stages. When data is divided and transferred by a certain amount (for example, when image data is transferred to a plotter in the image forming system by dividing it into one line in the main scanning direction), the packet data is transmitted from the transmission source to the transmission destination. The influence of the initial delay that reaches the point becomes larger with the number of switch stages through which it passes.

  FIG. 22 is a graph showing the relationship between the payload size and the transfer rate, using the number of switches (number of stages) passed through as a parameter in the data transfer path, and the influence of the number of switches (stage number) passed through on the transfer rate. I understand. In the figure, in order from the top, there is no timing constraint, the switch has one stage, the delay structures 1, 2, 3, the switch has two stages, the delay structures 1, 2, 3, the switch has three stages, and the delay structures 1, 2, 3, The case where there are four stages of delay structures 1, 2, 3 and five switches of delay structures 1, 2, 3 is shown. Each time the number of switches passing through increases by one, the packet transfer delay time is added. The larger the packet data size, the greater the delay. For this reason, it can be seen that when there are a plurality of stages of switches on the data transfer path, the data transfer rate decreases as the size of data transmitted in one packet increases. In this regard, according to the present embodiment, with respect to the plurality of end points A1 to A4, B1 to B4, C1 to C4, and D1 to D4, the number of stages of the switch 1 passing through each is the smallest in relation to the switches 1A to 1D. Since the end points to be used are arbitrated so as to be equal to one stage, it can be seen that a decrease in the data transfer rate can be suppressed.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. (A) is a block diagram showing an existing PCI architecture, and (b) is a block diagram showing a PCI Express architecture. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is a time chart which shows the example of control of active state power management. It is a principle schematic diagram which shows the example of a tree structure in the data transfer system of this Embodiment. It is a principle schematic diagram showing an example of a tree structure in the image forming system of the present embodiment. It is a schematic flowchart which shows an example of the management method of the route information of this Embodiment. It is a schematic flowchart which shows the other example of the management method of the route information of this Embodiment. It is a schematic flowchart which shows an example of the timing control in the management method of the route information of this Embodiment. It is a schematic flowchart which shows the other example of the timing control in the management method of the route information of this Embodiment. 4 is a graph showing characteristics when four different types of traffic are simultaneously started in a PCI Express switch, and data transfer is sequentially terminated according to the transfer rate. 6 is a graph showing the relationship between the payload size and the transfer rate, with the number of switches (number of stages) passing through the data transfer path as a parameter. It is a principle schematic diagram which shows the example of a tree structure by the normal usage form of PCI Express. It is a principle schematic diagram which shows the modification.

Explanation of symbols

1A to 1D switch 2A to 2D arbiter A to D device A1 to A4 to D1 to D4 endpoint

Claims (6)

A communication channel transmission received independently by a data communications network according to a tree structure is established Lud over data transfer system,
The first device located on the downstream side in the tree structure has a first end point capable of communicating with the first switch located upstream and a second end point capable of communicating with the second switch located upstream. A second device having a plurality of end points including a point and located on the downstream side in the tree structure is located on the third end point and the upstream side capable of communicating with the first switch located on the upstream side A plurality of endpoints including a fourth endpoint capable of communicating with the second switch;
The first device uses the first endpoint and the second endpoint in an operation mode in which independent data transfer is performed for each of the first switch and the second switch. As described above, the first device includes a first arbiter that arbitrates an endpoint to be used among the plurality of endpoints included in the first device, and the second device includes the first switch and the second switch. Among the plurality of endpoints included in the second device, the third endpoint and the fourth endpoint are used in an operation mode in which data transfer is performed independently for each of the switches. A data transfer system comprising a second arbiter that adjusts an endpoint used in the network. The data transfer system according to claim 1, wherein the data transfer system is a PCI Express system. 3. The data transfer system according to claim 1, wherein the first device and the second device are devices involved in image formation. The image forming apparatus according to claim 3 , wherein the first device or the second device includes at least an image input device, an image output device, an image processing device, and a storage device. system. Communication channel transmission received independently by a data communications network according to a tree structure is established, the first positioned on the downstream side in the prior SL tree device first capable of communicating with the first switch located on the upstream side A plurality of end points including a second end point capable of communicating with the end point and the second switch located on the upstream side, and the second end point located on the downstream side in the tree structure is located on the upstream side Data utilizing a data transfer system having a plurality of endpoints including a third endpoint that can communicate with the first switch and a fourth endpoint that can communicate with the second switch located upstream A transfer method,
The first endpoint and the second endpoint are used when the first device is in an operation mode in which independent data transfer is performed for each of the first switch and the second switch. As described above, the second device arbitrates an endpoint to be used among the plurality of endpoints of the first device, and the second device has independent data for each of the first switch and the second switch. In the case of the operation mode in which the transfer is performed, the endpoint to be used among the plurality of endpoints of the second device is arbitrated so that the third endpoint and the fourth endpoint are used. To
A data transfer method characterized by the above. 6. The data transfer method according to claim 5 , wherein the data transfer system is a PCI Express system.

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