JP2006113798A - Data transfer system, reception buffer device, method for setting specification of data transfer system and image formation system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce costs due to the miniaturization of the chip size of an LSI, and to attain serial data transfer without deteriorating a transfer rate. <P>SOLUTION: When the rate of the payload size of transfer package data to be data-transferred to the reception buffer size of a reception buffer device installed in a data receiving part or a switch is provided with such a relation that the reception buffer size is equivalent to the two payload sizes, a transfer rate can be more improved compared with the case that the rate is 1. When such a relation that the reception buffer size is equivalent to the two payload sizes is established, it is possible to reduce costs due to the miniaturization of the chip size of an LSI without increasing the reception buffer size so much. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data transfer system, a reception buffer device, a data transfer system specification setting method, and an image forming system.

  Generally, in an image forming system (image forming apparatus) such as a digital copying machine or MFP that handles image data and other data, a PCI bus is used as an interface between devices. However, the parallel PCI bus has problems such as racing and skew, and the transfer rate has been low for use in high-speed and high-quality image forming apparatuses. The use of a high-speed serial interface such as IEEE1394 or USB is being considered in place of the parallel interface. As an example of such a high-speed serial interface, an interface called PCI Express (registered trademark) corresponding to a successor standard of the PCI bus system has been proposed and has been put into practical use (for example, see Non-Patent Document 1).

“Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  In PCI Express, the data reception unit has a data payload size (payload size means the size of the data portion other than the header information of the entire packet data size) due to the communication protocol. If the reception buffer size of the device is exceeded, credits cannot be supplied and communication cannot be established. For this reason, the reception buffer size needs to be larger than the data payload size of the transfer packet data. On the other hand, the smaller the reception buffer size, the smaller the chip size of the LSI, and the cost can be reduced.

  For this reason, it is considered optimal that the reception buffer size is the same as the data payload size of the transfer packet data. However, according to the experimental results of the present inventors, it is clear that the transfer rate decreases when the reception buffer size is the same as the data payload size of the transfer packet data.

  Therefore, an object of the present invention is to enable serial data transfer without reducing the transfer rate while reducing the cost by reducing the chip size of the LSI.

  According to the first aspect of the present invention, there is provided a data transfer system for transferring data from a data transmission unit to a data reception unit via a serial transfer path, and a payload size of transfer packet data to be transferred and a reception buffer provided in the data reception unit The ratio with the reception buffer size of the apparatus has a relationship in which two payload sizes are included with respect to the reception buffer size.

  According to a second aspect of the present invention, in the data transfer system for transferring data from the data transmitting unit to the data receiving unit via the serial transfer path and the switch, all the receptions included in the switch and the data receiving unit on the data transfer path. The reception buffer sizes of the buffer devices are equal, and the ratio between the payload size of transfer packet data to which data is transferred and each reception buffer size of the reception buffer device has a relationship in which two payload sizes are included in the reception buffer size.

  According to a third aspect of the present invention, in a data transfer system for transferring data from a data transmission unit to a data reception unit via a serial transfer path and a switch, the payload size of transfer packet data to be transferred and the data on the data transfer path The ratio of the reception buffer device having the smallest size among the reception buffer devices included in the switch and the data reception unit has a relationship in which two payload sizes are included with respect to the reception buffer size.

  According to a fourth aspect of the present invention, in the data transfer system according to any one of the first to third aspects, the payload size of the transfer packet data is 512 bytes or less.

  According to a fifth aspect of the present invention, in the data transfer system according to any one of the first to fourth aspects, the serial bus standard of the serial transfer path is a PCI Express standard.

  According to a sixth aspect of the present invention, in the data transfer system according to the fifth aspect, the payload size of the transfer packet data is a maximum payload size of the PCI Express standard.

  The invention according to claim 7 is a reception buffer device included in the data reception unit in the data transfer system for transferring data from the data transmission unit to the data reception unit via a serial transfer path, wherein the reception buffer size is data The transfer packet data to be transferred is set to have a payload size of two.

  According to an eighth aspect of the present invention, there is provided a reception buffer device having the same reception buffer size provided in the switch and the data reception unit in the data transfer system for transferring data from the data transmission unit to the data reception unit via a serial transfer path and a switch. The reception buffer size is set to a size that allows two payload sizes of transfer packet data to be transferred.

  According to a ninth aspect of the present invention, there is provided a receive buffer among the switch and the receive buffer device provided in the data receiver in a data transfer system for transferring data from a data transmitter to a data receiver through a serial transfer path and a switch. The reception buffer device is the smallest in size, and the reception buffer size is set to a size that allows two payload sizes of transfer packet data to be transferred.

  According to a tenth aspect of the present invention, in the reception buffer device according to any one of the seventh to ninth aspects, the payload size of the transfer packet data is 512 bytes or less.

  According to an eleventh aspect of the present invention, in the reception buffer device according to any one of the seventh to tenth aspects, the serial bus standard of the serial transfer path is a PCI Express standard.

  According to a twelfth aspect of the present invention, in the reception buffer device according to the eleventh aspect, the payload size of the transfer packet data is a maximum payload size of the PCI Express standard.

  A thirteenth aspect of the invention is a data transfer system specification setting method for transferring data from a data transmission unit to a data reception unit via a serial transfer path, wherein a reception buffer size of a reception buffer device provided in the data reception unit The operation is performed by setting the payload size so that two payload sizes of the transfer packet data to be transferred are included.

  The invention according to claim 14 is a specification setting method of a data transfer system for transferring data from a data transmission unit to a data reception unit via a serial transfer path and a switch, the switch on the data transfer path and the data reception When the reception buffer sizes of all the reception buffer devices included in the unit are equal, the payload size is set so that there are two payload sizes of transfer packet data to be transferred for each reception buffer size of the reception buffer device. Make it work.

  The invention according to claim 15 is a specification setting method of a data transfer system for transferring data from a data transmission unit to a data reception unit via a serial transfer path and a switch, the switch on the data transfer path and the data reception The operation is performed with the payload size set so that two payload sizes of transfer packet data to be transferred with respect to the reception buffer size of the reception buffer device having the smallest size among the reception buffer devices included in the unit are included.

  According to a sixteenth aspect of the present invention, in the data transfer system specification setting method according to any one of the thirteenth to fifteenth aspects, the payload size of the transfer packet data is 512 bytes or less.

  According to a seventeenth aspect of the present invention, in the data transfer device specification setting method according to any one of the thirteenth to sixteenth aspects, the serial bus standard of the serial transfer path is a PCI Express standard.

  The invention described in claim 18 is the data transfer system specification setting method according to claim 17, wherein the payload size of the transfer packet data is a maximum payload size of the PCI Express standard.

  According to a nineteenth aspect of the present invention, there is provided an image forming system comprising the data transfer system according to any one of the first to sixth aspects, wherein a device involved in image formation is a data transmitting unit or a data receiving unit.

  According to the present invention, the ratio between the payload size of the transfer packet data to be transferred and the reception buffer size of the reception buffer device included in the data receiving unit or the switch is such that two payload sizes are included in the reception buffer size. As described above, the reception buffer size is set or the payload size is set, so the reception buffer size is not increased unnecessarily, the cost is reduced by reducing the chip size of the LSI, and the payload size is reduced. It is possible to perform data transfer without reducing the transfer rate due to the margin of the reception buffer size.

  The best mode for carrying out the present invention will be described with reference to the drawings.

[Outline of PCI Express standard]
First, this embodiment conforms to PCI Express (registered trademark), which is one of high-speed serial buses. As a premise of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. PCI Express 114b connects the switch 117a to which the PCI Express 114b is connected, and the PCI bridge 119 to which the switch 117b to which the endpoint 115b and the legacy endpoint 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Furthermore, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c. The switch 134 is connected to the mobile dock 135, Gigabit Ethernet (Ethernet is a registered trademark) 136, and an add-in by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects components one-to-one (point-to-point). The transfer rate is, for example, one-way 2.5 Gbps (in the future, 5 Gbps or 10 Gbps is assumed). The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint basically does not request I / O port resources in the BAR (base address register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and has no concept of hierarchy. In PCI Express, as shown in FIG. 7B, Like general communication protocols and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, the transaction layer 153, the data link layer 154, and the physical layer 155 are provided between the uppermost software layer 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration uses a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the crosspoint of the data signal. The clock is extracted.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting conventional access to PCI Express access is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (Express Cards), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (for in-band event notification and general message transmission (exchange) between PCI Express devices ... Interrupt requests and confirmations are communicated by using messages as "virtual wires" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled (arbitration means). VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed to avoid the overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (a mechanism that confirms the buffer availability on the receiving side before starting data transfer and prevents overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. If the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power management and link state As shown in Table 1, a link state of L0 / L0s / L1 / L2 is defined in order to keep the power consumption of the link low.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 14, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Image forming system]
The data transfer system according to the present embodiment is used in an image output system such as an image output apparatus such as a printer, an image input apparatus such as a scanner, and an image forming system such as a digital copying machine and an MFP such as an MFP. It is used as a serial interface and conforms to the PCI Express standard as described above.

  An example of an image forming system to which the data transfer system of this embodiment is applied will be described with reference to FIG. FIG. 15 is a block diagram showing an outline of connections of devices, devices, etc. of an image forming system to which the data transfer apparatus of this embodiment is applied. The image forming system 1 uses a PCI Express standard bus system for serial data transfer. That is, a CPU 11 that centrally controls each part of the image forming system 1 and a system memory 12 that is a work area of the CPU 11 are connected to a root complex 13 of the PCI Express standard. A root complex 13 and a PCI Express standard switch (or switch network) 14 are connected via a PCI Express standard general-purpose bus 15. The PCI Express standard switch (or switch network) 14 is connected to various devices and devices serving as PCI Express standard end points. That is, a hard disk (HDD) unit 21 for storing image data, an image memory unit 22 and a memory unit 23, an image processing unit 24 for performing various image processing, a high-speed network 25 for communicating with an external network, A scanner 26 as an input engine, a plotter 27 as an image output engine, an image input engine, another multifunction device 28 having an image output engine, and the like.

[Data transfer system]
In such an image forming system, since the data transfer rate required for each device / device is different, it is necessary to specify the payload size of the transfer packet data in a combination that provides the required data transfer rate. Come. At this time, in the data transfer system included in the image forming system of the present embodiment, the cost performance can be optimized by optimizing the relationship between the payload size and the reception buffer size.

  That is, in the data transfer system of this embodiment that performs data transfer from the data transmission unit to the data reception unit via the PCI Express standard serial transfer path, the payload size of the transfer packet data to be transferred and the data reception unit are provided. The ratio of the reception buffer device to the reception buffer size has a relationship in which two payload sizes are included with respect to the reception buffer size. Here, the payload size of the transfer packet data in the present embodiment means the maximum payload size (Max Paylord Size) of the PCI Express standard related to image data handled by the image forming system. In this case, since the relationship between the two is relative, for example, when designing the system configuration, the reception buffer size of the reception buffer device included in the data reception unit is equal to the payload size of the transfer packet data to be transferred. It may be realized by setting the size to be two, or, in actual use, as a specification setting method of the data transfer system, with respect to the reception buffer size of the reception buffer device included in the data reception unit You may make it operate | move by setting a payload size so that the payload size of the transfer packet data transmitted by data may contain two.

  FIG. 16 is a block diagram showing a simple configuration example for facilitating understanding of the data transfer system of the present embodiment. In the illustrated example, a node 31 (for example, a data receiving unit) from a node 32 corresponding to a certain endpoint, which is a data transmission unit, via a link 31 (corresponding to the link 15) which is a serial transfer path of the PCI Express standard. An example of a data transfer system having a simple configuration for transferring data to the route complex 13) is shown. Transfer packet data from the port A of the node 32 to the reception buffer device 34 provided in the port B of the node 33 via the link 31 35 is transmitted as a TLP (transaction layer packet), and a DLLP (data link layer packet) is returned from port B to port A. In the present embodiment, the ratio between the payload size of the transfer packet data 35 and the reception buffer size of the reception buffer device 34 included in the node 33 has a relationship in which two payload sizes are included with respect to the reception buffer size. ing. Specifically, the reception buffer size of the reception buffer device 34 is set to a size that includes two payload sizes of the transfer packet data 35.

  The basis for setting the relationship between the payload size and the reception buffer size in this way will be described with reference to the characteristic diagram shown in FIG. In FIG. 17, the payload size of the transfer packet data 35 is a parameter (64, 128, 256, 512 bytes), the ratio between the reception buffer size and the payload size of the reception buffer device 34 is taken on the horizontal axis, and the transfer rate is taken on the vertical axis. FIG. According to the characteristic diagram shown in FIG. 17, it can be seen that the transfer rate is higher as the payload size is larger if the ratio is the same. It should be noted that the payload size is 128 bytes and the ratio is 1 (that is, the ratio considered to be the best in the conventional example and the reception buffer size is 128 bytes), and the payload size is 64 bytes. Is 2 (that is, the reception buffer size is 128, that is, the size in which two payload sizes are included), the transfer rate is higher. This tendency is the same up to a payload size of 512 bytes. Furthermore, even if the ratio is 3, there is no significant difference from the case where the ratio is 2. Conversely, it is meaningful to set the ratio to 2, but even if the ratio is 3 or more, the reception buffer size is increased and the cost is increased, so that the cost is reduced by downsizing the LSI chip. It means not preferable above. Therefore, according to the present embodiment in which the ratio between the reception buffer size and the payload size is 2, the relationship between the payload size and the reception buffer size can be optimized, and the cost performance can be optimized. .

  In the description with reference to FIG. 16, the reception buffer size of the reception buffer device 34 has been described as an example in which two payload sizes of the transfer packet data 35 are set at the time of system design. When the system is actually used, the payload size is set so that there are two payload sizes of transfer packet data to be transferred with respect to the reception buffer size of the reception buffer device 34 as the specification setting method of the data transfer system. May be operated.

  FIG. 18 is a block diagram showing another example of a simple configuration example to facilitate understanding of the data transfer system of the present embodiment. The illustrated example shows a case where a PCI Express standard switch 36 (corresponding to the switch 14) is interposed on the data transfer path between the nodes 32 and 33, and the link between the port A and the port 0 of the node 32 and the switch 36 is shown. 31 and the link 37 between the port 36 and the port B of the switch 36 and the node 33, so that the port 0 of the switch 36 includes the reception buffer device 38 in addition to the reception buffer device 34 of the node 33. This is an application example.

  In the present embodiment, the reception buffer sizes of the plurality of reception buffer devices 38 and 34 existing on the data transfer path are set to be equal, and the payload size of the transfer packet data 35 and the reception buffer device provided in the switch 36 and the node 33 The ratio between the reception buffer sizes 38 and 34 is such that two payload sizes are included in the reception buffer size. Specifically, the reception buffer sizes of the reception buffer devices 38 and 34 are set to a size that can include two payload sizes of the transfer packet data 35.

  The reason for setting the relationship between the payload size and the reception buffer size in this way will be described with reference to the characteristic diagram shown in FIG. FIG. 19 is a characteristic diagram showing the relationship between the payload size of the transfer packet data 35 and the transfer rate when the reception buffer size is used as a parameter. The four types of graphs in the figure show the characteristics when the reception buffer size is 128, 512, 2K, and 8K bytes, respectively. In the communication protocol based on the PCI Express standard, credits exceeding the upper limit of the buffer cannot be supplied, and communication cannot be established. Therefore, the characteristics of any buffer size are interrupted at the right end. On the other hand, the common points of these four types of graphs are the same as the reception buffer size, whereas a sufficient transfer rate corresponding to the payload size is obtained up to a payload size that is ½ of the reception buffer size. The transfer rate at the payload size is deteriorated as compared with the case where the payload size is ½ of the reception buffer size. Therefore, even when the switch 36 is interposed on the data transfer path and includes a plurality of reception buffer devices 38 and 34, if the reception buffer sizes are equal, the ratio of each reception buffer size to the payload size is set to 2 ( According to the present embodiment in which two payload sizes are included (reception buffer size), the relationship between the payload size and the reception buffer size can be optimized, and cost performance can be optimized.

  In the description with reference to FIG. 18, the reception buffer size of the reception buffer devices 38 and 34 has been described as an example in which two payload sizes of the transfer packet data 35 are set at the time of system design. When the actual system is used, as a specification setting method of the data transfer system, two payload sizes of transfer packet data to be transferred with respect to the reception buffer size of the reception buffer devices 38 and 34 are included. You may make it operate | move by setting a payload size.

  FIG. 20 is a block diagram showing still another example of the simple configuration example in order to facilitate understanding of the data transfer system of the present embodiment. The illustrated example is the same as the system configuration example shown in FIG. 18, but is an application example when the reception buffer sizes of the reception buffer devices 38 and 34 are different.

  In the present embodiment, the reception size of the transfer packet data 35 and the reception buffer device having the smallest reception buffer size among the plurality of reception buffer devices 38 and 34 existing on the data transfer path, for example, reception by the reception buffer device 38. The ratio with the buffer sizes is configured such that two payload sizes are included with respect to the reception buffer size. Specifically, the reception buffer size of the reception buffer device 38 is set to a size that can include two payload sizes of the transfer packet data 35.

  The reason for setting the relationship between the payload size and the reception buffer size in this way will be described with reference to the characteristic diagram shown in FIG. FIG. 21 shows the payload size of the transfer packet data 35 when the reception buffer size of the reception buffer device 38 is fixed to 128 bytes and the reception buffer size of the reception buffer device 34 is changed to 128, 512, 2K, and 8K bytes. It is a characteristic view which shows the relationship between (horizontal axis) and a transfer rate (vertical axis). FIG. 21 shows that even if the combination of the reception buffer sizes related to a plurality of reception buffer devices is changed, the payload size is up to ½ payload size (64 bytes) of the buffer size (128 bytes) of the mounted reception buffer device 38. The transfer rate with the same payload size (128 bytes) as the reception buffer size is degraded compared to the case where the payload size is 1/2 of the reception buffer size. It shows the characteristic of This means that the transfer rate is determined by the reception buffer device having the smallest reception buffer size among the plurality of reception buffer devices existing on the data transfer path, and the reception buffer size that determines the transfer rate. According to the present embodiment in which the ratio between the payload size and the payload size is 2 (reception buffer size including two payload sizes), the relationship between the payload size and the reception buffer size can be optimized, and the cost performance is optimal. Can be achieved. Although not shown in the graph in FIG. 21, it has been confirmed that the transfer rate is determined by the smallest reception buffer size on the data transfer path in each combination of 128 to 8 Kbytes.

  In the description with reference to FIG. 20, the reception buffer size of the reception buffer device 38 having the minimum reception buffer size at the time of system design is described as an example in which two payload sizes of the transfer packet data 35 are set. In the actual use of a system that is already on the market, the specification setting method of the data transfer system can be applied to the receive buffer size of the receive buffer device having the smallest size among the receive buffer devices on the data transfer path. You may make it operate | move by setting a payload size so that the payload size of the transfer packet data transmitted by data may contain two. More practically, in the data transfer system, the smallest receive buffer size is automatically detected among the plurality of receive buffer devices on the data transfer path, and the smallest receive buffer in which the payload size of the transfer packet data is detected. If it is automatically set to ½ of the size (that is, the size in which two payload sizes are included), the relationship between the payload size and the reception buffer size can always be optimized.

[Consideration of transfer rate degradation]
By the way, the reason why the transfer rate deteriorates in the case of the conventional system (when the ratio between the payload size and the reception buffer size is 1) will be considered based on the comparison with the system of the present embodiment.

  FIG. 22 is a block diagram showing a simple transfer system configuration example for explaining the transfer rate deterioration. FIG. 22 shows the same example as in FIG.

  FIG. 23 is an explanatory diagram for explaining the deterioration of the transfer rate. FIG. 23A shows an example of a timing chart in the link 31 when the payload size (64 bytes) is 1/2 of the reception buffer size (128 bytes) according to the present embodiment. (B) shows an example of a timing chart in the link 31 when the payload size (128 bytes) and the reception buffer size (128 bytes) are the same according to the conventional method.

  First, when the reception buffer sizes of the two reception buffer devices 38 and 34 as shown in FIG. 23A are 128 bytes, 128 bytes, and the payload size is 64 bytes, the node 32 gives credit for two packets. Since it has the initial value, the first two can always be issued consecutively. The state of the reception buffer device 38 on the switch 36 side is a buffer full condition upon arrival of the first transfer packet data (PCI Express specification). The first transfer packet is being transferred during the transfer of the second transfer packet data. Since data is transferred to another port (port 1) in the switch 36, there is a credit vacancy and a flow control (FC) packet is issued. Since the node 32 receives this FC packet during the transmission of the second packet, the next second transfer packet data can be issued without a gap as shown in FIG.

  On the other hand, when the reception buffer sizes of the two reception buffer devices 38 and 34 as shown in FIG. 23B are 128 bytes, 128 bytes, and the payload size is 128 bytes, the node 32 has one packet. Since it has only the initial credit as an initial value, it enters a state waiting for FC packet issuance after the first packet issuance. The state of the reception buffer device 38 on the switch 36 side becomes a buffer full condition upon arrival of the first transfer packet data (PCI Express specification), and this first packet is sent to another port (port 1) in the switch 36. At last, the credit is vacant and the FC packet is issued. The node 32 can finally issue the next second transfer packet data when the FC packet arrives.

That is, in the case of the conventional method shown in FIG.
(Completed issuance of the first packet from the node 32 → transmission time to the switch 36)
+ (Time required for consumption inside switch 36)
+ (Transmission time of FC packet from switch 36 to node 32)
Minute gaps are generated each time, and the transfer rate deteriorates.

  Furthermore, since the above calculation formula is the same even if the payload size and the reception buffer size are changed, it can be understood that the degree of deterioration of the data transfer rate is smaller as the setting value of the reception buffer size is larger. FIG. 24 is a timing chart showing this situation due to the difference in size. FIG. 24A shows a case where the buffer size of the reception buffer devices 38 and 34 is 128 bytes, 128 bytes, and the payload size is 128 bytes, for example. FIG. 24B shows a case where the buffer sizes of the reception buffer devices 38 and 34 are 512 bytes, 512 bytes, and the payload size is 512 bytes, for example.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. (A) is a block diagram showing an existing PCI architecture, and (b) is a block diagram showing a PCI Express architecture. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is a time chart which shows the example of control of active state power management. 1 is a block diagram schematically showing a configuration example of an image forming system of an embodiment. It is a block diagram which shows the simple structural example, in order to make an understanding of the data transfer system of this Embodiment easy. FIG. 6 is a characteristic diagram when the payload size of transfer packet data is used as a parameter, the ratio between the reception buffer size and the payload size of the reception buffer device is taken on the horizontal axis, and the transfer rate is taken on the vertical axis. It is a block diagram which shows another example of the simple structural example, in order to make an understanding of the data transfer system of this Embodiment easy. It is a characteristic view which shows the relationship between the payload size of the transfer packet data when a reception buffer size is used as a parameter, and the transfer rate. It is a block diagram which shows another example of the simple structural example, in order to make an understanding of the data transfer system of this Embodiment easy. Characteristic diagram showing the relationship between the transfer packet data payload size (horizontal axis) and transfer rate (vertical axis) when the minimum receive buffer size is fixed at 128 bytes and the receive buffer size of other receive buffer devices is changed It is. It is a block diagram which shows the simple structural example of a transfer system for demonstrating deterioration of a transfer rate. It is explanatory drawing for demonstrating deterioration of a transfer rate. It is a timing chart which shows the mode of the deterioration of the transfer rate by the difference in size.

Explanation of symbols

31 Serial Transfer Path 32 Data Transmitter 33 Data Receiver 34 Receive Buffer Device 35 Transfer Packet Data 36 Switch 37 Serial Transfer Path 38 Receive Buffer Device

Claims (19)

In a data transfer system for transferring data from a data transmission unit to a data reception unit via a serial transfer path,
Data in which the ratio between the payload size of transfer packet data to be transferred and the reception buffer size of the reception buffer device included in the data receiving unit has a relationship in which two payload sizes are included with respect to the reception buffer size Transfer system. In a data transfer system for transferring data from a data transmission unit to a data reception unit via a serial transfer path and a switch,
The reception buffer sizes of all the reception buffer devices included in the switch and the data reception unit on the data transfer path are equal,
A data transfer system, wherein a ratio between a payload size of transfer packet data to be transferred and each reception buffer size of the reception buffer device has a relationship in which two payload sizes are included with respect to the reception buffer size. In a data transfer system for transferring data from a data transmission unit to a data reception unit via a serial transfer path and a switch,
The ratio of the payload size of transfer packet data to be transferred and the reception buffer size of the reception buffer device having the smallest size among the reception buffer devices included in the switch and the data reception unit on the data transfer path is the reception buffer size. A data transfer system characterized by having a relationship in which two payload sizes are included.   The data transfer system according to any one of claims 1 to 3, wherein the payload size of the transfer packet data is 512 bytes or less.   5. The data transfer system according to claim 1, wherein the serial bus standard of the serial transfer path is a PCI Express standard.   6. The data transfer system according to claim 5, wherein the payload size of the transfer packet data is a maximum payload size of the PCI Express standard. A reception buffer device provided in the data receiving unit in the data transfer system for transferring data from the data transmitting unit to the data receiving unit via a serial transfer path,
A reception buffer device, wherein the reception buffer size is set to a size that allows two payload sizes of transfer packet data to be transferred. A reception buffer device having the same reception buffer size provided in the switch and the data reception unit in the data transfer system for transferring data from the data transmission unit to the data reception unit via a serial transfer path and a switch;
A reception buffer device, wherein the reception buffer size is set to a size that allows two payload sizes of transfer packet data to be transferred. A receiving buffer device having the smallest receiving buffer size among the receiving buffer device included in the switch and the data receiving unit in the data transfer system for transferring data from the data transmitting unit to the data receiving unit via the serial transfer path and the switch. There,
A reception buffer device, wherein the reception buffer size is set to a size that allows two payload sizes of transfer packet data to be transferred.   The reception buffer device according to any one of claims 7 to 9, wherein the payload size of the transfer packet data is 512 bytes or less.   11. The reception buffer device according to claim 7, wherein a serial bus standard of the serial transfer path is a PCI Express standard.   12. The reception buffer device according to claim 11, wherein the payload size of the transfer packet data is a maximum payload size of the PCI Express standard. A specification setting method for a data transfer system for transferring data from a data transmission unit to a data reception unit via a serial transfer path,
An operation of the data transfer system, wherein the payload size is set to operate so that two payload sizes of transfer packet data to be transferred with respect to a reception buffer size of a reception buffer device provided in the data reception unit are included. Specification setting method. A data transfer system specification setting method for transferring data from a data transmission unit to a data reception unit via a serial transfer path and a switch,
When the reception buffer sizes of all the reception buffer devices included in the switch and the data reception unit on the data transfer path are equal,
A specification setting method for a data transfer system, wherein the payload size is set so that two payload sizes of transfer packet data to be transferred with respect to each reception buffer size of the reception buffer device are entered. A data transfer system specification setting method for transferring data from a data transmission unit to a data reception unit via a serial transfer path and a switch,
Two payload sizes of transfer packet data to be transferred with respect to the reception buffer size of the reception buffer device having the smallest size among the reception buffer devices included in the switch and the data reception unit on the data transfer path are included. A specification setting method for a data transfer system, characterized in that the payload size is set to operate.   The data transfer system specification setting method according to any one of claims 13 to 15, wherein the payload size of the transfer packet data is 512 bytes or less.   17. The data transfer apparatus specification setting method according to claim 13, wherein a serial bus standard of the serial transfer path is a PCI Express standard.   18. The data transfer system specification setting method according to claim 17, wherein the payload size of the transfer packet data is a maximum payload size of the PCI Express standard. An image forming system comprising the data transfer system according to claim 1, wherein a device involved in image formation is a data transmission unit or a data reception unit.

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