JP4287325B2 - Imaging system - Google Patents

Description

  The present invention relates to an image system such as a scanner, a printer, a digital copier equipped with these, a multifunction peripheral (MFP), or the like that handles various image data and performs various processes.

  Generally, in a device / system that handles image data and other data, a PCI bus is used as an interface between devices. However, the parallel PCI bus has problems such as racing and skew, and the transfer rate has been low for use in high-speed and high-quality image equipment. The use of a high-speed serial interface is being considered in place of the system interface. Conventionally, there are standards such as IEEE1394 and USB as a widely used serial interface, but there are problems such as insufficient transfer rate and difficulty in securing a scalable bus width compared to PCI. . For this reason, the use of an interface called PCI Express (registered trademark) corresponding to the successor standard of the PCI bus system is being studied as another high-speed serial interface (see Non-Patent Document 1).

“Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, when paying attention to an image processing unit such as a DSP used in an image system such as a scanner, printer, digital copier, or MFP, the image processing function is matched to the maximum capability of these image systems regardless of the interface. A single designed image processing unit is used. For this reason, if the specifications of the image system are changed, the specifications of the image processing unit itself must be changed, lacking versatility and flexibility, or excessive image processing functions depending on the contents of the image processing. There are disadvantages such as waste.

  An object of the present invention is to provide an image system in which an image processing unit is provided with versatility and flexibility by effectively utilizing a PCI Express system that is a high-speed serial interface.

In order to solve the above problems, an image system according to the present invention can be connected to a root complex connected to a processor and a memory, an upstream port connected to the root complex, and a serial interface compliant with the PCI Express standard. A switch having first to fourth downstream ports; a first device connected to the first downstream port via the serial interface and capturing image data; and the second downstream port A first image processing unit connected via a serial interface and having an image processing function; and a second image processing unit connected to the third downstream port via the serial interface and having an image processing function; The above A second device connected to the fourth downstream port via the serial interface and printing based on image data, wherein the first downstream port of the switch includes the first device The second downstream port receives the image data generated by dividing the image data input via the first downstream port, The third image processing unit is a port that outputs to the first image processing unit and receives image data generated by image processing by the first image processing unit, and the third downstream port includes the first image processing unit. An image generated by dividing image data input through one downstream port Is output to the second image processing unit, and image data generated by image processing by the second image processing unit is input to the fourth downstream port. Is the image data generated by the image processing by the first image processing unit input through the second downstream port, and the input through the third downstream port. It is a port for outputting image data generated by combining image data generated by image processing by the second image processing unit to the second device .

In order to solve the above-described problem, the image system according to the present invention is configured such that the image data captured by the first device is image data corresponding to relatively wide paper, and the second down The stream port is a port for outputting the image data generated by dividing the image data corresponding to the relatively wide paper to the first image processing unit, and the third downstream port is the port It is a port for outputting image data generated by dividing image data corresponding to relatively wide paper to the second image processing unit .

In order to solve the above problem, the image system according to the present invention is configured such that the image data captured by the first device is image data having a relatively high resolution image density. The downstream port is a port for outputting the image data generated by dividing the image data having the relatively high resolution image density to the first image processing unit, and the third downstream port. The port is a port for outputting image data generated by dividing the image data having a relatively high resolution image density to the second image processing unit .

In order to solve the above problem, in the image system according to the present invention, the second downstream port is generated by dividing the image data captured by the first device in the main scanning direction. The port that outputs image data to the first image processing unit, and the third downstream port is an image generated by dividing the image data captured by the first device in the main scanning direction. It is a port for outputting data to the second image processing unit .

In order to solve the above problems, an image system according to the present invention is connected to a root complex connected to a processor and a memory, an upstream port connected to the root complex, and a serial interface compliant with the PCI Express standard. A switch having possible first to fourth downstream ports, a first device connected to the first downstream port via the serial interface and capturing image data, and the second downstream port A first image processing unit that is connected to the third interface and having an image processing function, and an image that is connected to the third downstream port via the serial interface and that the first image processing unit has. Processing machine A second image processing unit having an image processing function different from the first function, and a second device connected to the fourth downstream port via the serial interface and printing based on image data, The first downstream port of the switch is a port to which image data captured by the first device is input, and the second downstream port is connected to the first downstream port via the first downstream port. A port for outputting the input image data to the first image processing unit and for inputting image data generated by image processing by the first image processing unit; The downstream port is the first image processing unit that is input via the second downstream port. The image data generated by image processing by the unit is output to the second image processing unit, and the image data generated by image processing by the second image processing unit is input. And the fourth downstream port receives image data generated by image processing by the second image processing unit input via the third downstream port, It is a port that outputs to the device .

  According to the present invention, at least a plurality of independent image processing units are connected by a PCI Express standard high-speed serial interface as a device located at the end point in the tree structure of the PCI Express standard high-speed serial interface system. Multiple image processing, taking advantage of the features of the PCI Express standard high-speed serial interface system with high-speed serial communication, scalability, and protocol flexibility, and in particular, taking advantage of the extensibility features when using PCI Express standard switches By causing the unit to perform parallel or selective operation or pipeline-like image processing, the image processing function targeted by the image system can be exhibited without waste. Must be designed for the highest capacity of the system It can be without, to provide an image system with versatility, flexibility in image processing unit.

  In particular, when using a plurality of standard image processing units having the same image processing function, the required number of image processing units is used according to the image processing content required by the image system, thereby achieving high image quality. Even when processing is required, the processing speed can be maintained by parallel processing. For this reason, a standard general-purpose product may be used as the image processing unit, so the only image processing unit that is expensive and lacks flexibility. As compared with the case of using the image system, it is possible to construct an image system that is inexpensive, versatile, and versatile. In addition, at the time of image processing that does not require high image quality processing etc., it is possible to flexibly cope with such as suppressing the overall power consumption by selectively operating only some image processing units without using all of them. .

  In addition, multiple image processing units, each assigned a different image processing function, are prepared, and the target image data is continuously flowed through the PCI Express standard high-speed serial interface system using these image processing units. By efficiently processing in a pipeline manner, desired image processing can be performed flexibly and at high speed without designing the image processing unit in accordance with the maximum capability of the image system.

  The best mode for carrying out the present invention will be described with reference to the drawings.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. A tree structure in which a PCI-X bridge 105b to which PCI-X devices 104c and 104d are connected and a PCI bridge 107 to which a PCI bus slot 106 is connected are connected via a PCI-X bridge 105c ( Tree structure).

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. The switch 117a connected by the PCI Express 114b is connected by the PCI Express 114c, and the PCI bridge 119 to which the switch 117b to which the end point 115b and the legacy end point 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected is a PCI. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to a desktop / mobile. For example, graphics 125 is connected to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. An x16 PCI Express 126a and an I / O hub 127 having a conversion function are connected by a PCI Express 126b. For example, a memory 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Furthermore, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c. The switch 134 is connected to the mobile dock 135, Gigabit Ethernet (Ethernet is a registered trademark) 136, and an add-in by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects components one-to-one (point-to-point). The transfer rate is, for example, one-way 2.5 Gbps (in the future, 5 Gbps or 10 Gbps is assumed). The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint basically does not request I / O port resources in the BAR (base address register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and has no concept of hierarchy. In PCI Express, as shown in FIG. 7B, Like general communication protocols and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, the transaction layer 153, the data link layer 154, and the physical layer 155 are provided between the uppermost software layer 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration uses a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the crosspoint of the data signal. The clock is extracted.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting conventional access to PCI Express access is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (NEWCARD), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

Virtual Channel (VC: V i rtual Channel) is in each independent virtual communication bus (mechanism using a plurality of independent data flow buffers sharing the same link), each resource (buffer or queue) And performs independent flow control as shown in FIG. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted according to the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed to avoid the overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (a mechanism that confirms the buffer availability on the receiving side before starting data transfer and prevents overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power management and link state As shown in Table 1, a link state of L0 / L0s / L1 / L2 is defined in order to keep the power consumption of the link low.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 14, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Image system]
An image system such as a scanner, a printer, a digital copying machine, and an MFP according to the present embodiment is configured by using the PCI Express standard high-speed serial bus as described above as an interface between the devices.

  FIG. 15 is a schematic block diagram illustrating a configuration example of the image system according to the present embodiment. Here, in the present embodiment, an example of application to an image system including a scanner 1 that captures image data and a printer 2 that performs print output based on the image data will be described. An image system having a system configuration in which the scanner 1 and the printer 2 are each provided as a single device may be used, or an image system such as a digital copying machine, an MFP, and the like that are integrally provided with the scanner 1 and the printer 2 may be used. . For example, a laser printer capable of high-speed printing is used as the printer 2, but the printing method is not particularly limited. The present invention can also be applied to an image system such as a scanner or a printer that includes only one of the scanner 1 and the printer 2.

  The scanner 1 and the printer 2 are connected to the PCI Express standard switch 3 as endpoint devices via PCI Express standard high-speed serial interfaces 4a and 4b, respectively.

  In addition, in the present embodiment, a plurality of, for example, two image processing units 5 and 6 are prepared as one of the endpoint devices, and the PCI Express high-speed serial interfaces 4c and 4d are respectively provided to the switch 3. Connected as an endpoint device. Here, in the present embodiment, these image processing units 5 and 6 are devices constituted by, for example, a DSP (digital signal processor) or the like, but none of them has a particularly advanced image processing function. Standard products that are all standard and have the same image processing function are used.

  Although not particularly illustrated, a root complex to which a CPU and a system memory are connected is connected to the upstream port of the tree structure in the PCI Express system with respect to the switch 3.

  According to the configuration of such an image system, as indicated by an arrow in FIG. 15, image data read from a document by the scanner 1 is subjected to image processing via the high-speed serial interface 4a, the switch 3, and the high-speed serial interfaces 4c and 4d. The image data can be transferred to the units 5 and 6 at high speed, and the image processing for the image data can be shared and executed simultaneously in parallel. Then, the image data processed in parallel by these image processing units 5 and 6 is transferred at high speed to the printer 2 via the high-speed serial interfaces 4c and 4d, the switch 3, and the high-speed serial interface 4b, and after image processing. These image data can be combined and printed out on a recording sheet. In this case, in the illustrated example, the number of image processing units is two. However, the number of image processing units may be increased or decreased according to the required image processing content. Even if the number of image processing units is increased or decreased, the switch in the PCI Express system 3 can be easily accommodated by the extensibility.

  That is, when using a plurality of standard image processing units 5, 6,... Having the same image processing function as in the present embodiment, it is necessary according to the image processing content required for the image system. By using a large number of image processing units, the processing speed can be maintained by parallel processing even when high image quality processing or the like is required.

  To give a more specific example, as a required image processing content, for example, when a document read by the scanner 1 is relatively wide paper, the processing function is insufficient with one image processing unit 5 or 6. However, the document read by the scanner 1 is divided into two in the main scanning direction of the document, and the right half of the image data is assigned to the image processing unit 5 as shown in FIG. By assigning the left half of the image data to the image processing unit 6 and simultaneously performing image processing in parallel, the individual image processing units 5 and 6 can be processed with the image data amount substantially reduced to half. Therefore, even when high image quality processing or the like is required, the processing speed can be maintained by parallel processing. Although not particularly illustrated, the same applies to the case where image processing with relatively high resolution is required as image processing content, and the processing function is not possible with one image processing unit 5 or 6. Although it is sufficient, the document read by the scanner 1 is divided into two in the main scanning direction of the document, the right half of the image data is assigned to the image processing unit 5, and the left half of the image data is the image processing unit. 6 and simultaneously performing image processing in parallel, the individual image processing units 5 and 6 can be processed with the image density substantially reduced to half, and therefore high image quality processing is required. Even in this case, the processing speed can be maintained by parallel processing.

  On the other hand, as the requested image processing content, for example, when the document read by the scanner 1 is a paper having a width less than or equal to the normal width (relative), the image processing function is sufficient with one image processing unit 5 or 6. Therefore, for example, only the image processing unit 5 can be operated, and the image processing unit 6 can be selectively operated depending on the contents of the image processing, as indicated by a broken line in FIG. In this case, the entire power consumption can be suppressed by setting the image processing unit 6 in the power saving state. This is the same when the image processing of normal image density (relative) is required as the image processing content, and the image processing function is sufficient with one image processing unit 5 or 6. Therefore, for example, only the image processing unit 5 can be operated, and the image processing unit 6 can be selectively operated. In this case, the entire power consumption can be suppressed by setting the image processing unit 6 in the power saving state.

  FIG. 17 is a schematic block diagram illustrating a configuration example of another image system according to the present embodiment. Basically, it conforms to the configuration example of the image system shown in FIG. 15, but in this embodiment, a plurality of, for example, three image processing units 11, 12, and 13 are prepared as one of the endpoint devices. The switch 3 is connected as an endpoint device via PCI Express standard high-speed serial interfaces 4e, 4f, and 4g, respectively. Here, in the present embodiment, these image processing units 11, 12, and 13 are devices configured by, for example, a DSP (digital signal processor) or the like, and all of them have a particularly advanced image processing function. Instead, an image processing unit to which different image processing functions (image processing A, B, C) are assigned is used as shown in FIG. For example, image processing A is basic image processing, image processing B is image rotation processing, and so on.

  According to such an image system, as indicated by an arrow in FIG. 17, the image data read from the document by the scanner 1 is transferred to the image processing unit 11 via the high-speed serial interface 4a, the switch 3, and the high-speed serial interface 4e. The image processing unit 11 executes the image processing A, and the image data subjected to the image processing A is transferred from the image processing unit 11 through the high-speed serial interface 4e, the switch 3, and the high-speed serial interface 4f. The image processing unit 12 is caused to transfer the image data to the processing unit 12 at a high speed, and the image processing unit 12 executes the image processing B. Further, the image data subjected to the image processing B is transferred from the image processing unit 12 to the high-speed serial interface 4f Image processing unit 1 via 4g Image data is continuously transferred to each of the image processing units 11, 12, and 13 so that the image processing unit 12 executes image processing C at high speed. Can do. Then, the image data finally processed by the image processing unit 13 is transferred to the printer 2 at high speed via the high-speed serial interface 4g, the switch 3, and the high-speed serial interface 4b. Can be printed on recording paper. In this case, in the illustrated example, the number of image processing units is three. However, the number of image processing units may be increased or decreased according to the required image processing contents. Even if the number of image processing units is increased or decreased, the switch in the PCI Express system 3 can be easily accommodated by the extensibility. For example, even when image processing A and C are image processing functions prepared from the beginning and image processing B is required as new image processing later, the image processing unit 12 is additionally connected to the switch 3. By configuring the system, it is possible to cope with high flexibility.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. (A) is a block diagram showing an existing PCI architecture, and (b) is a block diagram showing a PCI Express architecture. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is a time chart which shows the example of control of active state power management. It is a schematic block diagram which shows the structural example of the image system of one embodiment of this invention. It is a schematic block diagram which shows the example of the operating state / non-operating state. It is a schematic block diagram which shows the structural example of the image system of another embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Scanner 2 Printer 3 Switch 4 High-speed serial interface 5, 6 Image processing unit 11, 12, 13 Image processing unit

Claims (5)

A root complex connected to the processor and memory;
A switch having an upstream port connected to the root complex and first to fourth downstream ports connectable to a serial interface conforming to the PCI Express standard;
A first device connected to the first downstream port via the serial interface and capturing image data;
A first image processing unit connected to the second downstream port via the serial interface and having an image processing function;
A second image processing unit connected to the third downstream port via the serial interface and having an image processing function;
A second device connected to the fourth downstream port via the serial interface and printing based on image data;
The first downstream port of the switch is:
A port to which image data captured by the first device is input;
The second downstream port is
Image data generated by dividing the image data input via the first downstream port is output to the first image processing unit, and is subjected to image processing by the first image processing unit. Is a port to which the image data generated by
The third downstream port is
Image data generated by dividing the image data input via the first downstream port is output to the second image processing unit, and is subjected to image processing by the second image processing unit. Is a port to which the image data generated by
The fourth downstream port is
Image data generated by image processing by the first image processing unit input via the second downstream port, and the second input via the third downstream port An image system comprising: a port for outputting image data generated by combining image data generated by image processing by the image processing unit to the second device . When the image data captured by the first device is image data corresponding to relatively wide paper,
The second downstream port is
A port for outputting the image data generated by dividing the image data corresponding to the relatively wide paper to the first image processing unit;
The third downstream port is
2. The image system according to claim 1, wherein the image system is a port for outputting image data generated by dividing image data corresponding to the relatively wide paper to the second image processing unit . When the image data captured by the first device is image data having a relatively high resolution image density,
The second downstream port is
A port for outputting image data generated by dividing the image data having a relatively high resolution image density to the first image processing unit;
The third downstream port is
According to claim 1 or 2, wherein an image, characterized in that a port for outputting the image data generated by dividing the image data having the relatively high-resolution image density to the second image processing unit system. The second downstream port is
A port that outputs image data generated by dividing the image data captured by the first device in the main scanning direction to the first image processing unit;
The third downstream port is
4. A port for outputting image data generated by dividing image data captured by the first device in a main scanning direction to the second image processing unit . The image system according to any one of claims. A root complex connected to the processor and memory;
A switch having an upstream port connected to the root complex and first to fourth downstream ports connectable to a serial interface conforming to the PCI Express standard;
A first device connected to the first downstream port via the serial interface and capturing image data;
A first image processing unit connected to the second downstream port via the serial interface and having an image processing function;
A second image processing unit connected to the third downstream port via the serial interface and having an image processing function different from the image processing function of the first image processing unit;
A second device connected to the fourth downstream port via the serial interface and printing based on image data;
The first downstream port of the switch is:
A port to which image data captured by the first device is input;
The second downstream port is
The image data input via the first downstream port is output to the first image processing unit, and image data generated by image processing by the first image processing unit is input. Port
The third downstream port is
Image data generated by image processing by the first image processing unit input via the second downstream port is output to the second image processing unit, and the second image processing unit A port to which image data generated by image processing by the image processing unit is input,
The fourth downstream port is
The port is a port for outputting image data generated by image processing by the second image processing unit input via the third downstream port to the second device. Image system.

Images