JP2005332316A - Data distribution device, data transfer device and image processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To distribute mass data appropriately to each part and make data transfer faster. <P>SOLUTION: The device is equipped with an end point 21 with PCI Express standard for receiving the data transfer via a switch and a bus with the PCI Express standard. A buffer 22 buffers the data transferred via the switch and the bus of higher order. A distribution control circuit 23 performs control for distributing and transferring this transferred data to an output part as multiple output destinations of lower order. A route complex 24 and a switch 25 with the PCI Express standard performs the data transfer with control by the distribution control circuit 23. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data transfer apparatus that transfers data and an image processing apparatus that performs predetermined processing relating to image data.

  As a high-speed serial interface, an interface called PCI Express (registered trademark) corresponding to a successor standard of the PCI bus method has been proposed (for example, see Non-Patent Document 1).

“Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, in the PCI Express standard, the device configuration has a tree structure as described later, but a large amount of data is transmitted using a route through a root complex located at the root of the tree structure. In some cases, the data transfer speed cannot be increased.

  An object of the present invention is to appropriately distribute a large amount of data to each unit so as to increase the speed of data transfer.

  The present invention is connected to a higher-order switch for transferring data via a bus, buffers a buffer for data transferred through the switch and the bus, and distributes the transferred data to a plurality of lower-order output destinations. And a distribution control circuit that performs control to transfer the data.

  According to the present invention, even if a higher-level device such as a PCI Express standard root complex does not perform all data transfer processing, the data distribution device located in the lower level further controls the distribution of data to the lower level. Therefore, it is possible to appropriately distribute a large amount of data to each unit and to increase the data transfer speed.

  The best mode for carrying out the present invention will be described with reference to the drawings.

  In the following, details of PCI Express will be described in the columns [Outline of PCI Express Standard] to [Details of PCI Express Architecture], and then the [Image Processing Apparatus] column for the image processing apparatus of the present embodiment. I will explain it.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explain by excerpt. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. A tree structure in which a PCI-X bridge 105b to which PCI-X devices 104c and 104d are connected and a PCI bridge 107 to which a PCI bus slot 106 is connected are connected via a PCI-X bridge 105c ( Tree structure).

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. PCI Express 114b connects the switch 117a to which the PCI Express 114b is connected, and the PCI bridge 119 to which the switch 117b to which the endpoint 115b and the legacy endpoint 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, the graphics 125 is x16 with respect to the memory hub 124 (corresponding to the root complex) to which the CPU 121 is connected by the CPU host bus 122 and the memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a memory 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Furthermore, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c. The switch 134 is connected to the mobile dock 135, Gigabit Ethernet (Ethernet is a registered trademark) 136, and an add-in by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects components one-to-one (point-to-point). The transfer rate is, for example, one-way 2.5 Gbps (in the future, 5 Gbps or 10 Gbps is assumed). The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint basically does not request I / O port resources in the BAR (base address register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7 (a), the conventional PCI architecture has a structure in which protocols and signaling are closely related and has no concept of hierarchy. In PCI Express, as shown in FIG. 7 (b), Like general communication protocols and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration uses a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the crosspoint of the data signal. The clock is extracted.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting conventional access to PCI Express access is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (NEWCARD), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed in order to avoid overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (mechanism to check the buffer availability on the receiving side before starting data transfer and prevent overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that continuous “0” and “1” do not continue (in order not to maintain a state where a crosspoint does not exist for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power Management and Link State In order to keep the power consumption of the link low, a link state of L0 / L0s / L1 / L2 is defined as shown in FIG.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 15, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Image processing device]
FIG. 16 is a block diagram illustrating a schematic configuration of the image processing apparatus 1 according to the present embodiment. The image processing apparatus 1 executes predetermined processing relating to image data, in this example, reading of a document image, storing of the read image in a storage device, printing of the image data, and the like.

  The image processing apparatus 1 uses the data transfer apparatus of this embodiment for transferring image data. This data transfer device is connected to a root complex 11 and a switch 12 of the PCI Express standard connected by a PCI Express bus, and further connected to a lower level of the switch 12 by a PCI Express bus. The data distribution device 13 and the like.

  In addition to the data distribution device 13, the switch 12 includes an input unit 14 such as a scanner, a memory 15 used for temporary storage of image data, and image processing, compression, decompression, and data conversion processing (printer language) for the image data. PCI Express, a processing unit 16 that performs processing such as development, enlargement, and reduction), a storage unit 17 such as a hard disk that stores image data, a communication control unit that communicates with an external network, and the like. Connected by bus. In addition, the data distribution device 13 includes a plurality of output units 201, 202, 203,..., M, which are plotters for forming an image on a medium such as paper based on image data, on the PCI Express bus. It is connected. The switches 12 and lower are assumed to be xn links (n ≧ 1), and the data distributor 13 and lower are assumed to be x1 links.

  FIG. 17 is an explanatory diagram illustrating the configuration of the data distribution device 13. The data distribution device 13 is connected to the upper switch 12 via a PCI Express bus, and is connected to the upper route complex 11 and the PCI Express standard end point 21 receiving data transfer via the switch 12. A buffer 22 for buffering the transferred data; a distribution control circuit 23 having a CPU and temporarily storing the data transferred via the switch 12 in the buffer 22 to control data distribution; In accordance with the control of the distribution control circuit 23, the PCI Express standard route for distributing and transferring the image data to the output units 201, 202, 203,... And a complex 24 and a switch 25.

  The data distribution device 13 controls delivery of the image data transferred via the upper switch 12 to the lower output units 201, 202, 203,..., M under the control of the distribution control circuit 23. A specific example will be described.

(Specific example 1)
First, the output units 201, 202, 203,..., M are mixed so that different printing speeds are mixed. For example, the output unit 201 is a high-speed printing machine, the output unit 202 is a medium-speed printing machine, and the output unit 203 is a low-speed printing machine.

  The distribution control circuit 23 sets in advance how to distribute the image data to the output units 201, 202, 203,. This increases, for example, the priority of a printer with a high printing speed. Thus, even if data transmission is temporarily stopped because the buffer 22 is full, the waiting time for printing the image data can be reduced by automatically changing the output destination of the image data. it can. Furthermore, it is possible to increase the printing speed by giving priority to the one with a high printing speed.

(Specific example 2)
In addition, the output units 201, 202, 203,..., M may have different output image quality. For example, the output unit 201 is a normal image quality printing machine, the output unit 202 is also a normal image quality printing machine, and the output unit 203 is a high image quality printing machine. Here, the print speed is assumed to be higher in the order of the output unit 201, the output unit 202, and the output unit 203, for example.

  In this example, a large number of copies are output by each output unit 201, 202, 203,..., M depending on the purpose (high quality for distribution to customers, normal quality for general distribution). In this case, by providing the priority as in the first specific example, it is possible to perform print output according to the application at high speed.

(Specific example 3)
Furthermore, even when each of the output units 201, 202, 203,..., M is a medium to low-speed printing machine and has a similar printing speed, each of the output units 201, 202 is used when printing a large number of copies. , 203,..., M, as in the case of the specific example 1, it is possible to increase the overall print output speed even if a medium to low-speed printing machine is used.

  Next, the processing executed by the data distribution device 13 will be specifically described.

  In the case of the specific example 1, the output units 201, 202, and 203 are connected to the lower level of the data distribution device 13, and the print speed is higher in the order of the output units 201, 202, and 203 (the output unit 201 is the fastest). To do.

  In this example, a case where eight copies of two pages per copy are printed out will be described with reference to FIG. In FIG. 18, the timing for data transfer and plotting is displayed for each of the output units 201, 202, and 203. In the data transfer column of each of the output units 201, 202, and 203, data transfer is performed during the H level period, and waiting for transfer is performed during the L level period until printing is completed. Further, in the plot column of each output unit 201, 202, 203, the period during which the printing is performed is the H level period. Assume that each output unit 201, 202, 203 includes a buffer capable of storing image data corresponding to one page. In the data transfer column of each output unit 201, 202, 203, the data for one page is transferred to the buffer during the H level period, and the buffer is full, so the data transfer waits for the next L level period. . A buffer is secured during printing and released when printing is completed. Since the buffer is empty after release, data transfer is possible.

  Data distribution by the data distribution device 13 will be described. The numbers given in FIG. 18 are the order of the number of copies to be printed. Since there are two pages per copy, two same numbers are assigned. With the same number, the first one is the first page and the second one is the second page. The higher the print speed, the higher the priority. First, the process starts from the output unit 201 having the fastest printing speed. When the data transfer is completed in the output unit 201, the transfer is on standby, but the output unit 202 having the next highest priority is selected (distribution 1 in FIG. 18). When the data transfer of the output unit 202 is completed, the data transfer in the output unit 202 is on standby for transfer. Here, if there is an output unit with high transferable priority, it is newly selected. However, since the output unit 201 has not finished printing all pages per copy, data transfer and printing are continued. (Continuation 1 in FIG. 18). When the second data transfer of the output unit 201 is completed, the output unit 201 is in a transfer standby state. Here, the output unit 202 has the highest priority, but since the output unit 202 is waiting for transfer during printing, the output unit 203 is selected (distribution 2 in FIG. 18).

  The major processing procedure is as described above. However, when the number of copies is considered, the following processing flow is performed.

here,
t_sel: Print time per page in the output section selected at the time of distribution determination.
r_num: The remaining number of prints that must be printed for the set number of copies (total number of prints) at the time of distribution determination (see FIG. 19; the example of FIG. 19 is not related to FIG. 18). Note that the page being printed is not printed.
p_num: Number of pages per copy.
plot_sel: Output part selected at the time of distribution judgment.
sel_num: The total number of pages that can be printed in each output unit faster than plot_sel during the time when one copy of plot_sel is printed. If plot_sel is the fastest of all output parts, the number of pages per copy.
And

sel_num will be described. The print times per page of the output unit 201, the output unit 202, and the output unit 203 are t1, t2, and t3, respectively (see FIG. 18). Assume that the output unit selected at the time of distribution determination is the output unit 203.
Therefore, “t_sel = t3”.

  Since the output units faster than the output unit 203 are the output unit 201 and the output unit 202, the number of pages of the output unit 201 and the output unit 202 that can be printed at the time when the output unit 203 prints one copy is “(t_sel / t1) × p_num ”,“ (t_sel / t2) × p_num ”. Therefore, sel_num is “sel_num = (t_sel / t1) × p_num + (t_sel / t2) × p_num”.

  First, data transfer is started to the fastest output unit, and printing is performed using the fastest output unit. When the data transfer is completed, a distribution determination is performed. The distribution determination process will be described with reference to the flowchart of FIG.

  The CPU of the distribution control circuit 23 selects the fastest output unit among the output units 201 to 203 that are not currently printing (transfer standby). In the selected fastest output unit, printing of all pages per copy is not completed, so it is determined that there is no usable output unit (N in step S1). ). If printing of all pages per copy has been completed, or if no page has been printed yet, it is determined that there is an available output unit (Y in step S1). If all output units are printing, it is determined that there is no usable output unit (N in step S1). If there is no usable output unit (N in Step S1), data transfer and printing are continued until printing of all pages per copy is completed in the currently operating output unit (Step S2). If there is an available output unit (Y in step S1), the determination in step S3 is performed.

  In step S3, the total number of printable sheets in each output unit that is faster than the selected output unit is smaller than the number of remaining unprinted pages in the time for printing one copy in the selected output unit. (Y in step S3), it is determined to use the selected output unit (step S4). If not (N in step S3), data transfer and printing are continued in the currently operating output unit (step S5). That is, in step S3, it is determined whether or not the printing time as a whole does not become longer by printing with the selected output unit. This distribution determination is performed until the set number of copies is reached every time after the data transfer of each of the operating output units 201 to 203 is completed.

  Even if printing is not completed for the set number of copies, it is considered that the set number of copies has been reached at the start of data transfer for the first page of the last set number of copies (the tenth set if the number of set copies is 10). If the printing of all the pages per copy is completed in the fastest output unit among all, and if the printing is not completed for the set number of copies, the fastest output unit continues data transfer and printing ( Continuation 2 and continuation 3) in FIG.

  The above is an example in which data transfer is shown in units of one page, but the same applies even if data is transferred in units of one copy or in units of lines.

  Next, the trace example of FIG. 18 will be described with reference to FIG.

In the example of FIG.
1 copy 2 pages (p_num = 2), 8 copies print t2 = 2 × t1, t3 = 4 × t1
Sel_num when selecting the output unit 203 = 12 ((t3 / t1 + t3 / t2) × 2)
Sel_num when the output unit 202 is selected = 4 (t2 / t1 × 2)
Sel_num = 2 when the output unit 201 is selected
An example of the condition is shown.

The result of the distribution determination under this condition (some cases are not determined as distribution determination) is as follows. The following symbols A to L are as shown in FIG.
A: The available output unit is the output unit 202. From “r_num = 16> sel_num = 4”, the data is transferred to the output unit 202 and printed.
B: Although the output unit 201 is the fastest, there are no remaining output units because there are remaining pages per copy. Data transfer and printing are continued at the output unit currently in operation.
C: The output unit that can be used is the output unit 203. From “r_num = 15> sel_num = 12,” data is transferred to the output unit 203 and printed.
D: The available output unit is the output unit 201. From “r_num = 14> sel_num = 2”, the data is transferred to the output unit 201 and printed. Alternatively, since the number of copies is not set, the output unit 201 may determine that data transfer and printing are continued.
E: Although the output unit 202 is the fastest, there are no output units available because there are remaining pages per copy. Data transfer and printing are continued at the output unit currently in operation.
F: Although the output unit 201 is the fastest, there are no output units available because there are remaining pages per copy. Data transfer and printing are continued at the output unit currently in operation.
G: Since all output units are printing, there is no output unit available. Data transfer and printing are continued at the output unit currently in operation.
H: Not a distribution determination. Since the number of copies has not been reached, the output unit 201 continues data transfer and printing.
I: The output unit that can be used is the output unit 202. From “r_num = 10> sel_num = 4”, data is transferred to the output unit 202 and printed.
J: Although the output unit 201 is the fastest, there are no remaining output units because there are remaining pages per copy. Data transfer and printing are continued at the output unit currently in operation.
K: Although the output unit 203 is the fastest, there are no remaining output units because there are remaining pages per copy. Data transfer and printing are continued at the output unit currently in operation.
L: Not a distribution determination. Since the number of copies has not been reached, the output unit 201 continues data transfer and printing. Thereafter, since the number of copies reaches the set number, distribution determination is not performed thereafter.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. (A) is a block diagram showing an existing PCI architecture, and (b) is a block diagram showing a PCI Express architecture. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is explanatory drawing explaining the definition of the link state of L0 / L0s / L1 / L2. It is a time chart which shows the example of control of active state power management. It is a block diagram explaining the structure of the image processing apparatus of this Embodiment. It is a block diagram explaining the structure of the data distribution apparatus of this Embodiment. It is a timing chart explaining distribution of data by a data distribution device. It is explanatory drawing explaining the example of which output part prints a setting number of copies. It is a flowchart explaining the process of distribution determination. It is a timing chart explaining the example of a trace in the case of FIG.

Explanation of symbols

1 Image Processing Device 12 Switch 13 Data Distribution Device 21 Endpoint 22 Buffer 23 Distribution Control Circuit 24 Route Complex 25 Switch

Claims (4)

It is connected by a bus to the upper switch that transfers data,
A buffer for buffering data transferred via the switch and bus;
A distribution control circuit for performing control to distribute and transfer the transferred data to a plurality of lower output destinations;
A data distribution device comprising: PCI Express standard endpoint that receives data transfer via the PCI Express standard switch and bus,
A PCI Express standard route complex and switch for transferring the data under the control of the distribution control circuit;
The data distribution device according to claim 1, further comprising: PCI Express standard bus, route complex and switch for transferring data,
The data distribution device according to claim 2, wherein the data distribution device is connected to a lower level of the switch via the bus.
A data transfer device comprising: Perform predetermined processing on image data,
The data transfer device according to claim 3 for transferring image data.
Image processing device.

Images