JP4603335B2 - Data transfer system, image forming system, and data transfer method - Google Patents

Description

  The present invention relates to a data transfer system, and more particularly to an image forming system such as a multifunction peripheral (MFP) that handles various image data and performs various processes, and a data transfer method.

  Generally, in a device / system that handles image data and other data, a PCI bus is used as an interface between devices. However, the parallel PCI bus has problems such as racing and skew, and the transfer rate has been low for use in high-speed and high-quality image equipment. The use of a high-speed serial interface is being considered in place of the system interface. Conventionally, there are standards such as IEEE1394 and USB as a widely used serial interface, but there are problems such as insufficient transfer rate and difficulty in securing a scalable bus width compared to PCI. . For this reason, the use of an interface called PCI Express (registered trademark) corresponding to a successor standard of the PCI bus system is being studied as another high-speed serial interface.

  Although details will be described later, this PCI Express system is schematically configured as a data communication network having a tree structure (tree structure) as shown in FIG.

  An example thereof is simplified and shown in FIG. That is, the PCI Express system 200 sets a plurality of end nodes (end points) A, B, C, D,... Via the switches SW1, SW2, SW3,. Connected to a tree structure. Here, each of the switches SW1, SW2, SW3,... Has one upstream port (route node side) and a plurality of downstream ports (end node side), and other than the switches SW1, SW2, SW3,. Each of the devices A, B, C, D,... Has only one port, and the communication path between each device is uniquely determined by a tree structure.

  The connection lines between nodes and switches are connected in advance according to the speed required for data transfer. At this time, each connection line has a different performance (for example, a bus width). The number of lanes shown is x8, x4.x2, etc.). Further, the switches SW1, SW2, SW3,... Can adjust the transfer speed when a plurality of data transfers are processed in parallel (when contention occurs) by setting priority to each port. it can.

“Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, when such a PCI Express system is simply used, the communication path is fixed, so when multiple independent data transfers are processed in parallel, contention of the data transfer path occurs and transfer efficiency decreases. There is an inconvenience.

  For example, in the example shown in FIG. 28, when two types of data transfer are to be processed simultaneously on the route 202 from the root node 201 to the end node A and the route 203 from the end node C to the end node B. As shown in an enlarged view in FIG. 28, the downstream port competes with the switch SW2 in the switch SW1. Therefore, when the packet of the route 202 and the packet of the route 203 are alternately output, the transfer rate is reduced to half and the transfer efficiency is lowered. In addition, it is possible to give priority to one path 202 or 203 by arbitration of the switch SW1, but the transfer efficiency of the other path 203 or 202 is further reduced.

  In order to prevent the competition shown in FIG. 28 from occurring, for example, as shown in FIG. 29, the connections of the end nodes A, B, C, and D to the switches SW2 and SW2 may be changed in advance. In another parallel processing operation, when the processing of the route 202 and the processing of the route 204 from the end node C to the end node D have to be processed at the same time, a conflict similar to the case of FIG. The rate will drop and it will not be an essential improvement.

  Such a decrease in the data transfer rate is the same not only when the data transfer path competes but also in the case of a data transfer path that passes through more switches than necessary.

  An object of the present invention is to improve data transfer efficiency by avoiding data transfer path contention when a plurality of independent data transfers are processed in parallel or a data transfer path that passes through more than necessary switches. It is.

Invention of claim 1, wherein a communication channel transmission received independently by a data communications network according to a tree structure is established Lud over data transfer system, the first endpoint before Symbol tree structure located on the upstream side A first port that can communicate with the first switch and a second port that can communicate with the second switch located upstream, and the second endpoint in the tree structure is located upstream having said first switch and said second switch capable of communicating with a fourth port located on the third port capable of communicating and upstream, the first endpoint in accordance with the operating mode having a first port selection means for selecting either one of the ports of the first port or the second port, the second endpoint, in response to said operation mode first 3 points DOO or a second port selection means for selecting either one port of said fourth port.

The invention according to claim 2 is the data transfer system according to claim 1, wherein the data transfer system is a PCI Express system.

According to a third aspect of the invention, in claim 1 or 2, wherein the data transfer system, said first port selecting means and said second port selecting means, port selection Lupolen over preparative select at reset link Update means having a memory for storing information in a rewritable manner, wherein the first endpoint and the second endpoint rewrite and update the port selection information on the memory upon reception of a message packet including port selection information The computer that manages the data transfer system has the first endpoint and the second endpoint in accordance with the port selection information specified on the memory by default when the data transfer system is activated. said first end with Ipoh over preparative obtains a tree structure of the initial state to link up in a state of being selected And initializing means for identifying and Into and the second said by the configuration for the endpoint of the first endpoint and the second endpoint device features and the required data transfer performance, required a specific devices function a data transfer performance and reference determining means for determining a port of the first endpoint and the second endpoint of the optimum in accordance with the operation mode of the data transfer system of a port selection determined A notification means for notifying the update means of the first endpoint and the second endpoint of the message packet including the information and rewriting and updating the port selection information on the memory; and the data after the notification ports specified by resetting the transfer system rewrite updated on the memory Includes a relink up means to relink up in a state in which port was chosen in the first endpoint and the second endpoint of the according-option information, the operation after re linkup of the data transfer system Data transfer is started according to the mode.

The invention of claim 4, wherein, in the data transfer system according to claim 3, wherein the determination unit, when the operating mode for processing in parallel a plurality of independent data transfers in the data transfer system, the first switch or to compete in the data transfer path through the second switch does not occur, one port and said second port selecting means, wherein the first port selecting means select and use the selection One port to be used is determined.

According to a fifth aspect of the invention, according to claim 3 or 4, wherein the data transfer system, said determining means, as stages through to absence switch is minimum, the first port selecting means selects one port and the second port selecting means to be used to determine one of the ports to select and use.

An image forming system according to a sixth aspect of the present invention is the data transfer system according to any one of the first to fifth aspects, wherein the first endpoint and the second endpoint are devices involved in image formation. .

The invention of claim 7, wherein is established a communication channel for sending and receiving independently as a data communications network according to a tree structure, capable of communicating with the first switch first endpoint before Symbol tree structure is located on the upstream side And a second port capable of communicating with a second switch located upstream and a second endpoint in the tree structure capable of communicating with the first switch located upstream. a such third port and the data transfer method utilizing a data transfer system having a second switch and the fourth port capable of communicating located upstream, the first endpoint is operating mode It said first port or select one of the ports of said second port, the second endpoint, the third port in response to the operation mode in accordance with the Other selects any one port of said fourth port.

The invention according to claim 8 is the data transfer method according to claim 7, wherein the data transfer system is a PCI Express system.

The invention according to claim 9 is the data transfer method according to claim 7 or 8, wherein the first endpoint is in an operation mode in which a plurality of independent data transfers are processed in parallel in the data transfer system. and the like wherein the second endpoint of the first switch or conflicting data transfer path through the second switch does not occur, one port of the first endpoint is selected and used And the second endpoint selects and uses one port .

The invention of claim 10, wherein, in the data transfer method according to claim 7, 8 or 9, wherein, as the number of stages through to absence switch is minimized, one of the first endpoint is selected and used port and the second endpoint of was made to determine a single port to be selected and used.

According to the present invention, causes no upper stream side first first capable of communicating with the switch ports and the upstream second switch and a second port capable of communicating in the first endpoint, the The second endpoint has a third port that can communicate with the upstream first switch and a fourth port that can communicate with the upstream second switch, and the first endpoint according to the operation mode. There by one port and the second endpoint to be used to select one of the ports to be used, it is possible to dynamically change the tree structure, therefore, in parallel a plurality of independent data transfers Even if processing is performed, it is possible to avoid data transfer path contention by securing an independent data transfer path, or to avoid data transfer paths that pass through more stages than necessary, thereby improving data transfer efficiency. Rukoto can.

  The best mode for carrying out the present invention will be described with reference to the drawings.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. The switch 117a connected by the PCI Express 114b is connected by the PCI Express 114c, and the PCI bridge 119 to which the switch 117b to which the end point 115b and the legacy end point 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected is a PCI. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Furthermore, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c. The switch 134 is connected to the mobile dock 135, Gigabit Ethernet (Ethernet is a registered trademark) 136, and an add-in by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects components one-to-one (point-to-point). The transfer rate is, for example, 2.5 Gbps in one direction. The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint basically does not request I / O port resources in the BAR (base address register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 117
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and has no concept of hierarchy. In PCI Express, as shown in FIG. 7B, Like general communication protocols and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration uses a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the crosspoint of the data signal. The clock is extracted.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting the conventional access to the access by PCI Express is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (Express Cards), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed to avoid the overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (a mechanism that confirms the buffer availability on the receiving side before starting data transfer and prevents overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power management and link state As shown in Table 1, a link state of L0 / L0s / L1 / L2 is defined in order to keep the power consumption of the link low.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 14, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Data transfer system; Image forming system]
The data transfer system according to the present embodiment uses the above-described PCI Express system, particularly with the tree structure added with expansion and improvement.

  FIG. 15 is a principle schematic diagram showing an example of a tree structure in the data transfer system of the present embodiment. According to the specification of the PCI Express system described above, there is only one upstream port of the endpoint, but in this embodiment, each endpoint A, B, C,... Has a plurality of upstream points. In addition, each end point A, B, C,... Has a port selector (port selection means) 1A, 1B, 1C,... For selecting one upstream port to be used according to the operation mode of the data transfer system. It is what I did.

  Therefore, in the tree structure of the data transfer system according to the present embodiment, a plurality of endpoints A, B, C,... Are routed via a plurality of switches 3A, 3B, 3C with the root complex 2 managing the whole as a vertex. Although each of the end points A, B, and C has a plurality of upstream ports, the data transfer path is connected to the switches 3A, 3B, and 3C in the end point A, for example. The endpoint B has a data transfer path connected to the switches 3A, 3B, 3C, and the endpoint C has a data transfer path connected to the switches 3A, 3B, 3C. . From the switch side, the switch 3A has a data transfer path connected to the end points A, B, and C, and the switch 3B has a data transfer path connected to the end points A, B, and C, and the switch 3C Has data transfer paths connected to endpoints A, B, and C.

  Further, in the present embodiment, for example, the switch 3A is linked to both the upstream side (route complex side) and the downstream side (endpoint side) in order to make the data transfer width different for each of the switches 3A, 3B, 3C. X8 is used for large volume data transfer, the switch 3B has a link x4 on the upstream side and the downstream side, and the switch 3C has a link x1 on the upstream side and the downstream side, and an appropriate data width according to the type of data It is set so that data transfer can be selected. However, if there is a margin in cost, all bus widths may be set to x8, for example.

  In such a configuration, the port selector 1 is used so that no conflict occurs in the data transfer path passing through the switch 3 in the operation mode in which a plurality of independent data transfers are processed in parallel in the data transfer system. Select one upstream port. For example, when a large amount of data transfer is required between the endpoint A and the endpoint B and at the same time data transfer is required between the route complex 2 and the endpoint 3C, the port selectors 1A, 1B , B as an upstream port, as shown by a solid line, one upstream port is selected so that the path of the x8 link to the switch 3A is valid, and the port selector 1C is shown as a solid line as an upstream port of the endpoint C One upstream port is selected so that the route of the x4 link to the switch 3B is valid. As a result, the x4 path 4 between the end points A and B is secured, and the x4 path 5 of the route complex 2-switch 3B-endpoint C is secured. Therefore, a large amount of data can be transferred between the end points A and B by the x8 link, and at the same time, between the route complex 2 and the end point C, the data transfer between the end points A and B is not disturbed, and the x4 link. Can be used to transfer data fully.

  By selecting one upstream port to be used in accordance with the operation mode in this way, the tree structure can be dynamically changed. Therefore, even when a plurality of independent data transfers are processed in parallel, independent tree transfer is possible. By securing the data transfer path, data transfer path contention can be avoided and data transfer efficiency can be improved.

  A preferred example of the data transfer system as in this embodiment is an image forming system as shown in FIG. The image forming system is an image forming device, and corresponds to the above-described endpoints A, B, and C. The scanner engine unit 11 (input unit), the printer engine unit 12 (output unit), and the facsimile unit 13 (MFP) configuration including a (communication unit). Reference numeral 14 denotes a controller corresponding to the root complex, which includes a switch 15 for the switches 3A, 3B, and 3C, and is connected to a CPU 16 and a memory 17 as a computer in the system.

  In such a configuration, for example, in the case where data transfer processing for high-speed copy operation and data transfer processing for facsimile reception are performed simultaneously in parallel, as shown in FIG. And the upstream port of the printer engine unit 12 is selected so that the x8 port of the switch 3A is valid, and the upstream port of the facsimile unit 13 is selected so that the x4 port of the switch 3B is valid. ), By using the paths 4 and 5 as indicated by the solid line, the facsimile unit 13 and the controller 14 are connected between the scanner engine unit 11 and the printer engine unit 12 while performing high-speed copying on the x4 link path 4. Facsimile reception data can be stored in the memory 17 by using the route 5 of the x4 link with the memory 17 via the interface.

  On the other hand, for example, in the case where the printing operation of the facsimile reception data and the storage (reserved copy) operation of the high-speed scanning data in the memory are performed simultaneously in parallel, as shown in FIG. 16 is selected so that the x3 link of the switch 3A is valid, and the upstream ports of the print engine unit 12 and the facsimile unit 13 are selected so that the x4 link of the switch 3B is valid. (B) By using the paths 6 and 7 as indicated by the solid line in the figure, the high speed scanning data by the scanner engine unit 11 is transferred to the memory 17 while the facsimile reception data is being printed by the print engine unit 12. Can be stored for reserved copy.

[Specific configuration example]
By the way, a more specific configuration example of the endpoint for realizing the operation as described above, an operation control example by the CPU 16 as a computer managing the system, and the like will be described.

  FIG. 17 is a schematic block diagram illustrating a configuration example of each endpoint 21. Each end point 21 has a plurality of ports 22A to 22C as indicated by ports 1 to 3 as a plurality of upstream ports individually connected one-to-one with a plurality of switches (SW1 to SW3) existing upstream. It has. On the downstream side of these ports 22A to 22C, corresponding to the above-described port selector 1, a port selection to be connected to any of the ports 22A to 22C of the end point 21 by switching the communication path with the physical layer 24 A port selector 23 is provided as a means. On the downstream side of the port selector 23, in addition to the physical layer 24 and the endpoint logical layer circuit 25 described above, a PIPE interface 26 conforming to a de facto interface standard for connecting the physical layer 24 and the endpoint logical layer circuit 25 is provided. A PCI Express core 27 is provided. A user circuit 28 for specifying a function for each end point 21 is connected to the downstream side of the PCI Express core 27. The user circuit 28 receives the PCI Express standard packet to control the function of each application (scanner, plotter, network card, etc.).

  Here, the port selector 23 has a memory 29 that rewritably stores the port number (port selection information) of the upstream port that is selected when the link is reset. The memory 29 stores an arbitrary port number selected by the port selector 23 in the initial state. In the port selector 23, the port number (port selection information) input from the external control circuit 30 is stored in the memory 29. When the link is next reset, it is stored in the memory 29 at that time. The ports 22A to 22C having the same port number are selected. On the other hand, at the end point 21, the user circuit 28 has a control circuit 30 that receives a message packet and notifies when the message packet includes a port number (port selection information). The control circuit 30 receives the notification. It functions as an update means for outputting the port number of the message packet to the memory 29 to rewrite and update it.

  FIG. 18 to FIG. 23 show the processing procedure of the dynamic change of the tree structure of the system, which is executed by the CPU 16 that controls the operation of the entire system by a program and each endpoint 21 under the configuration of the endpoint 21. The description will be given with reference. 18 to 21 are principle schematic diagrams showing examples of tree structures at different stages, FIG. 22 is a schematic flowchart of an example of operation control executed by the CPU 16, and FIG. 23 is an example of operation at each of the endpoints 21A to 21D. It is a schematic flowchart which shows. Here, the system configuration example includes three switches 3A to 3C, four end points 21A to 21D, and two ports 22A and 22B each. This procedure is roughly divided into an initialization procedure and a route optimization procedure.

  First, when the system is activated, the endpoints 21A to 21D are linked up in a state where the ports designated by the port numbers stored in the memory 29 by default are selected by the port selectors 23A to 23D. That is, in each of the end points 21A to 21D, as shown in FIG. 23, when link reset is detected (step S11), by referring to the port number stored in the memory 29 (S12), the port selector 23 Selects an upstream port (S13) and links up (S14). The CPU 16 searches the switches 3A to 3C and the respective endpoints 21A to 21D downstream of the controller (root complex) 14 at the time of such a link up (steps S1 and S2), and thereby the initial tree structure. (Tree structure) is acquired and held in a table or the like in the memory 17 (S3). At this time, each of the switches 3A to 3C and each of the end points 21A to 21D is given a unique vendor ID and device ID determined by the standard, and the above-described configuration register (not shown) defined by the PCI Express standard. Z). Therefore, the CPU 16 obtains the vendor ID and device ID by performing configuration read access to each of the switches 3A to 3C and the end points 21A to 21D, and specifies the device function and the necessary data transfer performance (note that Information regarding the vendor ID, device ID, function, and performance is included in the memory 17 connected to the program or the controller (root complex) 14 in advance). Such processing in steps S1 to S3 is executed by the CPU 17 as a function of initialization means.

  FIG. 18 is a principle schematic diagram showing an example of a tree structure in which the link is up when the system is activated. That is, in the initial setting, it is assumed that the port number is stored in the memory 29 so that the port 22A is selected for the endpoints 21A and 21B and the port 22B is selected for the endpoints 21C and 21D. The tree structure and the IDs (functions and performance information) of the end points 21A to 21D when linked up are held in the memory 17.

  After completion of such an initialization procedure, the CPU 16 selects a system operation mode, and according to the system operation, for example, calculates a data communication path that does not cause competition in the output ports of the switches 3A to 3C by a program. A process is performed in which the optimum port number specified by the process and selected by the port selector 23 in each of the endpoints 21A to 21D is determined as the port selection information. That is, it is possible to avoid contention on the data transfer path when executing the operation mode of the system while referring to the device function specified by the initialization procedure and the required data transfer performance. Thus, it is determined whether or not the number of switches can be reduced (S5). If not, the data transfer path is already optimized and the data transfer process is executed as it is (S6). If this is the case (Y in S5), the optimum upstream port of each of the endpoints 21A to 21D is determined according to the operation mode, and the port number (port) of the endpoint control circuit 30 that needs to be changed is determined. A message bucket including selection information is transmitted (S7). The processes of Y and S7 in these steps S4 and S5 are executed as functions of a determination unit and a notification unit.

  FIG. 19 is a principle schematic diagram showing an example of an operation mode in which port contention occurs in the switch in the initial setting state. For example, an operation mode example in which data is transferred from the end point 21C to the end point 21B while performing data communication from the memory 17 to the end point 21A is shown. In this case, the switch of the switch 3A is kept in the initial setting state. Contention occurs at the output port to 3B (corresponding to the case described in FIG. 28). In such a case, for example, by switching the port of the end point 21C to the port 22A connected to the switch 3B instead of the port 22B, contention of the data transfer path can be avoided. Therefore, the CPU 16 determines the port 22A as the optimum upstream port of the end point 21C in such an operation mode. Then, the CPU 16 transmits a message packet including port selection information of port number = port 22A to the endpoint 21C to be changed before actually executing data transfer.

  At this time, when each of the endpoints 21A to 21D receives a message packet (S15), it determines whether or not the message packet includes a port number (port selection information) (S16), and determines a port number (port selection). Information) is not included (N in S16), normal packet reception processing is performed (S17). If a port number (port selection information) is included (Y in S16), the control circuit 30 The port number (port selection information) is notified (S18), and the control circuit 30 notifies the port selector 23 of the target endpoint 21C of the information of port number = port 22A connected to the switch 3B (for example, S19), the memory 29 is rewritten and updated with the port number = port 22A (S20).

  After the notification of the port number that needs to be changed (S7), the CPU 16 resets the PCI Express link on the system, and according to the port number (port selection information) designated on the rewritten and updated memory 29, each of the endpoints 21A to 21A. Relink up is performed with the upstream port 22A or 22B of 21D selected (S8). The process of step S8 is executed as a function of the relink-up means. That is, in each of the end points 21A to 21D, as shown in FIG. 23, when a link reset is detected (S11), by referring to the port number stored in the memory 29 (S12), the port selector 23 The upstream port is selected (S13), and the link is up (S14). In the case of this example, the link is made up in a state in which the port selected by the end point 21C is switched to the port 22A connected to the switch 3B specified by the message packet. FIG. 20 is a principle schematic diagram showing an example of a tree structure in a state where re-linking is performed before actual data transfer.

  The CPU 16 searches for the switches 3A to 3C and the end points 21A to 21D downstream of the controller (root complex) 14 at the time of such link-up as in the system startup (steps S1 and S2). The tree structure (tree structure) in the initial state is acquired and held in a table in the memory 17 (S3). Then, the CPU 16 updates the information related to the vendor ID, device ID, function, and performance by making configuration read access to each device again. Thereafter, actual data transfer is started (S6).

  FIG. 21 is a schematic diagram showing the principle of an operation mode example under a relinked tree structure. According to the configuration example shown in FIG. 21, since there is no contention in the output port of the switch 3A in this operation mode, the data transfer of the memory 17-switch 3A, 3B-end point 21A and the end point 21C-switch 3B- The data transfer as the end point 21B can be performed at high speed.

  In the above description, the port determination example is such that the end point 21C is switched from the port 22B side to the port 22A side, but the end point 21B is the port determination that is switched from the port 22A side to the port 22B side. Even if data is transferred through a route of 21C-switch 3C-end point 21B, it is equivalent.

  In the description with reference to FIGS. 18 to 21, the CPU 16 determines the upstream port of the endpoint to be selected so as not to cause the competition of the output ports of the switch, but step S <b> 5 in FIG. 22 is described. As shown in the figure, the upstream port of the endpoint to be selected may be determined so that the number of switches passing through (the number of switches through which the switch passes) is minimized.

  This point will be described with reference to FIGS. 24 and 25. FIG. FIG. 24 is a schematic diagram showing the principle of a tree structure example in a state where the link is made up when the system is started, as in FIG. In the connection state at the time of starting the system, as an operation mode, for example, when data communication is performed from the end point 21A to the end point 21D, the switch 3B → the switch 3A → the switch 3C is passed, and the three stages. Packet transfer via this switch is required, resulting in a large delay. In such a case, as shown in FIG. 25, the CPU 16 determines that the upstream port to be selected by the end point 21A is the port 22B instead of the port 22A, whereby the end point 21A → the switch 3C → the end point. The data transfer through the route 21D, that is, the route through the single-stage switch of only the switch 3C, reduces the delay time required for packet transfer to 1/3 compared to the data transfer route shown in FIG. it can.

  Also in this case, the port to be selected on the end point 21D side may be determined to be on the port 22A side.

[Discussion about effects]
First, consider the effect of switch output port contention. When a conflict occurs in the output port in the PCI Express switch, the data transfer rate is lowered. In FIG. 26, under the condition that there is one output port for four input ports in the PCI Express switch, four different types of traffic are started at the same time, and data transfer is completed in order according to the transfer rate. It is the graph which showed the characteristic in the case of going. In the figure, the horizontal axis represents the transfer time, the vertical axis represents the data transfer amount (integrated value) of each port, and the slope of each graph represents the transfer rate. It should be noted that the payload size (meaning the size of the data portion other than the header information out of the total packet data size) is a measurement example under the condition that all four types are fixed to 64 bytes. The data transfer algorithm is a weighted round robin (WRR) in the PCI Express standard, and shows an example of characteristics when data transfer is set at a ratio of 1: 2: 4: 8 for four types. When the data transfer of one traffic class is completed, the algorithm is to transfer data while changing the ratio, such as 8: 4: 2 and further 8: 4 for the remaining traffic classes.

  In FIG. 26, it can be seen that, from the left side, four transfers are in conflict, three transfers are in conflict, two transfers are in conflict, and there is no conflict. Here, it can be seen that as the number of competing traffics decreases, the slope of each graph, that is, the transfer rate becomes steep, and the data transfer rate improves. In this regard, according to the present embodiment as described above, since the ports to be selected are determined so that the upstream ports of the endpoints 21A to 21D do not compete with the output ports of the switches, the data It can be seen that the transfer rate can be improved.

  Next, consider the effect of the number of switch stages. When data is divided and transferred by a certain amount (for example, when image data is transferred to a plotter in the image forming system by dividing it into one line in the main scanning direction), the packet data is transmitted from the transmission source to the transmission destination. The influence of the initial delay that reaches the point becomes larger with the number of switch stages through which it passes.

  FIG. 27 is a graph showing the relationship between the payload size and the transfer rate using the number of switches (number of stages) passed in the data transfer path as a parameter, and the effect of the number of switches (number of stages) passed on the transfer rate. I understand. In the figure, in order from the top, there is no timing constraint, the switch has one stage, the delay structures 1, 2, 3, the switch has two stages, the delay structures 1, 2, 3, the switch has three stages, and the delay structures 1, 2, 3, The case where there are four stages of delay structures 1, 2, 3 and five switches of delay structures 1, 2, 3 is shown. Each time the number of switches passing through increases by one, the packet transfer delay time is added. The larger the packet data size, the greater the delay. For this reason, it can be seen that when there are a plurality of stages of switches on the data transfer path, the data transfer rate decreases as the size of data transmitted in one packet increases. In this regard, according to the present embodiment as described above, the ports to be selected are determined so as to minimize the number of stages of the switch 3 through which the upstream ports of the end points 21A to 21D pass. It can be seen that a decrease in data transfer rate can be suppressed.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. (A) is a block diagram showing an existing PCI architecture, and (b) is a block diagram showing a PCI Express architecture. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is a time chart which shows the example of control of active state power management. It is a principle schematic diagram which shows the example of a tree structure in the data transfer system of this Embodiment. It is a principle schematic diagram showing a specific example in the case of an image forming system. It is a schematic block diagram which shows the structural example of each endpoint. It is a principle schematic diagram which shows the example of a tree structure of the state linked up at the time of system starting. It is a principle schematic diagram showing an example of an operation mode in which port contention occurs in the switch in the initial setting state. It is a principle schematic diagram which shows the example of a tree structure of the state re-linked up before actual data transfer. It is a principle schematic diagram which shows the example of an operation mode under the tree structure re-linked up. It is a schematic flowchart of the example of operation control performed by CPU. It is a schematic flowchart which shows the operation example in each endpoint. It is a principle schematic diagram which shows the example of a tree structure of the state linked up at the time of system starting. It is a principle schematic diagram which shows the example of an operation mode under the tree structure re-linked up. 4 is a graph showing characteristics when four different types of traffic are simultaneously started in a PCI Express switch, and data transfer is sequentially terminated according to the transfer rate. 6 is a graph showing the relationship between the payload size and the transfer rate, with the number of switches (number of stages) passing through the data transfer path as a parameter. It is a principle schematic diagram which shows the example of a tree structure by the normal usage form of PCI Express. It is a principle schematic diagram which shows the modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Port selection means 2A-2C Switch 11-13 Device 21 End point 22 Upstream port 23 Port selection means 29 Memory 30 Update means A-C Endpoint

Claims (10)

A communication channel transmission received independently by a data communications network according to a tree structure is established Lud over data transfer system,
With the first endpoint before Symbol tree having a first switch and a second port capable of communicating with a second switch located on the first port and the upstream communicable positioned upstream, The second end point in the tree structure has a third port that can communicate with the first switch located on the upstream side and a fourth port that can communicate with the second switch located on the upstream side. ,
The first endpoint has a first port selection means for selecting either one of the ports of the first port or the second port in response to the operating mode, the The second endpoint has second port selection means for selecting any one of the third port and the fourth port according to an operation mode .
A data transfer system characterized by that. The data transfer system according to claim 1, wherein the data transfer system is a PCI Express system. It said first port selecting means and the second port selection unit has a memory for rewritably storing port selection information Lupolen over preparative select at reset link,
The first endpoint and the second endpoint have update means for rewriting and updating the port selection information on the memory by receiving a message packet including port selection information,
Computer, the data transfer system when starting the first endpoint and the second slave endpoints to port selection information specified on the memory by default Ipoh over you want to manage the data transfer system Link up to obtain an initial state tree structure, and configure the first endpoint and the second endpoint according to the configuration for the first endpoint and the second endpoint . The first end which is optimized according to the operation mode of the data transfer system with reference to the specified device function and the required data transfer performance with reference to the specified device function and the required data transfer performance. a point and determining means for determining a port of the second endpoint is determined A notification unit which notifies the updating unit of the first endpoint and the second endpoint of the target message packet is rewritten updated port selection information on said memory including a port selection information, after the notification re relink up in a state in which port of the data transfer system reset rewriting the accordance port selection information specified in the updated on the memory first endpoint and the second endpoint is selected Link-up means,
And so as to start data transfer in accordance with the operation mode after re linkup of the data transfer system, data transfer system according to claim 1 or 2, wherein the. In the operation mode in which a plurality of independent data transfers are processed in parallel in the data transfer system, the determination unit does not cause a conflict in the data transfer path passing through the first switch or the second switch. claim way, to determine a single port in which one port and said second port selecting means, wherein the first port selecting means selects and uses is selected and used, it is characterized by 3. The data transfer system according to 3 . It said determination means, as the number of stages through to absence switch is minimized, one port and said second port selecting means, wherein the first port selecting means selects and uses the selected data transfer system according to claim 3 or 4, wherein determining one of the ports to be used, it is characterized. 6. The data transfer system according to claim 1, wherein the first endpoint and the second endpoint are devices involved in image formation. Communication channel transmission received independently by a data communications network according to a tree structure is established, prior Symbol first switch and the first port and the upstream communicable to the first endpoint is located upstream in the tree structure A second port communicable with the second switch located at the second side, and a third port and upstream side capable of communicating with the first switch located at the upstream side of the second end point in the tree structure A data transfer method using a data transfer system having a fourth port capable of communicating with the second switch located in
The first endpoint, in response to the operating mode select one of the ports of the first port or the second port, the second endpoint, the operating mode Selecting one of the third port and the fourth port according to
A data transfer method characterized by the above. The data transfer method according to claim 7, wherein the data transfer system is a PCI Express system. In the case of the operation mode for processing in parallel a plurality of independent data transfers in the data transfer system, the first switch or the second switch in the first endpoint and the second endpoint of the through so that the data transfer path to the conflict does not occur, so as to determine a single port in which one port and the second endpoint of the first endpoint is selected and used to select and use 9. The data transfer method according to claim 7, wherein the data transfer method is performed. As the number of stages through to absence switch is minimized, determining one of the ports one port and the second endpoint of the first endpoint is selected and used to select and use 10. The data transfer method according to claim 7, 8 or 9, wherein the data transfer method is performed.

Images