JP2007241882A - Data communication device, and image forming system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data communication device and an image forming system, capable of specifying a priority order among a plurality of pieces of target packet data, using a virtual channel required to the minimum, and transmitting necessary information at the time of necessity. <P>SOLUTION: The virtual channel is assigned based on the traffic nature of each of a plurality of issued packet data, and the priority order of each virtual channel to which the packet data is assigned is specified. Thus, the priority order among the plurality of pieces of target packet data can be specified using the virtual channel required to the minimum, and necessary information can be transmitted at the time of necessity. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data communication apparatus and an image forming system.

  In general, in an information processing apparatus such as a digital copying machine or a multifunction peripheral (MFP) that handles image data and other data, a PCI bus is used as an interface between devices. However, the parallel PCI bus has problems such as racing and skew, and the transfer rate has been low for use in high-speed and high-quality image forming apparatuses. The use of a high-speed serial interface such as IEEE1394 or USB is being considered in place of the parallel interface. For example, according to Patent Document 1, it is proposed to use a high-speed serial interface such as IEEE1394 or USB as an internal interface.

  As a method of separately transferring image data and command data on such a high-speed serial interface, there is a method of using an isochronous transfer mode and an asynchronous transfer mode defined by the IEEE1394 standard or the USB standard.

  However, in the method of separating traffic using the isochronous transfer mode and the asynchronous transfer mode, it is difficult to set the priority order between the image data when there are a plurality of image data.

  As another high-speed serial interface, an interface called PCI Express (registered trademark), which is a successor to the PCI bus system, has been proposed and has been put to practical use (for example, see Non-Patent Document 1). This PCI Express system is schematically configured as a data communication network having a tree structure (tree structure) such as a root complex-switch (arbitrary hierarchy) -device as shown in FIG. Has been.

  According to the PCI Express standard, a virtual channel function that transmits packet data of multiple traffic by using a serial bus in a time-sharing manner in units of virtual channels (Virtual Channel) and priority to issue packet data for each virtual channel It has an arbitration function that adjusts the speed, and when it is desired to simultaneously transfer packet data of a plurality of traffics having different data transfer priorities using a serial bus, the transfer rate can be adjusted.

  More specifically, in the arbitration algorithm of the virtual channel of the PCI Express standard, a round robin (Round Robin) method for issuing packet data at an equal frequency for each virtual channel VC, a table that can be arbitrarily designated for each virtual channel VC There are weighted round robin (Weighted Round robin) method that issues packet data at a weighted frequency according to the standard, and strict method that issues packet data in a fixed priority order for each virtual channel VC. It is possible to adjust the priority of the packet transferred to the transaction in units of transactions.

JP 2001-016382 A “Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, even when virtual channels prepared in the PCI Express standard are used, if virtual channels are allocated without considering the nature of generated traffic (for example, directionality and transfer rate), many virtual channels are used. There is a problem that is necessary.

  The present invention has been made in view of the above, and it is possible to specify a priority order among a plurality of target packet data using a minimum necessary virtual channel, and to provide necessary information when necessary. It is an object of the present invention to provide a data communication apparatus and an image forming system that can send data.

  In order to solve the above-described problems and achieve the object, a data communication apparatus according to a first aspect of the present invention includes virtual channel means for transmitting packet data of a plurality of traffic by using a serial bus in a time division manner in units of virtual channels. And an arbitration unit that arbitrates a priority for issuing the packet data for each virtual channel, wherein the arbitration unit is configured to perform the virtual communication based on traffic characteristics of each of the issued packet data. A channel is assigned and the priority of each virtual channel to which packet data is assigned is designated.

  According to a second aspect of the present invention, in the data communication apparatus according to the first aspect, the generated traffic is classified into image data and command data for system control, and the virtual channel is assigned to each.

  According to a third aspect of the present invention, in the data communication apparatus according to the second aspect, the same virtual channel is allocated to a plurality of the image data having different transfer directions.

  According to a fourth aspect of the present invention, in the data communication apparatus according to the second aspect, a virtual channel that can be used by default is used for transferring the command data for system control.

  According to a fifth aspect of the present invention, in the data communication apparatus according to the second aspect, an independent virtual channel is used for transferring the command data for system control.

  According to a sixth aspect of the present invention, in the data communication apparatus according to the second aspect, a high priority is given to a virtual channel used for data transfer of the command data for system control between the virtual channels.

  According to a seventh aspect of the present invention, in the data communication apparatus according to the second aspect, a high priority is given to a virtual channel used for data transfer of the image data between the virtual channels.

  According to an eighth aspect of the present invention, in the data communication apparatus according to the first aspect, the arbitration means collects information on devices and connection forms connected when the system is started up, and assigns the virtual channel or the virtual channel. Priority order setting means for setting the priority order between them is provided.

  The invention according to claim 9 is the data communication device according to claim 8, wherein the arbitration means includes a plurality of arbitration tables in which different priorities are set in advance. The arbitration table is changed according to the instruction.

  An image forming system according to a tenth aspect of the present invention includes an image input engine, an image output engine, a controller that controls and drives the image input engine and the image output engine, these controllers, and the image input engine. And an interface by the data communication apparatus according to any one of claims 1 to 9, wherein the interface is connected to the image output engine.

  According to the first aspect of the present invention, a virtual channel is allocated based on the traffic characteristics of a plurality of issued packet data, and the priority of each virtual channel to which the packet data is allocated is specified, so that the necessary minimum It is possible to specify a priority order among a plurality of target packet data using the virtual channel, and it is possible to send necessary information when necessary.

  According to the invention of claim 2, the generated traffic is classified into image data and command data for system control, and a virtual channel is allocated to each of them, so that a high data transfer rate and isochronism can be obtained. There is an effect that another virtual channel can be used for the transfer of the requested traffic image data and the command data with a small amount of data and a weak isochronous constraint.

  According to the invention of claim 3, by assigning the same virtual channel to a plurality of image data having different transfer directions, for example, the direction dependency of traffic differs between scanner data and plotter data, and the reverse direction. Since there is no serial bus contention between virtual channels, the two traffics can be allocated to a single virtual channel and both can obtain high transmission performance and the required virtual There is an effect that the number of channels can be reduced.

  According to the invention of claim 4, by using a virtual channel that can be used by default for transferring command data for system control, there is an effect that it is not necessary to newly add software.

  According to the invention of claim 5, by using an independent virtual channel for transferring command data for system control, if there is a command channel having lower transfer performance required than image data, an image can be obtained. There is an effect that it can be assigned to a virtual channel different from that for data transfer.

  According to the invention of claim 6, if a high priority is given to a virtual channel used for data transfer of command data for system control between the virtual channels, and if the weight of the command channel is set large, the virtual channel There is an effect that the command data of the channel is prioritized over the image data.

  According to the seventh aspect of the present invention, if a high priority is given to the virtual channel used for data transfer of the image data between the virtual channels, and the weight of the data channel is set large, the image data of the data channel However, there is an effect that a high bandwidth can be secured with priority over the command data for system control.

  The invention according to claim 8 further includes priority order setting means for collecting information on devices and connection forms connected when the system is started, and assigning virtual channels and setting priorities between virtual channels. As a result, the priority order between the virtual channels can be changed during operation.

  According to the ninth aspect of the present invention, there are a plurality of arbitration tables in which different priorities are set in advance, and by changing the arbitration table according to an instruction from the priority setting means, during operation, There is an effect that the priority order between the virtual channels can be changed.

  According to the invention of claim 10, a virtual channel is allocated based on the traffic characteristics of each issued packet data, and the priority of each virtual channel to which the packet data is allocated is specified. It is possible to specify the priority order among a plurality of target packet data using the minimum virtual channel, and it is possible to send necessary information when necessary.

  Exemplary embodiments of a data communication apparatus and an image forming system according to the present invention are explained in detail below with reference to the accompanying drawings.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIGS. In the following, details of PCI Express will be described in the columns [Outline of PCI Express Standard] to [Details of Architecture of PCI Express], and then, regarding the data communication apparatus and the image forming system of the present embodiment, [Image Forming] This is described in the “System” column.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In an existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect a PCI-X bridge 105a to a host bridge 103 to which a CPU 100, AGP graphics 101, and memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. PCI Express 114b connects the switch 117a to which the PCI Express 114b is connected, and the PCI bridge 119 to which the switch 117b to which the endpoint 115b and the legacy endpoint 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Further, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c, and the mobile dock 135, Gigabit Ethernet 136 (Ethernet is a registered trademark), and an add-in are connected to the switch 134 by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects component links in a one-to-one relationship (point-to-point). . The transfer rate is, for example, 2.5 Gbps in one direction. The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint does not request I / O resources in the BAR (Base Address Register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double arrows indicate the PCI Express link 114 (or 126), and 142a to 142d indicate ports. Among these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and there is no concept of hierarchy. In PCI Express, as shown in FIG. Like the standard communication protocol and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration employs a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the cross-point of the data signal. The system extracts the clock.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting the conventional access to the access by PCI Express is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions extended by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Although various form factors (shapes) can be considered as PCI Express, examples of specific examples include an add-in card, a plug-in card (Express Card), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be effectively used by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed in order to avoid overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (mechanism to check the buffer availability on the receiving side before starting data transfer and prevent overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
The transaction layer packet (TLP) is automatically divided into data link layer packets (DLLP) as shown in FIG. 12 and transmitted to each lane when transmitted from the physical layer. A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power Management and Link State In order to keep the power consumption of the link low, a link state of L0 / L0s / L1 / L2 is defined as shown in FIG.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 15, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Image forming system]
The image forming system according to the present embodiment includes an image output device such as a printer, an image input device such as a scanner, a digital copier having both of them, and an image forming device such as an MFP (Multi Function Peripheral). The present invention is applied to an image forming system and uses a high-speed serial bus conforming to the PCI Express standard as described above.

  An example of the image forming system of the present embodiment will be described with reference to FIG. FIG. 16 is a block diagram showing an outline of connection of each device / device in the image forming system according to the present embodiment. The image forming system 1 uses a PCI Express standard bus system for serial data transfer. That is, a CPU 11 that centrally controls each unit of the image forming system 1 and a memory 12 that is a work area of the CPU 11 are connected to a root complex 13 of the PCI Express standard. A root complex 13 and a PCI Express standard switch (or switch network) 14 are connected via a PCI Express standard serial bus 15. The PCI Express standard switch (or switch network) 14 is connected to various devices and devices serving as PCI Express standard end points. That is, a hard disk (HDD) unit 21 that stores image data and the like, an image memory unit 22 and a memory unit 23, an image processing unit 24 that performs various image processing, a high-speed network 25 that communicates with an external network, etc. A scanner 26 as an input engine, a plotter 27 as an image output engine, an image input engine, another MFP 28 having an image output engine, and the like.

  According to such a configuration, since the PCI Express system, which is a high-speed serial bus, is used, the data transfer speed can be basically increased. In addition, the PCI Express standard end point (End Point) and Further speeding up of data transfer between the various devices / devices 21 to 27 can be achieved. That is, the PCI Express system between the various devices / devices 21 to 27 is connected through a tree structure having the PCI Express standard switch (or switch network) 14 as the highest level without going through the root complex 13. Since data transfer between 21 to 27 is performed without passing through the route complex 13, high-speed processing is possible.

[Arbitration standard]
In such an image forming system, since the data transfer rate required for each device / device is different, it is necessary to adjust the data transfer rate with high accuracy. As a standard for this purpose, priority is given to issuing packet data for each virtual channel VC by using virtual channel means for transmitting packet data of a plurality of traffic by using the serial bus as described above in a time division manner for each virtual channel VC. There is a function to arbitrate (arbitration means).

  FIG. 17 is a schematic block diagram showing a configuration example of the switch 14 which is a data communication device configured according to the arbitration function of the PCI Express standard. The illustrated example shows an example defined in a 4-channel configuration among a maximum of 8 virtual channels VC. The serial transmission circuit 31 receives data 1 to 4 for each channel from the device and generates packet data 1 to 4, and a virtual channel that temporarily stores the generated packet data 1 to 4 for each virtual channel VC Buffers (virtual channel means) 33a to 33d and the packet data 1 to 4 stored in the virtual channel buffers 33a to 33d are arbitrated according to the priority prescribed in advance by the VC arbitration table for each virtual channel VC. And an arbitration circuit (arbitration means) 36 that outputs to the signal output circuit 35 via 34.

  The illustrated example illustrates the case of using an arbitration algorithm that issues packet data at an equal frequency for each virtual channel VC. According to the arbitration, packet data is transferred from the signal output circuit 35 of the serial transmission circuit 31 to the serial bus. 1-4 are output equally as shown in the figure.

  However, even when the virtual channel VC prepared in the PCI Express standard is used, if a virtual channel is allocated without considering the nature of the generated traffic (for example, directionality, transfer rate, etc.), a large number of virtual channels There is a problem that a channel is required.

  Therefore, in the present embodiment, a plurality of target image data using the minimum necessary virtual channel is assigned by allocating a virtual channel based on the nature of traffic generated (for example, directionality, transfer rate, etc.). It is possible to set the priority order between image data and system control command data.

  Here, FIG. 18 is a schematic diagram showing an example in which virtual channels are allocated based on the nature of generated traffic. In the example shown in FIG. 18, the generated traffic is classified into plotter data, scanner data, and system control command data, and a virtual channel is assigned to each. Here, it is assumed that the scanner data and the plotter data are traffic that requires a high data transfer rate and isochronism, and that the system control command data has a small amount of data and has a weak isochronous constraint.

  In FIG. 18, the traffic of the plotter data transferred in the direction of the CPU 11 constituting the controller → the switch (or switch network) 14 → the plotter 27 is assigned to VC2, and the scanner 26 → the switch (or switch network) 14 → the CPU 11 constituting the controller. VC3 is assigned to the traffic of the scanner data transferred in the direction, and flows in the direction of CPU 11 constituting the controller → switch (or switch network) 14 → scanner 26 and CPU 11 constituting the controller → switch (or switch network) 14 → plotter 27. This is an example in which both system control command data traffic is assigned to VC1.

  The reason why the virtual channel VC is divided between the scanner data and the plotter data is that the direction dependency of traffic is different between the scanner data and the plotter data.

In such a case, the VC arbitration table is used in WRR (Weighted Round Robin) mode,
VC1: VC2: VC3 = 1: 2: 2
Thus, if the weights of the data channels VC2 and VC3 are set large, the scanner data of VC2 and the plotter data of VC3 are prioritized over the system control command data, as shown in FIG. Can be secured.

  The flow of packet data after VC arbitration is shown in Phy Ch at the center of FIG. For each command data packet of VC1, two data packets of VC2 and VC3 pass through the serial transmission path.

  As described above, according to the present embodiment, a virtual channel is allocated based on the traffic characteristics of each packet data that has been issued, and the priority order of each virtual channel to which the packet data is allocated is specified. By using a limited number of virtual channels, it is possible to specify priorities among a plurality of target packet data, and necessary information can be sent when necessary.

  In this embodiment, the independent virtual channel VC1 is used for the transfer of the system control command data. However, the present invention is not limited to this, and the virtual channel that can be used by default for the transfer of the system control command data. The channel VC0 may be used. This eliminates the need to add new software.

  In this embodiment, high priority is given to the virtual channels VC2 and VC3 used for data transfer between the virtual channels. However, the priority is not limited to this, and the system control command data is transferred between the virtual channels. High priority may be given to the virtual channel VC1 to be used.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is also omitted.

  In the first embodiment, the generated traffic is classified into plotter data, scanner data, and system control command data, and a virtual channel is assigned to each. On the other hand, in this embodiment, scanner data and plotter data having different traffic direction dependencies are combined into the same virtual channel VC.

  FIG. 19 shows the traffic of the plotter data transferred in the direction of the CPU 11 → switch (or switch network) 14 → plotter 27 constituting the controller and the scanner 26 → switch (or switch network) 14 → controller opposite to the plotter data. This is an example in which VC3 is assigned to the traffic of the scanner data transferred in the direction of the CPU 11 that constitutes. Since there is no contention for serial communication paths between the virtual channels VC between the traffic in the reverse direction, it is possible to obtain high transmission performance by allocating the two traffics together to one VC3.

  Even in such a case, if there is a command channel whose transfer performance is lower than that required for scanner data and plotter data, a VC different from that for data transfer (in FIG. 19), as in the first embodiment. , VC1).

In this case, the VC arbitration table is used in WRR (Weighted Round Robin) mode,
VC1: VC3 = 1: 2
As described above, if the weight of the data channel VC3 is set to be large, the VC3 plotter data is prioritized over the system control command data in the same direction to secure a high bandwidth as shown in FIG. it can.

  A flow of packet data after VC arbitration is shown in the center Phy Ch of FIG. For one command data packet of VC1, two VC3 data packets pass through the serial transmission path.

  As described above, according to the present embodiment, by assigning the same virtual channel to a plurality of image data having different transfer directions, for example, the direction dependency of traffic differs between scanner data and plotter data, and the reverse direction is reversed. Since there is no serial bus contention between the virtual channels between the traffic, by assigning the two traffics together to one virtual channel, both can obtain high transmission performance and the required virtual channel The number of can be reduced.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIG. In addition, the same part as 1st Embodiment mentioned above or 2nd Embodiment is shown with the same code | symbol, and description is also abbreviate | omitted.

  In the present embodiment, information on devices and connection forms connected at system startup is collected, and virtual channel assignment and priority setting between virtual channels are automatically performed.

  FIG. 20 is a schematic block diagram illustrating a configuration example of the switch 14 configured according to the arbitration function of the PCI Express standard. The switch 14 according to the present embodiment has a priority setting unit 40 added to the configuration described with reference to FIG.

  The priority setting unit 40 collects information on connected devices and connection forms at the time of system startup, and automatically assigns virtual channels and sets priorities between virtual channels. More specifically, the priority order setting unit 40 collects information on connected devices and connection forms when the system is started up, and outputs a VC arbitration table according to these information to the arbitration circuit 36. Note that the priority order setting process by the priority order setting unit 40 may be realized by a program process by the CPU.

  Here, FIG. 21 is a flowchart showing the flow of priority order setting processing in the priority order setting unit 40. As shown in FIG. 21, the priority order setting unit 40 sets device information (connection port, device type, use band, use frequency) (step S1), and calculates based on the use band and use frequency for each communication direction. The devices are aligned by the evaluation value (step S2).

  In the subsequent step S3, the number of usable virtual channels VC is compared with the number of devices. If the number of usable virtual channels VC is equal to or larger than the number of devices (Yes in step S3), the virtual channel VC is 1: 1. (Step S4), if the number of usable virtual channels VC is smaller than the number of devices (No in step S3), virtual channels VC are assigned in descending order of evaluation values for each communication direction, and devices with low evaluation values are assigned. The virtual channel VC is shared (step S5).

  After that, pairs are formed in descending order of evaluation values in each communication direction, VC No. is assigned (step S6), and a VC arbitration table is generated between the assigned VC No. based on device bandwidth and frequency of use. (Step S7). In the VC arbitration table, the number of slots to be allocated and the arrangement of slots (whether they are arranged collectively or distributed) are determined depending on the bandwidth.

  As described above, according to the present embodiment, the system includes the priority order setting unit 40 that collects information on connected devices and connection forms at the time of system startup, and assigns virtual channels and sets priorities between virtual channels. This makes it possible to change the priority between virtual channels during operation.

  Note that the arbitration circuit 36 has a plurality of arbitration tables, and by changing the arbitration table according to an instruction from the priority setting unit 40, the priority between virtual channels can be changed during operation. Also good.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. It is a block diagram which shows the architecture of the existing PCI. It is a block diagram which shows the architecture of PCI Express. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is explanatory drawing explaining the definition of the link state of L0 / L0s / L1 / L2. It is a time chart which shows the example of control of active state power management. 1 is a block diagram illustrating an outline of connections of devices, devices, and the like of an image forming system according to a first embodiment of the present invention. It is a schematic block diagram which shows the structural example of the switch comprised according to the arbitration function of the PCI Express specification. It is a schematic diagram which shows the example which allocated the virtual channel based on the property of the generated traffic. FIG. 10 is a schematic diagram illustrating an example in which virtual channels are allocated based on the nature of traffic generated in the image forming system according to the second embodiment of the present invention. It is a schematic block diagram which shows the structural example of the switch comprised according to the arbitration function of the PCI Express specification of the 3rd Embodiment of this invention. It is a flowchart which shows the flow of the priority setting process in a priority setting part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image forming system 11 Controller 14 Data communication apparatus 26 Image input engine 27 Image output engine 33a-33d Virtual channel means 36 Arbitration means

Claims (10)

A data communication apparatus comprising: virtual channel means for transmitting packet data of a plurality of traffics by using a serial bus in a time division manner in units of virtual channels; and arbitration means for arbitrating the priority for issuing the packet data for each virtual channel In
The arbitration means assigns the virtual channel based on traffic characteristics of each of the issued packet data, and designates the priority order of the virtual channels to which packet data is assigned.
A data communication device. Classifying the generated traffic into image data and command data for system control, and assigning the virtual channel to each;
The data communication apparatus according to claim 1. Assigning the same virtual channel to a plurality of image data having different transfer directions;
The data communication apparatus according to claim 2. A virtual channel that can be used by default is used to transfer the command data for system control.
The data communication apparatus according to claim 2. An independent virtual channel is used to transfer the command data for system control.
The data communication apparatus according to claim 2. A high priority is given to a virtual channel used for data transfer of the command data for system control between the virtual channels.
The data communication apparatus according to claim 2. A high priority is given to a virtual channel used for data transfer of the image data between the virtual channels.
The data communication apparatus according to claim 2. The arbitration means includes a priority setting means that collects information of devices and connection forms connected at the time of system startup, and assigns the virtual channels and sets priorities between the virtual channels.
The data communication apparatus according to claim 1. The arbitration means has a plurality of arbitration tables in which different priorities are set in advance, and changes the arbitration table according to an instruction from the priority order setting means.
The data communication apparatus according to claim 8.   The image input engine, the image output engine, a controller that controls and drives the image input engine and the image output engine, and the controller, the image input engine, and the image output engine are connected to each other. An image forming system comprising: an interface using the data communication device according to any one of items 1 to 9.

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