JP4683457B2 - Nonvolatile memory, data processor and IC card microcomputer - Google Patents

Description

  The present invention relates to a nonvolatile memory in which one memory cell is constituted by one transistor and retains information according to a threshold voltage, and a data processor in which a central processing unit is on-chip together with the nonvolatile memory, for example, an IC card TECHNICAL FIELD OF THE INVENTION

  Patent Document 1 discloses a two-element / one-cell type of a memory transistor having a MONOS (metal oxide nitride oxide semiconductor) structure and a MOS (metal oxide semiconductor) switch transistor using a nitride film as a charge storage layer. A non-volatile memory is described. When the nonvolatile memory is set to a low threshold voltage, a voltage for setting the low threshold voltage is applied. Conversely, when a high threshold voltage is set, a voltage for setting a high threshold voltage is applied. A non-volatile memory cell having a low threshold voltage is a depletion type. However, when the memory cell is not selected, the switch transistor is turned off to cut off the current, so that even if the threshold voltage of the memory transistor becomes too low, the non-volatile memory cell is not turned on. An undesired current does not flow through the bit line in the selected state.

  Patent Document 2 describes a threshold voltage setting method for a non-volatile memory in which one memory cell is formed by one transistor (one element / one cell type). That is, when the nonvolatile memory cell is set to a low threshold voltage, voltage application for setting a high threshold voltage is performed before voltage application for setting a low threshold voltage. Conversely, when a high threshold voltage is used, voltage application for lower threshold voltage is performed before voltage application for higher threshold voltage.

  In Patent Document 3, in a one-element / one-cell type nonvolatile memory, when an erased bit is made a depletion type, a voltage (negative voltage) lower than the threshold voltage is applied to the unselected read word line potential. There is a description about preventing overcurrent from flowing.

International Publication No. 03/012878 Pamphlet Japanese Unexamined Patent Publication No. 1-111397 JP 60-095795 A

  The inventor has studied a one-element / one-cell nonvolatile memory using one memory transistor having a MONOS structure. Similar to the non-volatile memory having a two-element / one-cell structure described in Patent Document 1, when the memory cell is a depletion type, a current flows even when it is not selected, so that selective reading is impossible. Regarding this point, in the nonvolatile memory cell having the floating gate, neither of the high and low threshold voltages can be generated in the above-mentioned Patent Document 2 in which the threshold voltage is limited to the enhanced type.

  The present inventor adopts a negative voltage for the word line non-selection level in order to turn off the memory transistor when the one-element / one-cell type memory cell that is made a depletion type when the threshold voltage is set to a low threshold voltage. did. In particular, the verify operation is not performed in order to shorten the erase and write time. Then, when a voltage that lowers the threshold voltage is applied to a plurality of nonvolatile memory cells in units such as bytes, among the plurality of nonvolatile memory cells in which a low threshold voltage state and a high threshold voltage state are mixed, the low threshold voltage A voltage for setting a low threshold voltage is applied to the nonvolatile memory cell in the state in an overlapping manner. As described above, when the voltage is applied repeatedly, the threshold voltage gradually decreases, and the verification is not performed. Patent Document 3 does not mention a method for avoiding this. Further, at this time, the threshold voltage of the one-element / one-cell type memory cell to be a depletion type is gradually lowered, and the word line non-selection level may be lowered below the lowest level to be finally reached gradually. Although it is possible, it has been found that it takes a relatively long time to drive the word line from the unselected to the selected level and is subject to a reduction in access speed.

  An object of the present invention is to prevent an undesired current from flowing through a non-selected nonvolatile memory cell.

  Another object of the present invention is to prevent a situation in which the threshold voltage of a one-element / one-cell type memory cell that is made a depletion type when the threshold voltage is lowered is undesirably transitioned to a low level.

  Still another object of the present invention is to stabilize and increase the speed of a read operation from a one-element / one-cell type memory cell that is made a depletion type when a low threshold voltage is set, and to change the threshold value for the memory cell. It is to contribute to speeding up.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] The nonvolatile memory has a plurality of nonvolatile memory cells and a plurality of word lines, and each of the plurality of word lines is a corresponding nonvolatile memory cell among the plurality of nonvolatile memory cells. Connected. Each of the plurality of nonvolatile memory cells can store data according to the level of the threshold voltage level. The low threshold voltage level is a negative voltage region, and the high threshold voltage level is a positive voltage region. The The non-volatile memory has a first operation in which the non-volatile memory cell having the low threshold voltage level is changed to a high threshold voltage level, and a second operation in which the non-volatile memory cell having the high threshold voltage level is changed to a low threshold voltage level. In the first operation, a first voltage is applied to a word line connected to a nonvolatile memory cell whose threshold voltage level is to be changed. In the second operation, a threshold voltage level is applied. After applying a first voltage to the word line connected to the nonvolatile memory cell to be changed, a second voltage for changing the threshold voltage of the nonvolatile memory cell to a lower threshold voltage level is applied to the word line. In short, when the first operation is the write operation and the second operation is the erase operation, the erase operation is performed in advance by performing a light write operation in advance from the viewpoint of voltage or voltage application time and then lowering the threshold voltage. It is possible to prevent a situation in which the threshold voltage of the one-element / one-cell type memory cell that is made a depletion type when the threshold voltage is lowered is undesirably shifted to a low level. Therefore, an undesired current does not flow in the non-selected nonvolatile memory cell. It is not necessary to reduce the non-selection level of the nonvolatile memory cell in the read operation to the limit. Therefore, the read operation from the memory cell is stabilized and speeded up without verifying at the time of erasing / writing to the one-element / one-cell type memory cell which is made a depletion type when the threshold voltage is lowered. Therefore, it is possible to contribute to speeding up of the threshold value changing process for the memory cell.

  In order to perform the light writing, for example, the time during which the first voltage is applied to the word line in the second operation is shorter than the time during which the first voltage is applied to the word line in the first operation. Good. Alternatively, the first voltage applied to the word line in the second operation may be lower than the first voltage applied to the word line in the first operation. When light writing is performed, the threshold voltage of the nonvolatile memory cell in the erased state becomes relatively high, but the threshold voltage of the nonvolatile memory cell in the written state hardly changes. In that sense, it is light writing.

  In a specific form of the present invention, the nonvolatile memory cell includes a source electrode, a drain electrode, a channel formation region between the source electrode and the drain electrode, and a charge storage insulation formed on the channel formation region. And a gate electrode disposed on the charge storage insulating layer.

  In a more specific form of the invention, the nonvolatile memory cells connected to the common word line are arranged in different well regions in units of n, and the nonvolatile memory whose threshold voltage level is to be changed in the first operation is provided. A first well voltage is applied to a well region in which cells are arranged, and among the nonvolatile memory cells arranged in the well region to which the first well voltage is applied, a nonvolatile memory cell whose threshold voltage level is to be changed is changed. A first source / drain voltage is applied to the source / drain, a second source / drain voltage is applied to the source / drain of the nonvolatile memory cell whose threshold voltage level should be suppressed, and the second source / drain voltage is applied. The voltage is a voltage that forms a channel with respect to the first well voltage and the gate voltage. From the above, it is possible to control writing and write blocking in units of memory cells for n nonvolatile memory cells sharing the word line and well region.

  At this time, in the second operation, the second well voltage is applied to the well region where the nonvolatile memory cell whose threshold voltage level is to be changed is arranged, and the second well voltage is arranged in the well region to which the second well voltage is applied. A voltage equal to the second well voltage is applied to word lines connected to nonvolatile memory cells other than the nonvolatile memory cells whose threshold voltage level is to be changed among all nonvolatile memory cells. Thereby, batch erasure can be controlled in units of n nonvolatile memory cells sharing the word line and well region. As a typical example, the n is 8.

  [2] A nonvolatile memory according to another aspect of the present invention has a nitride film as a charge storage layer, and is controlled so that a threshold voltage in either one of a write state and an erase state becomes a negative voltage It has a plurality of cells. When a transition is made from either the write or erase state in which the threshold voltage of the nonvolatile memory cell is a positive voltage to the write or erase state, the state of the nonvolatile memory cell to be transitioned After applying a voltage that changes the threshold voltage in the direction of the higher threshold voltage of the positive voltage, control is performed to apply a voltage that changes the threshold voltage of the nonvolatile memory cell that changes the state to a negative voltage. In short, when the first operation is the write operation and the second operation is the erase operation, the erase operation is performed in advance by performing a light write operation in advance from the viewpoint of voltage or voltage application time and then lowering the threshold voltage. It is possible to prevent a situation in which the threshold voltage of the one-element / one-cell type memory cell that is made a depletion type when the threshold voltage is lowered is undesirably shifted to a low level. Therefore, an undesired current does not flow in the non-selected nonvolatile memory cell. It is not necessary to reduce the non-selection level of the nonvolatile memory cell in the read operation to the limit. Therefore, the read operation from the memory cell is stabilized and speeded up without verifying at the time of erasing / writing to the one-element / one-cell type memory cell which is made a depletion type when the threshold voltage is lowered. Therefore, it is possible to contribute to speeding up of the threshold value changing process for the memory cell.

  In order to perform the light writing, for example, a voltage that changes the threshold voltage in a higher threshold voltage direction than a positive voltage is set to be higher than a voltage that is applied when a negative threshold voltage is changed to a positive threshold voltage. Use a low voltage. Alternatively, the voltage application time for changing the threshold voltage in a higher threshold voltage direction is set to a time shorter than the voltage application time when the negative voltage threshold voltage is changed to the positive threshold voltage.

  [3] A data processor according to still another aspect of the present invention includes the nonvolatile memory and a central processing unit that executes instructions on a single semiconductor substrate. The non-volatile memory is used for storing data accessed by the central processing unit, for example. In addition, the nonvolatile memory can perform random access by the central processing unit to perform the first operation, the second operation, and the read operation of stored data.

  [4] A microcomputer for an IC card according to still another aspect of the present invention has a nonvolatile memory and a central processing unit on a single semiconductor substrate, and the nonvolatile memory is in a first information storage state. From a second information storage state in which a plurality of nonvolatile memory cells are controlled so that a threshold voltage is a negative voltage, and the threshold voltage of the nonvolatile memory cell is a positive voltage, to the first information storage state In the case of transition, after applying a voltage that changes the threshold voltage of the non-volatile memory cell whose state is to be changed in a higher threshold voltage direction, the threshold voltage of the non-volatile memory cell whose state is to be changed is a negative voltage. Control is performed to apply a voltage to be changed.

  The IC card microcomputer further has a non-volatile program memory for storing a program executed by the central processing unit.

  [5] A nonvolatile memory according to still another aspect of the present invention includes a plurality of nonvolatile memory cells and a plurality of word lines, and each of the plurality of word lines includes the plurality of nonvolatile memory cells. Of these, they are connected to corresponding nonvolatile memory cells. Each of the plurality of nonvolatile memory cells is capable of storing data according to the level of the threshold voltage level, and the first operation in which the nonvolatile memory cell having the low threshold voltage level is changed to the high threshold voltage level. And the second operation in which the nonvolatile memory cell having the high threshold voltage level is changed to the low threshold voltage level is controlled. In the first operation, a first voltage is applied to a word line connected to a nonvolatile memory cell whose threshold voltage level is to be changed. In the second operation, a nonvolatile memory cell whose threshold voltage level is to be changed is connected. After the first voltage is applied to the word line, a second voltage for changing the threshold voltage of the nonvolatile memory cell to a lower threshold voltage level is applied to the word line.

  In a specific form of the invention, the low threshold voltage level is a negative voltage region, and the high threshold voltage level is a positive voltage region. At this time, it is impossible to execute a verify operation for verifying the threshold voltage changed in the first operation and the second operation. Further, when the stored information of the nonvolatile memory cell is read, the selection level of the nonvolatile memory cell is the ground level of the circuit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to prevent an undesired current from flowing through the non-selected nonvolatile memory cell.

  In addition, it is possible to prevent the threshold voltage of the one-element / one-cell type memory cell that is made a depletion type when the threshold voltage is set to a low threshold voltage from undesirably transitioning to a low level.

  Further, it is possible to contribute to the stabilization and speeding up of the read operation from the one-element / one-cell type memory cell that is made a depletion type when the threshold voltage is set to a low threshold voltage, and speeding up of the threshold value changing process for the memory cell. .

<Microcomputer>
FIG. 1 shows a microcomputer as an example of a data processor. The microcomputer 1 shown in the figure is an IC card microcomputer called a so-called IC card microcomputer, although it is not particularly limited. The microcomputer 1 shown in the figure is formed on a single semiconductor substrate or semiconductor chip such as single crystal silicon by a semiconductor integrated circuit manufacturing technique such as CMOS.

  The microcomputer 1 includes a central processing unit (CPU) 2, a random access memory (RAM) 4, a timer 5, an EEPROM (electrically erasable and programmable read only memory) 6, a coprocessor 7, and a clock. A generation circuit 9, a mask ROM 10, a system control logic 11, an input / output port (I / O port) 12, a data bus 13, and an address bus 14 are provided.

  The EEPROM 6 is used to store data used for arithmetic processing by the CPU 2 and the like. The mask ROM is used for storing a program (operation program) executed by the CPU 2. The RAM 4 is a work area of the CPU 2 or a temporary data storage area, and is composed of, for example, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). The CPU 2 fetches an instruction from the mask ROM 10, decodes the fetched instruction, and performs operand fetch and data operation based on the decoding result. The coprocessor 7 is a processor unit that performs a modular multiplication process in RSA or elliptic curve cryptography instead of the CPU 2. The I / O port 12 has 2-bit input / output terminals I / O1 and I / O2, and is used for both data input / output and external interrupt signal input. The I / O port 12 is coupled to a data bus 13, and the CPU 2, RAM 4, timer 5, EEPROM 6, mask ROM 10, and coprocessor 7 are connected to the data bus 13. In the microcomputer 1, the CPU 2 is a bus master module, and an address signal can be output to an address bus 14 connected to the RAM 4, timer 5, EEPROM 6, mask ROM 10, and coprocessor 7. The system control logic 11 controls the operation mode and interrupt control of the microcomputer 1 and further has a random number generation logic used for generating an encryption key. RES / is a reset signal for the microcomputer 1. When a reset operation is instructed by the reset signal RES /, the microcomputer 1 is initialized internally, and the CPU 2 starts executing instructions from the top address of the program stored in the mask ROM 10. The clock generation circuit 9 receives the external clock signal CLK and generates an internal clock signal CK. The microcomputer 1 is operated in synchronization with the internal clock signal CK.

  Although not particularly limited, the CPU 2 is a so-called 32-bit CPU, and can perform arithmetic processing in units of 32 bits. Although not shown, the CPU 2 includes a 32-bit general-purpose register, a 32-bit arithmetic logic unit, and the like. The data bus 13 is 32 bits. Therefore, most of data transfer instructions and arithmetic instructions included in the instruction set of the CPU 2 can process data in units of 32 bits. The data access unit by the CPU 2 is 8 bits. Here, the data access unit means the number of bits in the data area constituting the minimum address unit in the address space managed by the CPU 2, and the data access unit is 8 bits.

  The EEPROM 6 is a non-volatile memory that can be electrically erased and written. Here, the erasing operation is one method for erasing stored information held in the nonvolatile memory cell, and means, for example, a process for lowering the threshold voltage of the nonvolatile memory cell. A state in which the threshold voltage of the memory cell realized by this operation is low is called an erased state. The write operation is one method for holding information in the nonvolatile memory cell, and means, for example, an operation for increasing the threshold voltage of the nonvolatile memory cell. A state in which the threshold voltage of the memory cell realized by this operation is high is referred to as a write state. The EEPROM 6 can be erased in units of 8 bits, for example, and can be written and read in units of 32 bits. The EEPROM 6 is used as an area for storing data of a predetermined arithmetic processing unit such as an encryption key used for encryption of input / output data and ID information used for specifying an individual. In the writing process of the encryption key or the like used in the calculation process of the CPU 2, the stored information can be erased in accordance with the required data length (for example, 8 bits) of the calculation process unit. The mask ROM 10 holds a program processed by the CPU 2. For example, a virtual machine language program, an encryption program, a decryption program, and the like are held.

  FIG. 2 shows another example of the microcomputer 1. The microcomputer 1 shown in the figure is different from the microcomputer in FIG. 1 in the external interface means. That is, the microcomputer of FIG. 2 includes a high-frequency unit 15 having antenna terminals TML1 and TML2 that can be connected to an antenna (not shown). The high-frequency unit 15 outputs a power supply voltage Vcc using an induced current generated when the antenna crosses a predetermined radio wave (for example, a microwave) as an operation power supply, generates a reset signal RES and a clock signal CK, and performs non-contact information from the antenna. I / O is performed. The I / O port 12 exchanges information to be input / output with the outside with the RF unit 15.

《Nonvolatile memory》
FIG. 3 illustrates the structure of a nonvolatile memory cell employed in the EEPROM 6 by a vertical section. A nonvolatile memory cell (also simply referred to as a memory cell) MC illustrated in FIG. 3 has a MONOS structure formed in a p-type well region 27 provided on a silicon substrate. That is, an n-type diffusion layer (n-type impurity region) 20 as a source line connection electrode (source electrode Soc) connected to the source line, and an n-type diffusion layer as a bit line connection electrode (drain electrode Drn) connected to the bit line (N-type impurity region) 21, channel formation region 22 between the source electrode and the drain electrode, charge storage insulating film (for example, silicon nitride film) 23, and charge storage insulating film 23 are arranged above and below, for example, a silicon oxide film It has a memory gate electrode (MG) 26 that is formed by the formed insulating films 24 and 25 and an n-type polysilicon layer or the like and is used to apply a high voltage during a write operation / erase operation. For example, the insulating film 24 has a thickness of 1.5 nm, the charge storage insulating film 23 has a thickness of 10 nm (in terms of a silicon oxide film), and the insulating film 25 has a thickness of 3 nm. The charge storage insulating film 23 and the insulating film 24 and the insulating film 25 disposed on the front and back thereof together form a memory gate insulating film having an ONO (oxide film / nitride film / oxide film) structure.

  FIG. 4 illustrates a block diagram of the EEPROM 6. The memory array (MARY) 30 is divided into eight well regions WEL0 to WELn in the row direction, and has a plurality of nonvolatile memory cells MC arranged in a matrix. In FIG. 4, the nonvolatile memory cells MC for one row are shown as a representative, but a plurality of rows are actually arranged. In each of the well regions WEL0 to WELn, eight nonvolatile memory cells MC are arranged for one common word line. The drain electrodes 21 of the nonvolatile memory cells MC arranged in the same column are connected to the corresponding bit lines D0 to D7, and the source electrodes 20 of the nonvolatile memory cells MC arranged in the same column are connected to the corresponding source lines S0 to S7. Is done.

  The word line WL is driven by the memory gate driver circuit (MGD) 32 in accordance with the decode output of the X address decoder (XDEC) 31. The voltages of the well regions WEL0 to WELn are controlled by a well decoder (WDEC) 33. The voltages of the bit lines D0 to D7 and the source lines S0 to S7 are controlled by a sense latch circuit (SLAT) 34. An input / output switch (IOSW) circuit 35 is connected to the sense latch circuit 34. The input / output switch circuit 35 enables input / output of write data or read data in units of 32 bits between the 32-bit common data line 37 and the sense latch circuit 34 according to the decode output of the Y address decoder (YDEC) 36. A booster circuit (VPG) 38 generates a high voltage for a write operation and an erase operation and supplies the high voltage to the well decoder 33, the memory gate driver 32, and the sense latch circuit 34.

  The control circuit (TCONT) 40 is connected as external terminals to a plurality of address input terminals ADR, access control terminals CNT, and data input / output terminals DAT. Among the address signals input from the address input terminal ADR, the X address signal used for selecting the word line WL is supplied to the X address decoder 31, and Y used for selecting the bit lines D0 to D7 and the source lines S0 to S7. The address signal is supplied to the well decoder 33 and the Y address decoder 36. Write data input from the data input / output terminal DAT is applied to the common data line 37, and read data from the memory cells is output from the data input / output terminal DAT via the common data line 37. The erase operation, write operation, and read operation of the EEPROM 6 are instructed by an access control signal supplied to the access control terminal CNT. Vdd is a power supply voltage supplied from the outside, and Vss is a circuit ground voltage.

  The control mode of the memory operation by the control circuit 40 is roughly divided into an erase operation, a write operation, and a read operation. The erase operation is performed by applying a pre-write voltage, applying an erase voltage, and applying an erase blocking voltage. The write operation is performed by applying a write voltage and applying a write blocking voltage. The read operation is performed by applying a read voltage and applying a read non-selection voltage.

  FIG. 5 shows a voltage application mode when information is stored in a nonvolatile memory cell. “0” program means holding the information of logical value “0” by increasing the threshold voltage of the memory cell (holding “0” information). “1” program means holding the information of logical value “1” by lowering the threshold voltage of the memory cell (holding “1” information). The storage of the logical value “0” information in the nonvolatile memory cell is performed by applying a pre-write voltage, applying an erase voltage, and applying a write voltage. The storage of the logical value “1” information in the nonvolatile memory cell is performed by applying a pre-write voltage, applying an erase voltage, and applying a write blocking voltage.

  FIG. 6 illustrates an erase voltage and an erase block voltage applied in the erase operation. The erase target well region has a 1.5V well voltage, the erase non-target well region has a -8.5V well voltage and the erase target word line has a -8.5V erase voltage. A memory gate voltage of 1.5 V is supplied to the gate voltage and erase non-target word line as an erase block voltage, and all bit lines and source lines are set to 1.5 V. As a result, the representatively shown memory cells MC1 and MC2 are to be erased, and an electric field from the well region to the memory gate electrode is formed and captured by the charge storage insulating film 23 of the memory cells MC1 and MC2. Electrons are emitted to the well region through the oxide film through the FN tunnel. The threshold voltages of the memory cells MC1 and MC2 are made negative, and the memory cells MC1 and MC2 are depletion type. The memory cells MC3 and MC4 shown as representatives are not targeted for erasure, and the formation of an electric field necessary for electron emission is prevented. As is apparent from the figure, erasing is performed with a minimum unit of 8 bits per well. In the example of FIG. 6, the memory cell MC1 is a memory cell holding “0” information (bit to be set to “0”), and the memory cell MC2 is a memory cell to hold “1” information (bit to be set to “1”). It is said.

  FIG. 7 illustrates a write voltage and a write blocking voltage applied in the write operation. All well regions have a well voltage of -10.7V as a write voltage, a write target word line has a memory gate voltage of 1.5V, and a write non-target word line has a write inhibition voltage of -10.7V. A memory gate voltage is supplied. The source line and bit line connected to the memory cell that wants to hold “0” information has a write voltage of −10.7 V, and the source line and bit line that connects to the memory cell that wants to hold “1” information are blocked from writing. A voltage of 1.5 V is applied. According to the figure, the memory cell M1 is selected for writing and the memory cells M2 to M4 are not selected for writing. An electric field from the memory gate electrode to the well region is formed in the memory cell M1 selected for writing, and electrons are captured from the well region of the memory cell MC1 by the FN tunnel to the charge storage insulating film 23, and the threshold voltage is Positive voltage. Such an electric field is not formed in the memory cells MC3 and MC4 which are representatively shown, and no electrons are captured. The electric field is formed in the memory cell MC2 representatively shown, but the channel region is inverted, so that electrons are not trapped in the charge storage insulating film 23 from the well region. As a result, the threshold voltage of the memory cell MC1 that wants to hold “0” information (bit that wants to be “0”) MC1 is high, and the threshold voltage of the memory cell that wants to hold “1” information (bit that wants to be “1”) MC2 is Leave negative voltage.

  Here, attention is focused on the memory cell MC2 of FIGS. The memory cell MC2 is a memory cell that wants to retain “1” information (a bit that is to be set to “1”), and is a memory cell in which application of a write voltage is blocked in 8 bits as a minimum write unit. An erase voltage is also applied to the memory cell MC2 by an erase operation as shown in FIG. Therefore, when a specific memory cell included in 8 bits of the minimum programming unit is repeatedly excluded from the application of the write voltage, the erase voltage is continuously applied to the memory cell, and the threshold voltage becomes excessively low. It is possible. In particular, since the verify operation is not performed in the write operation and the erase operation, it cannot be directly detected even if the threshold voltage becomes excessively low. In order to prevent the threshold voltage in the erase state from becoming excessively low, in the erase operation in the EEPROM 6, a pre-write voltage is applied prior to the application of the erase voltage.

  The pre-write voltage is set to the same level as the write voltage applied to the memory cell whose threshold voltage is to be increased, such as the memory cell MC1 in FIG. In short, the well region applied voltage (-10.7 V), the memory gate voltage (1.5 V), the bit line and source line voltage (-10.7 V) applied to the memory cells MC1 and MC2 in FIG. The application time of the pre-writing voltage is shorter than the application time of the writing voltage. That is, the operation by applying the pre-write voltage is positioned as a light write operation. When light writing is performed, the threshold voltage of the nonvolatile memory cell in the erased state becomes relatively high, but the threshold voltage of the nonvolatile memory cell in the written state hardly changes. Therefore, after the pre-write voltage is applied, the threshold voltage of each memory cell is set to a positive threshold voltage with some variation. By applying an erase voltage thereafter, the threshold voltage of the memory cell originally in the erased state can be reduced to the negative side by about the same level as the memory cell originally in the written state. Occurrence of a situation in which the threshold voltage of the nonvolatile memory cell is cumulatively reduced can be prevented.

  FIG. 8 shows an example of the booster circuit 38. The clock signal CLKi output from the oscillation circuit 43 is supplied to the charge pump circuit 45 via the NAND gate 44. The charge pump circuit 45 performs the boosting operation in synchronization with the clock signal CLKi during the high level period of the signal CLKSTP, and stops the boosting operation during the low level period of the signal CLKSTP. The boosted voltage Vpp output from the charge pump circuit 45 is divided by the resistance voltage dividing circuit 46, compared with the reference voltage Vref by the comparison circuit 47, and the comparison result is fed back to the NAND gate 44 as a signal CLKSTP. If boosted voltage Vpp is lower than specified, signal CLKSTP is at a high level, and if it is higher, signal CLKSTP is at a low level, and a predetermined boosted voltage is formed by negative feedback control. The level of boosted voltage Vpp is different between writing and erasing, and the level is instructed to resistance voltage dividing circuit 46 by control signal E / W. A boost control circuit (WSM) 48 generates a reference voltage Vref, an oscillation control signal, and a control signal E / W according to instructions from the control circuit 40.

  FIG. 9 shows a boosted voltage waveform when information is stored in a nonvolatile memory cell. For example, the pre-write voltage application period is 0.1 milliseconds (ms), the erase voltage application period is 1 ms, and the write voltage application period is 1 ms. Each time is uniquely controlled by a control signal from the control circuit 40 or programmable by a register set value.

  FIG. 10 illustrates the state of the threshold voltage when the pre-write voltage as shown in FIG. 9 is applied and information is stored in the nonvolatile memory cell. There are four combinations of storage processing modes for the storage information in the initial state. Assume that the initial threshold voltage in the writing state holding the storage information “0” is +1.5 V, and the initial threshold voltage in the erasing state holding the storage information “1” is −1.0 V. When a pre-write voltage is applied, the threshold voltages of the memory cells in the write state (A) and (C) are not changed, and the memory cells in the erase state (B) and (D) have a positive threshold voltage. Shifted to + 1.1V. This is because the pre-write voltage application time is relatively short, such as 0.1 ms. Thereafter, when an erase voltage is applied, the threshold voltage of each of the memory cells (A) to (D) is adjusted to 1.1V. This is because the erase voltage application time is relatively long, such as 1 ms. A write voltage is applied to the memory cell of the form (A) or (B) that holds “0” information (“0” program), and the threshold voltage is set to + 1.5V. A write inhibition voltage is applied to the memory cells of the forms (C) and (D) that hold “1” information (“1” program), and the threshold voltage is kept at −1.1V.

  As a comparative example, FIG. 11 shows a voltage application mode when no pre-write voltage is applied when information is stored in a nonvolatile memory cell. The logical “0” information is retained in the nonvolatile memory cell by applying an erase voltage and a write voltage. The logical “1” information is retained in the nonvolatile memory cell by applying an erase voltage and a write blocking voltage. The state of the threshold voltage when information is stored in the nonvolatile memory cell in this way is illustrated in FIG. When the initial threshold voltage in the erased state holding the stored information “1” in the initial state is −1.1 V, if the erase voltage is applied as it is without applying the pre-write voltage, the threshold voltage becomes higher than the initial threshold voltage. Becomes -1.4V. Thereafter, the threshold voltage remains at -1.4 V, which is too low in the memory cell to which the write blocking voltage is applied as shown in (d).

  FIG. 13 shows the transition tendency of the threshold voltage when “1” information holding in FIG. 12D is repeatedly performed, and the threshold when “1” information holding in FIG. 10D is repeatedly performed. The voltage transition tendency is shown in contrast. As is clear from the figure, the former threshold voltage gradually decreases.

  FIG. 14 illustrates the application state of the read voltage in the read operation. All well regions are set to -2.0V, unselected word lines are set to -2.0V, and selected word lines are set to 0V. In the example of FIG. 14, since the memory cell MC3 is in the erased state and is in the depletion type, it is turned on by the word line selection operation with 0V. Since the memory cell MC4 is an enhancement type in a writing state, it is turned off. On the other hand, the memory cells MC1 and MC2 connected to the non-selected word lines should be turned off regardless of whether they are in the written state or the erased state. However, as shown in FIG. 13, there is a possibility that the threshold voltage of a memory cell with a large number of consecutive erasures will be −2.0 V or less, and in such a case, the memory cell leaks from the memory cell connected to the unselected word line. The current and the current flowing in accordance with the read data of the memory cell connected to the selected word line by the memory gate collide on the bit line, resulting in an error in the read data. As can be seen from FIG. 13, if the pre-write voltage is applied before the erase voltage is applied, such read data error does not occur.

  From the viewpoint of eliminating errors in read data, it is possible to cope with even lower word line non-selection levels. For example, FIG. 15 shows the high voltage application time dependence of the threshold voltage in the nonvolatile memory cell MC. Even if the erasing voltage application time is increased, the threshold voltage is saturated at −2.5 V and does not fall below that. According to this result, if the unselected word line potential is set to about −3 V in consideration of, for example, a single unit or a potential variation of −2.5 or less, the memory cells connected to the unselected word lines are not desired at all. No overcurrent flows. However, it takes time to invert and drive the word potential from the non-selection level of −3 V to the selection level, resulting in the disadvantage that the operation speed is slow and the power consumption is increased.

  In the description of FIG. 9, the pre-write voltage is applied before the erase voltage is applied to suppress the occurrence of the over-erased state. As a comparative example, a method of avoiding over-erasing by performing weak writing (post-writing) after applying an erasing voltage is conceivable. However, weak writing in which the threshold voltage is slightly increased to −1.1 V is very short. In the case of post-writing, a short pulse must be applied in a stable manner, which is very difficult. Even in the case of pre-writing, although the application time of the write pulse is short, the erase voltage in the opposite direction is applied after a relatively long time, so even if the variation in threshold voltage due to pre-writing increases somewhat, the nonvolatile memory The threshold voltage finally obtained in the cell is not greatly affected.

  In the writing and erasing operations by the EEPROM 6, verification is not performed. If verification is performed while a high voltage is applied, the threshold voltage can be distributed in a required area, and an overerased state is not caused by applying a cumulative erase voltage. If verify is employed, the erase and write operations are remarkably slowed. This is because, in applications where data is rewritten by random access by the CPU 2, unlike random storage applications such as memory cards, higher speed random access is required. In particular, the EEPROM 6 that is on-chip in the IC card microcomputer 1 is excellent in satisfying the requirement for rewriting data requiring security in as short a time as possible.

  According to the on-chip EEPOROM 6 in the microcomputer 1 described above, the non-volatile memory cell is composed of one transistor / one cell, and in a low threshold voltage state (erased state), the depletion type with a threshold voltage of 0 V or less is low. When a high threshold voltage is desired before applying the threshold voltage, the pre-write voltage application is inserted before the erase voltage application in about one-tenth the time of the (Write) voltage application. By doing so, it is possible to eliminate the inconvenience that the threshold voltage is excessively lowered when the erase voltage is applied cumulatively to the memory cell in the erased state, and the word line is not selected. When the pre-write voltage is applied prior to the erase voltage application, the threshold voltage remains stable even when the erase voltage application is repeated. There is no reduction in random access speed caused by making the word line non-selection level as low as possible or performing verification. The pre-write voltage application time is about 1/10 of the write voltage application time for obtaining a high threshold voltage in the write operation, and an increase in the erase time is about 10%, for example.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  In the above description, the information storage system in the memory cell is in the order of applying the write voltage after applying the erase voltage. In the reverse order, when the erase voltage is applied after the application of the write voltage, the problem that the high threshold voltage on the “0” information holding side increases excessively becomes obvious. For example, as shown in FIG. 16, when the application of the write voltage is repeated, the non-volatile memory cell whose threshold voltage has increased excessively has a low threshold voltage on the “1” information holding side even when the erase voltage is applied. There may be a problem that the target value is not lowered. In FIG. 16, the threshold voltage increases as the number of repeated application of the write voltage increases. In FIG. 16, the characteristic line at the left end is the initial characteristic, and the characteristic line on the right is the characteristic line when the erasing is performed once by applying the erasing voltage after 10 times of redundant writing by applying the write voltage. The line is a characteristic line when the erasing by applying the erasing voltage is performed once after performing the overlapping writing by applying the writing voltage 100 times, and the characteristic line on the right is the erasing voltage after performing the overlapping writing by applying the writing voltage 1000 times. It is a characteristic line when erasing by application is performed once. In order to solve this, it is considered effective to perform weak erasure (pre-erasure voltage application) before application of the write voltage. Weak erasing means that the voltage application time is shorter than the normal erasing voltage application time or the applied voltage is lower than the normal erasing voltage.

  The memory array is not limited to the NOR type. It can also be applied to an EEPROM such as a NAND memory array. For example, in the NAND type memory array illustrated in FIG. 17, when reading stored information, the non-selected word line is set to a high level (for example, 0.5 V) and the selected word line is set to a non-selected level of 0 V. The logical value “1” or “0” of the stored information is determined according to whether or not current flows in the DC path. Therefore, the threshold voltage after writing must be between 0V and 0.5V. If the threshold voltage is 0 V or less, an erroneous determination of the logical value occurs. If the threshold voltage is 0.5 V or more, a current does not flow through the unselected word line, resulting in a malfunction. When information is applied in the order of application of erase voltage and application of write voltage, if the application of erase voltage is repeated continuously, the threshold voltage of the memory cell becomes too low, and even if the write voltage is applied, there is a problem that it does not become 0 V or more. It is possible to do. In this case, it is effective to apply a pre-write voltage in which a weak write process is performed before the erase voltage is applied. In addition, when information is stored in the order of application of the write voltage and application of the erase voltage, if the application of the write voltage is repeated continuously, the threshold voltage of the memory cell is excessively increased and the threshold voltage is increased from the unselected word potential. This may cause a read defect. In this case, it is effective to adopt a pre-erase voltage application method in which weak erasure is performed before application of a write voltage.

  The definition of writing / erasing is relative, and an operation for increasing the threshold voltage can be defined as an erasing operation, and an operation for reducing the threshold voltage can be defined as a writing operation in reverse.

  The charge storage insulating film is not limited to a silicon nitride film, and may be a film in which carbon particles or silicon is dispersed in a dielectric.

It is a block diagram which shows a microcomputer as an example of a data processor. It is a block diagram which shows another example of the microcomputer which has a non-contact interface. It is a longitudinal cross-sectional view which illustrates the structure of the non-volatile memory cell employ | adopted as EEPROM. It is a block diagram of EEPROM. It is explanatory drawing which shows the voltage application form in the case of storing information in a non-volatile memory cell. It is explanatory drawing which illustrates the erase voltage and erase stop voltage which are applied in erase operation. It is explanatory drawing which illustrates the write voltage and write inhibition voltage which are applied in write operation. It is a block diagram showing an example of a booster circuit. FIG. 5 is a waveform diagram showing a boosted voltage waveform when information is stored in a nonvolatile memory cell. FIG. 10 is an explanatory diagram illustrating a state of a threshold voltage when information is stored in a nonvolatile memory cell by applying a pre-write voltage as shown in FIG. 9. It is explanatory drawing which shows the voltage application form in the case of not applying a pre-write voltage when storing information in a non-volatile memory cell as a comparative example. FIG. 12 is an explanatory diagram illustrating a state of a threshold voltage when information is stored in a nonvolatile memory cell according to FIG. The threshold voltage transition tendency when “1” information holding is repeatedly performed in FIG. 12D and the threshold voltage transition tendency when “1” information holding is repeatedly performed in FIG. It is explanatory drawing which compares and shows. It is explanatory drawing which illustrates the application state of the read voltage in read-out operation | movement. It is a characteristic view which shows the high voltage application time dependence of the threshold voltage in a non-volatile memory cell. It is explanatory drawing which shows that a threshold voltage rises, so that the repetition frequency of writing voltage application increases. 1 is a circuit diagram schematically showing a NAND type memory array of an EEPROM. FIG.

Explanation of symbols

1 Microcomputer 2 CPU
4 RAM
6 EEPROM (nonvolatile memory)
10 Mask ROM (program memory)
MC, MC1 to MC4 Memory cell 20 Source electrode 21 Drain electrode 22 Channel forming region 23 Charge storage insulating film 24, 25 Insulating film 26 Memory gate electrode 30 Memory array WEL0 to WELn Well region D0 to D7 Bit line S0 to S7 Source line 31 X Address Decoder 32 Memory Gate Driver Circuit 33 Well Decoder 34 Sense Latch Circuit 36 Y Address Decoder 38 Booster Circuit

Claims (14)

A plurality of nonvolatile memory cells and a plurality of word lines;
Each of the plurality of word lines is connected to a corresponding nonvolatile memory cell among the plurality of nonvolatile memory cells,
Each of the plurality of nonvolatile memory cells is a transistor having two diffusion layer regions serving as a source electrode and a drain electrode, and a charge storage layer and a gate electrode above a channel region sandwiched between the diffusion layer regions, Data can be stored according to the level of the threshold voltage level, a low threshold voltage level is a negative voltage region, a high threshold voltage level is a positive voltage region,
In the read operation of the data stored in the nonvolatile memory cell, a negative voltage is applied to the well region where the nonvolatile memory cell to be read is formed, and 0 V is applied to the gate electrode, which is not read. The same voltage as that applied to the well region is applied to the gate electrode of the nonvolatile memory cell,
A first operation in which the non-volatile memory cell having the low threshold voltage level is changed to a high threshold voltage level, and a second operation in which the non-volatile memory cell having the high threshold voltage level is changed to a low threshold voltage level. Operation control,
In the first operation, a well write voltage is applied to a well region where a nonvolatile memory cell whose threshold voltage level is to be changed is formed, a first voltage is applied to a word line to which the nonvolatile memory cell is connected,
In the second operation, the threshold voltage of the non-volatile memory cell is applied to the gate electrode of the non-read-out non-volatile memory cell to the word line connected to the non-volatile memory cell whose threshold voltage level is to be changed. In order to prevent the voltage from becoming lower than the voltage, after applying the first voltage for a time shorter than the time for applying the first voltage to the word line in the first operation, the nonvolatile memory cell is formed. Applying a well erase voltage to the well region to apply a second voltage to the word line to change the threshold voltage of the nonvolatile memory cell to a low threshold voltage level;
A non-volatile memory in which the well write voltage is a negative voltage and the well erase voltage is a positive voltage.   The nonvolatile memory cell includes a source electrode, a drain electrode, a channel formation region between the source electrode and the drain electrode, a charge storage insulating layer formed on the channel formation region, and the charge storage insulating layer The non-volatile memory according to claim 1, wherein the non-volatile memory is a field effect transistor having a gate electrode disposed thereon. Nonvolatile memory cells connected to a common word line are arranged in different well regions in units of n,
In the first operation, a first well voltage is applied to a well region in which a nonvolatile memory cell whose threshold voltage level is to be changed is disposed,
Of the nonvolatile memory cells arranged in the well region to which the first well voltage is applied, the source / drain of the nonvolatile memory cell whose threshold voltage level is to be changed according to data to be stored in the nonvolatile memory cell. Applies a first source / drain voltage, and a second source / drain voltage is applied to the source / drain of the nonvolatile memory cell whose change in threshold voltage level should be suppressed according to the data to be stored in the nonvolatile memory cell. 3. The nonvolatile memory according to claim 2, wherein the second source / drain voltage is a voltage forming a channel with respect to the first well voltage and the gate voltage. In the second operation, a second well voltage is applied to a well region in which a nonvolatile memory cell whose threshold voltage level is to be changed is disposed,
Among all the nonvolatile memory cells arranged in the well region to which the second well voltage is applied, the word line to which the nonvolatile memory cells other than the nonvolatile memory cells whose threshold voltage level is to be changed is connected The nonvolatile memory according to claim 3, wherein a voltage equal to the second well voltage is applied.   The non-volatile memory according to claim 4, wherein n is eight. Two diffusion layer regions to be a source electrode and a drain electrode, and a nitride film as a charge storage layer on the channel region sandwiched between the diffusion layer regions and a gate electrode, and is in either a writing or erasing state In a non-volatile memory having a plurality of non-volatile memory cells controlled so that the threshold voltage at is a negative voltage,
In the read operation of the data stored in the nonvolatile memory cell, a negative voltage is applied to the well region where the nonvolatile memory cell to be read is formed, and 0 V is applied to the gate electrode, which is not read. The same voltage as that applied to the well region is applied to the gate electrode of the nonvolatile memory cell,
In the case where transition is made from either the write or erase state in which the threshold voltage of the nonvolatile memory cell is a positive voltage to the write or erase state, the nonvolatile memory cell after the state transition is changed. The threshold voltage of the non-volatile memory cell whose state is changed in order to prevent the threshold voltage from becoming lower than the voltage applied to the gate electrode of the non-read-out non-volatile memory cell is set to the threshold voltage direction of higher positive voltage. A non-volatile memory that performs control to apply a voltage that changes a threshold voltage of the non-volatile memory cell that changes the state to a negative voltage after applying a voltage to be changed.   The nonvolatile voltage according to claim 6, wherein the voltage that changes the threshold voltage in the direction of the higher threshold voltage of the positive voltage is a voltage that is lower than a voltage applied when the negative threshold voltage is shifted to the positive threshold voltage. memory.   The voltage application time for changing the threshold voltage in the direction of the higher threshold voltage of the positive voltage is shorter than the voltage application time when the negative voltage threshold voltage is changed to the positive threshold voltage. Non-volatile memory.   A data processor comprising the nonvolatile memory according to claim 1 and a central processing unit for executing instructions on a single semiconductor substrate.   The data processor according to claim 9, wherein the nonvolatile memory is enabled to perform the first operation, the second operation, and the read operation of stored data by random access by a central processing unit. Having a non-volatile memory and a central processing unit on a single semiconductor substrate,
The non-volatile memory is a transistor having two diffusion layer regions to be a source electrode and a drain electrode, and a charge storage layer and a gate electrode above a channel region sandwiched between the diffusion layer regions. Having a plurality of nonvolatile memory cells controlled so that the threshold voltage in the state is a negative voltage,
In the read operation of the data stored in the nonvolatile memory cell, a negative voltage is applied to the well region where the nonvolatile memory cell to be read is formed, and 0 V is applied to the gate electrode, which is not read. The same voltage as that applied to the well region is applied to the gate electrode of the nonvolatile memory cell,
In the transition from the second information storage state in which the threshold voltage of the nonvolatile memory cell is a positive voltage to the first information storage state, the threshold voltage of the nonvolatile memory cell after the state transition is not read. Apply a voltage that changes the threshold voltage of the non-volatile memory cell that changes the state in the direction of a higher threshold voltage so that the voltage is not lower than the voltage applied to the gate electrode of the target non-volatile memory cell. Then, the microcomputer for IC card which performs control which applies the voltage which changes the threshold voltage of the said non-volatile memory cell which changes a state to a negative voltage.   The microcomputer for IC card of Claim 11 which further has a non-volatile program memory which stores the program which the said central processing unit performs. A plurality of nonvolatile memory cells and a plurality of word lines;
Each of the plurality of word lines is connected to a corresponding nonvolatile memory cell among the plurality of nonvolatile memory cells,
Each of the plurality of nonvolatile memory cells is a transistor having two diffusion layer regions serving as a source electrode and a drain electrode, and a charge storage layer and a gate electrode above a channel region sandwiched between the diffusion layer regions. It is possible to store data according to the level of the threshold voltage level,
In the read operation of the data stored in the nonvolatile memory cell, a negative voltage is applied to the well region where the nonvolatile memory cell to be read is formed, and 0 V is applied to the gate electrode, which is not read. The same voltage as that applied to the well region is applied to the gate electrode of the nonvolatile memory cell,
Operation control of a first operation in which a nonvolatile memory cell having a low threshold voltage level is changed to a high threshold voltage level and a second operation in which the nonvolatile memory cell having a high threshold voltage level is changed to a low threshold voltage level Was
In the first operation, a well write voltage is applied to a well region where a nonvolatile memory cell whose threshold voltage level is to be changed is formed, a first voltage is applied to a word line to which the nonvolatile memory cell is connected,
In the second operation, the threshold voltage of the non-volatile memory cell is applied to the gate electrode of the non-read-out non-volatile memory cell to the word line connected to the non-volatile memory cell whose threshold voltage level is to be changed. The nonvolatile memory cell is formed after applying the first voltage for a time shorter than the time for applying the first voltage to the word line in the first operation to prevent the voltage from becoming lower than the voltage. Applying a well erase voltage to the well region to apply a second voltage to the word line to change the threshold voltage of the nonvolatile memory cell to a low threshold voltage level;
A non-volatile memory in which the well write voltage is a negative voltage and the well erase voltage is a positive voltage.   14. The nonvolatile memory according to claim 13, wherein execution of a verify operation for verifying a threshold voltage changed in the first operation and the second operation is disabled.

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