JP2007188547A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which erasure can be easily performed in a short period of time. <P>SOLUTION: The nonvolatile semiconductor memory device is provided with memory cells having MOSFET structure. In the case where a first logic state is stored when the threshold voltage of the memory cell is lower than the prescribed first reference voltage, and a second logic state is stored when the threshold voltage of the memory cell is higher than the first reference voltage and lower than a second reference voltage being higher than the first reference voltage, when the storage state of the memory cell in the second logic state is changed to the first logic state, reference voltage change processing is performed in which the setting value of the first reference voltage discriminating the first logic state or the second logic state is changed to the setting value of second reference voltage before the change instead of changing the threshold voltage of the memory cell. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device having a floating gate. In particular, the present invention relates to a method for shortening the time for erasing.

  As a memory cell according to the prior art, an ETOX (registered trademark of US Intel Corporation) type memory cell is known in a flash type EEPROM. As shown in FIG. 8, in this ETOX type cell, a source 12 and a drain 13 having opposite polarities to the semiconductor substrate are formed in a semiconductor substrate 11, and a gate insulating film is formed between the source 12 and the drain 13. 14, a floating gate 15, an interlayer insulating film 16, and a control gate 17 are formed in this order.

  The operation principle of the ETOX type cell includes a write operation, a read operation, and an erase operation. During a write (program) operation, a low voltage (eg, 0V) is normally applied to the source 12 as the voltage Vs, a voltage Vd (eg, 6V) is applied to the drain 13, and a high voltage Vpp (eg, 12V) is applied to the control gate 17. Apply. At this time, hot electrons and hot holes are generated between the drain 13 and the source 12. Hot holes flow into the substrate as substrate current. On the other hand, hot electrons are injected into the floating gate 15 and the threshold voltage seen from the control gate 17 of the transistor increases.

  In a read operation, a low voltage (for example, 0 V) is applied to the source 12, a voltage (for example, 1 V) slightly higher than the voltage applied to the source 12 is applied to the drain 13, and 5 V is applied to the control gate 17. At this time, the current flowing between the source 12 and the drain 13 differs between the memory cell in the written state and the memory cell in the non-written state because the threshold voltage is different. This is sensed, and when the current is larger than a certain constant current, it is “1” (erased memory cell), and when it is smaller, it is “0” (written memory cell).

  During the erase operation, a high voltage Vpp (for example, 12V) is applied to the source 12, a low voltage (for example, 0V) is applied to the control gate 15, and the drain 13 is kept in a floating state. As a result, a Fowler-Nordheim current flows between the floating gate 17 and the source 12 via the tunnel oxide film, and electrons are extracted from the floating gate 17.

  Further, verification is performed in order to confirm whether the memory cell to be written and erased is above or below a predetermined threshold voltage according to such an operation principle. The write verify is determined to be in the write state when the threshold voltage of the memory cell is equal to or higher than the threshold voltage of the reference cell as compared with a reference cell having a high threshold voltage (Vthp) (for example, 5.3 V). . On the other hand, the erase verify is determined to be in the erased state when the threshold voltage of the memory cell is equal to or lower than the threshold voltage of the reference cell as compared with the reference cell having a low threshold voltage (Vthe) (eg, 3.1 V). is doing.

Here, normally, the characteristics of the memory cells in the chip vary, and the threshold voltage distribution of the cells after erasure varies. 9 and 10 show an example of the threshold voltage distribution of the cells in the memory array after erasure. As can be seen from FIG. 9, after erasing, the threshold voltage Vth of the memory cell has a value from the voltage Vthmin to the voltage Vthmax rather than a certain constant value. The voltage Vthe is a threshold voltage of the reference cell for determining the erased state and the written state. If an erase pulse is further applied, the value of the voltage Vthmin becomes 0 V or less as shown in FIG. This is over-erasing. In the memory cell in which over-erasure, that is, Vth <0, the memory cell is turned on even when the word line voltage = 0V, and all the data in the memory cell connected to the bit line in which the memory cell exists is determined to be “1”. Data reading cannot be performed normally. Therefore, the threshold voltage Vth of the memory cell must be distributed in the range of 0 <Vth <Vthe.

  In order to prevent such excessive erasure, the threshold voltage Vthe of the reference cell for erasure is normally set to a value considerably higher than 0V (for example, 3.3V). For this reason, when the voltage is lowered and the power supply voltage is 3 V, for example, the transistor of the reference cell is always turned off when the power supply voltage is applied to the word line, and accurate verification and reading cannot be performed. Therefore, normally, operations such as a read operation under such a low voltage power source are performed by boosting the word line voltage. In the case of this method, the timing for boosting the word line voltage is delicate, so it is difficult to increase the access time and the like. Furthermore, a circuit for boosting the word line is required, and current consumption becomes a problem. To advance the voltage reduction, it is desirable to set the threshold voltage of the reference cell to at least a value lower than the power supply voltage. .

  FIG. 11 shows a configuration of a common source memory cell array using such a conventional flash memory. Address signals A6 to A16 are input to the row decoder 21, data (D0 to D7) and address signals A0 to A5 are input to the column decoder 22, and an erase signal E is input to the erase circuit 23. . This memory cell array has m (for example, m = 2048) word lines WL1,..., WLm, and n (for example, n = 512) control gates of memory cells MC are connected to each word line. ing. That is, it has n bit lines BL1,..., BLn. Therefore, the memory capacity of this memory cell array is m × n (for example, 1 MB). The sources of the memory cell array are common, and the common source line SL is connected to the erase circuit 23.

  During the write operation, the memory cell that performs the selected write, that is, the memory cell that sets the data to “0”, depending on the data content, sets the voltage of the bit line to the voltage Vd, and the cell that does not perform the write, that is, the data The memory cell that remains “1” has the bit line voltage Vss. Further, a voltage Vpp is applied to the selected word line, whereby desired data is written in the memory cell.

  During the read operation, a voltage Vcc is applied to the word line and a voltage of about 1 V is applied to the bit line, as in the write operation. The sense amplifier determines “1” or “0” based on the current flowing through the memory cell, and data is read from the I / O.

  During the erase operation, an erase signal is input to the erase circuit, and as shown in FIG. 11, by applying the voltage Vpp to the sources of the transistors of all the memory cells arranged in an array, all of the memory cell arrays Memory cells can be erased simultaneously.

  A sequence at the time of erasing operation of the flash memory having the above operating principle and memory cell configuration will be described. FIG. 12 shows a general erase sequence. First, in order to prevent over-erasing, a preconditioning process for raising the threshold voltage is performed with all memory cells in a write state (step 51). Subsequently, write verification is performed to verify whether or not the threshold voltage of the memory cell exceeds the threshold voltage of the reference cell used in the preconditioning process (step 52). If the threshold voltage of the memory cell does not exceed the threshold voltage of the reference cell (No branch at step 52), the process of step 51 is repeated again to perform a write operation for increasing the threshold voltage of the memory cell. If the threshold voltage of the memory cell is higher than the threshold voltage of the reference cell (Yes in step 52), an erasing process is performed to lower the threshold voltage of the memory cell (step 53). Subsequently, erase verification is performed to verify whether the threshold voltage of the memory cell is lower than the threshold voltage of the reference cell used in the erase operation, and it is determined that the memory cell threshold voltage is not lower than the reference cell threshold voltage and is not in the erased state. If it is (No branch at step 54), the process returns to step 53, and the erase process for lowering the threshold voltage of the memory cell is performed again. If it is determined that the threshold voltage of the memory cell is lower than the threshold voltage of the reference cell (Yes in step 54), the memory cell whose threshold voltage is too low is included in the threshold voltage range of the normal erase state. Post-condition processing for writing is performed (step 55). Subsequently, it is verified whether the threshold voltage of the memory cell is within the normal erase state threshold voltage range (step 56). If not within the normal erase state threshold voltage range (No branch at step 56), the process returns to step 55. Then, post-condition processing is performed again. If it is within the threshold voltage range of the normal erase state (Yes branch at step 56), the erase sequence is completed.

FIG. 13 shows a threshold voltage distribution during an erase operation in the case of a conventional binary memory cell. The threshold voltage 70 of the reference cell is constant and there is only one type. When erasing a memory cell in the write state in the threshold voltage distribution 73, the erase operation shown in FIG. 12 is always performed, and the threshold voltage of the memory cell is erased. Must be lowered to the region of the threshold voltage distribution 71 (arrow 72)
. For this reason, it takes time to erase the memory cell in the threshold voltage distribution 73 in the written state, and the current consumption also increases by the number of times.

Japanese Patent Laid-Open No. 11-144480

  Since the conventional erase operation requires the operation shown in FIG. 12, there is a problem that it takes a longer processing time than the read operation and the write operation. If the threshold voltage verification is not successful, the writing process and the erasing process are repeated, which further increases the time required for the erasing operation. Furthermore, there is a problem that power consumption increases by repeating the writing process and the erasing process. For this reason, in a nonvolatile semiconductor memory device such as an electrically writable and erasable flash memory, there is a problem of shortening the erasing time of a certain memory space called a whole chip or a block or a sector.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device that can be easily erased in a short time.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention is a nonvolatile semiconductor memory device including a memory cell having a MOSFET structure, and the threshold voltage of the memory cell is a predetermined first reference voltage. It is assumed that the first logic state is stored when lower, and the second logic state is stored when higher than the first reference voltage and lower than the second reference voltage higher than the first reference voltage. When the storage state of the memory cell in the second logic state is changed to the first logic state, the first logic state and the first logic state are changed instead of changing the threshold voltage of the memory cell. The first characteristic is that a reference voltage changing process is performed to change the set value of the first reference voltage for determining the two logic state to the set value of the second reference voltage before the change.

  In the nonvolatile semiconductor memory device according to the present invention having the above characteristics, after the reference voltage changing process, the threshold voltage of the memory cell is changed from the first logic state in which the threshold voltage of the memory cell is lower than the changed first reference voltage. When switching to the second logic state where the voltage is higher than the first reference voltage after the change, the threshold voltage of the memory cell is set so that the threshold voltage of the memory cell becomes higher than the first reference voltage after the change. Switching is a second feature.

  In the nonvolatile semiconductor memory device according to the first aspect of the present invention, after the reference voltage changing process, the memory cell is changed from the first logic state in which a threshold voltage of the memory cell is lower than the changed first reference voltage. When switching to the second logic state in which the threshold voltage of the memory cell is higher than the first reference voltage after the change, the threshold voltage of the memory cell is higher than the first reference voltage after the change and before the change in the reference voltage changing process According to a third aspect of the present invention, the threshold voltage of the memory cell is switched so as to be lower than the changed second reference voltage set higher than the second reference voltage.

  The nonvolatile semiconductor memory device according to the present invention having any one of the above features includes a control unit that performs switching control of the set values of the first reference voltage and the second reference voltage by switching of the threshold voltage of the read reference cell. This is the fourth feature.

  The nonvolatile semiconductor memory device according to the present invention having the above characteristics is characterized in that the control section is arranged in the whole memory cell array or in a part of divided blocks.

  According to the present invention, when the storage state of the memory cell in the second logic state (for example, the write state) is changed to the first logic state (for example, the erase state), instead of changing the threshold voltage of the memory cell. Since the reference voltage changing process for changing the set value of the first reference voltage for determining the first logic state and the second logic state to the set value of the second reference voltage before the change is performed, the erase operation is actually performed. Although the memory cell can be erased without being performed and the number of times is limited, the erase time can be significantly shortened by repeating the reference voltage changing process. For example, the sector erase time of the flash memory in the ETOX configuration is normally several hundred ms to several s, but by using the present invention, the time for sector erase is only the storage of the reference cell information. It can be suppressed to about 10 us (writing time in a normal flash memory). In addition, since the erase operation is not actually performed, the power consumption can be suppressed without applying an erase pulse for the erase operation. Further, since the erase operation is not actually performed, the number of erase pulses applied can be reduced. Therefore, the burden on the memory cell itself is reduced, which is advantageous in terms of durability.

  Note that erasure of memory cells when writing to a threshold voltage higher than the read reference cell having the highest threshold voltage is a conventional operation. However, when there are few erasure operations on the system or temporary setup / shutdown etc. on the system This is effective when high-speed rewrite (erase + write) processing is required.

  Embodiments of a nonvolatile semiconductor memory device according to the present invention (hereinafter simply referred to as “device of the present invention” as appropriate) will be described below with reference to the drawings.

  FIG. 1 shows a circuit configuration example of the device of the present invention in this embodiment. The device according to the present embodiment of the present embodiment reads a reference cell 112 that stores information of a selected reference cell, a reference cell 112 (RVt0 to Rvtn), and a read that switches the reference cell 112 based on the information of the read reference memory unit 110. A reference cell switching circuit 113 and a main memory cell 114 are provided. When reading the memory cell, the sensing is performed by the main memory cell 114 and the switched reference cell 112. The read reference storage unit 110 is configured by a non-volatile memory (Cell0 to Celln) similar to the main memory, and does not lose information related to the read reference even when the power is turned off. Further, the read reference storage unit 110 can be set for each sector by arranging the read reference storage unit 110 for each sector like the read reference storage unit 120 of FIG. On the other hand, it is possible to set the entire chip by providing each device as in the read reference storage unit 130 of FIG.

  As shown in FIG. 4, when the reference cell is switched (step 60), the read reference storage unit 110 stores which read reference cell is currently used (step 61).

  Then, operation | movement of this invention apparatus is demonstrated based on FIGS. In the present embodiment, as shown in FIG. 5, a plurality of types of reference cells 80 (comparison cells for determining whether memory cell data is “0” or “1”) having different threshold voltages are provided (see FIG. 5). RVt0 <RVt1 <RVt2... <RVtn).

  In the initial erase state (corresponding to the first logic state) of the memory cell, the threshold voltage (Vt0) of the memory cell is set to be within the region of the distribution range 81 (Vt0 <RVt0). Subsequently, when performing a data write operation, the write is performed so that the threshold voltage (Vt1) of the memory cell is within the region of the distribution range 84 (RVt1 <Vt1 <RVt2). In other words, the threshold voltage of the memory cell in the region where the threshold voltage exceeds the threshold voltage of the reference cell 82 (RVt0, corresponding to the first reference voltage) is within the erased distribution range 81 (Vt0 <RVt0). (Arrow 83) so that the threshold voltage (Vt1) of the memory cell is in the distribution range 84 (RVt0 <Vt1 <RVt1) of the write state (corresponding to the second logic state). At this time, the threshold voltage of the memory cell is controlled to fall within the distribution range 85 so as not to exceed the threshold voltage of the reference cell 85 (RVt1, corresponding to the second reference voltage). Note that there is a multi-value technique that can hold several bits of data in one cell as a technique for suppressing the distribution range of the memory cells at the time of writing to a certain area.

  As shown in FIG. 6, the memory cell erase operation is performed while the threshold voltage (Vt1) of the memory cell to be written is in the distribution range 91 between the reference cell 90 (RVt0) and the reference cell 92 (RVt1). When performing the above, the reference cell 90 (RVt0) is switched to the reference cell 92 (RVt1) having a higher threshold voltage. As a result, the memory cells in the written state that are in the distribution range 91 beyond the reference cell 90 (RVt0) can be recognized as erased without actually undergoing a series of conventional erase processes. In other words, the threshold voltage of the written memory cell is set to Vt0 <RVt0, whereas the reference cell is changed to RVt1 without performing the erase operation, and it appears as if the erase operation has been performed. Time can be shortened.

  Furthermore, as shown in FIG. 7, when writing to a memory cell in the distribution range 100 in which the threshold voltage is between RVt0 and RVt1 but in the erased state, the memory is placed in a region exceeding the reference cell 101 (RVt1). Processing for increasing the threshold voltage of the cell (arrow 102) is performed. Thereby, by comparing with the reference 101, the memory cells in the distribution range 103 are determined to be in the writing state. However, at the time of writing, control is performed so that the threshold voltage of the memory cell does not exceed the threshold voltage of the reference cell 104 (Rvt2) and falls within the distribution range 103.

  When writing a memory cell in the distribution range Vti (i = 0, 1,..., N−1), the threshold voltage of the memory cell to be written is changed from the threshold voltage of the reference cell RVti to the threshold of the reference cell RVti + 1. Control is performed so as to be within the region of the distribution range Vti + 1 between the voltages. Furthermore, when erasing the memory cell, a process of switching the setting of the reference cell used at the time of reading from the reference cell RVti to the reference cell RVti + 1 is performed. That is, the first reference voltage for discriminating between the erased state and the written state and the second reference voltage which is the upper limit value of the threshold voltage distribution in the written state are set to the first reference cell set value for each erase operation. The threshold voltage of the second reference cell to which the two reference voltages are applied is changed, and the set value of the second reference voltage is changed to the threshold voltage of the next higher reference cell.

  By repeating such a process, the erase time of the memory cell can be greatly shortened without performing an erase operation. However, when the switching proceeds to the reference cell 105 (RVtn) having the highest threshold voltage, the normal erasing process is performed to return to the state shown in FIG. When the memory cell array is composed of a plurality of sectors, if the normal erase operation is performed in parallel with the read or write operation for other sectors, the erase operation time is apparently reduced from the outside. Is possible.

<Another embodiment>
In the above embodiment, control of the threshold voltage of the reference cell is described by a method using a reference cell generally used in a nonvolatile memory. However, other methods such as changing the voltage of the reference cell using a resistor are used. It is also possible to control with.

1 is a schematic circuit diagram showing a circuit configuration example of a nonvolatile semiconductor memory device according to the present invention. Schematic configuration diagram showing a configuration example of a read reference storage unit when erasing is performed for each sector in the nonvolatile semiconductor memory device according to the present invention Schematic configuration diagram showing a configuration example of a read reference storage unit when erasing the entire chip in the nonvolatile semiconductor memory device according to the present invention Flowchart showing the operation of the nonvolatile semiconductor memory device according to the present invention. Explanatory drawing explaining the change of the threshold voltage at the time of writing of the non-volatile semiconductor memory device based on this invention Explanatory drawing explaining switching of the reference cell of the nonvolatile semiconductor memory device according to the present invention Explanatory drawing explaining the change of the threshold voltage at the time of writing of the non-volatile semiconductor memory device based on this invention Schematic configuration diagram showing a schematic configuration of a memory cell according to the prior art Graph showing the threshold voltage distribution of an erased memory cell Graph showing the threshold voltage distribution of an erased memory cell Schematic configuration diagram showing a schematic configuration of a memory cell array according to the prior art A flowchart showing an erase operation of a memory cell according to the prior art Distribution diagram showing threshold voltage distribution of binary memory cell

Explanation of symbols

11 Semiconductor substrate 12 Source 13 Drain 14 Gate insulating film 15 Floating gate 16 Interlayer insulating film 17 Control gate 21 Row decoder 22 Column decoder 23 Erase circuit

Claims (5)

A non-volatile semiconductor memory device including a memory cell having a MOSFET structure,
The first logic state is stored when the threshold voltage of the memory cell is lower than a predetermined first reference voltage, and is higher than the first reference voltage and lower than a second reference voltage higher than the first reference voltage. Sometimes when the second logic state is set to be stored,
When the memory state of the memory cell in the second logic state is changed to the first logic state, the first logic state and the second logic state are changed instead of changing the threshold voltage of the memory cell. A non-volatile semiconductor memory device, wherein reference voltage change processing is performed to change a set value of the first reference voltage to be determined to a set value of the second reference voltage before the change.   After the reference voltage change process, the threshold voltage of the memory cell is higher than the first reference voltage after the change from the first logic state where the threshold voltage of the memory cell is lower than the first reference voltage after the change. 2. The nonvolatile memory according to claim 1, wherein when switching to the two logic state, the threshold voltage of the memory cell is switched so that the threshold voltage of the memory cell is higher than the first reference voltage after the change. Semiconductor memory device.   After the reference voltage change process, the threshold voltage of the memory cell is higher than the first reference voltage after the change from the first logic state where the threshold voltage of the memory cell is lower than the first reference voltage after the change. When switching to the two logic state, the threshold voltage of the memory cell is higher than the first reference voltage after the change, and the changed second reference voltage is set higher than the second reference voltage before the change in the reference voltage change process. The nonvolatile semiconductor memory device according to claim 1, wherein the threshold voltage of the memory cell is switched so as to be lower than a reference voltage.   The control part which performs switching control of the set value of the said 1st reference voltage and the said 2nd reference voltage by switching of the threshold voltage of a read-out reference cell is provided, The any one of Claims 1-3 characterized by the above-mentioned. Nonvolatile semiconductor memory device. 5. The nonvolatile semiconductor memory device according to claim 4, wherein the control unit is arranged in the whole memory cell array or in a part of a divided block.