JP2004158053A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device in which a program voltage optimum for every word line can be set. <P>SOLUTION: The nonvolatile semiconductor storage device has a feature that it includes memory cells arranged in every direction, a plurality of word lines connected to each column of the memory cells, and a control circuit for deciding the program voltage with respect to the word line selected on the basis of data read out from a part of the memory cells among all memory cells connected to the selected word line in a plurality of word lines. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device having a function of optimizing a program voltage.
[Prior art]
In a nonvolatile semiconductor memory device, a high voltage (program voltage) is applied to a word line during a program operation to inject electric charge into a floating gate. In a memory cell of a nonvolatile semiconductor memory device, the thickness of an oxide film varies due to a difference in process conditions, and the writing efficiency differs for each product even when a voltage applied to a word line is constant. Therefore, the optimum program voltage during the program operation also differs for each product.
[0002]
Conventionally, in order to correct such variations in the optimum program voltage, a nonvolatile memory area is provided separately from the memory cell array for storing data, and code information such as the optimum program voltage is stored in this area. . During a program operation, code information of an optimal program voltage is read from the memory area, and a program operation is executed based on the code information. For this code information, a test of the memory writing speed is executed on the manufacturer side at the time of shipping the nonvolatile semiconductor memory device, and information of an optimum program voltage is written in accordance with the test result.
[0003]
As a conventional technique, there is a flash memory that corrects a write / erase voltage for a storage element in accordance with a characteristic (initial threshold) of a target storage element (Patent Document 1).
[0004]
[Patent Document 1]
JP-A-2000-123584
[Problems to be solved by the invention]
With the above configuration, it is possible to correct the variation of the optimum program voltage for each product, but it is not possible to correct the variation within one product. Actually, even in one product of the nonvolatile semiconductor memory device, there is a slight difference in the thickness of the oxide film or the like depending on the position of the memory cell, and the optimum program voltage differs for each word line. However, in the configuration in which correction can be performed only for each product as described above, there is no other choice but to use a program voltage that can be reliably programmed for a word line with the worst condition, and there is a disadvantage that the efficiency of the program operation is low.
[0005]
In view of the above, an object of the present invention is to provide a nonvolatile semiconductor memory device capable of setting an optimum program voltage for each word line.
[Means for Solving the Problems]
A nonvolatile semiconductor memory device according to the present invention is connected to memory cells arranged vertically and horizontally, a plurality of word lines connected to each column of the memory cells, and a selected word line of the plurality of word lines. And a control circuit for determining a program voltage for the selected word line based on data read from some of the memory cells.
[0006]
In the nonvolatile semiconductor memory device, by providing a memory cell for storing a program voltage correction code so as to share a word line with a memory cell for storing data to be read / written, a program voltage correction code is designated for each word line. can do. Therefore, by reading out the optimum program voltage correction code from the selected word line and setting the program voltage based on the correction code, an efficient program operation according to the characteristics of each word line can be performed.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0007]
FIG. 1 is a diagram showing one embodiment of a core circuit of a nonvolatile semiconductor memory device according to the present invention.
[0008]
FIG. 1 shows a NAND type core circuit in which a plurality of memory cell transistors 11 are arranged vertically and horizontally. A plurality of memory cell transistors 11 are connected in series, and n bit lines BL0 to BLn-1 are connected to the drain side of the memory cell transistor serial connection. Further, the ground potential VSS is connected to the source side of the memory cell transistor series connection.
[0009]
When a word line corresponding to a read row address among a plurality of word lines WL0 to WLn is selectively activated, the memory cell transistor 11 connected to the word line becomes conductive or nonconductive according to the data content to be stored. State. A current flows through the bit lines BL0 to BLn-1 according to the conduction or non-conduction state, and data determination is performed by detecting this current.
[0010]
In the nonvolatile semiconductor memory device according to the present invention, a memory cell transistor 12 for storing an optimum program voltage is provided so as to share a word line with a memory cell transistor 11 for storing read / write data. Bit lines BLV0, BLV1,... Are provided for the memory cell transistors 12, and data is read from and written to the memory cell transistors 12 via the bit lines BLV0, BLV1,. For example, by providing five memory cell transistors 12 for each word line, it becomes possible to store a 5-bit program voltage correction code for each word line. The number of bits of the program voltage correction code stored for each word line may be any number as needed.
[0011]
Here, the bit lines BL0 to BLn-1 are bit lines to be selected according to a column address supplied from outside the nonvolatile semiconductor memory device, whereas bit lines BLV0, BLV1,. It is not a bit line to be selected according to the column address supplied from.
[0012]
FIG. 2 is a diagram showing a well structure of a memory cell of the nonvolatile semiconductor memory device according to the present invention.
[0013]
As shown in FIG. 2, an N-well 22 is formed in a substrate 21. In the N-well 22, a P-well 23 for forming a memory cell for storing normal read / write data and a P-well 24- for forming a memory cell for storing a program voltage correction code are formed. 1 and 24-2 are formed. In the example of FIG. 2, two memory cell transistors 12 are provided for each word line to store a 2-bit program voltage correction code, and P-wells 24-1 and 24-2 are connected to these two memory cells. Corresponding to the bit.
[0014]
In the P-well 23, a source / drain region 25 corresponding to a memory cell for storing normal read / write data is provided. Similarly, source / drain regions 26 corresponding to the memory cells for storing the program voltage correction code are provided in the P-wells 24-1 and 24-2. Bit lines 28 corresponding to the bit lines BL0 to BLn-1 of FIG. 5 are formed on the source / drain regions 25, and corresponding to the bit lines BLV0 and BLV1 of FIG. Bit line 29 is formed. Further, a word line 27 is provided above these bit lines.
[0015]
In the example of FIG. 2, wells 24-1 and 24-2 corresponding to a memory cell for storing a program voltage correction code are separated from wells 23 corresponding to a memory cell for storing normal read / write data. This is to prevent the optimum correction code of the program voltage that has been tested and written at the time of shipment from being erased or rewritten when the user uses the nonvolatile semiconductor memory device. Writing or erasing of a correction code to a memory cell for storing a program voltage correction code can be performed only in a test mode available to a manufacturer.
[0016]
FIG. 3 is a block diagram showing an example of the configuration of the nonvolatile semiconductor memory device according to the present invention.
[0017]
3 includes a control circuit 31, a command register 32, an I / O control circuit 33, an address register 34, a status register 35, a memory cell array 36, a row address decoder 37, a row address buffer 38, and a column decoder. 39, a data register 40, a sense amplifier 41, a column address buffer 42, a high voltage generation circuit 43, and a logic control 44.
[0018]
The logic control 44 receives control signals such as a chip enable, a command latch enable, an address latch enable, a write enable, a read enable, a write protect, and a spare area enable from outside the nonvolatile semiconductor memory device, and based on these control signals. The logic control signal is supplied to the control circuit 31.
[0019]
The I / O control circuit 33 exchanges input / output signals including an address signal, a data signal, and a command signal with the outside. The I / O control circuit 33 receives an address signal, a data signal, and a command signal from the outside, and supplies the address signal to the address register 34, the data signal to the data register 40, and the command signal to the command register 32. The address register 34 supplies a row address to a row address buffer 38 and a column address to a column address buffer 42.
[0020]
The control circuit 31 receives a logic control signal from the logic control 44, receives a command from the command register 32, operates as a state machine based on the logic control signal and the command, and controls each part of the nonvolatile semiconductor memory device 30. Control behavior.
[0021]
The control circuit 31 controls the memory cell array 36, the row address decoder 37, the column decoder 39, and the like to read data from the address of the memory cell array 36 indicated by the address register 34. Further, the control circuit 31 controls the memory cell array 36, the row address decoder 37, the column decoder 39, and the like in order to write data to the write address of the memory cell array 36. In addition, the control circuit 31 controls the memory cell array 36, the row address decoder 37, the column decoder 39, and the like in order to collectively erase a specified area of the memory cell array 36 in a predetermined unit.
[0022]
The memory cell array 36 includes an array of memory cell transistors, word lines, bit lines, and the like, and stores data in each memory cell transistor. In the present invention, the memory cell array 36 includes a memory cell array 36a for storing normal read / write data and a memory cell array 36b for storing a correction code of a program voltage, and has a structure in which the memory cell cell arrays 36a and 36b share a word line. ing. The memory cell cell arrays 36a and 36b may be a continuous monolithic array. At the time of data reading, data from a memory cell specified by the activation word line is read to a bit line. At the time of programming or erasing, by setting the word line and the bit line to appropriate potentials according to the respective operations, the operation of injecting or extracting the charge to the memory cell is executed. The operation of selecting the bit line of the memory cell array 36a at the time of access such as read / write is performed according to a column address supplied from outside the nonvolatile semiconductor memory device 30.
[0023]
The sense amplifier 41 operates under the control of the control circuit 31, and compares the current of the data supplied from the memory cell array 36 in accordance with the designation by the row address decoder 37 and the column decoder 39 with the reference current, so that the data becomes 0. Or 1 is determined. This determination result is stored in the data register 40 as read data, and is further supplied from the data register 40 to the I / O control circuit 33.
[0024]
In the verify operation accompanying the program operation and the erase operation, the data current supplied from the memory cell array 36 in accordance with the designation by the row address decoder 37 and the column decoder 39 is compared with the reference currents for the program verify and the erase verify. It is done by that. In the program operation, write data is stored in the data register 40, and the word lines and the bit lines of the memory cell array 36 are set to appropriate potentials based on the data, thereby executing charge injection into the memory cells.
[0025]
The status register 35 is a register for storing status information relating to the operation of the nonvolatile semiconductor memory device 30. By reading the contents of this register from outside via the I / O control circuit 33, it is determined whether the device is in a ready state. It can be determined whether the mode is the write protection mode or the program / erase operation. The high voltage generation circuit 43 is a circuit that generates a high potential used for a program operation and an erase operation.
[0026]
In the present invention, a correction code determined at the time of product shipment is written in the memory cell array 36b. When executing a program operation, a correction code corresponding to a row address (word line) to be programmed is read from the memory cell array 36b and supplied to the control circuit 31 via the sense amplifier 41 and the data register 40. At this time, a data selection operation for reading data from the memory cell array 36b instead of the memory cell array 36a is performed irrespective of a column address supplied from outside the nonvolatile semiconductor memory device 30.
[0027]
The control circuit 31 decodes the correction code to determine an optimal program voltage for the row address (word line) to be programmed, and controls the high voltage circuit 43 to generate the program voltage. The program voltage generated by the high voltage circuit 43 is applied to a corresponding word line, and a program operation is performed on a memory cell corresponding to the word line.
[0028]
FIG. 4 is a flowchart showing a program operation according to the present invention. The control of the program operation is performed by the control circuit 31 of FIG.
[0029]
In step ST1, a program voltage correction code is read from a row address (word line) to be programmed in the memory cell array 36b. The read correction code is supplied to the control circuit 31 via the sense amplifier 41 and the data register 40.
[0030]
In step ST2, the read correction code is decoded, and the program voltage PVPP is set based on the result.
[0031]
In step ST3, a program verify operation is performed. That is, data is read from a memory cell to be programmed, and it is determined whether or not the memory cell is in a programmed state (written state).
[0032]
In step ST4, it is determined whether or not the program verify has passed. If the memory cell to be written is already programmed and the program verify is passed, the program processing ends. If the write-target memory cell is not in the program state and fails the program verify, the process proceeds to step ST5.
[0033]
In step ST5, the program voltage PVPP is set based on the correction code.
[0034]
In step ST6, a program operation is performed. That is, the word line potential, the bit line potential, and the source line potential are set to predetermined write potentials, and charges are injected into the floating gate of the memory cell to be written. At this time, the voltage applied to the word line is the program voltage PVPP set based on the correction code, and has an optimum voltage value for each word line.
[0035]
In step ST7, a program verify operation is performed. That is, data is read from a memory cell to be programmed, and it is determined whether or not the memory cell is in a programmed state (written state).
[0036]
In step ST8, it is determined whether or not the program verification has passed. When the write-target memory cell is in a programmed state and the program verify is passed, the program processing ends. If the write target memory cell is not in the program state and fails the program verify, the process proceeds to step ST9.
[0037]
In step ST9, the correction code N is increased by one. As a result, the program voltage is set to a voltage one step higher. That is, if writing cannot be performed even when the program operation is performed at a certain program voltage, the program voltage is set to one step higher when the program operation is performed again.
[0038]
Thereafter, returning to step ST5, a program voltage PVPP based on the increased correction code is set, a program operation based on the program voltage is executed in step ST6, and a state determination is made by program verification. This operation is repeated until the memory cell to be written is in the programmed state. When the memory cell to be written is in the programmed state, the determination in step ST8 is YES and the program operation ends.
[0039]
FIG. 5 is a diagram showing another embodiment of the core circuit of the nonvolatile semiconductor memory device according to the present invention. Although the NAND type memory cell array is shown in the embodiment of the core circuit in FIG. 1, as shown in FIG. 5, the present invention can be applied to a NOR type memory cell array.
[0040]
The configuration of FIG. 5 shows a memory cell array and its peripheral circuits, a plurality of memory cell transistors 51 arranged vertically and horizontally, a plurality of memory cell transistors 52 for storing a correction code of an optimum program voltage, bit lines BL0 to BLn, and bits. It includes a line BLV, word lines WL0 to WLn, a plurality of Y gate transistors 53, sector decoders 54-1 and 54-2, a row decoder 55, a column decoder 56, a source switch 57, and a plurality of transistors 58 for sector selection.
[0041]
Sector decoders 54-1 and 54-2 make transistor 58 corresponding to the selected sector conductive, and make the corresponding bit line drivable. The row decoder 55 selectively activates a word line of a selected row address, and enables read, write, and erase operations for a corresponding memory cell. The column decoder 56 connects the bit line to a sense amplifier (not shown) (corresponding to the sense amplifier 41 in FIG. 3) by selectively turning on the Y gate transistor 53 corresponding to the selected column address. The source switch 57 is a circuit for setting the source potential of the memory cell transistors 51 and 52 to a predetermined potential at the time of reading, programming (writing), and erasing (erasing).
[0042]
In the example of FIG. 5, a plurality of memory cell transistors 52 for storing a correction code of the optimal program voltage are arranged in two columns, and two bit lines BLV are provided corresponding to the memory cell transistors 52. That is, the configuration is such that a 2-bit program voltage correction code is stored for each of the word lines WL0 to WLn. The number of bits is not limited to two, and may be any number as needed.
[0043]
Here, the bit lines BL0 to BLn are bit lines to be selected in accordance with a column address supplied from outside the nonvolatile semiconductor memory device, whereas the bit line BLV is in response to a column address supplied from outside. It is not a bit line to be selected.
[0044]
As described above, in the nonvolatile semiconductor memory device according to the present invention, a memory cell array for storing a program voltage correction code is provided in parallel with a memory cell array for storing data to be read / written, and both arrays share a word line. Thus, an optimum program voltage correction code can be set for each word line. This configuration can be applied to either a NOR type memory cell array or a NAND type memory cell array as shown in the embodiment, and is not basically limited by the structure of the memory cell array.
[0045]
In FIG. 2, the memory cells storing the data to be read / written and the memory cells storing the program voltage correction code have a structure formed in different wells. However, the present invention is not limited to this. It is good also as the form formed in. The memory cell array storing the data to be read / written and the memory cell array storing the program voltage correction code may be one memory cell array that is continuously integrated.
[0046]
As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the claims.
【The invention's effect】
In the above-described nonvolatile semiconductor memory device, by providing a memory cell storing a program voltage correction code so as to share a word line with a memory cell storing data to be read / written, a program voltage correction code is provided for each word line. Can be specified.
[0047]
Therefore, by reading out the optimum program voltage correction code from the selected word line and setting the program voltage based on the correction code, an efficient program operation according to the characteristics of each word line can be performed.
[Brief description of the drawings]
FIG. 1 is a diagram showing one embodiment of a core circuit of a nonvolatile semiconductor memory device according to the present invention.
FIG. 2 is a diagram showing a well structure of a memory cell of a nonvolatile semiconductor memory device according to the present invention.
FIG. 3 is a block diagram showing an example of a configuration of a nonvolatile semiconductor memory device according to the present invention.
FIG. 4 is a flowchart showing a program operation according to the present invention.
FIG. 5 is a diagram showing another embodiment of the core circuit of the nonvolatile semiconductor memory device according to the present invention.
[Explanation of symbols]
11 Memory cell transistor for storing read / write data 12 Memory cell transistor for storing program voltage correction code 30 Nonvolatile semiconductor memory device 31 Control circuit 32 Command register 33 I / O control circuit 34 Address register 35 Status register 36 Memory cell array 37 Low address decoder 38 Row address buffer 39 column decoder 40 data register 41 sense amplifier 42 column address buffer 43 high voltage generation circuit 44 logic control

Claims (9)

Memory cells arranged vertically and horizontally,
A plurality of word lines connected to each column of the memory cells;
A control circuit that determines a program voltage for the selected word line based on data read from some of the memory cells connected to the selected word line of the plurality of word lines. A nonvolatile semiconductor memory device characterized by the above-mentioned. A first well in which a memory cell other than the part of the memory cells is formed,
2. The nonvolatile semiconductor memory device according to claim 1, further comprising a second well in which the part of the memory cells is formed, wherein the first well and the second well are separated. A first bit line connected to a memory cell that is not the one of the memory cells of the all memory cells;
The nonvolatile memory device further includes a second bit line connected to the some memory cells, wherein the first bit line is a bit line selected according to a column address supplied from outside the nonvolatile semiconductor memory device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said second bit line is a bit line selected independently of said column address. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a high voltage circuit for generating said program voltage determined by said control circuit. 2. The non-volatile semiconductor memory device according to claim 1, wherein said control circuit programs memory cells of said all memory cells except for said some memory cells by said program voltage. A word line,
A first memory cell connected to the word line;
A nonvolatile semiconductor memory device comprising a second memory cell connected to the word line and storing a program voltage correction code for the first memory cell. 7. The non-volatile semiconductor memory device according to claim 6, further comprising a control circuit for supplying a program voltage based on said program voltage correction code to said word line to program said first memory cell. A first well in which the first memory cell is formed;
7. The nonvolatile semiconductor memory device according to claim 6, further comprising a second well in which said second memory cell is formed, wherein said first well and said second well are separated. A first bit line connected to the first memory cell;
The nonvolatile memory device further includes a second bit line connected to the second memory cell, wherein the first bit line is a bit line selected according to a column address supplied from outside the nonvolatile semiconductor memory device. 7. The nonvolatile semiconductor memory device according to claim 6, wherein said second bit line is a bit line selected independently of said column address.

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