JP2624716B2 - Method for setting threshold voltage of nonvolatile semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating gate nonvolatile semiconductor memory device, and more particularly, to a method for erasing a one-element / bit type memory.

[Conventional technology]

The one-element / bit nonvolatile memory element must be in the enhancement mode as long as a unipolar voltage is used.

As described in Japanese Patent Application Laid-Open No. 54-69037, a conventional one-element / bit nonvolatile memory erase method uses a high output impedance circuit between a drain and a substrate of a p-channel memory device to apply a reverse bias voltage. Hot electrons are injected into the floating gate by applying the voltage to lower the impedance between the source and the drain of the memory device, thereby self-suppressing the erasing operation, or erasing by irradiating ultraviolet rays and depleting. It prevented the transition to the chillon mode.

[Problems to be solved by the invention]

In the above prior art, it is necessary to cause avalanche or impact ionization near the drain in order to generate hot electrons at the time of erasing. Therefore, there is a problem that the current consumption per bit is large, which is not preferable for a large-capacity memory. In addition, when erasing with ultraviolet rays, there are problems that on-board rewriting cannot be performed and erasing time is long.

An object of the present invention is to provide an erasing method capable of realizing a large-capacity one-element / bit nonvolatile semiconductor memory device by drastically reducing current consumption per bit at the time of erasing.

[Means for solving the problem]

The object of the present invention is to provide a method of setting a threshold voltage of a floating gate type nonvolatile semiconductor memory device which stores information by being any one of a first threshold voltage and a second threshold voltage. When setting the threshold voltage of the nonvolatile semiconductor memory to the state of the first threshold voltage, a voltage for changing from the state of the first threshold voltage to the state of the second threshold voltage is changed. After the voltage is applied to the nonvolatile semiconductor memory, the voltage is changed by changing the state of the second threshold voltage to the state of the first threshold voltage.

[Action]

In the case of the first threshold voltage, the second threshold
When a voltage that changes the state of the threshold voltage to the state of the first threshold voltage is applied to the nonvolatile semiconductor memory, the sub-threshold current increases and the current consumption increases. However, once a voltage that changes the state of the first threshold voltage to the state of the second threshold voltage is applied to the nonvolatile semiconductor memory, the threshold voltage of the nonvolatile semiconductor memory becomes Since the voltage shifts to the second threshold voltage side, even if a voltage that changes from the second threshold voltage state to the first threshold voltage state is subsequently applied, the sub-threshold current at the initial stage of the application is increased. Is reduced, and as a result, the current consumption is reduced. When a plurality of single memory devices are connected in parallel, the sub-threshold current of the single memory device, which was the first threshold voltage, becomes small, so that a decrease in applied voltage due to this is avoided, and the second threshold voltage is reduced. The threshold voltage change of the single memory device at the threshold voltage is promoted.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

Prior to erasing, the source and substrate of the floating gate type memory are set to the ground potential, 12.5 V is applied to the control gate and 6 V is applied to the drain, and hot electrons are injected into the floating gate.
Light writing was performed on all 1M bits every 8 bits. 8
With a write time of 30 μS per bit, the 1V threshold voltage became 2V and the 6V bit became 6.1V.

FIG. 1 is a schematic diagram of the case of erasing. Reference numeral 1 denotes a memory array, which is in a state where single memory devices are connected in parallel by 1M bits when erasing. The gate oxide film thickness between the floating gate and the substrate of the single memory device is 10 nm.
The control gate and the substrate of the memory array were set to the ground potential, and the drain was connected to the diode-connected MOS transistor 3. On the other hand, a charge pump type internal booster circuit 2 having an output impedance RS150 kΩ and an output voltage VS24 V at no load was connected to the source. When the internal booster circuit operates and a voltage of 10 V or more is applied to the source of the memory device, the electrons accumulated in the floating gate gradually begin to be emitted to the source. When the source potential reached about 12 V, erasure proceeded, sub-threshold current began to flow, the current flowing into the common source of the memory array exceeded the supply capacity of the internal booster circuit, and the source potential dropped below 10 V, and erasure stopped. . At this time, the drain potential was 0.6 V. When the threshold voltage V _th after erasing was measured, it was about 1 V,
The intended purpose was achieved.

In FIG. 1, a similar experiment was conducted by short-circuiting the diode-connected MOS transistor 3 and setting the common drain of the memory array to the ground potential. As a result, the threshold voltage after erasing was 2.
It was 2V. In this state, the threshold voltage difference between writing and erasing is small, which is not preferable in circuit design. The difference between the threshold voltages after erasing in the two experiments is that when a voltage is applied to the drain, the sub-threshold current does not start to flow unless the potential of the floating gate is increased by that amount, and the apparent threshold voltage is reduced by the substrate bias effect. Raising is the result of a combination.

FIG. 2 shows the embodiment of FIG. 1 as erasing characteristics. At the same time, the erase characteristics in the drain open state are also shown for comparison. In the drain open state, it is difficult to set the threshold voltage after erasing to about 1 V. However, according to the present embodiment, the threshold voltage after erasing of the memory array can be adjusted to about 1 V in the erasing time of 10 ms or more. .

If the light writing of all bits before erasure is insufficient and the threshold voltage 1V bit shifts only to 1.5V, the source voltage will not exceed 10V even after erasing, and the threshold voltage will not be reached. 6V bits can only be erased up to 5V. That is, light writing before erasing requires shifting the threshold voltage of the low threshold voltage by 1 V or more.

In this embodiment, an example of simultaneous erasure of all bits has been described, but erasure for each block is also possible.

〔The invention's effect〕

According to the present invention, current consumption when changing the threshold voltage of the nonvolatile semiconductor memory can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram for explaining one embodiment of the present invention, and FIG. 2 is an erasing characteristic diagram when the drain is opened with the embodiment in FIG. 1. Memory array 2. Internal booster circuit 3. Diode-connected MOS transistor.

Claims (9)

(57) [Claims] 1. A method according to claim 1, wherein the sources are connected in common, the drains are connected in common, and each is used in an enhancement mode, wherein information is provided by a first threshold voltage and a higher second threshold voltage. In a threshold voltage setting method for a floating gate type nonvolatile semiconductor memory device having a plurality of single memory devices each of which stores one element, the plurality of single memory devices are collectively set to the first threshold voltage state. At this time, a first step of applying a voltage that changes in a direction of the second threshold voltage to the element in the state of the first threshold voltage, and after the first step, And a second step of applying a voltage for returning to the first threshold voltage state to the memory device. 2. The method according to claim 1, wherein in the first step, a state at the first threshold voltage is set to a state of a third threshold voltage higher than the first threshold voltage by at least 1 V or more. 2. The method for setting a threshold voltage of a nonvolatile semiconductor memory device according to claim 1, wherein: 3. In the first step, the voltage to be changed in the direction of the second threshold voltage is higher than the potential of the source and drain of the single memory device and the potential of the substrate on which the single memory device is formed. 3. The method for setting a threshold voltage of a nonvolatile semiconductor memory device according to claim 1, wherein the gate potential of said single memory device is set to be high. 4. In the first step, the voltage to be changed in the direction of the second threshold voltage is higher than the potential of the source of the single memory device and the potential of the substrate on which the single memory device is formed. 4. The method according to claim 3, wherein the drain voltage of the memory device is set to be higher. 5. In the second step, the voltage for returning to the state of the first threshold voltage is higher than the potential of the gate and drain of the single memory device and the potential of the substrate on which the single memory device is formed. 5. The threshold voltage setting method for a nonvolatile semiconductor memory device according to claim 1, wherein the source potential of the single memory device is set to be higher. 6. In the second step, the voltage for returning to the state of the first threshold voltage is set so that the voltage of the drain of the single memory device is higher than the potential of the gate of the single memory device. 7. The method for setting a threshold voltage of a nonvolatile semiconductor memory device according to claim 5, wherein the threshold voltage is set. 7. In the second step, the voltage for returning to the first threshold voltage state is the same as the potential of the gate of the single memory device and the potential of the substrate on which the single memory device is formed. 7. The method for setting a threshold voltage of a nonvolatile semiconductor memory device according to claim 5, wherein the threshold voltage is set to a potential. 8. The method for setting a threshold voltage of a nonvolatile semiconductor memory device according to claim 1, wherein said single memory device comprises an n-channel type memory device. . 9. The nonvolatile semiconductor memory according to claim 1, wherein a time of said first step is shorter than a time of said second step. How to set the threshold voltage of the device.