JP2005057106A - Non volatile semiconductor memory device and its charge injecting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non volatile semiconductor memory device for making an application voltage at the time of writing data lower than that in conventional channel hot electron injection by providing a memory transistor with a single layer gate structure for injecting hot electrons due to ionization collision, for example, secondary ionization collision into a floating gate, for improving the injecting efficiency of the hot electrons at the time of providing a high concentration channel area, and for reducing a voltage and a method for injecting the charge. <P>SOLUTION: This non volatile semiconductor memory device is provided with a floating gate 29 constituted of a single polysilicon layer, two source/drain areas 23 and 24, a control gate 30 constituted of an impurity area formed in a p-type well 21 and a voltage supply circuit. The voltage supply circuit supplies a write drain voltage to the two source/drain areas 23 and 24 at the time of writing data, and supplies a write gate voltage to the control gate 30. Thus, it is possible to inject hot electron HE due to secondary ionization collision generated at the source/drain area 24 side serving as the drain to the flowing gate 29. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a non-volatile semiconductor memory device having a single-layer gate structure capable of low-voltage operation, and a charge injection method thereof.

  When a CMOS logic circuit and a non-volatile memory cell array are mixedly mounted in the same IC, the same process can be used for the memory cell without changing the single polysilicon gate process typically used when manufacturing the logic circuit. It is desirable to form the transistors simultaneously. As a memory cell satisfying such a requirement, a P-type source region and drain region in an N-type well formed in a P-type substrate, and a channel region between the P-type source region and the P-type drain region are provided above. A memory cell having a single polysilicon gate structure including a formed polysilicon gate (floating gate) is known. (For example, refer to Patent Document 1).

  In this memory cell, a P-type impurity diffusion layer (hereinafter referred to as an impurity region) formed in an N-type well functions as a control gate and is capacitively coupled to the floating gate through a thin oxide layer. . The control gate and floating gate of this single polysilicon gate structure memory cell form a capacitor in a manner similar to that of more traditional stacked gate memory cells, so this single polysilicon gate structure These memory cells can be programmed (data write), erased and read out by the same method as in the case of a memory cell having a double polysilicon gate structure. In programming, that is, data writing, the electrons traveling in the channel are increased in energy by a horizontal electric field to generate hot electrons at the drain end, and the hot electrons are injected into the floating gate by the vertical electric field and accumulated. On the other hand, data is erased by extracting electrons from the floating gate to the substrate or drain region by a tunnel operation.

When the technique described in Patent Document 1 described above is applied to a memory cell having an N-type single polysilicon gate structure, the gate application voltage at the time of data writing or erasing may be, for example, 12 V or more. Has the disadvantages. These high write and erase voltages limit the extent to which the size of such memory cells can be reduced.
Japanese Patent No. 2951605

  The problem to be solved is that when data is written to a memory transistor having a single-layer gate structure, the voltage used is higher than the power supply voltage, and the scale of the circuit that generates this voltage is increased. The process common to the transistor cannot be used.

A nonvolatile semiconductor memory device according to the present invention includes a gate insulating film and a floating gate sequentially formed on a P-type well formed on a semiconductor substrate, and surfaces of the P-type well located on both sides of the floating gate. Nonvolatile semiconductor memory having two source / drain regions formed in a portion and a control gate formed of an impurity region formed in the P-type well and capacitively coupled to the floating gate via an insulating film A device that supplies a write drain voltage between the two source / drain regions, supplies a write gate voltage to the control gate, and serves as a drain of the two source / drain regions when writing data.・ Is caused by ionization collision of the channel charge to the semiconductor lattice on the drain region side To generate hot electrons, a voltage supply circuit for injecting the hot electrons into the floating gate further comprises.
Preferably, a high-concentration channel region having a higher concentration than the P-type well is formed in at least one of the two source / drain regions.

According to the non-volatile semiconductor memory device charge injection method of the present invention, a gate insulating film and a floating gate sequentially formed on a P-type well formed on a semiconductor substrate, and the P located on both sides of the floating gate. Two source / drain regions formed in the surface portion of the type well, and a control gate formed of an impurity region formed in the P type well and capacitively coupled to the floating gate through an insulating film. In the nonvolatile semiconductor memory device, the charge injection method supplies a write drain voltage between the two source / drain regions, supplies a write gate voltage to the control gate, and writes the 2 Of the two source / drain regions, the channel is on the source / drain region side that is the drain The hot electrons due to ionization collision of the load of the semiconductor lattice is generated, comprising the step of injecting the hot electrons into the floating gate.
Preferably, at the time of writing the data, the channel traveling charge is rapidly increased by an electric field which is provided on at least one side of the two source / drain regions and has a high concentration channel region having a higher concentration than the P-type well. Accelerate.

According to the present invention, the voltage supply circuit applies a write drain voltage between the two source / drain regions in the step corresponding to the operation (when writing data), and capacitively couples the floating gate via the insulating film. A write gate voltage is applied to the control gate composed of the impurity region. As a result, electrons that are supplied from one of the source / drain regions functioning as the source and run through the channel collide with the semiconductor lattice in the depletion layer on the drain side or are scattered to generate pairs of high-energy holes and electrons. Let Among these, hot holes are accelerated in the depletion layer of the PN junction and collide with the semiconductor lattice to generate electron-hole pairs again. The electrons therein become hot electrons and drift. The part is further accelerated by the electric field in the vertical direction toward the floating gate. As a result, hot electrons having high energy get over the potential barrier of the gate insulating film and are injected into the floating gate. As a result, the threshold voltage of the memory transistor rises from a low level in the erased state, and changes to a high level in which the data is written.
When the high-concentration channel region is formed, the electric field in the channel direction that causes the first ionization collision becomes steep at the drain end, so that more electron-hole pairs are generated. Hot electrons are generated by the next ionization collision.

  The nonvolatile semiconductor memory device and the charge injection method thereof according to the present invention includes a memory transistor having a single-layer gate structure that injects hot electrons caused by ionization collision, for example, secondary ionization collision, into the floating gate. There is an advantage that the applied voltage can be made lower than in the conventional channel hot electron injection. In particular, when a high-concentration channel region is provided, the hot electron injection efficiency is increased, and the voltage can be further reduced accordingly.

FIG. 1 shows a schematic configuration of a nonvolatile semiconductor memory device.
The nonvolatile semiconductor memory device illustrated in FIG. 1 includes a memory cell array (MCA) 1 and a memory peripheral circuit that controls the operation of the memory cell array 1.
The memory peripheral circuit includes a column buffer 2a, a row buffer 2b, a pre-row decoder (PR.DEC) 3, a main row decoder (MR.DEC) 4, a column decoder (C.DEC) 5, and an input / output circuit (I / O). 6, a column gate array (C.SEL) 7, and a well charge / discharge circuit (WC / DC) 8. When no well bias is performed, the well charge / discharge circuit 8 can be omitted. The memory peripheral circuit is not specifically illustrated, but the power supply voltage is slightly boosted as necessary, and the boosted voltage is supplied to the main row decoder 4 and the well charge / discharge circuit 8. A control circuit for controlling is included.

The input / output circuit 6 includes a program and read data buffer (BUF), a bit line driving circuit (BLD) for applying a predetermined voltage to the bit line BL at the time of writing or erasing, and a source line SL at the time of writing or erasing. Includes a source line driver circuit (SLD) for applying a predetermined voltage to the sense amplifier and a sense amplifier (SA). The input / output circuit 6, the word line drive circuit (WLD) and the well charge / discharge circuit 8 in the main row decoder 4, and a power supply circuit and a control circuit (not shown) for supplying power to these are provided as "voltage supply" of the present invention. Constitutes an embodiment of a circuit.
Since FIG. 1 shows a general memory configuration, descriptions of functions and operations of other configurations of the peripheral circuit are omitted here.

  The memory cell array 1 is configured by arranging memory cells in a matrix. Each memory cell has a gate electrode structure made of one polysilicon layer, and each cell has a memory transistor whose channel conductivity type is N type (hereinafter referred to as N channel type).

FIG. 2 is a schematic plan view of the memory cell. 3 shows a cross section taken along line AA in FIG. 2, FIG. 4 shows a cross section taken along line BB, and FIG. 5 shows a cross section taken along line CC.
FIG. 2 shows a serial connection portion of the memory transistor 10 constituting the memory cell and the select transistor 11 for controlling the connection of the memory cell to the bit line. A select transistor is not essential, but in a cell array system in which memory transistors such as so-called NAND type are connected in series, or in a cell array system in which memory transistors are connected in parallel to two impurity diffusion layers, these memory transistor groups and bit lines Alternatively, a select transistor for controlling connection with the source line is required.

As shown in FIGS. 3 to 5, the memory transistor 10 and the select transistor 11 are formed in a well (hereinafter referred to as a P well) 21 having a P type impurity conductivity type provided in an N type semiconductor substrate 20. ing.
More specifically, the surface portion of the P well 21 includes, for example, a portion where the element isolation insulating layer 22 is formed by a LOCOS (Local Oxidation of Silicon) method and a portion where the element isolation insulating layer 22 is not formed, that is, a transistor It is divided into active areas. As shown in the sectional view of FIG. 4, three N-type impurity regions 23, 24 and 25 are formed in the active region so as to be separated from each other in this order. The N-type impurity region 23 functions as the source of the memory transistor 10, the N-type impurity region 24 functions as the drain of the memory transistor 10 and the source of the select transistor 11, and the N-type impurity region 25 functions as the drain of the select transistor. An active region 26 between the N-type impurity regions 23 and 24 is a channel formation region of the memory transistor 10, and an active region 27 between the N-type impurity regions 24 and 25 is a channel formation region of the select transistor 11. The N-type impurity regions 23 and 24 constitute one embodiment of “two source / drain regions” in the present invention.

  A gate insulating film 28 made of a silicon oxide film having a thickness of about 8 to 13 nm, for example, is formed on the channel forming region 26, and a polysilicon gate 29 is formed on the gate insulating film 28. The polysilicon gate 29 functions as a floating gate of the memory transistor 10. Hereinafter, this polysilicon gate is described as a floating gate. As shown in FIG. 2, the floating gate 29 has a pattern including a gate finger portion 29A having a narrow width above the channel formation region 26 and a wide portion 29B formed on one side thereof.

Below the wide portion 29B of the floating gate 29 is an active region in which the element isolation insulating layer 22 is not formed. As shown in FIGS. 3 and 5, a P functioning as a control gate on the surface of the active region. A type impurity region 30 is formed. Hereinafter, this P-type impurity region is described as a control gate.
The control gate 30 is formed in an N-type well (hereinafter referred to as N well) 31 formed in the P well 21. That is, the formation part of the control gate has a well-in-well structure.
Between the control gate 30 and the floating gate 29, an inter-gate insulating film 32 made of a silicon oxide film having a thickness of, for example, about 8 to 13 nm is formed. The control gate 30 and the floating gate 29 are capacitively coupled via an inter-gate insulating film 32. The inter-gate insulating film 32 can be formed at the same time as the gate insulating film 28. In this case, both are formed as a common insulating film.
As shown in FIG. 2, the opening 33 is collectively formed in the floating gate 29 and the inter-gate insulating film 32, and the contact 34 made of a conductive plug or the like having a slightly smaller pattern is formed inside thereof. . On this contact 34, as indicated by a broken line in FIG. 2, a voltage supply layer to the control gate, for example, a word line WL is formed.

On the other hand, a gate insulating film 35 made of, for example, a silicon oxide film is formed on the channel formation region 27 of the select transistor 11, and a polysilicon gate 36 is formed on the gate insulating film 35. The polysilicon gate 36 is formed by patterning the same polysilicon film as the floating gate 29 of the memory transistor, and functions as a select gate line of the select transistor. Hereinafter, this polysilicon gate is referred to as a select gate.
As shown in FIG. 2, the select gate 36 is formed in parallel with the word line WL, for example, and is provided in common between cells in that direction.

  Although the memory transistor of this embodiment has an N-type channel, for the purpose of increasing its charge injection efficiency, a P-type having a higher concentration than the channel formation region 26 is formed in the channel formation region portion on the drain side as shown in FIG. A high concentration channel region 37 made of an impurity region is formed. The high-concentration channel region 37 has a role of increasing the concentration of the electric field in the channel direction in the adjacent channel formation region 26.

Hereinafter, the operation of the memory transistor will be described.
Data is written by injecting high energy charges (hot electrons) generated by ionization collision, for example, secondary ionization collision, into the floating gate.
FIG. 6A is a conceptual diagram of the data writing operation, and FIG. 6B is a diagram showing an acceleration electric field E of electrons in the channel direction. FIG. 7 is a chart showing the bias conditions at the time of writing together with the bias conditions at the time of erasing and reading. These bias voltages are supplied from the voltage supply circuit shown in FIG. 1, that is, the input / output circuit 6, the word line drive circuit (WLD) in the main row decoder 4, the well charge / discharge circuit 8, and the like.

  Here, the “ionization collision” is not limited to the secondary ionization collision, but hot electrons generated by the secondary ionization collision can be efficiently injected into the floating gate 29, so it is desirable to use secondary ionization collision hot electron injection. . The secondary ionization collision hot electron injection is a depletion when holes generated in the vicinity of the N-type impurity region 24 serving as a drain are injected into the substrate (P well 21) across the depletion layer in the vicinity of the N-type impurity region 24. Energy is generated from the electric field in the layer and it becomes hot, causing secondary ionization collision to the semiconductor lattice, generating further electron-hole pairs, part of the electrons crossing the depletion layer and moving vertically It is moved and injected into the floating gate 29 over the energy barrier of the gate insulating film 28.

In the erased state where the floating gate 29 is not charged, the memory transistor 10 has a threshold voltage Vth of about 1.5V.
As a bias condition for causing secondary ionization collision at the time of data writing, as shown in FIG. 7, 0 V is applied to the source line SL (N-type impurity region 23), and the bit line BL is connected via the select transistor 11 in the on state. A write drain voltage of 3.5 to 5.0 V is applied to the N-type impurity region 24. A voltage of 0 to −4 V is applied to the P well 21 where the memory transistor is formed, and a voltage of 5 V is applied to the N well 31 where the control gate 30 is formed, and a 5 V write gate is applied from the word line WL to the control gate 30. Apply voltage. At this time, since the control gate 30 and the N well 31 are at the same potential, even if a current flows from the P well 21 to the N well 31, this current does not flow into the control gate 30. The potential does not fluctuate.

Under this bias condition, as shown in FIG. 6A, the electrons e supplied from the source line SL (N-type impurity region 23) and traveling through the channel form silicon in the depletion layer on the drain side or in the high concentration channel region 37. Colliding with the lattice or being scattered, a pair of high energy holes HH and electron HE is generated. Among these, the hot hole HH is accelerated in the depletion layer of the PN junction and collides with the silicon lattice to generate a pair of electrons and holes again. The electrons therein drift as hot electrons HE, A part of it is further accelerated by an electric field in the vertical direction toward the floating gate 29. As a result, hot electrons HE having high energy overcome the potential barrier of the gate insulating film 28 and are injected into the floating gate 29.
As a result, the threshold voltage Vth of the memory transistor 10 rises from about 1.5 V in the erased state, and changes to about 4.5 V, which is the threshold voltage in the state where “1” data is written. In the case of “0” data writing in which “1” data is not written, hot electron injection does not occur when the bit line potential is set to 0 V, and the threshold voltage Vth is maintained at about 1.5 V in the erased state.

  Data is erased by extracting electrons accumulated in the floating gate 29 to at least one of the source and drain by FN tunneling, or by extracting the electrons to the entire surface of the channel. FIG. 7 shows bias conditions for two types of erasing methods.

In the method of [Erase 1] illustrated in FIG. 7, a positive voltage, for example, 3.5 to 5.0 V is applied to the N-type impurity region 24 on the drain side via the bit line BL, and the source via the source line SL. 0V is applied to the N-type impurity region 23 on the side, and 0V is applied to the P well 21. Further, a negative voltage, for example, −5 V is applied to the control gate 30 through the word line WL. At this time, 0V is applied to the N well 31 in which the control gate 30 is formed, or an open state is set.
Under this bias condition, a negative voltage is induced in the floating gate 29 coupled to the control gate 30 through a capacitor, and floating is caused by an electric field generated by this negative voltage and a positive voltage applied to the drain (N-type impurity region 24). Electrons in the gate 30 are extracted from the drain side, and the threshold voltage Vth is lowered to about 1.5 V in the erased state. At this time, since the N well 31 is at the same potential as the P well 21 or in a floating state, the parasitic transistor effect is effectively prevented.

In the [erase 2] method illustrated in FIG. 7, a positive voltage, for example, 5.0 V is applied to the drain-side N-type impurity region 24 via the bit line BL, and the same positive voltage is also applied to the P well 21. . This positive voltage may be applied to the source-side N-type impurity region 23 via the source line SL, but here the N-type impurity region 23 is in an open state. At this time, 5 V is applied to the N well 31 in which the control gate 30 is formed, or the open state is set. Other bias conditions are the same as those in [Erase 1].
Under this bias condition, a negative voltage is induced in the floating gate 29 coupled to the control gate 30 through the capacitance, and this negative voltage is applied to the drain (N-type impurity region 24) and channel (inversion layer on the surface of the P well 21). Electrons in the floating gate 30 are extracted from the drain side and the entire channel surface by the electric field generated by the applied positive voltage, and the threshold voltage Vth is lowered to about 1.5 V in the erased state. Similar to [Erase 1], the N well 31 is at the same potential as the P well 21 or in a floating state, so that the parasitic transistor effect is effectively prevented.

  Data reading may be performed bit by bit or page reading. In any case, when data is read from the memory transistor 10, 0V is applied to the N-type impurity region 23 via the source line, and the positive voltage at the power supply voltage Vcc level is applied with the P well 21 held at 0V. The voltage is applied to the drain via the bit line BL and to the control gate 30 via the word line WL. At this time, the N well 31 is set to the same potential as that of the control gate 30 for the same reason as at the time of writing. In the example of the bias voltage in FIG. 7, 1 to 3.3 V is applied to the bit line BL as a read drain voltage, and 2.5 to 5.0 V is applied to the control 30 as a read gate voltage. Also applied to the well 31. As a result, when the memory transistor 10 is programmed, that is, in a “1” data write state in which an appropriate amount of negative charge is stored in the floating gate 29, a channel current flows and the memory transistor 10 is turned on. To do. On the other hand, when an appropriate amount of negative charge is not stored in the floating gate 29, the memory transistor 10 remains off. The on / off of the memory transistor is detected by, for example, amplifying a change in the potential of the bit line BL, and the stored data is read.

As described above, the ionization collision phenomenon is used for data writing in this embodiment. Hot electrons HE generated by ionization collision are generated at a lower electric field than hot electrons simply accelerated in the channel to increase energy.
In the present embodiment, since the high concentration channel region 37 is provided, as shown in FIG. 6B, the electric field concentration in the channel direction is more concentrated than in the case where the high concentration channel region 37 indicated by the broken line is not provided. As a result, the energy with which the channel traveling electrons e collide with the silicon lattice increases. Alternatively, the voltage between the source and drain regions for obtaining the same energy may be low. In the present embodiment, the formation of the high concentration channel region 37 is not essential, but it is more desirable to form the high concentration channel region 37 for the above reason.
Furthermore, the PN junction between the P well 21 and the N-type impurity region 24 serving as the drain is reverse-biased by the back bias in which a negative voltage is applied to the P well 21, and the depletion layer is likely to expand with a lower drain voltage. Further, even if the write gate voltage is also lower than when no back bias is applied, the necessary hot electron injection efficiency can be easily obtained.

As described above, in this embodiment, the operating voltage is reduced as compared with the conventional case.
In the conventional channel hot electron injection method, about 12V is required as a write gate voltage in order to inject the same amount of charge into the floating gate in the same amount of time.
On the other hand, in this embodiment, the voltage applied to the control gate 30 is about 5V. As a result, the scaling of the gate length is easier than in the prior art, and the writing speed is 100 μs or less. In this embodiment, a one-layer polysilicon gate structure is adopted, and by combining this with the maximum required voltage of about 5 V, a memory transistor can be manufactured as in a logic embedded memory device. It is possible to realize a logic-embedded memory device at a low cost because the process and the logic transistor manufacturing process have high commonality or affinity.
Furthermore, by adopting a well-in-well structure, the control gate potential does not fluctuate and a reliable operation is realized.

In addition, power consumption is reduced by improving the charge injection efficiency.
In the conventional data writing method using CHE injection, the typical value of the write current for charging the floating gate is as large as about 0.5 mA. On the other hand, the memory transistor 10 according to the present embodiment only needs a write current of several tens of μA. The ability to reduce the write current to about 1/10 or less not only reduces the power consumption during data writing, but also reduces the size of the power supply circuit, and also allows page writing, that is, a plurality of memory transistors 10 in one row of the memory array. It is possible to simultaneously write “1” data.

  Further, in the conventional memory transistor, it is necessary to increase the coupling ratio between the floating gate and the control gate to 0.8 or more in order to realize a low voltage operation. Therefore, the area of the control gate is increased, and the area of the entire memory cell is large. On the other hand, in this embodiment, the voltage is reduced by writing using ionization collision. As a result, compared with the conventional N-channel type memory transistor having a single-layer polysilicon gate structure, this embodiment This memory transistor has a small control gate area. Thereby, in the memory cell of the present embodiment, the cell area is smaller than that of the conventional memory cell.

  Hereinafter, some modifications will be described.

  The memory transistor 10 is capable of multilevel data storage in which a plurality of bits, each of which is binary data, are written during one data write cycle. The level of the threshold voltage Vth of the memory transistor 10 depends on the voltage value applied to the control gate 30, and multilevel data storage is possible by finely controlling this voltage value. Alternatively, multilevel data storage is possible even if the bit line voltage value is finely controlled. In such multilevel data storage, it is necessary to accurately measure the threshold voltage Vth of the memory transistor 10. Therefore, the N-type impurity 25 serving as the drain of the select transistor 11 is coupled to the supply line of the power supply voltage Vcc via the high impedance resistor R and coupled to the voltage detection circuit 40 as shown in FIG. The voltage detection circuit 40 can accurately measure the threshold voltage Vth. Therefore, multilevel data can be accurately stored in the memory transistor 10.

Here, it is assumed that the threshold voltage Vth in the erased state of the memory transistor 10 is 1V, and the threshold voltage Vth in the written state in which the floating gate 29 is fully charged is about 6V. In this case, if a voltage range of 5 to 15 V is used as the write gate voltage Vcgw applied to the control gate 30 during the write cycle, the threshold voltage Vth of the memory transistor can be finely controlled within a range of about 1 to 6 V. is there.
More specifically, for example, when the power supply voltage Vcc is about 3.3 V, the voltage range of the bit line BL is set to about 1 to 3.3 V, and the write gate voltage Vcgw is sequentially changed a plurality of times. Write data. As a result, the threshold voltage Vth of the memory transistor 10 changes within a range having a width of 4V. In this case, the writing can be repeated a plurality of times so that the threshold voltage Vth of the memory transistor 10 is increased in increments of 4 mV, that is, sequentially in voltage steps that can be sufficiently identified at the time of reading.
In data reading, for example, the reading operation is repeated while sequentially changing the reading gate voltage from the higher threshold voltage to the level between the voltage steps, thereby sequentially determining the level of the stored data. Thereby, a plurality of bits can be read.
In erasing data, the erasing method described above is performed, and all levels of data are erased collectively.

  In other variations, a current limiting device may be coupled to the bit line BL to prevent the programming current from exceeding about 200 μA.

  In another modification, the select transistor can be provided only on the source side, and can be provided on both the source and drain.

  In another modification, the well structure may be a twin well structure, that is, a CMOS well structure in which a P well and an N well are provided adjacent to each other. This modification is particularly suitable for realizing a logic-embedded memory device having increased commonality with a logic circuit having a CMOS configuration. The N-channel memory transistor is usually formed on the P well side. Note that the control gate portion of the memory transistor may have a well-in-well structure, and the number of wells to be stacked can be increased. In this case, since more P-type and N-type wells are formed to overlap each other, current consumption at the time of well bias can be further reduced as compared with the case of the double well.

  The present invention can be widely applied to non-volatile semiconductor memories such as flash EEPROMs.

A block diagram showing a schematic configuration of a nonvolatile semiconductor memory device Schematic plan view of memory cell Sectional view of the AA line of FIG. Sectional view taken along line BB in FIG. Sectional view of the CC line of FIG. (A) is a conceptual diagram of the data write operation, (B) is an explanatory diagram of the acceleration electric field of electrons in the channel direction. Chart showing bias conditions for writing, erasing and reading

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2a ... Column buffer, 2b ... Row buffer, 3 ... Pre-row decoder, 4 ... Main row decoder, 5 ... Column decoder, 6 ... Input / output circuit, 7 ... Column gate array, 8 ... Well charge / discharge circuit DESCRIPTION OF SYMBOLS 10 ... Memory transistor, 11 ... Select transistor, 20 ... Semiconductor substrate, 21 ... P well, 22 ... Element isolation insulating layer, 23-25 ... Source / drain region, 26, 27 ... Channel formation region, 28 ... Gate insulating film 29 ... floating gate, 29A ... gate finger part, 29B ... wide part of floating gate, 30 ... control gate, 31 ... N well, 32 ... insulating film between gates, 33 ... opening, 34 ... contact, 35 ... insulation Membrane 36 ... select gate 37 ... high concentration channel region 40 ... voltage detection circuit BL Bit line, SL ... source line, WL ... word lines, HH ... hot holes, HE ... hot electron

Claims (11)

A gate insulating film and a floating gate sequentially formed on a P-type well formed on a semiconductor substrate, and two sources / drains formed on a surface portion of the P-type well located on both sides of the floating gate A nonvolatile semiconductor memory device having a region and a control gate formed of an impurity region formed in the P-type well and capacitively coupled to the floating gate via an insulating film,
At the time of writing data, a write drain voltage is supplied between the two source / drain regions, a write gate voltage is supplied to the control gate, and the source / drain region serving as a drain of the two source / drain regions is supplied. A non-volatile semiconductor memory device further comprising a voltage supply circuit that generates hot electrons caused by ionization collision of channel charges with a semiconductor lattice and injects the hot electrons into the floating gate. The nonvolatile semiconductor memory device according to claim 1, wherein a high-concentration channel region having a higher concentration than the P-type well is formed in at least one of the two source / drain regions. The voltage supply circuit is configured such that the write drain voltage and the write gate voltage that generate the hot electrons due to secondary ionization collision in which charges generated by the ionization collision further collide with a semiconductor lattice are respectively applied to the two source / drain regions. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is supplied to the control gate. The voltage supply circuit divides a write gate voltage applied between the P-type well and the control gate into a positive voltage and a negative voltage having opposite polarities, supplies a positive voltage to the control gate, and supplies a negative voltage to the control gate. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is supplied to the P-type well. An N-type well is formed in the semiconductor substrate, the P-type well is formed in the N-type well to form a well-in-well structure, and the control gate is in the innermost well of the well-in-well structure. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is formed. The nonvolatile semiconductor memory device according to claim 5, wherein the voltage supply circuit further applies a reverse bias to a PN junction formed by the P-type well and the N-type well when the data is written. A gate insulating film and a floating gate sequentially formed on a P-type well formed on a semiconductor substrate, and two sources / drains formed on a surface portion of the P-type well located on both sides of the floating gate A charge injection method for a non-volatile semiconductor memory device having a region and a control gate formed of an impurity region formed in the P-type well and capacitively coupled to the floating gate via an insulating film. ,
At the time of writing data, a write drain voltage is supplied between the two source / drain regions, a write gate voltage is supplied to the control gate, and the source / drain region serving as a drain of the two source / drain regions is supplied. A charge injection method for a non-volatile semiconductor memory device, comprising the steps of generating hot electrons caused by ionization collision of channel charges with a semiconductor lattice and injecting the hot electrons into the floating gate. When the data is written, the channel charge is rapidly accelerated by an electric field that is provided on at least one side of the two source / drain regions and has a high concentration channel region having a higher concentration than the P-type well. 8. A method for injecting charges in a nonvolatile semiconductor memory device according to claim 7. By supplying the write drain voltage and the write gate voltage to the two source / drain regions and the control gate, respectively, the charge generated by the ionization collision further collides with the semiconductor lattice to cause the hot ionization. The method of injecting electrons into the nonvolatile semiconductor memory device according to claim 7. In the hot electron injection step, a write gate voltage applied between the P-type well and the control gate is divided into a positive voltage and a negative voltage having opposite polarities, and a positive voltage is supplied to the control gate; The charge injection method of the nonvolatile semiconductor memory device according to claim 7, wherein a negative voltage is supplied to the P-type well. In the nonvolatile semiconductor memory device, an N-type well is formed in the semiconductor substrate, the P-type well is formed in the N-type well to have a well-in-well structure, and the control gate is Formed in the innermost well of the well-in-well structure,
The charge injection method of the nonvolatile semiconductor memory device further includes a step of applying a reverse bias to a PN junction formed by the P-type well and the N-type well when the data is written. A charge injection method for a nonvolatile semiconductor memory device according to claim 1.

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