JPS6095795A - Read-only semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a memory which inhibits a rewriting when necessary by inhibiting the rewriting for the contents which can rewrite the memory contents any number of times when necessary and are wanted to fix finally. CONSTITUTION:If the programmed contents have an error, the programming is carried out again erasion of data through irradiation of ultraviolet rays or an electrical operation. When it is desired that the programmed and corrected contents are finally fixed, the voltage is impressed between power supply terminals 11 and 12 so as to give the sequential bias to a diode 15. Thus a large current is supplied to a breaking circuit 14, and the circuit 14 is cut off. Thus high voltage VPP is not supplied to a program circuit although the voltage VPP is impressed to the terminal 11. As a result, only read-out of data is carried out. In a data writing mode the read-only voltage VCC is supplied to a route to which the voltage VPP is supplied via a diode 15. Thus a data reading circuit is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a read-only semiconductor memory device in which data can be electrically programmed.

[Technical background of the invention and its problems]

A read-only semiconductor memory device in which data can be electrically programmed is generally called an EPROM. This EP
ROM is advantageous as a memory in the prototype stage because data can be reprogrammed by irradiating it with ultraviolet light or erasing the data by electrical operation. However, if you want to prohibit rewriting of data as a ROM with many products, for example, a FROM that stores the code container of a recent personal radio
Let't = c1. & and prohibits replacement, the EPROM originally has (i'J
Since the structure is such that data can be erased and reprogrammed at any time, it is impossible to prevent rewriting of stored contents that are ultimately desired to be fixed.

On the other hand, it is conceivable to use a fuse ROM that cannot be rewritten for the above purpose. However, although this fuse ROM can be electrically programmed, it cannot be erased, and it is virtually impossible to change the stored contents by rewriting. Therefore, if a problem such as an error occurs in the written content, it cannot be recovered.

[Purpose of the invention]

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to allow the memory contents to be rewritten as many times as necessary, and to keep them fixed in the end. An object of the present invention is to provide a read-only semiconductor memory device that can prohibit rewriting of desired storage contents.

[Summary of the invention]

A read-only semiconductor memory device according to the present invention has a program power supply terminal and a read power supply terminal, and is capable of electrically programming data, and a high voltage is applied to the program power supply terminal during siprogramming. A diode is inserted between the read power supply terminal and the program power supply terminal in a direction that will create a reverse bias state during programming, and in the middle of the path that leads the high voltage applied to the program power supply terminal to the internal circuit. In this case, a fuse is inserted between the program power supply terminal and the upper diode. After finally memorizing the content to be identified, the fuse is blown, and even if a high voltage is applied to the glogram's power source 1f' + fli, this fuse will cause the high voltage to be 'f'. l! 1, and rewriting is prohibited.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor diagram 1, t4, exclusively for ω extraction, according to the present invention.
FIG. 2 is a circuit diagram showing the configuration of the device. This single memory crystal is made into a single IC and is housed in a storage box.When data is programmed, a high programming voltage Vpp of about 21V to 25V is applied to the storage package from the outside.
is applied to the power supply terminal 1, for example 5V.
Power supply terminal No. 2 to which the data read pressure VCC is applied
In addition to the power supply terminal J3 to which the ground voltage v88 of , QV is applied, an address input terminal, a data input/output terminal, a control signal input terminal, etc. (not shown) are provided. The above voltage Vp
The power supply terminal 1 to which p is applied is connected to one end of a cutoff circuit J4 which is made up of a fuse made of polycrystalline silicon, aluminum, etc. inside the IC, and the other end of this cutoff circuit J4 and the above-mentioned A diode switch 5 configured inside the IC is inserted between the power source tI'1 and the switch 2 to which the voltage Vco is applied, with the polarity shown in the figure. 4 to the internal circuit of the IC, and the voltage ■cc r VBg is similarly supplied to the internal circuit of the IC.

FIG. 2 is a circuit diagram schematically showing a configuration example of a data program circuit portion provided inside an IC and supplied with the voltages v, . . . vcc and vss. In the figure, numeral 2 is a decoder to which the voltages vce and V811 are supplied and an address is input. One output from the decoder 21 is input to the dart of the memory cell 22. This memory cell 22 has, for example, a floating dart structure, and is composed of a MOSFET in which data is harvested by injecting electrons into the floating darts, and this memory device has a storage capacity of, for example, 16 bits. If there is an IC chip, 16 memory cells 22 are provided in the IC chip. The voltage v88 is supplied to the source of the memory cell 22, and the drain is connected to the connection point between the other end of the cutoff circuit 14 and the cathode of the diode 15 in FIG. 1 through the MOSFET RJ. This MO8FgT23 is used as a write control MOSFET when reading data into the memory cell 22, and is used as a load when reading data from the memory cell 22.

The dart of the MO8FET 23 is supplied with the voltage at the connection point between the other end of the cutoff circuit 14 and the cathode of the diode 15 and the voltage V8g, and an output from an input circuit 24 into which write data is input. There is.

In such a configuration, when writing data to the memory cell 22 in FIG. 2, each power supply terminal 11 in FIG.
, 12.13, each voltage V1. .

Apply veel v8B. Immediately after manufacturing, the auxiliary circuit 4 is not cut off, so the % source terminal 11
The high voltage vpp applied to is output to the other end of the cutoff circuit J4. At this time, since the voltage PP is sufficiently larger than VCC, the diode 5 is put into a reverse bias state,
Voltages vpp and Vcc are independently supplied to the data program circuit and other internal circuits. Furthermore, in the case of data writing, an address and write data corresponding to the memory cell 22 are input.

When an address is input, the decoder 21 in FIG. 2 selects this memory cell 22 by outputting a signal at the vcc level to the dart of the memory cell 22. .

When further data is input, the input circuit 24 outputs a pp level signal to the dart of the MOSFET 23.

Therefore, this MOSFET 23 is turned on. At this time, one end of the MO8FET 23 has t'
Since the voltage "pp" applied to the terminal 11 is supplied to the terminal 11, the drain of the memory cell 22 is set to a level close to (2) through this MOSFET 23, and after this,
Electrons are injected into the floating darts of the memory cell 22 by impact ionization, thereby writing data. In parallel with this, data is also selectively written into other memory cells (not shown).

If the programmed contents are found to be incorrect after the above-mentioned data has been loaded, the data is erased by the conventional method of ultraviolet irradiation or electrical operation, and then the obtained data is programmed. Further, if the content of the glodarum is incorrect, the same operation as above is repeated. Then, if the contents after programming are correct and you finally want to fix them, power terminals 1 and 1
By applying a voltage that forward-biases the diode 15 between
Block 4. After the cutoff circuit 14 is cut off, no matter how much high voltage PP is applied to the power supply terminal 1, it will not be supplied to the data program circuit, so that data rewriting is prohibited from now on and only data reading is possible. is carried out extensively. Since the reading voltage ``co'' is supplied via the diode 15 to the path to which the high voltage ``pp'' was supplied during data writing, the circuit shown in FIG. Operates as a readout circuit. The read data from the memory cell 22, that is, the signal at the drain of the memory cell 22, is then selected according to necessity, detected by a sense amplifier, etc., and output.

In this way, according to the above embodiment, after the content to be finally fixed is written, the cutoff circuit No. 4 is cut off.
Since the high voltage vpp for programming is not supplied internally, subsequent rewriting can be prohibited.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the above embodiment, the cutoff circuit 14 is made up of a fuse made of polycrystalline silicon, aluminum, etc.
Although the explanation has been made regarding the case in which the r15 is provided in one chip IC, it may also be provided in the same package as a discrete component.

Furthermore, in the above embodiment, a case has been described in which the cutoff circuit 14 is constituted by a fuse, but as shown in FIG. J-
)' 31 is narrower than other parts inside the package 32, and the lead 3 is torn off from the narrow part 93 after data is written. It's okay. When the cutoff circuit 14 is constructed with a fuse, a problem arises in which the reliability decreases due to the blown fuse scattering, but this problem can be avoided if the circuit is constructed so that the external leads 3 are torn off as described above. Does not occur.

〔Effect of the invention〕

As explained above, according to the present invention, the memory contents can be rewritten as many times as necessary, and furthermore, it is possible to prohibit the writing of $3 for the contents that are ultimately desired to be fixed. It is possible to provide a read-only semiconductor memory device that can perform

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a smart read semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram of a data program circuit portion of the device shown in FIG. 1, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. FIG. 11.12.13... Power supply terminal, 14... Breaking circuit, No. 5... Diode, No. 3... External lead, 32
...Package, 33...Narrow width part. Applicant's representative Patent attorney Takehiko Suzue Continued from page 1 @ Inventor Nobuo Hiraiwa 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki City Toshiba Microcomputer Engineering Co., Ltd.

Claims (3)

[Claims] (1) A read-only semiconductor memory device that has a program power supply terminal and a read power supply terminal, allows electrical data programming, and applies a high voltage to the program power supply terminal during syphrogram. , comprising a diode element inserted between the read power terminal and the program power terminal, and a cutoff means for cutting off a path for guiding the high voltage applied to the program power terminal to the internal circuit. Semiconductor storage device for continuous output. (2) The read-only semiconductor memory device according to claim 1, wherein the cutoff means is constituted by a heater inserted between the program 'i1Lm terminal and the diode element. (3) A claim in which the cutoff means is constituted by a portion in which the width of an external lead for guiding the high voltage applied to the program' power supply terminal to the internal circuit is narrower than other portions. The read-only semiconductor memory device according to item 1.