YU1890A - Uredjaj za povećanu raspoloživost operanda u sistemu za obradu podataka - Google Patents

Uredjaj za povećanu raspoloživost operanda u sistemu za obradu podataka

Info

Publication number
YU1890A
YU1890A YU1890A YU1890A YU1890A YU 1890 A YU1890 A YU 1890A YU 1890 A YU1890 A YU 1890A YU 1890 A YU1890 A YU 1890A YU 1890 A YU1890 A YU 1890A
Authority
YU
Yugoslavia
Prior art keywords
operand
address
write instruction
instruction
cache
Prior art date
Application number
YU1890A
Other languages
English (en)
Other versions
YU47428B (sh
Inventor
T. Joyce
M. Miu
R. Kelly
Original Assignee
Bull Hn Information Systems Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull Hn Information Systems Inc. filed Critical Bull Hn Information Systems Inc.
Publication of YU1890A publication Critical patent/YU1890A/sh
Publication of YU47428B publication Critical patent/YU47428B/sh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

Abstract

UREDJAJ ZA POVECANU RASPOLOZIVOST OPERANDA U SISTEMU ZA OBRADU PODATAKA, uredjaj i postupak za povecanu raspolozivost operanda u jedinici za obradu podataka sa strategijom smestanja preko jedinice kes memorije prema ovom pronalasku ima za novost to, sto u sistemu za obradu podataka (1) u kome je svaka od jedinica (2) za obradu podataka implementirana pomocu protocnih (pipeline) tehnika i koji poseduje jedinicu kes memorije (6) koja se koristi strategijom protocnog smestanja, vreme koje je potrebno za pripremu adrese operanda instrukcije upisa moze biti znacajno krace od vremena neophodnog izvrsnoj jedinici (2-6) za pripremu odgovarajuceg operanda instrukcije upisa. U cilju efikasnog resenja vremenske razlike, u izvrsnu (E-) kes jedinicu (6-9) ukljucuje se uredjaj (6-421) za smestanje adrese operanda instrukcije upisa za vreme pripreme operanda instrukcije upisa. Po smestanju adrese operanda instrukcije upisa, sledeca adresa se unosi u ulazni registar (6-401) E-kes jedinice. Kada se nova adresa poveze sa instrukcijom citanja, kada ona nije u konfliktu sa adresarom operanda instrukcije upisa, i kada proizvede signal "UDARA" kada se primeni na popisni direktorijum (6-403) E-kes jedinice, instrukcija citanja se obradjuje u E-kes jedinici. Kada se u ulazni regtistar unese adresa operanda druge instrukcije upisa, kada je adresa operanda instrukcije citanja u konfliktu sa smestenom adresom operanda instrukcije upisa, ili kada adresa operanda instrukcije citanja rezultira "promasajem" kada se primeni na popisni direktorijum E-kes jedinice, adresa se cuva u ulaznom registru dok se ne odredi operand instrukcije upisa i dok se odgovarajuca instrukcija upisa ne obradi u E-kes jedinici (6-4).
YU1890A 1989-01-05 1990-01-05 Uredjaj za povećanu raspoloživost operanda u sistemu za obradu podataka YU47428B (sh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/294,529 US5123097A (en) 1989-01-05 1989-01-05 Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy

Publications (2)

Publication Number Publication Date
YU1890A true YU1890A (sh) 1994-04-05
YU47428B YU47428B (sh) 1995-03-27

Family

ID=23133839

Family Applications (1)

Application Number Title Priority Date Filing Date
YU1890A YU47428B (sh) 1989-01-05 1990-01-05 Uredjaj za povećanu raspoloživost operanda u sistemu za obradu podataka

Country Status (8)

Country Link
US (1) US5123097A (sh)
EP (1) EP0377436A3 (sh)
JP (1) JP2575219B2 (sh)
KR (1) KR950000549B1 (sh)
AU (1) AU616831B2 (sh)
CA (1) CA2007167C (sh)
SG (1) SG48794A1 (sh)
YU (1) YU47428B (sh)

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US5179679A (en) * 1989-04-07 1993-01-12 Shoemaker Kenneth D Apparatus and method for permitting reading of data from an external memory when data is stored in a write buffer in the event of a cache read miss
US5222240A (en) * 1990-02-14 1993-06-22 Intel Corporation Method and apparatus for delaying writing back the results of instructions to a processor
US5388226A (en) * 1992-10-05 1995-02-07 Motorola, Inc. Method and apparatus for accessing a register in a data processing system
US6219773B1 (en) 1993-10-18 2001-04-17 Via-Cyrix, Inc. System and method of retiring misaligned write operands from a write buffer
US5471598A (en) * 1993-10-18 1995-11-28 Cyrix Corporation Data dependency detection and handling in a microprocessor with write buffer
US5615402A (en) * 1993-10-18 1997-03-25 Cyrix Corporation Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch
US5740398A (en) * 1993-10-18 1998-04-14 Cyrix Corporation Program order sequencing of data in a microprocessor with write buffer
US5692152A (en) * 1994-06-29 1997-11-25 Exponential Technology, Inc. Master-slave cache system with de-coupled data and tag pipelines and loop-back
US5802586A (en) * 1995-02-27 1998-09-01 Motorola, Inc. Cache memory having a read-modify-write operation and simultaneous burst read and write operations and a method therefor
US5872946A (en) * 1997-06-11 1999-02-16 Advanced Micro Devices, Inc. Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch
US7210026B2 (en) * 2002-06-28 2007-04-24 Sun Microsystems, Inc. Virtual register set expanding processor internal storage
US7890657B2 (en) * 2008-06-12 2011-02-15 Genband Us Llc System and method for correct routing and enforcement policy in a network having address or port translation
US20140281391A1 (en) * 2013-03-14 2014-09-18 Qualcomm Incorporated Method and apparatus for forwarding literal generated data to dependent instructions more efficiently using a constant cache
CN110377339B (zh) * 2019-08-17 2024-03-01 中昊芯英(杭州)科技有限公司 长延时指令处理装置、方法以及设备、可读存储介质

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US4345309A (en) * 1980-01-28 1982-08-17 Digital Equipment Corporation Relating to cached multiprocessor system with pipeline timing
US4349871A (en) * 1980-01-28 1982-09-14 Digital Equipment Corporation Duplicate tag store for cached multiprocessor system
JPS6022376B2 (ja) * 1980-08-28 1985-06-01 日本電気株式会社 キャッシュメモリ制御装置
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4541045A (en) * 1981-09-21 1985-09-10 Racal-Milgo, Inc. Microprocessor architecture employing efficient operand and instruction addressing
US4521851A (en) * 1982-10-13 1985-06-04 Honeywell Information Systems Inc. Central processor
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EP0159712B1 (en) * 1984-04-27 1991-01-30 Bull HN Information Systems Inc. Control means in a digital computer
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
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US4802085A (en) * 1987-01-22 1989-01-31 National Semiconductor Corporation Apparatus and method for detecting and handling memory-mapped I/O by a pipelined microprocessor
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US5051894A (en) * 1989-01-05 1991-09-24 Bull Hn Information Systems Inc. Apparatus and method for address translation of non-aligned double word virtual addresses

Also Published As

Publication number Publication date
US5123097A (en) 1992-06-16
KR900012279A (ko) 1990-08-03
JP2575219B2 (ja) 1997-01-22
SG48794A1 (en) 1998-05-18
AU4762790A (en) 1990-07-12
EP0377436A3 (en) 1991-11-21
AU616831B2 (en) 1991-11-07
YU47428B (sh) 1995-03-27
KR950000549B1 (ko) 1995-01-24
CA2007167A1 (en) 1990-07-05
EP0377436A2 (en) 1990-07-11
JPH02239331A (ja) 1990-09-21
CA2007167C (en) 1994-04-05

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