WO2025255944A1 - 一种氧化硅自整流忆阻器及其制备方法 - Google Patents

一种氧化硅自整流忆阻器及其制备方法

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Publication number
WO2025255944A1
WO2025255944A1 PCT/CN2024/113384 CN2024113384W WO2025255944A1 WO 2025255944 A1 WO2025255944 A1 WO 2025255944A1 CN 2024113384 W CN2024113384 W CN 2024113384W WO 2025255944 A1 WO2025255944 A1 WO 2025255944A1
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Prior art keywords
memristor
silicon oxide
functional layer
oxygen
layer
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PCT/CN2024/113384
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English (en)
French (fr)
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程晓敏
冯少鹏
罗云皓
缪向水
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Huazhong University of Science and Technology
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Huazhong University of Science and Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/25—Multistable switching devices, e.g. memristors based on bulk electronic defects, e.g. trapping of electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides

Definitions

  • This application belongs to the field of microelectronic devices, and more specifically, relates to a silicon oxide self-rectified memristor and its fabrication method.
  • Memristors with their simple structure, suitability for 3D integration, fast switching speed, and low power consumption, have become a highly anticipated new type of memory in the post-Moore era.
  • Drain current is the primary challenge in 3D integration.
  • a voltage is applied to the select cell electrode in the array, in addition to the corresponding select current, a drain current flows through other low-resistance cells.
  • the current read by the device is the sum of the select current and the drain current, leading to misreading.
  • a conventional method to address drain current is to connect a gating device to each memristor cell.
  • the additional gating devices increase manufacturing costs and peripheral circuit complexity, reducing chip integration density.
  • a high voltage is required for initialization (forming). This causes the resistive switching material to undergo soft breakdown, forming conductive filaments. Subsequent electrical operations then cause these filaments to melt or grow. The random growth of these filaments is difficult to address, ultimately leading to poor consistency in the device's electrical characteristics.
  • the high-voltage forming process can also cause device breakdown, reducing memristor reliability and increasing the complexity of the external circuitry.
  • the purpose of this application is to provide a silicon oxide self-rectified memristor and its fabrication method, aiming to solve the problems of drain current and the need for high-voltage forming in memristor arrays.
  • the memristor is processed by a low-temperature annealing process, which causes the functional layer and the upper electrode to react and form a silicon oxide oxygen-deficient layer at the contact interface between the functional layer and the upper electrode.
  • the upper electrode is an Al, Ti, or Ta metal electrode
  • the lower electrode is a Pt electrode
  • the thickness of the functional layer is less than or equal to 20 nm.
  • step S50 the device prepared in step S40 is placed in an annealing furnace for low-temperature annealing, so that the functional layer and the upper electrode react and form a silicon oxide oxygen-deficient layer at the contact interface between the functional layer and the upper electrode.
  • step S50 the annealing temperature in the low-temperature annealing process is controlled at 300°C ⁇ 550°C, and the annealing time is 500 seconds ⁇ 2500 seconds.
  • the functional layer is prepared by chemical vapor deposition or physical vapor deposition.
  • both the upper electrode and the lower electrode are prepared by physical vapor deposition or chemical vapor deposition.
  • the upper electrode is patterned on the functional layer using photolithography.
  • the potential barrier difference between the upper electrode and the functional layer is small, when a positive bias voltage is applied to the lower electrode and the upper electrode is grounded, under the action of the electric field, the charge is easy to flow from the upper electrode to the silicon oxide oxygen-deficient layer and be captured by the oxygen vacancy trap, thereby reducing the resistance of the memristor.
  • the lower electrode and the functional layer have a high potential barrier difference, which can effectively suppress the charge from flowing from the lower electrode to the silicon oxide oxygen-deficient layer.
  • the device current value is very low, which is equivalent to cutoff. This self-rectification effect prevents the leakage current from passing through.
  • the memristor provided in this application does not need to add an additional gating device to suppress the leakage current, which is beneficial to the improvement of three-dimensional integration and provides a reliable solution to the leakage current problem of the memristor array.
  • Memristors rely on the capture and release of charge in the oxygen-deficient layer of silicon oxide to complete the resistive switching process. By applying different voltages to the electrodes, memristors can have multiple conduction states, thus possessing reliable conductivity. Multi-value storage characteristics; at the same time, since there is no growth and breakage process of conductive wires, there is no high-voltage forming process, which can effectively improve the reliability of memristors and reduce the complexity of peripheral circuits.
  • SiO2 and/or oxygen-deficient SiO2 layers as memristor functional layer materials is low-cost, has a mature fabrication process, and is compatible with CMOS processes. Moreover, the fabrication method provided in this application is simple and efficient, and can be applied to large-scale, high-density planar or three-dimensional integrated arrays.
  • Figure 1 is a flowchart of the method for fabricating the silicon oxide self-rectifying memristor provided in this application;
  • Figure 2 is a schematic diagram of the structure of the silicon oxide self-rectifying memristor before and after annealing according to a specific embodiment of this application;
  • Figure 3 is a flowchart of the method for fabricating a silicon oxide self-rectifying memristor provided in a specific embodiment of this application;
  • Figure 4 is a current-voltage curve of the silicon oxide self-rectifying memristor before annealing provided in a specific embodiment of this application.
  • Figure 5 is a current-voltage curve of the silicon oxide self-rectifying memristor after annealing according to a specific embodiment of this application.
  • Figure 6 is a multi-value preservation characteristic diagram provided in a specific embodiment of this application.
  • Figure 7 is a band structure diagram provided in a specific embodiment of this application.
  • references to “an embodiment”; “an embodiment,” “an example,” or similar language indicate that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of this application. Therefore, the appearance of the phrase “in one embodiment;” throughout this specification, and similar language, may, but not necessarily, refer to the same embodiment.
  • this application provides a silicon oxide self-rectifying memristor, which sequentially comprises a substrate, a lower electrode, a functional layer, and an upper electrode.
  • the functional layer includes a silicon oxide oxygen-deficient layer, where oxygen vacancies serve as traps for capturing and releasing charges.
  • the memristor provided in this application utilizes the charge trapping and release mechanism of oxygen vacancy traps to achieve resistance changes. Specifically, when a negative voltage is applied between the upper and lower electrodes (i.e., a positive bias is applied to the lower electrode and the upper electrode is grounded), charge enters the oxygen-deficient layer of silicon oxide from the upper electrode and is gradually trapped by the oxygen vacancy traps, causing the resistance of the memristor to gradually decrease. When the oxygen vacancy traps are filled, the resistance of the memristor drops to its lowest value.
  • This resistive switching process allows the memristor provided in this application to obtain stable multi-value storage characteristics by applying different voltages between its upper and lower electrodes.
  • the memristor needs to undergo a low-temperature annealing process before use. This process causes a redox reaction between the SiO2 and the upper electrode, resulting in the loss of oxygen at the contact interface between the functional layer and the upper electrode, forming an oxygen-deficient phase, i.e., an oxygen-deficient interface layer.
  • the oxygen vacancies in the oxygen-deficient phase act as traps for capturing and releasing charges.
  • the upper electrode provided in this application can preferably be made of a material that is easily oxidized to facilitate its reaction with the functional layer.
  • the memristor can be treated with a low-temperature annealing process before use or without such treatment.
  • the SiO2 and the oxygen-deficient SiO X layers will undergo redox reactions with the easily oxidized upper electrode, causing the contact interface between the functional layer and the upper electrode to lose oxygen and form an oxygen-deficient phase.
  • the oxygen-deficient SiO X layer When not treated with a low-temperature annealing process, it is preferable to place the oxygen-deficient SiO X layer close to the lower part of the upper electrode, so that it directly serves as the oxygen-deficient interface layer between SiO2 and the upper electrode.
  • the memristor can be treated with a low-temperature annealing process before use or without such treatment.
  • the oxygen-deficient SiO2 layer will undergo a redox reaction with the easily oxidized upper electrode, further losing oxygen, so that the contact interface between the functional layer and the upper electrode loses oxygen and forms an oxygen-deficient phase.
  • the functional layer can be directly used as a silicon oxide oxygen-deficient layer.
  • the thickness of the functional layer can be set to less than or equal to 20 nm.
  • the materials of the substrate, upper electrode, and lower electrode provided in this application can be made of materials commonly used in the field of memristors, and this application does not impose any restrictions. Considering that traditional substrate materials include SiO2 , in order to prevent the substrate material from reacting with the lower electrode during the low-temperature annealing process of the memristor, the lower electrode material provided in this application is preferably made of an inert material.
  • this application provides a connection between the upper electrode and the functional layer.
  • the potential barrier difference must be less than the potential barrier difference formed between the lower electrode and the functional layer.
  • the upper electrode provided in this application can be an Al, Ti, or Ta metal electrode, and the lower electrode can be a Pt electrode.
  • the potential barrier difference between the upper electrode and the functional layer provided in this application is small, when a positive bias voltage is applied to the lower electrode and the upper electrode is grounded, under the action of the electric field, the charge easily flows from the upper electrode to the silicon oxide-deficient layer and is captured by oxygen vacancy traps, thereby reducing the resistance of the memristor.
  • the lower electrode and the functional layer have a high potential barrier difference, which can effectively suppress the flow of charge from the lower electrode to the silicon oxide-deficient layer.
  • the device current value is very low, which is equivalent to cutoff. This self-rectification effect prevents the leakage current from passing through.
  • the memristor provided in this application does not need to add an additional gating device to suppress the leakage current. Furthermore, since the memristor provided in this application relies on the capture and release of charge in the silicon oxide-deficient layer to complete the resistive switching process, there is no growth and breakage process of conductive wires. Therefore, there is no high-voltage forming process, which can effectively improve the reliability of the memristor and reduce the complexity of the peripheral circuit.
  • this application also provides a method for fabricating the aforementioned silicon oxide self-rectifying memristor, as shown in Figure 1, including steps S10 to S50, which are detailed below:
  • the substrate may be made of Si/ SiO2 material.
  • the lower electrode can be prepared by physical vapor deposition or chemical vapor deposition.
  • the functional layer adopts a single-layer or multi-layer stacked structure containing only SiO2 and/or oxygen-deficient SiO2 X layers, where 0 ⁇ X ⁇ 2.
  • the functional layer can be prepared by chemical vapor deposition (CVD) or physical vapor deposition (PVD).
  • the upper electrode can be prepared by physical vapor deposition or chemical vapor deposition.
  • the electrode can be patterned on the functional layer using photolithography.
  • step S50 the device prepared in step S40 is placed in an annealing furnace for low-temperature annealing, so that the functional layer and the upper electrode react and form a silicon oxide oxygen-deficient layer at the contact interface between the functional layer and the upper electrode.
  • the device prepared in step S40 can be annealed in an annealing furnace under a N2 atmosphere or a vacuum environment, which is not limited in this application.
  • the annealing temperature in the low-temperature annealing process can be controlled between 300°C and 550°C, and the annealing time can be between 500 seconds and 2500 seconds.
  • the potential barrier difference between the upper electrode and the functional layer is small, when a positive bias voltage is applied to the lower electrode and the upper electrode is grounded, under the action of the electric field, the charge is easy to flow from the upper electrode to the silicon oxide oxygen-deficient layer and be captured by the oxygen vacancy trap, thereby reducing the resistance of the memristor.
  • the lower electrode and the functional layer have a high potential barrier difference, which can effectively suppress the charge from flowing from the lower electrode to the silicon oxide oxygen-deficient layer.
  • the device current value is very low, which is equivalent to cutoff. This self-rectification effect prevents the leakage current from passing through.
  • the memristor provided in this application does not need to add an additional gating device to suppress the leakage current, which is beneficial to the improvement of three-dimensional integration and provides a reliable solution to the leakage current problem of the memristor array.
  • Memristors rely on the capture and release of charge in the oxygen-deficient layer of silicon oxide to complete the resistive switching process. By applying different voltages to the electrodes, memristors can have multiple conduction states and have reliable multi-value storage characteristics. At the same time, since there is no growth and breakage process of conductive wires, there is no large voltage forming process, which can effectively improve the reliability of memristors and reduce the complexity of peripheral circuits.
  • SiO2 and/or oxygen-deficient SiO2 layers as memristor functional layer materials is low-cost, has a mature fabrication process, and is compatible with CMOS processes. Moreover, the fabrication method provided in this application is simple and efficient, and can be applied to large-scale, high-density planar or three-dimensional integrated arrays.
  • a 10 nm SiO2 thin film was deposited on the Pt electrode using plasma-enhanced chemical vapor deposition (PECVD).
  • PECVD plasma-enhanced chemical vapor deposition
  • the deposition temperature was 300 °C
  • the reaction pressure was 850 mTorr
  • the reaction gas source was 5% SiH4 / N2 , N2 , N2O .
  • the upper electrode pattern is lithographically patterned on the functional layer using ultraviolet lithography and prepared through six processes: homogenization, pre-baking, pre-exposure, post-baking, post-exposure, and development.
  • DC magnetron sputtering was used with a power of 30W, an argon flow rate of 40sccm, and a gas pressure of 0.5Pa.
  • the target material was metallic Ti.
  • a Ti electrode with a thickness of 100nm was deposited.
  • the upper electrode was square with dimensions of 50 ⁇ m ⁇ 50 ⁇ m, 100 ⁇ m ⁇ 100 ⁇ m, 200 ⁇ m ⁇ 200 ⁇ m, and 300 ⁇ m ⁇ 300 ⁇ m.
  • step (6) Soak the sample prepared in step (5) in acetone for 15 to 30 minutes, then wash it with anhydrous ethanol and deionized water, and dry it with nitrogen.
  • step (7) Place the sample prepared in step (6) into an annealing furnace and anneal it in an atmosphere of N2 .
  • the temperature is set to 500°C and the holding time is 1500 seconds.
  • the unannealed and annealed Pt/ SiO2 /Ti memristor structures were prepared as shown in Figure 2.
  • the left side shows the unannealed device unit structure after performing processes (1) to (6), where 100 is the substrate, 101 is the lower electrode Pt, 102 is the functional layer SiO2 , and 103 is the upper electrode Ti.
  • the annealed self-rectifying memristor structure is shown on the right side of Figure 2. This memristor was annealed in an annealing furnace at 500°C under nitrogen atmosphere with a nitrogen flow rate of 1 Ln/min. Since metallic Ti is an electrode that is easily oxidized, the functional layer SiO2 ... The upper electrode Ti reacts with the contact interface to form an oxygen-deficient interface layer 104.
  • the oxygen-deficient phase includes TiO2X and SiO2X , where 0 ⁇ X ⁇ 2.
  • this specific embodiment uses PECVD to deposit a 10nm SiO2 thin film as the functional layer.
  • the deposition temperature is 300°C
  • the reaction pressure is 850mTorr
  • the reaction gas source is 5% SiH4 / N2 , N2 , and N2O , with corresponding gas flow rates of 400sccm, 400sccm, and 1000sccm, respectively.
  • the fabrication process of this specific embodiment is simple and efficient, and can be applied to large-scale, high-density planar or three-dimensional silicon oxide self-rectified memristor integrated arrays.
  • the DC voltage scan performance of the Pt/ SiO2 /Ti memristors without and after annealing in this specific embodiment is compared.
  • the memristor without the annealing step of the preparation process (7) does not exhibit rectification and non-volatile resistive switching characteristics.
  • the rectification ratio of the memristor is greater than 104 at a read voltage of 1.5V. This can effectively solve the leakage current problem of the three-dimensional integrated array and is beneficial to improving the integration density of the memristor array.
  • the memristor provided in this specific embodiment exhibits an on/off ratio as high as 221 at a read voltage of 1.5V.
  • Figure 6 shows the resistance retention characteristics of the annealed Pt/ SiO2 /Ti self-rectified memristor in this specific embodiment when a 2V read voltage is applied at room temperature.
  • the annealed Pt/ SiO2 /Ti self-rectified memristor in this specific embodiment can stably maintain its resistance for 700 seconds in four resistance states, exhibiting reliable non-volatility and multi-value characteristics, which is of great significance for improving the storage capacity of memristors.
  • Figure 7 shows the band structure of the annealed Pt/ SiO2 /Ti self-rectifying memristor in this specific embodiment. Due to the small barrier difference (3.35 eV) between the upper electrode Ti and SiO2 , under the influence of an electric field, charge easily enters the oxygen-deficient interface layer from the upper electrode and is captured by oxygen vacancy traps, thereby reducing the resistance of the memristor device—the SET process. When a negative bias is applied to the lower Pt electrode and the upper electrode is grounded, charge is released from the oxygen-deficient interface layer, increasing the device resistance—the RESET process.
  • the inert lower electrode Pt has a high barrier difference (4.65 eV) between it and SiO2 , effectively suppressing charge flow from Pt to the oxygen-deficient interface layer.
  • the significant barrier asymmetry formed on both sides of the upper and lower electrodes gives the annealed Pt/ SiO2 /Ti memristor strong self-rectifying characteristics, making this type of device well-suited for large-scale and high-density arrays, with great application potential.

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Abstract

一种氧化硅自整流忆阻器及其制备方法，该忆阻器依次包括衬底、下电极、功能层及上电极，上电极与功能层之间形成的势垒差小于下电极与功能层之间形成的势垒差；功能层包括氧化硅缺氧层，氧化硅缺氧层的氧空位为俘获和释放电荷的陷阱；忆阻器利用氧空位陷阱的电荷俘获和释放机制实现电阻的变化，当在上电极和下电极之间施加负向电压时，电荷从上电极进入氧化硅缺氧层，逐渐被氧空位陷阱俘获，忆阻器的阻值逐渐降低；当在上电极和下电极之间施加正向电压时，电荷从氧化硅缺氧层中移出，逐渐被氧空位陷阱释放，忆阻器的阻值逐渐升高。该忆阻器可有效解决传统离子迁移型忆阻器阵列中漏径电流以及需要大电压Forming问题。

Description

一种氧化硅自整流忆阻器及其制备方法 【技术领域】
本申请属于微电子器件领域，更具体地，涉及一种氧化硅自整流忆阻器及其制备方法。
【背景技术】
忆阻器凭借结构简单、适用于三维集成、开关速度快、功耗低等特点，成为后摩尔时代备受瞩目的新型存储器。
在忆阻器阵列中，随着集成密度上升，诸如漏径电流、线电阻、热串扰等严重制约着器件集成度的问题逐渐凸显。漏径电流(sneak path current)是三维集成中面临的首要难题，在阵列中对选择单元电极施加电压之后，除了会产生对应的选择电流，还有流经其他低阻单元的漏径电流。器件最后读取的电流是选择电流与漏径电流之和，从而导致误读。解决漏径电流的常规方法是将每一个忆阻器单元连接一个选通器件，而额外的选通器件增加了制造成本和外围电路复杂度，降低了芯片集成密度。
此外，在对常规基于离子迁移机制的氧化物忆阻器的上下电极施加电压时，需要一个大电压进行初始化操作(Forming)，从而使得阻变材料软击穿形成导电细丝，之后通过相应的电操作使导电丝熔断或生长，导电丝的随机性生长问题难以解决，最终导致器件的电特性一致性较差。大电压Forming过程可能会造成器件击穿，降低忆阻器可靠性，增加外围电路的复杂度。
因此，如何解决忆阻器阵列中漏径电流以及需要大电压Forming问题，是亟需研究的。
【发明内容】
针对现有技术的缺陷，本申请的目的在于提供一种氧化硅自整流忆阻器及其制备方法，旨在解决忆阻器阵列中漏径电流以及需要大电压Forming的问题。
为实现上述目的，第一方面，本申请提供了一种氧化硅自整流忆阻器，依次包括衬底、下电极、功能层及上电极，所述上电极与功能层之间形成的势垒差小于所述下电极与功能层之间形成的势垒差；
所述功能层包括氧化硅缺氧层，氧化硅缺氧层的氧空位为俘获和释放电荷的陷阱；所述忆阻器利用氧空位陷阱的电荷俘获和释放机制实现电阻的变化，当在所述上电极和下电极之间施加负向电压时，电荷从上电极进入所述氧化硅缺氧层，逐渐被氧空位陷阱俘获，忆阻器的阻值逐渐降低；当在所述上电极和下电极之间施正向电压时，电荷从氧化硅缺氧层中移出，逐渐被氧空位陷阱释放，忆阻器的阻值逐渐升高。
作为进一步优选的，所述功能层采用只包含SiO2及/或缺氧SiOX层的单层或多层叠加结构，其中，0<X<2；所述上电极采用易被氧化的材料制成，所述下电极采用惰性材料制成；
当所述功能层为SiO2单层时，所述忆阻器通过低温退火工艺处理，使得所述功能层和上电极发生反应，在功能层和上电极之间的接触界面形成氧化硅缺氧层。
作为进一步优选的，所述上电极采用Al、Ti或Ta金属电极，所述下电极采用Pt电极。
作为进一步优选的，所述功能层的厚度小于或等于20nm。
作为进一步优选的，所述忆阻器通过对其上电极和下电极之间施加不同大小的电压，可获得稳定的多值存储特性。
第二方面，本申请提供了一种如上述所述的氧化硅自整流忆阻器的制备方法，包括如下步骤：
S10，准备衬底；
S20，在所述衬底上沉积下电极；
S30，在所述下电极上沉积功能层，所述功能层采用只包含SiO2及/或缺氧SiOX层的单层或多层叠加结构，其中，0<X<2；
S40，在所述功能层上沉积并图形化上电极；
S50，将步骤S40制备的器件放入退火炉中进行低温退火工艺处理，使得所述功能层和上电极发生反应，在功能层和上电极之间的接触界面形成氧化硅缺氧层。
作为进一步优选的，在步骤S50中，低温退火工艺中的退火温度控制在300℃～550℃，退火时间为500秒～2500秒。
作为进一步优选的，所述功能层采用化学气相沉积法或物理气相沉积法制备而成。
作为进一步优选的，所述上电极和下电极均采用物理气相沉积法或化学气相沉积法制备而成。
作为进一步优选的，采用光刻技术在所述功能层上图形化上电极。
本申请提供的氧化硅自整流忆阻器及其制备方法，具有如下效果：
(1)由于上电极和功能层之间的势垒差较小，当在下电极施加正偏压，上电极接地时，在电场的作用下，电荷容易从上电极流向氧化硅缺氧层，被氧空位陷阱俘获，从而降低忆阻器的电阻，而下电极与功能层之间具有较高的势垒差，从而可有效抑制电荷从下电极流向氧化硅缺氧层中；当对下电极施加负偏压，上电极接地时，器件电流值非常低，相当于截止，这种自整流效果使漏径电流无法通过，因此对忆阻器阵列中不参与读写的器件施加适当的偏压即可抑制漏径电流，从而使得本申请提供的忆阻器不需要额外增加选通器件即可抑制漏径电流，有利于三维集成度的提升，为忆阻器阵列的漏径电流问题提供可靠的解决方案；
(2)忆阻器依靠电荷在氧化硅缺氧层中的俘获和释放完成阻变过程，通过对电极施加大小不同的电压，能使忆阻器有多个电导态，具有可靠的 多值存储特性；同时，由于没有导电丝的生长和断裂过程，因此无大电压Forming过程，可有效提高忆阻器可靠性，降低外围电路的复杂度；
(3)使用SiO2及/或缺氧SiOX层作为忆阻器功能层材料，成本低，制备工艺成熟，CMOS工艺兼容性好；而且本申请提供的制备方法简单高效，能够应用于大规模、高密度平面或者三维集成阵列中。
【附图说明】
图1是本申请提供的氧化硅自整流忆阻器的制备方法的流程图；
图2是本申请具体实施例提供的氧化硅自整流忆阻器退火前后的结构示意图；
图3是本申请具体实施例提供的氧化硅自整流忆阻器的制备方法的流程图；
图4是本申请具体实施例提供的氧化硅自整流忆阻器退火前的电流电压曲线图；
图5是本申请具体实施例提供的氧化硅自整流忆阻器退火后的电流电压曲线图；
图6是本申请具体实施例提供的多值保持特性图；
图7是本申请具体实施例提供的能带结构图。
【具体实施方式】
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需要理解的是，在本申请的描述中，术语“若干”的含义是至少一个，例如一个，两个等，除非另有明确具体的限定；术语“多个”的含义是两个或两个以上，除非另有明确具体的限定；术语“第一”和“第二”等是用于区别不 同的对象，而不是用于描述对象的特定顺序；术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
另外，贯穿本说明书对“一个实施例”的引用；“一个实施例”、“一个示例”或类似的语言表示结合该实施例描述的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，短语“在一个实施例中；”的出现贯穿本说明书的“在一个实施例中”和类似的语言可能但不一定都指代相同的实施例。
为解决传统忆阻器阵列中漏径电流以及需要大电压Forming问题，本申请提供了一种氧化硅自整流忆阻器，该忆阻器依次包括衬底、下电极、功能层及上电极。
其中，功能层包括氧化硅缺氧层，氧化硅缺氧层的氧空位为俘获和释放电荷的陷阱。
本申请提供的忆阻器利用氧空位陷阱的电荷俘获和释放机制以实现电阻的变化，即当在上电极和下电极之间施加负向电压(即在下电极施加正偏压，上电极接地)时，电荷从上电极进入氧化硅缺氧层，逐渐被氧空位陷阱俘获，使得忆阻器的阻值逐渐降低，当氧空位陷阱填满时忆阻器的阻值降到最低；当在上电极和下电极之间施正向电压(即在下电极施加负偏压，上电极接地)时，电荷从氧化硅缺氧层中移出，逐渐被氧空位陷阱释放，使得忆阻器的阻值逐渐升高，当陷阱中的电荷全部释放时忆阻器的阻值升到最高。
该阻变过程可使得本申请提供的忆阻器通过对其上电极和下电极之间施加不同大小的电压，可获得稳定的多值存储特性。
具体地，本申请提供的功能层可采用只包含SiO2及/或缺氧SiOX层的单层或多层叠加结构，其中，0<X<2。可以理解的是，本申请提供的功能层可以为SiO2单层、缺氧SiOX单层、SiO2与不同X值的缺氧SiOX层组成的两层或两层以上叠加结构、或者不同X值的缺氧SiOX层组成的两层或两层 以上叠加结构。
需要说明的是，当本申请提供的功能层采用SiO2单层结构时，在该忆阻器使用前，需对该忆阻器进行低温退火工艺处理，使得SiO2与上电极发生氧化还原反应，在该功能层和上电极之间的接触界面失氧形成缺氧相，即形成缺氧界面层，缺氧相的氧空位作为俘获和释放电荷的陷阱。具体地，本申请提供的上电极可优选采用易被氧化的材料制成，便于其与功能层发生反应。
当功能层采用SiO2与不同X值的缺氧SiOX层组成的两层或两层以上叠加结构，该忆阻器在使用前可经过低温退火工艺处理也可以不经过低温退火工艺处理，当经过低温退火工艺处理时，SiO2和缺氧SiOX层会分别与易被氧化的上电极发生氧化还原反应，使得该功能层和上电极之间的接触界面失氧形成缺氧相，当不经过低温退火工艺处理时，可优选将缺氧SiOX层紧贴设置在上电极的下方，使得其直接作为SiO2与上电极之间的缺氧界面层。
当功能层为缺氧SiOX单层或不同X值的缺氧SiOX层组成的两层或两层以上叠加结构时，该忆阻器在使用前可经过低温退火工艺处理也可以不经过低温退火工艺处理，当经过低温退火工艺处理时，缺氧SiOX层会与易被氧化的上电极发生氧化还原反应，进一步失氧，使得该功能层和上电极之间的接触界面失氧形成缺氧相，当不经过低温退火工艺处理时，该功能层可直接作为氧化硅缺氧层。
优选地，功能层的厚度可设置为小于或等于20nm。
本申请提供的衬底、上电极和下电极的材料可采用忆阻器领域常用的材料制成，本申请不作限制，考虑到传统的衬底材料包括SiO2，为防止在对忆阻器进行低温退火工艺处理时衬底材料与下电极发生反应，对此，本申请提供的下电极材料优选采用惰性材料制成。
另外，为解决漏径电流问题，本申请提供的上电极与功能层之间形成 的势垒差必须小于下电极与功能层之间形成的势垒差。具体地，本申请提供的上电极可采用Al、Ti或Ta金属电极，下电极可采用Pt电极。
由于本申请提供的上电极与功能层的势垒差较小，当在下电极施加正偏压，上电极接地时，在电场的作用下，电荷容易从上电极流向氧化硅缺氧层，被氧空位陷阱俘获，从而降低忆阻器的电阻，而下电极与功能层之间具有较高的势垒差，从而可有效抑制电荷从下电极流向氧化硅缺氧层中；当对下电极施加负偏压，上电极接地时，器件电流值非常低，相当于截止，这种自整流效果使漏径电流无法通过，因此对忆阻器阵列中不参与读写的器件施加适当的偏压即可抑制漏径电流，从而使得本申请提供的忆阻器不需要额外增加选通器件即可抑制漏径电流；且由于本申请提供的忆阻器依靠电荷在氧化硅缺氧层中的俘获和释放完成阻变过程，没有导电丝的生长和断裂过程，因此无大电压Forming过程，可有效提高忆阻器的可靠性，降低外围电路的复杂度。
此外，本申请还提供了一种面向上述氧化硅自整流忆阻器的制备方法，如图1所示，包括步骤S10～S50，详述如下：
S10，准备衬底。
在步骤S10中，衬底可采用Si/SiO2材料。
S20，在衬底上沉积下电极。
在步骤S20中，下电极可采用物理气相沉积法或化学气相沉积法制备而成。
S30，在下电极上沉积功能层，功能层采用只包含SiO2及/或缺氧SiOX层的单层或多层叠加结构，其中，0<X<2。
在步骤S30中，功能层可采用化学气相沉积法(CVD)或物理气相沉积法(PVD)制备而成。
S40，在功能层上沉积并图形化上电极。
在步骤S40中，上电极可采用物理气相沉积法或化学气相沉积法制备 而成。在功能层上可采用光刻技术图形化上电极。
S50，将步骤S40制备的器件放入退火炉中进行低温退火工艺处理，使得功能层和上电极发生反应，在功能层和上电极之间的接触界面形成氧化硅缺氧层。
具体地，步骤S40制备的器件可在退火炉中N2氛围下或真空环境下进行退火，本申请不作限制。为更好地使功能层和上电极发生反应形成氧化硅缺氧层，低温退火工艺中的退火温度可控制在300℃～550℃，退火时间为500秒～2500秒。
本申请提供的氧化硅自整流忆阻器及其制备方法，具有如下效果：
(1)由于上电极和功能层之间的势垒差较小，当在下电极施加正偏压，上电极接地时，在电场的作用下，电荷容易从上电极流向氧化硅缺氧层，被氧空位陷阱俘获，从而降低忆阻器的电阻，而下电极与功能层之间具有较高的势垒差，从而可有效抑制电荷从下电极流向氧化硅缺氧层中；当对下电极施加负偏压，上电极接地时，器件电流值非常低，相当于截止，这种自整流效果使漏径电流无法通过，因此对忆阻器阵列中不参与读写的器件施加适当的偏压即可抑制漏径电流，从而使得本申请提供的忆阻器不需要额外增加选通器件即可抑制漏径电流，有利于三维集成度的提升，为忆阻器阵列的漏径电流问题提供可靠的解决方案；
(2)忆阻器依靠电荷在氧化硅缺氧层中的俘获和释放完成阻变过程，通过对电极施加大小不同的电压，能使忆阻器有多个电导态，具有可靠的多值存储特性；同时，由于没有导电丝的生长和断裂过程，因此无大电压Forming过程，可有效提高忆阻器可靠性，降低外围电路的复杂度；
(3)使用SiO2及/或缺氧SiOX层作为忆阻器功能层材料，成本低，制备工艺成熟，CMOS工艺兼容性好；而且本申请提供的制备方法简单高效，能够应用于大规模、高密度平面或者三维集成阵列中。
下面结合具体实施例对本申请提供的氧化硅自整流忆阻器及其制备方 法做详细说明。
本具体实施例提供的氧化硅自整流忆阻器结构为Pt/SiO2/Ti，其中，下电极为Pt，功能层为SiO2，上电极为Ti，具体制备工艺流程如下(未描述衬底清洗过程)：
(1)提前准备好Si/SiO2衬底；
(2)在衬底上直流磁控溅射，功率30W，氩气流量40sccm，气压维持在0.5Pa，靶材为金属Ti，沉积10nm厚度的Ti电极作为下电极和衬底的黏附层；随后功率设为40W，气压0.5Pa，氩气流量40sccm，靶材为Pt金属靶，沉积100nm厚度的Pt电极；
(3)使用等离子体增强化学气相沉积法(PECVD)在Pt电极上面沉积10nm SiO2薄膜，沉积温度为300℃，反应压力为850mTorr，反应气源为5％SiH4/N2、N2、N2O；
(4)采用紫外光刻技术在功能层上光刻出上电极图形，通过匀胶、前烘、前曝、后烘、后爆、显影等六个过程制备；
(5)采用直流磁控溅射，功率30W，氩气流量40sccm，气压维持在0.5Pa，靶材为金属Ti，沉积100nm厚度的Ti电极，上电极为方块状，尺寸为50μm×50μm、100μm×100μm、200μm×200μm、300μm×300μm；
(6)将步骤(5)所制备出的样品放在丙酮中浸泡15～30分钟，再用无水乙醇和去离子水清洗，用氮气吹干；
(7)将步骤(6)制备出的样品放入退火炉中，在N2的气氛下退火，温度设置为500℃，保持时间为1500秒。
完成上述步骤后制备出未退火和退火的Pt/SiO2/Ti忆阻器结构如图2所示，其中左侧为执行工艺(1)～(6)后的未退火器件单元结构，100为衬底，101为下电极Pt，102为功能层SiO2，103为上电极Ti，退火后的自整流忆阻器结构如图2右侧所示，该忆阻器放入退火炉中在500℃氮气环境下退火，氮气流量为1Ln/min，由于金属Ti是容易被氧化的电极，功能层SiO2 与上电极Ti在接触界面发生反应形成缺氧界面层104，缺氧相包括TiOX和SiOX，其中，0<X<2。
如图3所示，本具体实施例采用PECVD沉积10nm SiO2薄膜作为功能层，沉积温度为300℃，反应压力为850mTorr，反应气源为5％ SiH4/N2、N2、N2O，对应气体流量分别为400sccm、400sccm、1000sccm，本具体实施例制备工艺简单高效，能够应用于大规模、高密度平面或者三维氧化硅自整流忆阻器集成阵列中。
如图4和5所示，本具体实施例Pt/SiO2/Ti未退火和退火的忆阻器直流电压扫描性能对比，没有执行制备工艺(7)退火步骤的忆阻器并没有表现出整流性和非易失阻变特性；对于完成退火步骤(7)的忆阻器，在1.5V的读电压下，该忆阻器整流比大于104，这可以很好地解决三维集成阵列的漏径电流问题，有利于提高忆阻器阵列的集成密度，本具体实施例提供的忆阻器在1.5V的读电压下展现了高达221的开关比。
图6为本具体实施例退火后的Pt/SiO2/Ti自整流忆阻器在室温下施加2V读电压时的阻值保持能力特性图，本具体实施例退火后的Pt/SiO2/Ti自整流忆阻器在四个阻态下能稳定保持700秒，具有可靠的非易失性和多值特性，这对提高忆阻器存储容量有重要意义。
图7为本具体实施例退火后的Pt/SiO2/Ti自整流忆阻器的能带结构图，由于上电极Ti和SiO2的势垒差较小，为3.35eV，在电场作用下，电荷容易从上电极进入缺氧界面层，被氧空位陷阱捕获，从而降低忆阻器件的电阻，即SET过程；对Pt下电极施加负偏压，上电极接地时，电荷从缺氧界面层中释放，器件电阻升高，即RESET过程。而惰性下电极Pt与SiO2之间具有高的势垒差，为4.65eV，从而有效地抑制电荷从Pt流向缺氧界面层，上下电极两侧形成的巨大的势垒不对称性，使得退火后的Pt/SiO2/Ti忆阻器具有较强的自整流特性，从而使得这类器件可以很好的应用到大规模和高密度阵列，具有极大的应用前景。
本领域的技术人员容易理解，以上所述仅为本申请的较佳实施例，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种氧化硅自整流忆阻器，其特征在于，依次包括衬底、下电极、功能层及上电极，所述上电极与功能层之间形成的势垒差小于所述下电极与功能层之间形成的势垒差；
    所述功能层包括氧化硅缺氧层，氧化硅缺氧层的氧空位为俘获和释放电荷的陷阱；所述忆阻器利用氧空位陷阱的电荷俘获和释放机制实现电阻的变化，当在所述上电极和下电极之间施加负向电压时，电荷从上电极进入所述氧化硅缺氧层，逐渐被氧空位陷阱俘获，忆阻器的阻值逐渐降低；当在所述上电极和下电极之间施正向电压时，电荷从氧化硅缺氧层中移出，逐渐被氧空位陷阱释放，忆阻器的阻值逐渐升高。
  2. 如权利要求1所述的氧化硅自整流忆阻器，其特征在于，所述功能层采用只包含SiO2及/或缺氧SiOX层的单层或多层叠加结构，其中，0<X<2；所述上电极采用易被氧化的材料制成，所述下电极采用惰性材料制成；
    当所述功能层为SiO2单层时，所述忆阻器通过低温退火工艺处理，使得所述功能层和上电极发生反应，在功能层和上电极之间的接触界面形成氧化硅缺氧层。
  3. 如权利要求1所述的氧化硅自整流忆阻器，其特征在于，所述上电极采用Al、Ti或Ta金属电极，所述下电极采用Pt电极。
  4. 如权利要求1所述的氧化硅自整流忆阻器，其特征在于，所述功能层的厚度小于或等于20nm。
  5. 如权利要求1所述的氧化硅自整流忆阻器，其特征在于，所述忆阻器通过对其上电极和下电极之间施加不同大小的电压，可获得稳定的多值存储特性。
  6. 一种如权利要求1所述的氧化硅自整流忆阻器的制备方法，其特征在于，包括如下步骤：
    S10，准备衬底；
    S20，在所述衬底上沉积下电极；
    S30，在所述下电极上沉积功能层，所述功能层采用只包含SiO2及/或缺氧SiOX层的单层或多层叠加结构，其中，0<X<2；
    S40，在所述功能层上沉积并图形化上电极；
    S50，将步骤S40制备的器件放入退火炉中进行低温退火工艺处理，使得所述功能层和上电极发生反应，在功能层和上电极之间的接触界面形成氧化硅缺氧层。
  7. 如权利要求6所述的氧化硅自整流忆阻器的制备方法，其特征在于，在步骤S50中，低温退火工艺中的退火温度控制在300℃～550℃，退火时间为500秒～2500秒。
  8. 如权利要求6所述的氧化硅自整流忆阻器的制备方法，其特征在于，所述功能层采用化学气相沉积法或物理气相沉积法制备而成。
  9. 如权利要求6所述的氧化硅自整流忆阻器的制备方法，其特征在于，所述上电极和下电极均采用物理气相沉积法或化学气相沉积法制备而成。
  10. 如权利要求6所述的氧化硅自整流忆阻器的制备方法，其特征在于，采用光刻技术在所述功能层上图形化上电极。
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