WO2025227635A1 - 一种面向交叉点阵铁电存储器的低扰动自恢复操作方法 - Google Patents

一种面向交叉点阵铁电存储器的低扰动自恢复操作方法

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Publication number
WO2025227635A1
WO2025227635A1 PCT/CN2024/128103 CN2024128103W WO2025227635A1 WO 2025227635 A1 WO2025227635 A1 WO 2025227635A1 CN 2024128103 W CN2024128103 W CN 2024128103W WO 2025227635 A1 WO2025227635 A1 WO 2025227635A1
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bit line
word line
voltage
memory cell
cross
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French (fr)
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黄芊芊
符芷源
曹胜杰
黄如
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Peking University
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Peking University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Definitions

  • This invention relates to the field of semiconductor memories, and in particular to a low-disturbance self-recovery operation method for cross-matrix ferroelectric memories.
  • DRAM Dynamic Random Access Memory
  • Conventional DRAM primarily achieves size reduction by shrinking the cell area of transistors and capacitors.
  • the large capacitor area requirements in DRAM and considerations for transistor reliability pose significant challenges to further miniaturization.
  • novel two-terminal non-volatile memories have been widely studied. These can form the smallest in-plane 4F2 cell area cross-matrix memory array and possess three-dimensional stacking capabilities, significantly increasing storage density.
  • Common two-terminal non-volatile devices include resistive devices (RRAM, MRAM, PCRAM, etc.) and capacitive devices (FeRAM).
  • RRAM resistive devices
  • MRAM MRAM
  • PCRAM PCRAM
  • FeRAM capacitive devices
  • cross-matrix memories based on ferroelectric capacitors due to their field-induced switching and polarization readout characteristics, feature ultra-low power access and fast readout. Furthermore, due to their good reliability and fluctuation characteristics, they are one of the popular technologies for next-generation memories.
  • hafnium oxide (HfO2 )-based ferroelectric materials exhibit excellent CMOS process compatibility and size reduction potential, making them more suitable for high-density memory fabrication and integration compared to traditional ferroelectric materials.
  • HfO2 -based ferroelectric materials due to the polycrystalline and multi-domain characteristics of HfO2 - based ferroelectric materials, and the wide coercive field distribution of their ferroelectric domains, unselected cells are subject to voltage pulse perturbations when writing information to cells in a cross-array without gated transistors.
  • ferroelectric memories read stored data through a destructive charge-sharing mechanism, the polarization charge of the original storage needs to be restored after the read operation, leading to a decrease in the overall access speed of the ferroelectric memory. Therefore, achieving a low-perturbation self-recovery operation method has become an urgent problem to be solved in cross-array ferroelectric memories.
  • This invention aims to propose a low-disturbance self-recovery operation method for cross-matrix ferroelectric memories. Operating a cross-matrix memory array using this invention enables the memory to exhibit smaller cell perturbations, lower bit error rates, and faster access speeds.
  • a low-disturbance self-recovery operation method for cross-matrix ferroelectric memory is disclosed.
  • This method operates on a CMM array.
  • the CMM array has multiple orthogonal word lines and bit lines. The intersection of each word line and bit line constitutes a memory cell.
  • Each memory cell is composed of a ferroelectric capacitor, which stores two data states through its spontaneous polarization direction: downward polarization corresponds to data "1", and upward polarization corresponds to data "0".
  • the operation method involves simultaneously applying voltage pulses to one word line and one bit line of the CMM array to select a memory cell in the array. This selected memory cell is called the selected memory cell, and all other memory cells are unselected memory cells.
  • the word line and bit line containing the selected memory cell are the selected word line and selected bit line, respectively, while all other word lines and bit lines are the unselected word line and unselected bit line, respectively.
  • the specific low-disturbance self-recovery operation method of this invention requires four consecutive pulse cycles to achieve. During the operation, only the selected word/bit line needs to be energized with voltage, while the unselected word/bit line always maintains the GND voltage.
  • a voltage pulse with an amplitude of Vdd /2 is applied to the selected word line, and the selected bit line remains floating to realize the data reading operation of the selected memory cell.
  • the data read is the change in the voltage signal of the selected bit line caused by the polarization charge generated by the polarization reversal of the ferroelectric dielectric of the selected memory cell under the high voltage access of Vdd ;
  • the voltage of the selected bit line is amplified to V dd /2 or -V dd / 2 by the external circuit connected to it.
  • the voltage of the selected bit line corresponds to the voltage value of the state stored in the selected memory cell. That is, if "1" is stored, it corresponds to V dd /2, and if "0" is stored, it corresponds to -V dd /2.
  • the voltage of the selected word line is set to -V dd /2 to realize the pre-charging of the selected word line and realize the data recovery of the selected memory cell.
  • the voltage of the selected word line and the selected bit line is set to GND to reset the selected memory cell and its word line and bit line.
  • the writing, reading, and automatic data recovery processes of a capacitive cross-matrix ferroelectric memory can be realized using the Vdd / 2 voltage operation mode.
  • the selected bit line is pre-charged to -Vdd / 2 and kept floating.
  • a Vdd /2 voltage is applied to the selected word line, and the selected memory cell is accessed by the Vdd voltage, reading data onto the selected bit line to realize the reading of the stored state data. Because the charge-sharing readout method of ferroelectric capacitors is destructive, the amount of polarization charge stored in the selected memory cell changes after being accessed.
  • the selected bit line voltage is amplified to Vdd / 2 or -Vdd /2, and the selected cell originally stored as "1" is accessed by the -Vdd / 2 voltage. When accessed by the dd voltage, a polarity flip occurs, and the previously stored data "1" is restored.
  • the selected previously stored "0" cell is accessed by the GND voltage, but its storage state remains unchanged.
  • the selected word line and selected bit line are reset, completing one read cycle, allowing data to be read from the next group of memory cells.
  • this operation method based on the Vdd /2 voltage pulse, can reduce cell write crosstalk to a certain extent while simultaneously completing the read and automatic recovery operations of the memory array data .
  • the low-disturbance self-recovery operation method of this invention is compatible with the standard "activation, read operation, write operation, precharge reset" memory operation logic. It combines write operation and precharge to achieve data self-recovery.
  • memory cells on unselected word lines and bit lines are not disturbed by voltage pulses.
  • the data in the selected memory cell is successfully read, and the state of the original "1" cell is destroyed.
  • a -Vdd voltage operation is applied to the original "1" cell to restore the data "1" without affecting the storage state of the "0" cell.
  • the low-disturbance self-recovery operation method of this invention can achieve smaller read/write disturbances, lower bit error rate, and faster access speed, further improving the reliability of high-density cross-matrix ferroelectric memories.
  • Figure 1 is a schematic diagram of the electrical properties of the cross-dot ferroelectric storage array of the low-disturbance self-recovery operation method of the present invention.
  • Figure 2 is a schematic diagram of the pulse waveform of the low-disturbance self-recovery operation method of the present invention.
  • the cross-matrix ferroelectric memory array has multiple orthogonal word lines and bit lines.
  • the intersection of each word line and bit line constitutes a memory cell. That is, the two sides of the memory cell array are connected by orthogonal word lines and bit lines.
  • the memory cell is composed of ferroelectric capacitors.
  • the word line and bit line containing the selected memory cell are the selected word line and selected bit line, respectively. All other memory cells are unselected memory cells.
  • the word line and bit line of the unselected memory cells are the unselected word line and unselected bit line, respectively.
  • the operation method requires four consecutive pulse cycles. During the operation, only the selected word/bit line needs to be energized, while the unselected word/bit line remains at GND voltage.
  • the selected memory cell is accessed, as shown in Figure 2.
  • a complete access operation consists of four cycles.
  • voltage pulses with amplitudes of GND and -Vdd / 2 are applied to the selected word line and bit line, respectively, while the unselected word line and bit line maintain the GND voltage.
  • the selected word line voltage is set to Vdd /2, and the selected bit line voltage remains floating.
  • the selected memory cell shares charge with the parasitic capacitance on the selected bit line.
  • the bit line voltage will rise significantly when the data "1" is read (corresponding to the solid line in the figure), and the bit line voltage will rise slightly when the data "0" is read (corresponding to the dashed line in the figure) .
  • the selected bit line voltage is amplified to Vdd / 2 or -Vdd /2 by the external read/write circuit, and then the selected word line voltage is set to -Vdd /2.
  • the selected memory cell that originally stored "1" is accessed by the -Vdd voltage to restore and write the data "1".
  • both the selected word line and selected bit line voltages are set to GND, realizing the reset of the selected memory cell and its corresponding word line and bit line.
  • This operation method avoids voltage pulse disturbances to non-word/bit line memory cells during access, resulting in smaller read/write disturbances and a lower bit error rate. It also allows for automatic recovery of the corrupted memory state after the selected memory cell read operation is completed, reducing the overall cycle time and enabling faster access speeds.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

一种面向交叉点阵铁电存储器的低扰动自恢复操作方法，属于半导体存储器技术领域。该方法对交叉点阵铁电存储器阵列进行操作，包括四个连续的脉冲周期，依次实现选中存储单元激活、数据读取、数据恢复以及复位操作。利用该低扰动自恢复操作方法，可以减小交叉点阵铁电电容存储器操作过程中未选中单元受到的电压脉冲扰动，同时实现了铁电电容型存储器数据自动恢复的功能；可以实现更小的读写扰动，更低的误码率，且具有更快的访问速度。

Description

一种面向交叉点阵铁电存储器的低扰动自恢复操作方法 技术领域
本发明涉及半导体存储器领域，特别涉及一种面向交叉点阵铁电存储器的低扰动自恢复操作方法。
 背景技术
在过去的几十年中，动态随机存取存储器（DRAM）因其高速读写、成本较低的特点，一直是存储系统中内存结构的主流选择，提升DRAM存储密度也是近年来的研究热点。常规DRAM主要通过缩小晶体管和电容的单元面积尺寸实现尺寸微缩，然而随着工艺节点的发展，晶体管特征尺寸的持续缩小，DRAM中较大的电容面积需求以及晶体管可靠性的考量使其进一步微缩带来较大挑战。近年来，基于二端的新型非易失性存储器被广泛研究，其可构成平面内最小的4F 2单元面积交叉点阵存储器阵列，且具备三维堆叠的能力，可大幅提升存储密度。常见的双端非易失性器件包括阻性器件（RRAM、MRAM、PCRAM等）和容性器件（FeRAM）。其中，基于铁电电容的交叉点阵存储器由于场致翻转与极化读出特点，具有超低功耗访问与快速读出的特点，且由于其具有良好的可靠性与涨落特性，是新一代存储器的热门技术路线之一。
在不同类型的铁电电容存储器中，氧化铪（HfO 2）基铁电材料的铁电电容具有优良的CMOS工艺兼容性和尺寸微缩潜力，相比传统铁电材料更适用于高密度存储器制备与集成。然而由于HfO 2基铁电材料具有多晶多畴的特性，且其铁电畴的矫顽场分布较宽，在向无选通晶体管的交叉点阵阵列中单元写入信息时，未被选中的单元会受到电压脉冲扰动；此外，由于铁电存储器通过破坏性的电荷共享方式读取存储数据，需要在读操作之后对原存储的极化电荷进行恢复，导致铁电存储器整体访问速度下降。因此，实现低扰动自恢复的操作方法成是交叉点阵铁电存储器中一个亟待解决的问题。
发明内容
本发明旨在提出一种面向交叉点阵铁电存储器的低扰动自恢复操作方法。采用本发明对交叉点阵存储器阵列进行操作，能够使存储器具有更小的单元扰动，更低的误码率和更快的访问速度。
本发明具体的技术方案如下：
一种面向交叉点阵铁电存储器的低扰动自恢复操作方法，该方法对交叉点阵铁电存储器阵列进行操作；所述交叉点阵铁电存储器阵列设有多条正交的字线与位线，每条字线与位线的交点为一个存储单元，所述存储单元由铁电电容器件构成，所述铁电电容器件通过自发极化方向存储两种数据状态，极化方向向下对应数据“1”，极化方向向上对应数据“0”；所述操作方法，分别对交叉点阵阵列的一字线与一位线同时施加电压脉冲以选中阵列中某存储单元，该单元称为选中存储单元，其他所有存储单元为未选中存储单元；所述选中存储单元所在的字线与位线为选中字线和选中位线，其他所有字线与位线为未选中字线和未选中位线。
本发明具体的低扰动自恢复操作方法需要四个连续脉冲周期实现，操作过程中仅需要对选中字/位线施加电压，未选中字/位线始终保持GND电压：
（1）在第一个周期中，对选中字线与选中位线分别施加幅度为GND与- V dd/2的电压脉冲，以激活选中字线与选中位线，并进行下一步操作；
（2）在第二个周期中，对选中字线施加幅度为 V dd/2的电压脉冲，选中位线保持浮置，以实现对选中存储单元的数据读取操作。其中，所述读取的数据为选中存储单元铁电电容的铁电介质在 V dd高电压访问下极化翻转产生的极化电荷量引起选中位线电压信号的变化；
（3）在第三个周期中，选中位线的电压通过与相连接的外围电路放大变为 V dd/2或- V dd/2，选中位线的电压与选中存储单元所存储状态电压值对应，即若存储“1”对应 V dd/2，存储“0”对应- V dd/2，随后将选中字线电压置为- V dd/2，以实现选中字线的预充电，同时实现对选中存储单元的数据恢复；
（4）在第四个周期中，将选中字线与选中位线的电压均置于GND，实现对选中存储单元及其所在字线与位线的复位。
采用本发明操作方法，可以利用 V dd/2电压操作模式实现电容型交叉点阵铁电存储器的写入、读出以及自动数据恢复过程。在第一、二个周期中，选中位线被预充至- V dd/2电位并保持浮空，随后对选中字线施加 V dd/2电压，选中存储单元会受到 V dd的电压访问，数据读取至选中位线上，实现存储状态数据的读取；由于铁电电容的电荷共享读出方式具有破坏性，选中存储单元在被访问之后，存储的极化电荷量会发生变化，其中，若选中单元原存“1”，读操作过程中极化翻转程度大，流失的极化电荷量多，状态发生严重破坏；若选中单元原存“0”，读操作过程中极化翻转程度微弱，流失的极化电荷量极少，状态几乎不变；因此需要对选中存储单元进行数据恢复；在第三个周期中，选中位线电压通过放大变为 V dd/2或- V dd/2，选中的原存“1”单元受到- V dd电压访问，发生极化翻转，原有存储的数据“1”得到恢复；选中的原存“0”单元受到GND电压访问，存储状态不发生变化；在第四个周期中，选中字线、选中位线复位，完成一次读取周期，可以进行下一组存储单元的数据读取。相比其他类型写入方式，本操作方式基于 V dd/2电压脉冲可以实现在一定程度降低单元写入串扰的同时，完成存储器阵列数据的读出以及自动恢复操作。
本发明的面向交叉点阵铁电存储器的低扰动自恢复操作方法有益效果及相应原理：
本发明的低扰动自恢复操作方法兼容标准的“激活、读操作、写操作、预充复位”存储器操作逻辑，其中将写操作和预充结合，实现了数据自恢复操作。当按照本发明的低扰动自恢复操作方法对交叉点阵铁电存储器某存储单元进行访问时，非选中字线和位线上的存储单元不会受到电压脉冲扰动，第一、二个周期中，选中存储单元中的数据被成功读出，原存“1”单元的状态被破坏，在第三个周期中，通过结合选中字线预充电的方式，对原存“1”单元施加- V dd电压操作，实现数据“1”的恢复，同时不影响存“0”单元的存储状态；由于恢复操作是在字线预充电过程中实现的，并不需要额外的操作数和访问时间，因此这是一种自动恢复的操作方法。与传统交叉点阵铁电存储器操作模式相比，本发明的低扰动自恢复操作方法可以实现更小的读写扰动，更低的误码率且具有更快的访问速度，能够进一步提高高密度交叉点阵铁电存储器的可靠性。
附图说明
图1是本发明低扰动自恢复操作方法的交叉点阵铁电存储阵列电学示意图。
图中：
1——位线
2——字线
3——单个存储单元（铁电电容器件）
图2是本发明的低扰动自恢复操作方法的脉冲波形示意图。
 具体实施方式
下面结合附图，通过实施对本发明做进一步说明。
本发明提供一种交叉点阵铁电存储器的操作方法。如图1所示，所述交叉点阵铁电存储器阵列设有多条正交的字线与位线，每条字线与位线的交点为一个存储单元，即存储单元阵列两侧由正交的字线和位线相连，所述存储单元由铁电电容器件构成。其中，在进行某存储单元访问的过程中，若对交叉点阵阵列的一字线与一位线同时施加电压脉冲以选中阵列中某存储单元，则该单元称为选中存储单元，所述选中存储单元所在的字线与位线为选中字线和选中位线，其他所有存储单元为未选中存储单元；未选中存储单元的字线与位线为未选中字线和未选中位线，操作方法需要四个连续脉冲周期实现，操作过程中仅需要对选中字/位线施加电压，未选中字/位线始终保持GND电压。
对选中存储单元实施访问操作，如图2所示，一个完整的访问操作分为四个周期。第一个周期中，选中字线和位线分别施加幅度为GND和- V dd/2的电压脉冲，同时未选中字线和位线保持GND电压；第二个周期中，选中字线电压置为 V dd/2，选中位线电压保持浮空状态，选中存储单元与选中位线上的寄生电容进行电荷共享，读取到数据“1”的位线电压会发生较大程度的抬升（对应图中实线），读取到数据“0”的位线电压会发生较小程度的抬升（对应图中虚线）；第三个周期中，选中位线电压通过外部读写电路放大变为 V dd/2或- V dd/2，随后将选中字线电压置为- V dd/2，原存“1”的选中存储单元受到- V dd的电压访问，对数据“1”进行恢复写入；第四个周期中，将选中字线和选中位线电压均置为GND，实现对选中存储单元及其所在字线与位线的复位。
利用该操作方法，可以避免访问过程中非同字/位线存储单元受到电压脉冲扰动，实现更小的读写扰动，更低的误码率，同时可以在选中存储单元读取操作完成后对被破坏的存储状态进行自动恢复，降低了整体周期的操作时间，可以实现更快的访问速度。
最后需要注意的是，公布实施例的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附的权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。

Claims (2)

  1. 一种面向交叉点阵铁电存储器的低扰动自恢复操作方法，其特征在于，所述交叉点阵铁电存储器阵列设有多条正交的字线与位线，每条字线与位线的交点为一个存储单元，所述存储单元由铁电电容器件构成，所述铁电电容器件通过自发极化方向存储两种数据状态，极化方向向下对应数据“1”，极化方向向上对应数据“0”；若对交叉点阵阵列的一字线与一位线同时施加电压脉冲以选中阵列中某存储单元，则该单元称为选中存储单元，所述选中存储单元所在的字线与位线为选中字线和选中位线，其他所有存储单元为未选中存储单元；未选中存储单元的字线与位线为未选中字线和未选中位线，操作方法需要四个连续脉冲周期实现，操作过程中仅需要对选中字线和位线施加电压，未选中字线和位线始终保持GND电压，具体步骤为：
    1）在第一个周期中，对选中字线与选中位线分别施加幅度为GND与- V dd/2的电压脉冲，以激活选中字线与选中位线，并进行下一步操作；
    2）在第二个周期中，对选中字线施加幅度为 V dd/2的电压脉冲，选中位线保持浮置，以实现对选中存储单元的数据读取操作，其中，所述读取的数据为选中存储单元的铁电电容的铁电介质在 V dd高电压访问下极化翻转产生的极化电荷量引起选中位线电压信号的变化；
    3）在第三个周期中，选中位线的电压通过与相连接的外围电路放大变为 V dd/2或- V dd/2，选中位线的电压与选中存储单元所存储状态电压值对应，即若存储“1”对应 V dd/2，若存储“0”对应- V dd/2，随后将选中字线电压置为- V dd/2，以实现选中字线的预充电，同时实现对选中存储单元的数据恢复；
    4）在第四个周期中，将选中字线与选中位线的电压均置于GND，实现对选中存储单元及其所在字线与位线的复位。
  2. 如权利要求1所述的面向交叉点阵铁电存储器的低扰动自恢复操作方法，其特征在于，所述铁电电容器件采用氧化铪基铁电材料。
PCT/CN2024/128103 2024-04-28 2024-10-29 一种面向交叉点阵铁电存储器的低扰动自恢复操作方法 Pending WO2025227635A1 (zh)

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