WO2025213615A1 - 半导体器件的制备方法、半导体器件及半导体器件 - Google Patents

半导体器件的制备方法、半导体器件及半导体器件

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Publication number
WO2025213615A1
WO2025213615A1 PCT/CN2024/106281 CN2024106281W WO2025213615A1 WO 2025213615 A1 WO2025213615 A1 WO 2025213615A1 CN 2024106281 W CN2024106281 W CN 2024106281W WO 2025213615 A1 WO2025213615 A1 WO 2025213615A1
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Prior art keywords
transistor
metal
semiconductor
active
source
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Pending
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PCT/CN2024/106281
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English (en)
French (fr)
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WO2025213615A9 (zh
Inventor
吴恒
葛延栋
彭莞越
卢浩然
黎明
王润声
黄如
卜伟海
康劲
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Beijing Intellectual Property Operations Management Co Ltd
Peking University
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Beijing Intellectual Property Operations Management Co Ltd
Peking University
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Publication of WO2025213615A1 publication Critical patent/WO2025213615A1/zh
Publication of WO2025213615A9 publication Critical patent/WO2025213615A9/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device, a semiconductor device, and an electronic device.
  • the source and drain epitaxial structures require higher process temperatures, while the metal gates and metal interconnects can withstand lower temperatures.
  • Stacked transistors on the other hand, require two layers of transistors and their interconnects. The thermal process during fabrication of the upper layer can affect the lower layer devices and interconnects.
  • the present disclosure provides a method for manufacturing a semiconductor device, a semiconductor device, and an electronic device.
  • the first aspect of the present disclosure provides a method for preparing a semiconductor device, comprising: forming an active structure on a substrate; wherein the active structure comprises a first active structure and a second active structure stacked in a first direction, the first direction being perpendicular to the substrate; forming a first semiconductor structure based on the first active structure, the first semiconductor structure comprising a first dummy gate structure and a first source-drain structure; bonding the first semiconductor structure to a first carrier wafer and flipping it; removing the substrate and exposing the second active structure; forming a second semiconductor structure based on the second active structure, the second semiconductor structure comprising a second gate structure and a second source-drain structure; bonding the second semiconductor structure to a second carrier wafer and flipping it; removing the first carrier wafer to expose the first semiconductor structure; in the first semiconductor structure, removing the first dummy gate structure filling metal to form a first gate structure; forming a first source-drain metal on the first source-drain structure to form a
  • a second aspect of the present disclosure provides a semiconductor device, which is prepared by the method of the first aspect or any possible embodiment of the first aspect; the semiconductor device comprises: a first transistor; a second transistor, the second transistor being arranged opposite to the first transistor; wherein the first active structure of the first transistor and the second active structure of the second transistor are connected to each other; The source structure is formed through the same process, and the first transistor and the second transistor are self-aligned in the vertical direction.
  • a third aspect of the present disclosure provides an electronic device, comprising: a circuit board and the semiconductor device according to the second aspect, wherein the semiconductor device is disposed on the circuit board.
  • An embodiment of the present application provides a method for preparing a semiconductor device. This method, through multiple wafer bonding and flipping, enables a first gate structure and a first metal interconnect structure of a first transistor to be formed after a second source-drain structure of a second transistor. This avoids the higher process temperature of the second transistor when forming the second source-drain structure from affecting the first gate structure and the first metal interconnect structure of the first transistor, thereby improving the thermal budget of the semiconductor device.
  • FIG1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
  • FIG2 is a top view of a semiconductor device according to an embodiment of the present disclosure.
  • 3 to 17 are schematic diagrams of a process for preparing a semiconductor device according to an embodiment of the present disclosure.
  • 18 to 24 are schematic diagrams of a process for preparing a semiconductor device according to an embodiment of the present disclosure.
  • Semiconductor device 10 first transistor 11; second transistor 12; first pseudo gate sidewall 111; first source-drain structure 112; first interlayer dielectric structure 113; first gate structure 114; first source-drain metal 115; first metal interconnection structure 116; second pseudo gate sidewall 121; second source-drain structure 122; second interlayer dielectric structure 123; second gate structure 124; second source-drain metal 125; second metal interconnection structure 126; substrate 20; first active structure 21; second active structure 22; stacked structure 23; first pseudo gate structure 24; shallow trench isolation structure 25; first insulating layer 26; first carrier wafer 27; second insulating layer 28; second carrier wafer 29; third insulating layer 30; third carrier wafer 31; first metal contact hole 32; second metal contact hole 33; first metal interconnection layer 34; second metal interconnection layer 35; first contact metal layer 36; second contact metal layer 37.
  • Stacked transistors through three-dimensional stacking, can integrate two or more layers of transistors in a vertical space, helping to further increase transistor integration density and improve circuit performance. It is considered one of the key technologies for continuing the scaling of integrated circuits.
  • the characteristics of the monolithic solution include: (1) Instead of using wafer bonding technology, N-type Metal-Oxide-Semiconductor (NMOS) transistors and P-type Metal-Oxide-Semiconductor (PMOS) transistors are made on the same substrate and the two types of transistors are stacked vertically. This means that transistors on the same layer must be of the same type, i.e., NMOS or PMOS; (2) Transistors on the same layer must be strictly in the same plane space, with no alignment deviation.
  • NMOS N-type Metal-Oxide-Semiconductor
  • PMOS Metal-Oxide-Semiconductor
  • the advantage of the monolithic solution is that it has a better integration density, while the disadvantages of the monolithic solution include the following: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied upon to form a basic complementary metal oxide semiconductor circuit, resulting in poor design flexibility.
  • the characteristics of the sequential approach include: based on wafer bonding and layer-by-layer processing, vertical stacking of upper and lower transistors is achieved. Thanks to wafer bonding, the device structure, channel crystal orientation, and even channel materials used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance.
  • the thermal process during the processing of the upper transistors may affect the lower transistors and interconnects, and the thermal budget of the entire processing process must be strictly controlled. At the same time, the temperature that the back-end interconnects can withstand is also limited, which will also limit the thermal budget.
  • the sequential approach currently has the following technical challenges: (1) Preparation of a high-quality upper transistor active layer; (2) Thinning and defect control of the upper transistor bonding wafer; (3) Alignment errors between the upper and lower transistors, which requires extremely high lithography accuracy.
  • the common technical difficulties faced by the above two solutions include: (1) the thermal stability of the lower layer device when manufacturing the upper layer device; (2) the performance of the upper layer device under a low thermal budget; and (3) the metal interconnection between the transistors in the upper and lower layers.
  • the source and drain epitaxial structures require higher process temperatures, while the metal gates and metal interconnects can withstand lower temperatures.
  • Stacked transistors on the other hand, require two layers of transistors and their interconnects. The thermal process during fabrication of the upper layer can affect the lower layer devices and interconnects.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor device to achieve self-alignment of gate structures between upper and lower transistors.
  • the present disclosure provides a method for fabricating a semiconductor device. This method can be used to fabricate a stacked transistor.
  • FIG1 is a schematic flow diagram of a method for fabricating a semiconductor device according to an embodiment of the present disclosure. Referring to FIG1 , the method can include steps S101 to S113.
  • Step S101 forming an active structure on a substrate; wherein the active structure includes a first active structure and a second active structure stacked in a first direction, and the first direction is perpendicular to the substrate;
  • Step S102 forming a first semiconductor structure based on the first active structure, where the first semiconductor structure includes a first dummy gate structure and a first source-drain structure;
  • Step S103 bonding the first semiconductor structure to the first carrier wafer and flipping the wafer over;
  • Step S104 removing the substrate and exposing the second active structure
  • Step S105 forming a second semiconductor structure based on the second active structure, where the second semiconductor structure includes a second gate structure and a second source-drain structure;
  • Step S106 bonding the second semiconductor structure to the second carrier wafer and flipping the wafer over;
  • Step S107 removing the first carrier wafer to expose the first semiconductor structure
  • Step S108 removing the first dummy gate structure filling metal in the first semiconductor structure to form a first gate structure
  • Step S109 forming a first source-drain metal on the first source-drain structure to form a first transistor
  • Step S110 forming a first metal interconnect structure on the first transistor through a back-end process
  • Step S111 bonding the first metal interconnect structure to the third carrier wafer and flipping the wafer over;
  • Step S112 removing the second carrier wafer to expose the second semiconductor structure
  • Step S113 forming a second metal interconnection structure based on the second semiconductor structure.
  • steps shown in FIG1 are not exclusive, and other steps may be performed before, after or between any steps in the shown operation; the steps shown in FIG1 may be adjusted in order according to actual needs.
  • Figure 2 is a top view of a semiconductor device provided according to an embodiment of the present disclosure, and Figure 2 has an A-A' cross section, a B-B' cross section, and a C-C' cross section.
  • the A-A' cross section is a cross section cut along the gate structure of the semiconductor device
  • the B-B' cross section is a cross section cut along the source-drain structure of the semiconductor device
  • the C-C' cross section is a cross section cut along the gate structure of the semiconductor device.
  • Figures 3 to 17 are schematic diagrams of a preparation process of a semiconductor device provided according to an embodiment of the present disclosure, wherein (a) in Figures 3 to 17 is a cross-sectional view along the dotted line A-A' in Figure 2; (b) in Figures 3 to 17 is a cross-sectional view along the dotted line B-B' in Figure 2; and (c) in Figures 3 to 17 is a cross-sectional view along the dotted line C-C' in Figure 2.
  • the following will exemplarily illustrate the method for manufacturing the semiconductor device 10 provided in the embodiment of the present disclosure and the manufactured semiconductor device 10 with reference to FIG. 1 to FIG. 17 .
  • step S101 an active structure is formed on a substrate 20 .
  • the active structure includes a first active structure 21 and a second active structure 22 stacked in a first direction.
  • the first direction is a direction perpendicular to the substrate 20.
  • the first active structure 21 and the second active structure 22 are two parts of the active structure, wherein the second active structure 22 is closer to the substrate 20 than the first active structure 21. Since the first active structure 21 and the second active structure 22 are formed by etching the substrate 20 once, the first active structure 21 and the second active structure 22 are respectively The transistor formed by the structure 22 can achieve self-alignment of the active structure in the first direction, thereby achieving self-alignment of the first transistor 11 and the second transistor 12.
  • a semiconductor material layer may be grown on a substrate 20.
  • one or more active structures are formed on the substrate 20.
  • the active structure may be divided into two parts, the upper part (i.e., the first active structure 21) serving as the active structure of the first transistor 11, and the lower part (i.e., the second active structure 22) serving as the active structure of the second transistor 12.
  • a sacrificial layer and a silicon layer may be sequentially grown on substrate 20.
  • an active structure is formed on substrate 20.
  • a sacrificial layer e.g., a silicon germanium (SiGe) layer
  • SiGe silicon germanium
  • the sacrificial layer is used to protect the main structure of the top silicon layer, reduce external impact and vibration, improve the durability and reliability of the top silicon layer, and extend its service life.
  • the thickness of the sacrificial layer is approximately 10nm-20nm, and the thickness of the top silicon layer is greater than 100nm. It should be noted that the thickness of the sacrificial layer and the top silicon layer can be selected based on actual use requirements. For example, in a fin field-effect transistor, the top silicon layer has a relatively large thickness to facilitate etching of the fin structure; while in a gate-all-around transistor, the sacrificial layer and the silicon layer are stacked, and the sacrificial layer is a semiconductor material layer disposed in the stack. In this case, the thickness of the sacrificial layer and the silicon layer are both selected based on actual use requirements; this is not limited in the present embodiment.
  • anisotropic etching can be used to form an active structure extending in the same direction in the active area (see the fin-shaped structure in Figure 4).
  • the fin-shaped structure can also be replaced by parallel nanosheets, block-shaped planar structures, etc.
  • the first transistor 11 and the second transistor 12 can be fin field effect transistors (FinFETs); when the active structure is a plurality of parallel nanosheets, the first transistor 11 and the second transistor 12 can be gate-all-around field effect transistors (GAAFETs); when the active structure is a block-shaped planar structure, the first transistor 11 and the second transistor 12 are planar transistors.
  • the first transistor 11 and the second transistor 12 may be different types of transistors.
  • one transistor is a FinFET and the other is a gate-all-around transistor; or one transistor is a FinFET and the other is a planar transistor; or one transistor is a gate-all-around transistor and the other is a planar transistor.
  • a stacked structure 23 is epitaxially grown on a substrate 20 , as shown in FIG3 ; then, the stacked structure 23 is etched to form an active structure, as shown in FIG4 .
  • the active structure includes a first active structure 21 and a second active structure 22 .
  • the substrate 20 may be a silicon (Si) substrate or a silicon-on-insulator (SOI) substrate.
  • the substrate 20 may also be other semiconductor materials, which is not limited in the present embodiment.
  • the etching process mentioned in the present embodiment may include any of the following: dry etching, wet etching, reactive etching, etc.
  • the ion etching and chemical oxide removal processes are not limited in the embodiments of the present disclosure.
  • ion implantation may be performed at the connection between the first active structure 21 and the second active structure 22 to form an electrical isolation layer for electrically isolating the first active structure 21 and the second active structure 22 .
  • the ions implanted may include P-type ions, N-type ions, oxygen ions, etc.
  • the P-type ions may be one of the following: boron (B), gallium (Ga), aluminum (Al).
  • the N-type ions may be one of the following: phosphorus (P), arsenic (As), antimony (Sb).
  • step S102 a first semiconductor structure is formed based on the first active structure 21 .
  • the first semiconductor structure may include a first dummy gate structure 24 and a first source/drain structure 112 .
  • a dummy gate material may be deposited on the first active structure 21 to form a first dummy gate structure 24, as shown in FIG7 ; then, a sidewall may be deposited on the periphery of the first dummy gate structure 24, and a first source/drain structure 112 may be epitaxially grown on the first active structure 21, and an interlayer dielectric material may be filled to form a first interlayer dielectric structure 113, as shown in FIG8 .
  • the dummy gate material can define the shape, structure and size of the subsequent gate structure.
  • the dummy gate structure formed by the dummy gate material has a high temperature resistance, which is conducive to the formation of the source and drain structure.
  • the dummy gate structure needs to be replaced by a metal gate in subsequent steps to meet the electrical performance requirements of the device (ie, a metal replacement gate process).
  • the dummy gate material may be polysilicon or amorphous silicon.
  • the interlayer dielectric material may be silicon oxide, silicon nitride, or the like.
  • trenches are formed in the regions between adjacent active structures. Oxide is filled in the trenches to form shallow trench isolation (STI) structures 25, as shown in FIG5 .
  • STI shallow trench isolation
  • the shallow trench isolation structures 25 are etched until the first active structure 21 is exposed and flush with the connection between the first active structure 21 and the second active structure 22, i.e., the upper half of the shallow trench isolation structures 25 is removed, as shown in FIG6 .
  • semiconductor material e.g., polysilicon
  • the first dummy gate structure 24 covers the first active structure 21.
  • a first dummy gate sidewall 111 may be formed on both sides of the first dummy gate structure 24 , and the first dummy gate sidewall 111 may be used as a mask to form a source structure and a drain structure (i.e., a first source-drain structure 112 ).
  • the oxide forming the shallow trench isolation structure 25 may be silicon dioxide (SiO 2 ), silicon oxycarbide (SiCO), etc.
  • the solvent used for etching the shallow trench isolation structure 25 may be a DHF (comprising hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2 ) and water (H 2 O)) solution or a buffered oxide etch (BOE) solution.
  • DHF hydrofluoric acid
  • H 2 O 2 hydrogen peroxide
  • H 2 O hydrogen peroxide
  • H 2 O water
  • BOE buffered oxide etch
  • the shallow trench isolation structure 25 in order to facilitate subsequent processing, after forming the first pseudo-gate structure 24, can also be polished or chemical-mechanical planarization (CMP) treated, so that when the shallow trench isolation structure 25 is subsequently etched, the corresponding corrosion depths of the shallow trench isolation structure 25 in different areas are the same, thereby making the top height of the exposed active structure the same.
  • CMP chemical-mechanical planarization
  • a first source/drain structure 112 is formed on both sides of the first dummy gate structure 24 based on the first active structure 21.
  • the first source/drain structure 112 can be understood as the source structure and/or drain structure of the first transistor 11.
  • an interlayer dielectric material e.g., silicon dioxide
  • the fabrication of the first semiconductor structure is complete.
  • the first dummy gate structure 24 and the first source-drain structure 112 are prepared when the first semiconductor structure is prepared in the above-mentioned step S102, and the gate dielectric, metal gate, metal interconnect structure, etc. are not prepared, therefore, when the second source-drain structure 122 of the second transistor 12 is prepared, the gate dielectric, metal gate, and metal interconnect structure in the first transistor 11 will not be affected, thereby effectively improving the thermal budget of the semiconductor device.
  • step S103 the first semiconductor structure is bonded to the first carrier wafer 27 and then flipped over.
  • step S103 after forming the first semiconductor structure, an insulating material (e.g., silicon oxide) is deposited on top of the first semiconductor structure to form a first insulating layer 26.
  • the formed first insulating layer 26 may be planarized using a CMP process. Subsequently, the planarized first insulating layer 26 may be bonded to a first carrier wafer 27. The substrate 20 may then be flipped over so that the first semiconductor structure faces downward and the substrate 20 faces upward.
  • step S104 the substrate 20 is removed, and the second active structure 22 is exposed.
  • wafer thinning such as by a CMP process, can be performed to remove the substrate 20 and expose the surface of the second active structure 22, as shown in FIG9 .
  • the lower half of the shallow trench isolation structure 25 is removed by etching to expose the second active structure 22 covered by the shallow trench isolation structure 25, as shown in FIG10 .
  • a portion of the shallow trench isolation structure 25 may be retained as an isolation layer to isolate the first transistor 11 from the second transistor 12 .
  • step S105 a second semiconductor structure is formed based on the second active structure 22 .
  • the second semiconductor structure includes a second gate structure 124 and a second source-drain structure 122 .
  • the front-end process can be performed first.
  • a semiconductor material such as polysilicon
  • the second dummy gate structure covers the second active structure 22.
  • a source structure and a drain structure i.e., a second source-drain structure 122
  • the second source-drain structure 122 can be understood as the source structure and/or drain structure of the second transistor 12.
  • an interlayer dielectric material such as silicon dioxide is deposited on the second source-drain structure 122 and the retained shallow trench isolation structure 25 to form a second interlayer dielectric Structure 123. At this point, the preparation of the second semiconductor structure is completed.
  • the second dummy gate structure can be removed by an etching process to deposit a metal material at the etched second dummy gate structure to form a second gate structure 124, i.e., the gate structure of the second transistor 12, as shown in FIG11 .
  • the thermal budget is basically not restricted.
  • the second gate structure 124 can be formed using a metal replacement gate process.
  • the second gate structure 124 can be a high-k metal gate (HKMG).
  • k refers to the dielectric constant.
  • a gate dielectric layer can be deposited on the surface of the second active structure 22 to isolate the second active structure 22 from the second gate structure 124.
  • the gate dielectric layer is formed of a high-k material.
  • step S106 the second semiconductor structure is bonded to the second carrier wafer 29 and then flipped over.
  • step S106 after forming the second semiconductor structure, an insulating material (e.g., silicon oxide) is deposited on top of the second semiconductor structure to form a second insulating layer 28, and the second insulating layer 28 is bonded to a second carrier wafer 29.
  • the second carrier wafer 29 can then be flipped over so that the second semiconductor structure faces downward and the first carrier wafer 27 faces upward, as shown in FIG12 .
  • depositing insulating material on top of the second semiconductor structure may include: depositing insulating material on the second gate structure 124 and the second interlayer dielectric structure 123 to form a second insulating layer 28 .
  • step S107 the first carrier wafer 27 is removed to expose the first semiconductor structure.
  • a CMP process may be used to thin the wafer until the first dummy gate structure 24 is exposed, that is, the first insulating layer 26 and the first carrier wafer 27 are removed, as shown in FIG. 13 .
  • step S108 in the first semiconductor structure, the metal filling the first dummy gate structure 24 is removed to form a first gate structure 114 .
  • the first dummy gate structure 24 may be removed using a countable process. Then, a metal material is filled in the removed first dummy gate structure 24 to form a first gate structure 114 , as shown in FIG14 .
  • the first gate structure 114 can be formed using a metal replacement gate process.
  • the first gate structure 114 can be HKMG.
  • a gate dielectric layer can be deposited on the surface of the first active structure 21 to isolate the first active structure 21 from the first gate structure 114.
  • the gate dielectric layer is formed of a high-K material.
  • the shallow trench isolation structure 25 may not be provided between the first gate structure 114 and the second gate structure 124, depending on the actual situation.
  • the shallow trench isolation structure 25 is etched until the second gate structure 124 is exposed, forming a gate direct connection groove. Metal is deposited on the second gate structure to form the first gate structure 114. In this way, the first transistor 11 and the second transistor 12 can be connected through the connection of their gate structures. Interconnection is achieved by touching, and there is no need to lead out interconnection wires.
  • the metal material used to prepare the first gate structure 114 and the metal material used to prepare the second gate structure 124 can be the same or different metal materials according to actual conditions, and the embodiment of the present disclosure does not limit this.
  • the above-mentioned metal material can be one of the following: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), which can be selected according to actual conditions and is not limited to the metal materials listed above.
  • step S109 a first source-drain metal 115 is formed on the first source-drain structure 112 to form the first transistor 11 .
  • the first interlayer dielectric structure 113 located above the first source/drain structure 112 is etched until the first source/drain structure 112 is exposed. Metal material is then deposited in the etched areas to form first source/drain metal 115. This completes the front-end process of the first transistor 11, resulting in the first transistor 11, as shown in FIG14 .
  • step S110 a first metal interconnection structure 116 is formed on the first transistor 11 .
  • a mid-line process is used to deposit an interlayer dielectric material (e.g., silicon dioxide) on the first source/drain metal 115 to form an interlayer dielectric.
  • an interlayer dielectric material e.g., silicon dioxide
  • First metal contact holes 32 for the first source/drain structure 112 are then formed in the interlayer dielectric layer.
  • a back-end process is then used to form a first metal interconnect layer 34 on the interlayer dielectric layer.
  • the first metal interconnect structure 116 is formed.
  • the interlayer dielectric layer in which the first metal contact hole 32 is formed constitutes the first contact metal layer 36 .
  • step S111 the first metal interconnect structure 116 is bonded to the third carrier wafer 31 and then flipped over.
  • step S111 after forming the first metal interconnect structure 116, an insulating material (e.g., silicon oxide) is deposited on top of the first metal interconnect structure 116 to form a third insulating layer 30.
  • the formed third insulating layer 30 may be planarized using a CMP process. Subsequently, the planarized third insulating layer 30 may be bonded to a third carrier wafer 31. The third carrier wafer 31 may then be flipped over so that the first transistor 11 is again placed facing downward and the second carrier wafer 29 is placed facing upward, as shown in FIG15 .
  • step S112 the second carrier wafer 29 is removed to expose the second semiconductor structure.
  • a CMP process may be used to thin the wafer until the second gate structure 124 is exposed, ie, the second insulating layer 28 and the second carrier wafer 29 are removed, as shown in FIG. 16 .
  • the second semiconductor structure includes the second gate structure 124 and the second source-drain structure 122 , after the second carrier wafer 29 is removed, the second gate structure 124 and the second interlayer dielectric structure 123 can be exposed.
  • step S113 a second metal interconnection structure 126 is formed based on the second semiconductor structure.
  • the second interlayer dielectric structure 123 located above the second source/drain structure 122 is etched until the second source/drain structure 122 is exposed. Then, a metal material is deposited at the etched portion to form a second source/drain metal 125. At this point, the front-end process of the second transistor 12 is completed. Then, a mid-end process is used to deposit an interlayer dielectric material (such as silicon dioxide) on the second source/drain metal 125 to form an interlayer dielectric, and a second metal contact hole 33 for the second source/drain structure 122 is made on the interlayer dielectric layer. Then, a back-end process is used to form a second metal interconnect layer on the interlayer dielectric layer. 35. At this point, the second metal interconnection structure 126 is formed.
  • an interlayer dielectric material such as silicon dioxide
  • the interlayer dielectric layer having the second metal contact hole 33 formed therein constitutes a second contact metal layer 37.
  • the second contact metal layer 37 is formed on the second gate structure 124 and the second source/drain metal 125.
  • a second metal interconnect layer 35 may be formed on the second contact metal layer 37 to form a second metal interconnect structure 126.
  • the metal material forming the second metal contact hole 33 may be a high temperature resistant material.
  • the metal material forming the second metal contact hole 33 may be tungsten (W), cobalt (Co), or the like.
  • the first gate structure and the first metal interconnection structure of the first transistor are formed after the second source-drain structure of the second transistor, thereby avoiding the high process temperature of the second transistor when forming the second source-drain structure affecting the first gate structure and the first metal interconnection structure of the first transistor, thereby improving the thermal budget of the semiconductor device.
  • Figures 18 to 24 are schematic diagrams of a preparation process of a semiconductor device provided according to an embodiment of the present disclosure, wherein (a) in Figures 18 to 24 is a cross-sectional view along the dotted line A-A' in Figure 2; (b) in Figures 18 to 24 is a cross-sectional view along the dotted line B-B' in Figure 2; and (c) in Figures 18 to 24 is a cross-sectional view along the dotted line C-C' in Figure 2.
  • the following will exemplarily illustrate the method for manufacturing the semiconductor device 10 provided in the embodiment of the present disclosure and the manufactured semiconductor device 10 with reference to FIG. 1 to FIG. 2 and FIG. 18 to FIG. 24 .
  • step S201 may also be performed during the process of fabricating the second semiconductor structure through step S105.
  • the second semiconductor structure further includes a second source/drain metal 125 and a second contact metal layer 37.
  • the second source/drain metal 125 is formed by depositing metal on the second source/drain structure 122, and the second contact metal layer 37 is formed on the second gate structure 124 and the second source/drain metal 125.
  • step S201 a second source/drain metal 125 and a second contact metal layer 37 are formed based on the second active structure 22 .
  • an exposed second active structure 22 is obtained.
  • a second source/drain structure 122, a second interlayer dielectric structure 123, and a second gate structure 124 can be formed in step S105.
  • a second source/drain metal 125 and a second contact metal layer 37 can also be formed in step S201.
  • the second interlayer dielectric structure 123 located above the second source/drain structure 122 may be etched until the second source/drain structure 122 is exposed. A metal material is then deposited in the etched area to form a second source/drain metal 125. An interlayer dielectric layer is formed on the second interlayer dielectric structure 123 and the second source/drain metal 125, and a second metal contact hole 33 for the second source/drain structure 122 is formed in the interlayer dielectric layer, as shown in FIG18 .
  • the interlayer dielectric layer formed with the second metal contact hole 33 constitutes the second contact metal layer 37, and the second contact metal layer 37 is formed on the second gate structure 124 and the second source and drain metal 125.
  • the second The metal material of the metal contact hole 33 can be high-temperature resistant tungsten, cobalt or other metal materials.
  • the process temperature during steps S108 and S109 is higher than the process temperature for forming the second contact metal layer 37 , so the second contact metal layer 37 is made of high-temperature resistant metal material, which can avoid affecting the second contact metal layer 37 during the execution of steps S108 and S109 .
  • the preparation of the second contact metal layer 37 facilitates the photolithography alignment of the front and back transistors.
  • step S201 the front-end and mid-end processes of the second transistor 12 are completed.
  • step S106 may be performed, as shown in FIG19 , to bond the second semiconductor structure to the second carrier wafer 29 , including bonding the second contact metal layer 37 to the second carrier wafer 29 .
  • an insulating material such as silicon oxide
  • the second insulating layer 28 can be bonded to the second carrier wafer 29 to obtain the structure shown in Figure 19.
  • steps S107 to S111 may be executed.
  • the first transistor 11 can be re-prepared after completing the second flip-flop using the steps in one or more of the above embodiments.
  • the second carrier wafer 29 can first be flipped so that the second semiconductor structure is placed downward and the first semiconductor structure and the first carrier wafer 27 are placed upward. Subsequently, a CMP process can be used to thin the wafer until the first dummy gate structure 24 is exposed, as shown in FIG20. Subsequently, a replacement metal gate (RMG) process can be used to form the first gate structure 114, a first source and drain metal 115 can be formed on the first source and drain structure 112 using a process for the first interlayer dielectric structure 113, and a first metal interconnect structure 116 can be formed using a mid-to-back-end process, as shown in FIG21. Subsequently, the first metal interconnect structure 116 can be bonded to the third carrier wafer 31 and flipped so that the third carrier wafer 31 is placed downward and the second carrier wafer 29 is placed upward, as shown in FIG22.
  • RMG replacement metal gate
  • step S112 may be performed to remove the second carrier wafer 29 to expose the second semiconductor structure (including the second source/drain metal 125 and the second contact metal layer 37).
  • the second contact metal layer 37 may be exposed, as shown in FIG23 .
  • step S113 is performed to form a second metal interconnect layer 35 on the second contact metal layer 37 through a back-end process to form a second metal interconnect structure 126, as shown in FIG24 .
  • the first gate structure and the first metal interconnection structure of the first transistor are formed after the second source-drain structure of the second transistor, thereby avoiding the high process temperature of the second transistor when forming the second source-drain structure affecting the first gate structure and the first metal interconnection structure of the first transistor, thereby improving the thermal budget of the semiconductor device.
  • the present disclosure provides a semiconductor device.
  • the semiconductor device The semiconductor device 10 is manufactured using the method described in one or more of the above embodiments.
  • the semiconductor device 10 includes a first transistor 11 and a second transistor 12.
  • the second transistor 12 is disposed opposite the first transistor 11.
  • the first active structure 21 of the first transistor 11 and the second active structure 22 of the second transistor 12 are formed using the same process, and the first transistor 11 and the second transistor 12 are self-aligned in the vertical direction.
  • the vertical direction refers to a direction perpendicular to the substrate forming the semiconductor device 10.
  • Self-alignment of the first transistor 11 and the second transistor 12 means that the gate region of the first transistor 11 is aligned with the gate region of the second transistor 12, and the source and drain regions of the first transistor 11 are aligned with the source and drain regions of the second transistor 12.
  • the gate region refers to a region where a gate structure is formed; and the source/drain region refers to a region where a source/drain structure is formed.
  • a deep STI and a higher active area are first formed by etching. Subsequently, the source and drain structures of the first transistor are fabricated above this active area. Subsequently, the wafer is flipped over, and the lower portion of the active area is exposed by self-aligned etching, while forming a partial structure of the second transistor. After the partial structure of the second transistor is fabricated, the wafer is flipped over again to complete the subsequent fabrication of the first transistor. Subsequently, the wafer is flipped over a third time to complete the subsequent fabrication of the second transistor.
  • multiple flips are performed to form dummy gates and fabricate source and drain layers in the upper and lower transistor layers, replacing the metal gate process.
  • the order of the middle-of-line (MOL) and back-end-of-line (BEOL) processes is optimized, prioritizing the fabrication of high-temperature resistant source and drain structures. This effectively improves the thermal budget in subsequent fabrication processes and addresses the technical issue of limited thermal budgets for stacked transistors due to the high process temperatures for source and drain fabrication of transistors, while the metal gates and metal interconnects can withstand lower process temperatures.
  • first and second fabrication processes for the semiconductor device described above are merely two exemplary embodiments embodying the technical concepts of the embodiments of the present disclosure. It should be understood that the technical solution of forming the first gate structure and first metal interconnect structure of the first transistor after the second source-drain structure of the second transistor, thereby preventing the process temperature during the formation of the second source-drain structure from affecting the first gate structure and first metal interconnect structure of the first transistor, is within the scope of protection of the embodiments of the present disclosure.
  • the secondary flipping scheme can use a standard process flow to etch deep STI and a higher active area on the original silicon substrate, and deposit a pseudo gate to form the source and drain structure of the first transistor. Subsequently, the first transistor is bonded to the first carrier wafer and flipped for the first time to place the substrate on the front. Subsequently, the standard STI etching and active area exposure process is used to expose the active area of the second transistor in a self-aligned manner.
  • the second transistor is bonded to the second carrier wafer and flipped for the second time. After flipping, the first carrier wafer is removed to expose the first transistor, and the gate forming process as well as the middle-end process and back-end process are completed in the first transistor.
  • the disclosed embodiment optimizes the process flow of stacked transistors and takes into account the consistency of the active areas and gates of the upper and lower transistors, defect density, alignment, and thermal budget.
  • the stacked transistor device structure and its back-end interconnect fabrication sequence improves the thermal budget of the overall device fabrication process.
  • the disclosed embodiments address long-standing challenges associated with existing monolithic stacked transistor solutions, such as complex processes and fixed polarity.
  • the disclosed embodiments address long-standing challenges associated with existing sequential stacked transistor solutions, such as alignment difficulties and high defect density in upper semiconductor materials.
  • the disclosed embodiments promote the industrialization of transistor stacking technology.
  • the solution in the disclosed embodiment is also an organic fusion of the current sequential and monolithic stacked transistor solutions.
  • the mature technology has a high degree of reuse, can avoid a large amount of expensive process development to save costs, and has high feasibility.
  • the flip-chip transistor adopts a self-aligned "back-to-back" active area and metal gate design.
  • the front and back transistors have independent signal and power supply networks and are connected through local interconnection. Without changing the extremely miniaturized 4T track unit design, the metal wiring resources are greatly released (compared to the current solution, an increase of more than 60%), and there is huge room for collaborative optimization of process design.
  • the flip-chip transistor solution is compatible with existing mainstream device architectures, and can realize front and back stacking of planar transistors, fin transistors, all-around gate transistors and even vertical transistors without the need for special process development for specific device architectures. It has strong flexibility and is very extensible from the perspective of semiconductor process node iteration.
  • the flip-chip transistor is very advanced in concept, has important industrial value, and is highly practical and has broad prospects for expansion.
  • the present disclosure provides an electronic device comprising: a circuit board and a semiconductor device according to one or more of the above embodiments, wherein the semiconductor device is disposed on the circuit board.

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Abstract

本公开提供一种半导体器件的制备方法、半导体器件及电子设备。半导体器件的制备方法包括：在衬底上形成有源结构；形成第一半导体结构；将第一半导体结构与第一载片晶圆键合并翻转；去除衬底，暴露第二有源结构；形成第二半导体结构；将第二半导体结构与第二载片晶圆键合并翻转；去除第一载片晶圆，暴露第一半导体结构；在第一半导体结构中，形成第一栅极结构；在第一源漏结构上形成第一源漏金属；在第一晶体管上形成第一金属互连结构；将第一金属互连结构与第三载片晶圆键合并翻转；去除第二载片晶圆，以暴露第二半导体结构；形成第二金属互连结构。

Description

半导体结构的制备方法、半导体结构及半导体器件
相关申请的交叉引用
本申请基于申请号为202410434413.4、申请日为2024年04月11日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体器件的制备方法、半导体器件及电子设备。
背景技术
在摩尔定律不断深化的当下，继续推进晶体管尺寸微缩是当前业界研发的热点问题。堆叠晶体管通过将两层或多层晶体管在垂直空间内集成，实现进一步提升晶体管集成密度，成为延续集成电路尺寸微缩的重要技术之一。
在晶体管的制备过程中，源极外延结构与漏极外延结构的制备工艺温度较高，而金属栅和金属互连线能耐受的工艺温度较低。而对于堆叠晶体管，需要制备两层晶体管及其互连线，加工上层器件时的热过程可能会影响下层器件和互连线。
发明内容
本公开提供一种半导体器件的制备方法、半导体器件及电子设备。
本公开第一方面提供一种半导体器件的制备方法，包括：在衬底上形成有源结构；其中，有源结构包括在第一方向上堆叠设置的第一有源结构和第二有源结构，第一方向垂直于衬底；基于第一有源结构，形成第一半导体结构，第一半导体结构包括第一伪栅结构和第一源漏结构；将第一半导体结构与第一载片晶圆键合并翻转；去除衬底，并暴露第二有源结构；基于第二有源结构，形成第二半导体结构，第二半导体结构包括第二栅极结构和第二源漏结构；将第二半导体结构与第二载片晶圆键合并翻转；去除第一载片晶圆，以暴露第一半导体结构；在第一半导体结构中，去除第一伪栅结构填充金属，以形成第一栅极结构；在第一源漏结构上形成第一源漏金属，以形成第一晶体管；通过后道工艺，在第一晶体管上形成第一金属互连结构；将第一金属互连结构与第三载片晶圆键合并翻转；去除第二载片晶圆，以暴露第二半导体结构；基于第二半导体结构，形成第二金属互连结构。
本公开第二方面提供一种半导体器件，半导体器件是采用如第一方面或第一方面任一种可能的实施方式的方法制备得到的；半导体器件包括：第一晶体管；第二晶体管，第二晶体管与第一晶体管相背设置；其中，第一晶体管的第一有源结构与第二晶体管的第二有 源结构是通过同一工序形成的，第一晶体管与第二晶体管在垂直方向上自对准。
本公开第三方面提供一种电子设备。电子设备包括：电路板以及如第二方面的半导体器件，半导体器件设置于电路板上。
本公开与现有技术相比，存在以下有益效果：
本申请实施例提供了一种半导体器件的制备方法，该方法通过多次晶圆键合与翻转，使第一晶体管的第一栅极结构和第一金属互连结构形成于第二晶体管的第二源漏结构之后，避免了第二晶体管在形成第二源漏结构时的较高工艺温度影响第一晶体管的第一栅极结构和第一金属互连结构，提高了半导体器件的热预算。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，而非限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，这些附图示出了符合本公开的实施例，并与说明书一起用于解释本公开实施例的原理。
图1是根据本公开实施例提供的一种半导体器件的制备方法的流程示意图。
图2是根据本公开实施例提供的一种半导体器件的俯视图。
图3至图17是根据本公开实施例提供的一种半导体器件的制备过程的示意图。
图18至图24是根据本公开实施例提供的一种半导体器件的制备过程的示意图。
附图标记说明
半导体器件10；第一晶体管11；第二晶体管12；第一伪栅侧墙111；第一源漏结构112；第一层间介质结构113；第一栅极结构114；第一源漏金属115；第一金属互连结构116；第二伪栅侧墙121；第二源漏结构122；第二层间介质结构123；第二栅极结构124；第二源漏金属125；第二金属互连结构126；衬底20；第一有源结构21；第二有源结构22；堆叠结构23；第一伪栅结构24；浅槽隔离结构25；第一绝缘层26；第一载片晶圆27；第二绝缘层28；第二载片晶圆29；第三绝缘层30；第三载片晶圆31；第一金属接触孔32；第二金属接触孔33；第一金属互连层34；第二金属互连层35；第一接触金属层36；第二接触金属层37。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开实施例相一致的所有实施方式。相反，它们仅是本公开实施例的一些方面相一致的装置和方法的例子。
在本公开实施例使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本公开 实施例。在本公开所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
在摩尔定律不断深化的当下，继续推进晶体管尺寸微缩是当前业界研发的热点问题。堆叠晶体管通过三维堆叠，可以实现两层或多层晶体管在垂直空间内的集成，有助于进一步提升晶体管集成密度，提高电路性能，被认为是延续集成电路尺寸微缩的重要技术之一。堆叠晶体管的制造工艺存在至少两种方案：一种是单片方案(Monolithic)，另一种是顺序方案(sequential)。
单片方案的特点包括：(1)没有采用晶圆键合技术，而是在同一个衬底上制作N型金属氧化物半导体(N-type Metal-Oxide-Semiconductor，简称NMOS)晶体管和P型金属氧化物半导体(P-type Metal-Oxide-Semiconductor，简称PMOS)晶体管，将两种类型的晶体管垂直堆叠，这决定了同层晶体管必须是同一类型的，即NMOS或PMOS；(2)同层晶体管要严格在同一平面空间，不存在对准偏差。单片方案的优点是具有更好的集成密度，而单片方案的缺点包括以下几点：(1)工艺复杂，需做大量工艺技术的开发和优化；(2)每一层晶体管极性固定，必须依赖两层晶体管才能组成基本的互补型金属氧化物半导体电路，设计灵活性差。
顺序方案的特点包括：基于晶圆键合且逐层加工，实现上层晶体管、下层晶体管的垂直堆叠。得益于晶圆键合，上层晶体管、下层晶体管所采用的器件结构、沟道晶向甚至是沟道材料均可以做相应优化以获得更好和更匹配的器件性能，但加工上层晶体管时的热过程可能影响下层晶体管和互连线，必须严格控制加工全程的热预算。同时，后道互连线能承受的温度也有限，也会限制热预算。因此，顺序方案目前存在以下技术上的挑战：(1)高质量上层晶体管有源层的制备；(2)上层晶体管键合晶圆的减薄和缺陷控制；(3)上层晶体管、下层晶体管存在着对准误差，对于光刻精度要求极高。
上述两种方案面临的共同的技术难点包括：(1)在制作上层器件时，下层器件的热稳定性；(2)上层器件在低热预算下的性能；(3)上层与下层之间晶体管的金属互连。
在晶体管的制备过程中，源极外延结构与漏极外延结构的制备工艺温度较高，而金属栅和金属互连线能耐受的工艺温度较低。而对于堆叠晶体管，需要制备两层晶体管及其互连线，加工上层器件时的热过程可能会影响下层器件和互连线。
为了解决上述技术问题，本公开实施例提供一种半导体器件的制备方法，以实现上下层晶体管之间的栅极结构自对准。
在一些实施例中，本公开实施例提供一种半导体器件的制备方法。半导体器件的制备方法可以用于制备堆叠晶体管。图1是根据本公开实施例提供的一种半导体器件的制备方法的流程示意图，参照图1所示，半导体器件的制备方法可以包括步骤S101至步骤S113。
步骤S101：在衬底上形成有源结构；其中，有源结构包括在第一方向上堆叠设置的第一有源结构和第二有源结构，第一方向垂直于衬底；
步骤S102：基于第一有源结构，形成第一半导体结构，第一半导体结构包括第一伪栅结构和第一源漏结构；
步骤S103：将第一半导体结构与第一载片晶圆键合并翻转；
步骤S104：去除衬底，并暴露第二有源结构；
步骤S105：基于第二有源结构，形成第二半导体结构，第二半导体结构包括第二栅极结构和第二源漏结构；
步骤S106：将第二半导体结构与第二载片晶圆键合并翻转；
步骤S107：去除第一载片晶圆，以暴露第一半导体结构；
步骤S108：在第一半导体结构中，去除第一伪栅结构填充金属，以形成第一栅极结构；
步骤S109：在第一源漏结构上形成第一源漏金属，以形成第一晶体管；
步骤S110：通过后道工艺，在第一晶体管上形成第一金属互连结构；
步骤S111：将第一金属互连结构与第三载片晶圆键合并翻转；
步骤S112：去除第二载片晶圆，以暴露第二半导体结构；
步骤S113：基于第二半导体结构，形成第二金属互连结构。
需要说明的是，图1中所示的步骤并非排他的，也可以在所示操作中的任何步骤之前、之后或之间执行其他步骤；图1中所示的各步骤可以根据实际需求进行顺序调整。
图2是根据本公开实施例提供的一种半导体器件的俯视图，并且在图2中具有A-A＇剖面、B-B＇剖面和C-C＇剖面。其中，A-A＇剖面为沿着半导体器件的栅极结构切割的剖面；B-B＇剖面为沿着半导体器件的源漏结构切割的剖面；C-C＇剖面为沿着半导体器件的栅极结构切割的剖面。图3至图17是根据本公开实施例提供的一种半导体器件的制备过程的示意图，其中，图3至图17中的(a)为沿图2中的虚线A-A＇方向的剖视图；图3至图17中的(b)为沿图2中的虚线B-B＇方向的剖视图；图3至图17中的(c)为沿图2中的虚线C-C＇方向的剖视图。
下面将结合图1至图17对本公开实施例提供的半导体器件10的制备方法以及制备得到的半导体器件10进行示例性的说明。
在步骤S101中，在衬底20上形成有源结构。
在一实施例中，有源结构包括在第一方向上堆叠设置的第一有源结构21和第二有源结构22。这里，第一方向为垂直于衬底20的方向。
在一些实施例中，第一有源结构21和第二有源结构22为有源结构的两部分，其中，第二有源结构22相对于第一有源结构21更靠近衬底20。由于第一有源结构21和第二有源结构22是通过对衬底20的一次刻蚀形成的，所以根据第一有源结构21和第二有源结 构22形成的晶体管，能够在第一方向上实现有源结构的自对准，进而实现第一晶体管11和第二晶体管12的自对准。
在一些实施例中，在步骤S101中，在衬底20上可以生长半导体材料层。通过刻蚀半导体材料层，在衬底20上形成一个或多个有源结构。其中，有源结构可以分为上下两个部分，上半部分(即第一有源结构21)用于作为第一晶体管11的有源结构，下半部分(即第二有源结构22)用于作为第二晶体管12的有源结构。
在一些实施例中，在步骤S101中，在衬底20上还可以依次生长牺牲层和硅层。通过刻蚀牺牲层和硅层，在衬底20上形成有源结构。示例性的，在底层硅层(即衬底20)上外延生长有一层牺牲层(如硅锗(SiGe)层)，在牺牲层的上方外延生长顶层硅层，牺牲层用于保护顶层硅层的主要结构，减少来自外界的冲击和振动，提高顶层硅层的耐久性和可靠性，延长使用寿命。
在一实施例中，牺牲层的厚度约为10nm-20nm，顶层硅层的厚度大于100nm。需要说明的是，牺牲层和顶层硅层的厚度可以根据实际使用需求进行选择，如在鳍式场效应晶体管中，顶层硅层具有较大的厚度，以便于刻蚀鳍状结构；而在全环绕栅极晶体管中，牺牲层和硅层为层叠设置的叠层，牺牲层为叠层中间隔设置的半导体材料层，此时，牺牲层的厚度与硅层的厚度都根据实际使用需求进行选择；本公开实施例对此不做限定。
在一实施例中，可以采用各向异性刻蚀，以在有源区形成沿同一方向延伸的有源结构(参见图4中的有鳍状结构)。当然，在其他类型的晶体管中，鳍状结构还可以替换成平行设置的纳米片、块状平面结构等。在有源结构为鳍状结构的情况下，第一晶体管11和第二晶体管12可以为鳍式场效应晶体管(fin field effect transistor，FinFET)；在有源结构为多个平行设置的纳米片的情况下，第一晶体管11和第二晶体管12可以为全环绕栅极晶体管(gate-all-around field effect transistor，GAAFET)；在有源结构为块状平面结构的情况下，第一晶体管11和第二晶体管12为平面晶体管(planar transistor)。
在一些实施例中，第一晶体管11和第二晶体管12可以为不同类型的晶体管。示例性的，一个晶体管为鳍式场效应晶体管，另一个为全环绕栅极晶体管；或者，一个晶体管为鳍式场效应晶体管，另一个为平面晶体管；或者，一个晶体管为全环绕栅极晶体管，另一个为平面晶体管。
在一实施例中，首先，在衬底20上外延生成出堆叠结构23，如图3所示；然后，对堆叠结构23进行刻蚀，以形成有源结构，如图4所示。有源结构包括第一有源结构21和第二有源结构22。
在一实施例中，衬底20可以为硅(Si)衬底、也可以为绝缘体上硅(silicon-on-insulator，SOI)衬底。当然，衬底20还可以为其他半导体材料，本公开实施例对此不做限定。需要说明的是，本公开实施例中提及的刻蚀工艺可以包括以下任一种：干蚀刻、湿蚀刻、反应 离子蚀刻和化学氧化物去除工艺，本公开实施例对此不做限定。
在一些实施例中，在通过S101形成有源结构之后，可以在有源结构的第一有源结构21和第二有源结构22的连接处进行离子注入，以形成电学隔离层，电学隔离层用于对第一有源结构21和第二有源结构22进行电学隔离。
示例性的，离子注入的离子可以包括P型离子、N型离子、氧离子等。其中，P型离子可以为以下之一：硼(B)、镓(Ga)、铝(Al)。N型离子可以为以下之一：磷(P)、砷(As)、锑(Sb)。
在步骤S102中，基于第一有源结构21，形成第一半导体结构。
在一实施例中，第一半导体结构可以包括第一伪栅结构24和第一源漏结构112。
在一些实施例中，在步骤S102中，可以在第一有源结构21上沉积伪栅材料，形成第一伪栅结构24，如图7所示；然后，在第一伪栅结构24的外围沉积形成侧墙，以及在第一有源结构21上外延生长第一源漏结构112，并填充层间介质材料形成第一层间介质结构113，如图8所示。
需要说明的是，伪栅材料能够定义后续栅极结构的形状、结构和尺寸。同时，相对于金属栅极来说，伪栅材料形成的伪栅结构耐受温度高，有利于源漏结构的形成。
需要说明的是，伪栅结构在后续工序中需要替代为金属栅极，以达到器件的电学性能要求(即金属替代栅工艺)。
在一示例中，伪栅材料可以为多晶硅或非晶硅。
在一示例中，层间介质材料可以为氧化硅、氮化硅等。
在一些实施例中，在形成有源结构之后，相邻的有源结构之间的区域形成有沟槽。在沟槽处填充氧化物，以形成浅槽隔离(shallow trench isolation，STI)结构25，如图5所示。接下来，在形成浅槽隔离结构25后，对浅槽隔离结构25进行刻蚀，直至暴露第一有源结构21，并与第一有源结构21和第二有源结构22的连接处平齐，即去除浅槽隔离结构25的上半部分，如图6所示。然后，在刻蚀掉的浅槽隔离结构25之上的栅极区域内沉积半导体材料(如多晶硅)，至此，第一伪栅结构24成型，如图7所示。在一示例中，第一伪栅结构24覆盖第一有源结构21。
在一些实施例中，在第一伪栅结构24成型之后，可以在第一伪栅结构24的两侧形成第一伪栅侧墙111，并以第一伪栅侧墙111作为掩模，形成源极结构和漏极结构(即第一源漏结构112)。
在一些实施例中，形成浅槽隔离结构25的氧化物可以为：二氧化硅(SiO2)、碳氧化硅(SiCO)等。在一些实施例中，上述刻蚀浅槽隔离结构25所用到的溶剂可以为：DHF(包括氢氟酸(HF)、过氧化氢(H2O2)和水(H2O))溶液或缓冲氧化物刻蚀(buffered oxide etch，BOE)溶液。本公开实施例在刻蚀处理中采用的溶剂可以根据实际情况进行选择， 并不限于上述DHF溶液或BOE溶液。
在一些实施例中，为了方便后续处理，在形成第一伪栅结构24之后，还可以对浅槽隔离结构25进行抛光处理或者化学机械平坦化(chemical-mechanical planarization，CMP)处理，使得后续对浅槽隔离结构25进行刻蚀时，不同区域的浅槽隔离结构25对应的腐蚀深度相同，从而使得暴露出的有源结构的顶部高度相同。
在一些实施例中，在第一伪栅结构24完成制备之后，在第一伪栅结构24的两侧，基于第一有源结构21形成第一源漏结构112。这里，第一源漏结构112可以理解为第一晶体管11的源极结构和/或漏极结构。接下来，在第一源漏结构112上沉积层间介质材料(如二氧化硅)，以形成第一层间介质结构113，如图8所示。至此，完成第一半导体结构的制备。
在本公开实施例中，由于在上述步骤S102中制备第一半导体结构时，仅制备第一伪栅结构24以及第一源漏结构112，而未制备栅介质、金属栅、金属互连结构等，因此，在制备第二晶体管12的第二源漏结构122时，不会影响第一晶体管11中的栅介质、金属栅、金属互连结构，使得有效提高半导体器件的热预算。
在步骤S103中，将第一半导体结构与第一载片晶圆27键合并翻转。
在一些实施例中，在步骤S103中，在形成第一半导体结构之后，在第一半导体结构的顶部沉积绝缘材料(如氧化硅)，以形成第一绝缘层26；形成的第一绝缘层26可采用CMP工艺进行平坦化处理；随后，可将平坦化处理后的第一绝缘层26与第一载片晶圆27键合。然后，可以翻转衬底20，使得第一半导体结构朝下放置，衬底20朝上放置。
在步骤S104中，去除衬底20，并暴露第二有源结构22。
在一些实施例中，在翻转衬底20之后，可以采用如CMP工艺等进行晶圆减薄，以去除衬底20，暴露第二有源结构22的表面，如图9所示。接下来，通过刻蚀去除浅槽隔离结构25的下半部分，以暴露出被浅槽隔离结构25覆盖的第二有源结构22，如图10所示。
在一些实施例中，在去除浅槽隔离结构25的下半部分时，可以保留一部分浅槽隔离结构25作为隔离层，以隔离第一晶体管11和第二晶体管12。
在步骤S105中，基于第二有源结构22，形成第二半导体结构。
在一实施例中，第二半导体结构包括第二栅极结构124和第二源漏结构122。
在一些实施例中，在暴露第二有源结构22之后，可以先进行前道工艺。首先，在刻蚀掉的浅槽隔离结构25之上的栅极区域内沉积半导体材料(如多晶硅)，至此，第二伪栅结构成型。这里，第二伪栅结构覆盖第二有源结构22。接下来，在第二伪栅结构的两侧，基于第二有源结构22形成源极结构和漏极结构(即第二源漏结构122)。这里，第二源漏结构122可以理解为第二晶体管12的源极结构和/或漏极结构。接下来，在第二源漏结构122和保留的浅槽隔离结构25上沉积层间介质材料(如二氧化硅)，以形成第二层间介质 结构123。至此，完成第二半导体结构的制备。
在一实施例中，在形成第二半导体结构之后，可以通过刻蚀工艺去除第二伪栅结构，以在刻蚀掉的第二伪栅结构处沉积金属材料，形成第二栅极结构124，即第二晶体管12的栅极结构，如图11所示。
需要说明的是，在制备第二晶体管12的栅极结构时，还未形成第一晶体管11的栅介质、金属栅、金属互连结构，因此热预算基本不受限制。
在一些实施例中，第二栅极结构124可以采用金属替代栅工艺形成，此时，第二栅极结构124可以为高k金属栅(high-k metal gate，HKMG)。其中，k指介电常数。那么，在制备去除第二伪栅结构之后，还可以在第二有源结构22的表面沉积栅极介质层，以隔离第二有源结构22与第二栅极结构124。在一示例中，栅极介质层由high k材料形成。
在步骤S106中，将第二半导体结构与第二载片晶圆29键合并翻转。
在一些实施例中，在步骤S106中，在形成第二半导体结构之后，在第二半导体结构的顶部沉积绝缘材料(如氧化硅)，以形成第二绝缘层28，并将第二绝缘层28与第二载片晶圆29键合。然后，可以翻转第二载片晶圆29，使得第二半导体结构朝下放置，第一载片晶圆27朝上放置，如图12所示。
可以理解的是，当第二半导体结构包括第二栅极结构124和第二源漏结构122时，在第二半导体结构的顶部沉积绝缘材料可以包括：在第二栅极结构124和第二层间介质结构123之上沉积绝缘材料，以形成第二绝缘层28。
在步骤S107中，去除第一载片晶圆27，以暴露第一半导体结构。
在一些实施例中，在翻转第一载片晶圆27之后，可以采用CMP工艺进行晶圆减薄，直至暴露出第一伪栅结构24，即去除第一绝缘层26和第一载片晶圆27，如图13所示。
在步骤S108中，在第一半导体结构中，去除第一伪栅结构24填充金属，以形成第一栅极结构114。
在一些实施例中，在步骤S108中，可以采用可数工艺去除第一伪栅结构24。然后，在去除的第一伪栅结构24处填充金属材料，以形成第一栅极结构114，如图14所示。
在一些实施例中，第一栅极结构114可以采用金属替代栅工艺形成，此时，第一栅极结构114可以为HKMG。那么，在制备去除第一伪栅结构24之后，还可以在第一有源结构21的表面沉积栅极介质层，以隔离第一有源结构21与第一栅极结构114。在一示例中，栅极介质层由high K材料形成。
在一些实施例中，可以根据实际情况，在第一栅极结构114和第二栅极结构124之间不设置浅槽隔离结构25。在一示例中，在形成第一栅极结构114之前，刻蚀浅槽隔离结构25直至暴露第二栅极结构124，形成栅极直连凹槽。在第二栅极结构之上沉积金属，形成第一栅极结构114。如此，第一晶体管11和第二晶体管12可以通过两者的栅极结构的接 触实现互连，不用再引出互连线。
在本公开实施例中，制备第一栅极结构114的金属材料和制备第二栅极结构124的金属材料可以根据实际情况采用相同或不同的金属材料，本公开实施例对此不做限定。
在本公开实施例中，上述金属材料可以为以下之一：氮化钽(TaN)、氮化钛(TiN)、氮化铝(AlN)、钛铝碳化物(TiAlC)、钛铝氮化物(TiAlN)，可以根据实际情况进行选择，并不限于上述列出的金属材料。
在步骤S109中，在第一源漏结构112上形成第一源漏金属115，以形成第一晶体管11。
在一些实施例中，刻蚀位于第一源漏结构112之上的第一层间介质结构113，直至暴露第一源漏结构112。然后，在刻蚀处沉积金属材料，以形成第一源漏金属115。至此，完成了第一晶体管11的前道工艺，从而得到了第一晶体管11，如图14所示。
在步骤S110中，在第一晶体管11上形成第一金属互连结构116。
在一些实施例中，仍参考图14，采用中道工艺，在第一源漏金属115上沉积层间介质材料(如二氧化硅)以形成层间介质，并在层间介质层上制作第一源漏结构112的第一金属接触孔32。然后，采用后道工艺，在层间介质层上形成第一金属互连层34。至此，第一金属互连结构116成型。
在一实施例中，形成有第一金属接触孔32的层间介质层组成第一接触金属层36。
在步骤S111中，将第一金属互连结构116与第三载片晶圆31键合并翻转。
在一些实施例中，在步骤S111中，在形成第一金属互连结构116之后，在第一金属互连结构116的顶部沉积绝缘材料(如氧化硅)，以形成第三绝缘层30；形成的第三绝缘层30可采用CMP工艺进行平坦化处理；随后，可将平坦化处理后的第三绝缘层30与第三载片晶圆31键合。然后，可以翻转第三载片晶圆31，使得第一晶体管11再次朝下放置，第二载片晶圆29朝上放置，如图15所示。
在步骤S112中，去除第二载片晶圆29，以暴露第二半导体结构。
在一些实施例中，在翻转第二载片晶圆29之后，可以采用CMP工艺进行晶圆减薄，直至暴露出第二栅极结构124，即去除第二绝缘层28和第二载片晶圆29，如图16所示。
可以理解的是，当第二半导体结构包括第二栅极结构124和第二源漏结构122时，去除第二载片晶圆29后，可暴露出第二栅极结构124和第二层间介质结构123。
在步骤S113、基于第二半导体结构，形成第二金属互连结构126。
在一些实施例中，参见图17，刻蚀位于第二源漏结构122之上的第二层间介质结构123，直至暴露第二源漏结构122。然后，在刻蚀处沉积金属材料，以形成第二源漏金属125。至此，完成了第二晶体管12的前道工艺。然后，采用中道工艺，在第二源漏金属125上沉积层间介质材料(如二氧化硅)以形成层间介质，并在层间介质层上制作第二源漏结构122的第二金属接触孔33。然后，采用后道工艺，在层间介质层上形成第二金属互连层 35。至此，第二金属互连结构126成型。
需要说明的是，形成有第二金属接触孔33的层间介质层组成第二接触金属层37，第二接触金属层37是在第二栅极结构124和第二源漏金属125上形成的。第二接触金属层37之上可以形成第二金属互连层35，从而获得第二金属互连结构126。
可以理解的是，形成第二金属接触孔33的金属材料可以是耐高温的材料。在一示例中，形成第二金属接触孔33的金属材料可以是钨(W)、钴(Co)等。
至此，完成了本公开实施例中的半导体器件的制备。
在本公开实施例中，通过多次晶圆键合与翻转，使第一晶体管的第一栅极结构和第一金属互连结构形成于第二晶体管的第二源漏结构之后，避免了第二晶体管在形成第二源漏结构时的较高工艺温度影响第一晶体管的第一栅极结构和第一金属互连结构，提高了半导体器件的热预算。
图18至图24是根据本公开实施例提供的一种半导体器件的制备过程的示意图，其中，图18至图24中的(a)为沿图2中的虚线A-A＇方向的剖视图；图18至图24中的(b)为沿图2中的虚线B-B＇方向的剖视图；图18至图24中的(c)为沿图2中的虚线C-C＇方向的剖视图。
下面将结合图1至图2以及图18至图24对本公开实施例提供的半导体器件10的制备方法以及制备得到的半导体器件10进行示例性的说明。
在一些实施例中，在上述制备过程中，在提高了堆叠晶体管制备过程的热预算的前提下，为了简化工艺流程，在通过步骤S105制备第二半导体结构的过程中，还可以执行步骤S201。在此情况下，第二半导体结构还包括第二源漏金属125和第二接触金属层37。其中，第二源漏金属125是在第二源漏结构122上沉积金属形成的，第二接触金属层37是在第二栅极结构124和第二源漏金属125上形成的。
在步骤S201中，基于第二有源结构22，形成第二源漏金属125和第二接触金属层37。
在一些实施例中，参见图10所示，通过步骤S101至步骤S104之后，可获得被暴露出的第二有源结构22。随后，参见图11所示，可通过步骤S105形成第二源漏结构122、第二层间介质结构123和第二栅极结构124。随后，还可通过步骤S201，形成第二源漏金属125和第二接触金属层37。
在一实施例中，可刻蚀位于第二源漏结构122之上的第二层间介质结构123，直至暴露第二源漏结构122。然后，在刻蚀处沉积金属材料，以形成第二源漏金属125。并在第二层间介质结构123和第二源漏金属125上形成层间介质层，并在层间介质层上制作第二源漏结构122的第二金属接触孔33，如图18所示。
需要说明的是，形成有第二金属接触孔33的层间介质层组成第二接触金属层37，第二接触金属层37是在第二栅极结构124和第二源漏金属125上形成的。这里，形成第二 金属接触孔33的金属材料可以是耐高温钨、钴等金属材料。
需要说明的是，在进行步骤S108和步骤S109时的工艺温度大于形成第二接触金属层37的工艺温度，所以第二接触金属层37采用耐高温金属材料，能够避免执行步骤S108和步骤S109时对第二接触金属层37产生影响。
需要说明的是，通过制备第二接触金属层37，有助于正反面晶体管的光刻对准。
在一些实施例中，在执行步骤S201之后，可完成了第二晶体管12的前道工艺和中道工艺。接下来，可执行步骤S106，参见图19所示，将第二半导体结构与第二载片晶圆29键合，包括：将第二接触金属层37与第二载片晶圆29键合。
可以理解的是，在形成第二接触金属层37之后，可以在第二接触金属层37的顶部沉积绝缘材料(如氧化硅)，以形成第二绝缘层28，并将第二绝缘层28与第二载片晶圆29键合，获得图19所示的结构。
在一些实施例中，在执行步骤S106之后，可以执行步骤S107至步骤S111。
参见图20至图22所示，在形成第二半导体结构(包括第二源漏金属125和第二接触金属层37)后，可以采用上述一个多个实施例中的步骤，完成第二次倒片后，重新制备第一晶体管11。
在一实施例中，首先可翻转第二载片晶圆29，使得第二半导体结构朝下放置，第一半导体结构和第一载片晶圆27朝上放置。随后，可采用CMP工艺进行晶圆减薄，直至暴露出第一伪栅结构24，如图20所示。随后，可采用替代金属栅(replacement metal gate，RMG)工艺形成第一栅极结构114，采用第一层间介质结构113的工艺在第一源漏结构112之上形成第一源漏金属115，以及采用中后道工艺形成第一金属互连结构116，如图21所示。随后，可将第一金属互连结构116与第三载片晶圆31进行键合并翻转，使得第三载片晶圆31朝下放置，第二载片晶圆29朝上放置，如图22所示。
在一些实施例中，在执行步骤S111之后，可以执行步骤S112，去除第二载片晶圆29，以暴露第二半导体结构(包括第二源漏金属125和第二接触金属层37)。在一示例中，采用CMP工艺进行晶圆减薄后，可暴露出第二接触金属层37，如图23所示。随后，执行步骤S113，通过后道工艺，在第二接触金属层37上形成第二金属互连层35，以形成第二金属互连结构126，如图24所示。
至此，完成了本公开实施例中的半导体器件10的制备。
在本公开实施例中，通过多次晶圆键合与翻转，使第一晶体管的第一栅极结构和第一金属互连结构形成于第二晶体管的第二源漏结构之后，避免了第二晶体管在形成第二源漏结构时的较高工艺温度影响第一晶体管的第一栅极结构和第一金属互连结构，提高了半导体器件的热预算。
在一些实施例中，本公开实施例提供了一种半导体器件。如图18和图24所示，该半 导体器件10是采用如上述一个或多个实施例中的方法制备得到的。该半导体器件10包括第一晶体管11和第二晶体管12。第二晶体管12与第一晶体管11相背设置。其中，第一晶体管11的第一有源结构21与第二晶体管12的第二有源结构22是通过同一工序形成的，第一晶体管11与第二晶体管12在垂直方向上自对准。
在一实施例中，垂直方向是指垂直于形成半导体器件10的衬底的方向。第一晶体管11与第二晶体管12自对准是指，第一晶体管11的栅极区域与第二晶体管12的栅极区域对准，第一晶体管11的源漏区域与第二晶体管12的源漏区域对准。
在一示例中，栅极区域是指形成栅极结构的区域；源漏区域是指形成源漏结构的区域。
可以理解的是，本公开实施例中的半导体器件在制备过程中，首先通过刻蚀形成深STI和较高有源区，随后在此有源区的上方制作第一晶体管的源漏结构，其后进行倒片，通过自对准刻蚀暴露出该有源区的下部，同时形成第二晶体管的部分结构。第二晶体管的部分结构制备完成后，再次倒片完成第一晶体管的后续制备。随后第三次倒片完成第二晶体管的后续制备。
在一实施例中，通过多次倒片的方式对上下两层晶体管中的伪栅成型，源漏制备，替代金属栅工艺。中道工序(MOL)及后道工序(BEOL)等工艺的顺序进行优化调整，使得耐高温的源漏结构具有优先级的制备顺序，从而有效提高后续制备工艺中的热预算，解决了晶体管的源漏制备工艺温度较高，而金属栅和金属互连线能耐受的工艺温度较低，导致堆叠晶体管的热预算受限的技术问题。
需要说明的是，上述半导体器件的第一种制备工艺和第二种制备工艺，仅为体现本公开实施例的技术构思的两个示例性的实施例。应理解的，将第一晶体管的第一栅极结构和第一金属互连结构形成于第二晶体管的第二源漏结构之后，避免形成第二源漏结构时的工艺温度影响第一晶体管的第一栅极结构和第一金属互连结构的技术方案，均在本公开实施例的保护范围之内。
在一示例中，存在一种二次倒片的方案。二次倒片方案可通过标准工艺流程，在原始硅衬底上刻蚀形成深STI和较高有源区，并沉积伪栅，形成第一晶体管的源漏结构。随后，第一晶体管与第一载片晶圆键合，进行第一次倒片，以将衬底置于正面。随后，采用标准STI刻蚀和有源区暴露工艺，以自对准的方式暴露第二晶体管的有源区。随后，完成第二晶体管的前道工艺、中道工艺和后道工艺(即制备到第二晶体管的金属互连层，且各金属互连线采用耐高温材料，以提高后续工艺的热预算)后，将第二晶体管与第二载片晶圆键合，进行第二次倒片。倒片后去除第一载片晶圆，暴露出第一晶体管，在第一晶体管中完成栅极成型工艺以及中道工艺和后道工艺。
本公开实施例优化了堆叠晶体管的工艺流程，还兼顾了上下层晶体管有源区和栅极的一致性、缺陷密度、对准和热预算等问题。本公开实施例采用了多次倒片的方案，考虑了 堆叠晶体管器件结构及其后道互连线的制备顺序，提高了整体器件制备过程的热预算。本公开实施例解决了堆叠晶体管现有单片方案所存在的工艺复杂、极性固定等长期难题层。本公开实施例解决了堆叠晶体管现有顺序方案所存在的对准困难、上层半导体材料缺陷密度高等长期难题。本公开实施例推进对晶体管堆叠技术产业化。
本公开实施例中的方案也是当前顺序和单片堆叠晶体管方案的有机融合，成熟技术复用度高，可以避免大量高昂的工艺开发以节省成本，具有很高的可行性。同时在本公开实施例中，倒装晶体管采用自对准的“背靠背”有源区和金属栅极设计，正反面晶体管拥有独立的信号和供电网络，并通过局域互联相接，在不改变极致微缩的4T轨道单元设计的条件下，极大的释放了金属布线资源(相较于当前方案提升达60％以上)，在工艺设计协同优化方向空间巨大。最后，倒装晶体管方案与已有主流器件架构兼容，可以实现包括平面晶体管、鳍式晶体管、全环绕栅极晶体管乃至垂直晶体管的正反面堆叠，而无需针对特定器件架构进行特殊工艺开发，灵活性强，从半导体制程节点迭代角度考虑其延伸性很强。倒装晶体管在概念上十分超前，具有重要的产业价值，且实用性强、拓展前景广泛。
在一些实施例中，本公开实施例提供一种电子设备。电子设备包括：电路板以及如上述一个或多个实施例中的半导体器件，半导体器件设置于电路板。
在上述实施例中，对各个实施例的描述各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上所述，仅为本公开示例性的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应该以权利要求的保护范围为准。

Claims (10)

  1. 半导体器件的制备方法，其中，包括：
    在衬底上形成有源结构；其中，所述有源结构包括在第一方向上堆叠设置的第一有源结构和第二有源结构，所述第一方向垂直于所述衬底；
    基于所述第一有源结构，形成第一半导体结构，所述第一半导体结构包括第一伪栅结构和第一源漏结构；
    将所述第一半导体结构与第一载片晶圆键合并翻转；
    去除所述衬底，并暴露所述第二有源结构；
    基于所述第二有源结构，形成第二半导体结构，所述第二半导体结构包括第二栅极结构和第二源漏结构；
    将所述第二半导体结构与第二载片晶圆键合并翻转；
    去除所述第一载片晶圆，以暴露所述第一半导体结构；
    在所述第一半导体结构中，去除所述第一伪栅结构填充金属，以形成第一栅极结构；
    在所述第一源漏结构上形成第一源漏金属，以形成第一晶体管；
    通过后道工艺，在所述第一晶体管上形成第一金属互连结构；
    将所述第一金属互连结构与第三载片晶圆键合并翻转；
    去除所述第二载片晶圆，以暴露所述第二半导体结构；
    基于所述第二半导体结构，形成第二金属互连结构。
  2. 根据权利要求1所述的方法，其中，所述基于所述第二半导体结构，形成第二金属互连结构，包括：
    在所述第二源漏结构上形成第二源漏金属，以形成第二晶体管；
    在所述第二晶体管上形成所述第二金属互连结构。
  3. 根据权利要求1所述的方法，其中，所述第二半导体结构还包括：第二源漏金属以及第二接触金属层，其中，所述第二源漏金属是在所述第二源漏结构上沉积金属形成的，所述第二接触金属层是在所述第二栅极结构和所述第二源漏金属上形成的；
    所述基于所述第二半导体结构，形成第二金属互连结构，包括：
    通过后道工艺，在所述第二接触金属层上形成第二金属互连层，以形成第二金属互连结构。
  4. 根据权利要求3所述的方法，其中，所述第二接触金属层是采用耐高温金属材料形成的。
  5. 根据权利要求1所述的方法，其中，在所述在衬底上形成有源结构之后，且在所述基于所述第一有源结构，形成第一半导体结构之前，所述方法还包括：
    在所述衬底上沉积半导体材料，以形成浅沟槽隔离层，所述浅沟槽隔离层包裹所述第二有源结构，所述第一有源结构暴露于所述浅沟槽隔离层之外。
  6. 根据权利要求5所述的方法，其中，所述去除所述衬底，并暴露所述第二有源结构，包括：
    通过化学机械抛光工艺，去除所述衬底以及浅沟槽隔离层的一部分，以暴露所述第二有源结构。
  7. 根据权利要求1所述的方法，其中，所述第一有源结构和所述第二有源结构的连接处通过离子注入形成有电学隔离层，所述电学隔离层用于对所述第一有源结构和所述第二有源结构进行电学隔离。
  8. 根据权利要求1所述的方法，其中，所述第一晶体管为鳍式场效应晶体管、全环绕栅极晶体管以及平面晶体管中之一。
  9. 一种半导体器件，所述半导体器件是采用如权利要求1至8任一项所述的方法制备得到的；其中，所述半导体器件包括：
    第一晶体管；
    第二晶体管，所述第二晶体管与所述第一晶体管相背设置；
    其中，所述第一晶体管的第一有源结构与所述第二晶体管的第二有源结构是通过同一工序形成的，所述第一晶体管与所述第二晶体管在垂直方向上自对准。
  10. 一种电子设备，其中，包括：电路板以及如权利要求9所述的半导体器件，所述半导体器件设置于所述电路板上。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
CN118280925B (zh) * 2024-04-11 2025-03-18 北京大学 半导体器件的制备方法、半导体器件及电子设备
CN119364884B (zh) * 2024-09-29 2026-02-27 北京知识产权运营管理有限公司 半导体结构的制备方法、半导体结构、器件及设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200279933A1 (en) * 2019-03-01 2020-09-03 International Buisness Machines Corporation Interlayer dielectric replacement techniques with protection for source/drain contacts
CN114450772A (zh) * 2019-09-27 2022-05-06 东京毅力科创株式会社 三维逻辑器件的反向触点和硅化物工艺
CN116264232A (zh) * 2021-12-15 2023-06-16 Imec 非营利协会 垂直堆叠的晶体管结构
CN117133719A (zh) * 2023-08-07 2023-11-28 北京大学 一种半导体结构的制备方法及半导体结构
CN117352459A (zh) * 2023-09-21 2024-01-05 北京大学 一种半导体结构的制备方法、半导体结构、器件及设备
CN118280925A (zh) * 2024-04-11 2024-07-02 北京大学 半导体器件的制备方法、半导体器件及电子设备

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5022549B2 (ja) * 2000-01-28 2012-09-12 アイメック 半導体デバイスを移動、及び、積層させる方法
JP5306589B2 (ja) * 2006-11-17 2013-10-02 シャープ株式会社 半導体発光素子及びその製造方法
JP5249173B2 (ja) * 2009-10-30 2013-07-31 新光電気工業株式会社 半導体素子実装配線基板及びその製造方法
US9171843B2 (en) * 2013-08-02 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabricating the same
FR3052293B1 (fr) * 2016-06-07 2018-11-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de fabrication d'un empilement de dispositifs electroniques
CN107658317B (zh) * 2017-09-15 2019-01-01 长江存储科技有限责任公司 一种半导体装置及其制备方法
KR102198344B1 (ko) * 2018-12-31 2021-01-04 연세대학교 산학협력단 3 차원 적층 소자 제조 방법
CN111129112B (zh) * 2019-12-19 2021-09-14 中国科学院微电子研究所 一种半导体器件及其制备方法
KR20230146374A (ko) * 2022-04-12 2023-10-19 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 제조방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200279933A1 (en) * 2019-03-01 2020-09-03 International Buisness Machines Corporation Interlayer dielectric replacement techniques with protection for source/drain contacts
CN114450772A (zh) * 2019-09-27 2022-05-06 东京毅力科创株式会社 三维逻辑器件的反向触点和硅化物工艺
CN116264232A (zh) * 2021-12-15 2023-06-16 Imec 非营利协会 垂直堆叠的晶体管结构
CN117133719A (zh) * 2023-08-07 2023-11-28 北京大学 一种半导体结构的制备方法及半导体结构
CN117352459A (zh) * 2023-09-21 2024-01-05 北京大学 一种半导体结构的制备方法、半导体结构、器件及设备
CN118280925A (zh) * 2024-04-11 2024-07-02 北京大学 半导体器件的制备方法、半导体器件及电子设备

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