Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/80—FETs having rectifying junction gate electrodes
  • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes

Definitions

• This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.
• Patent Document 1 requires an etching step to reduce contact resistance, which complicates the manufacturing process.
• This disclosure has been made to solve the above problems, and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can reduce contact resistance while minimizing the complexity of the manufacturing process.
• the semiconductor device disclosed herein comprises a semiconductor substrate, a channel layer formed on the semiconductor substrate, a barrier layer formed on the channel layer, and an electrode formed on the barrier layer and having a region diffused into the barrier layer to a depth of at least half the thickness of the barrier layer.
• This disclosure makes it possible to obtain a semiconductor device that reduces contact resistance while minimizing the complexity of the manufacturing process.
• FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment
• 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device according to a first embodiment
• 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device according to a first embodiment
• 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device according to a first embodiment
• 1 is an electron microscope photograph of a cross section of a conventional semiconductor device.
• 1 is an electron microscope photograph of a cross section of a semiconductor device according to a first embodiment.
• FIG. 10 is a diagram showing the annealing temperature dependence of the contact resistivity of the semiconductor device according to the first embodiment.
• the semiconductor device 10 includes a semiconductor substrate 12.
• the semiconductor substrate 12 is made of, for example, Si.
• a channel layer 14 is formed on the semiconductor substrate 12.
• the channel layer 14 is made of, for example, GaN.
• a barrier layer 16 is formed on the channel layer 14.
• the barrier layer 16 is made of, for example, AlGaN.
• a highly concentrated two-dimensional electron gas is formed at the boundary between the channel layer 14 and the barrier layer 16.
• the electrode 18 has a first alloy layer 20 and a second alloy layer 22 stacked from the side closest to the semiconductor substrate 12.
• the first alloy layer 20 has a region diffused into the barrier layer 16 to a depth of more than half the thickness of the barrier layer 16.
• the first alloy layer 20 contains, for example, Ga, N, Ta, Al, Au, or Nb, and further contains any of Ti, Ni, Mo, or Pt.
• the second alloy layer contains, for example, Al, Au, or Nb, and further contains any of Ti, Ni, Mo, or Pt.
• the electrode 18 may have more than the two alloy layers stacked above, as long as it has a multilayer structure in which at least the first alloy layer 20 and the second alloy layer 22 are stacked from the side closest to the semiconductor substrate 12.
• a channel layer 14 is formed on a semiconductor substrate 12.
• the channel layer 14 is formed, for example, by Metal Organic Chemical Vapor Deposition (MOCVD).
• MOCVD Metal Organic Chemical Vapor Deposition
• a barrier layer 16 is formed on the channel layer 14.
• the barrier layer 16 is also formed, for example, by MOCVD.
• thermal annealing is performed to form the first alloy layer 20 and the second alloy layer 22, thereby forming the semiconductor device 10 shown in Figure 1.
• Rapid thermal annealing for example, can be used as the thermal annealing method.
• Thermal annealing is performed in a nitrogen atmosphere at a temperature range of 830 to 900°C. Note that the electrode 18 may be exposed during thermal annealing, but thermal annealing may also be performed after forming an insulating film such as SiN by chemical vapor deposition, for example.
• Figure 5 is a photograph of the cross section of the conventional semiconductor device taken using an electron microscope. As can be seen from Figure 5, the electrodes do not diffuse deep into the barrier layer made of AlGaN.
• Ta/Al/Ni/Au are stacked as electrodes, and then thermal annealing is performed.
• alloying occurs due to thermal annealing, but only phases such as TaAlAuNi, AlNi, and AlAu are formed, and the degree of alloy diffusion is small.
• Figure 6 shows an electron microscope photograph of a cross section of the semiconductor device 10 according to the first embodiment.
• the semiconductor device 10 according to the first embodiment was fabricated by stacking Ta/Al/Ni/Au/Nb electrodes and then thermally annealing them at temperatures ranging from 830 to 900°C.
• the semiconductor device 10 exhibits a greater degree of diffusion in the electrode 18 than the conventional semiconductor device. Specifically, a region in the electrode where diffusion reaches more than half the depth of the barrier layer is observed, which is not observed in the conventional semiconductor device.
• AlAuNb is formed on the upper layer side of the electrode at around 800°C during temperature rise, and TaAlAuNi is formed on the lower layer side.
• the annealing temperature reaches at least 830°C, the Nb on the upper layer diffuses to the lower layer side, and in the process, the TaAlAuNbNi layer diffuses deep into the barrier layer. This action results in a region in the electrode where diffusion reaches more than half the depth of the barrier layer.
• FIG. 7 is a graph showing the results of measuring the contact resistivity of the electrode 18 in the semiconductor device 10 according to the first embodiment.
• the horizontal axis represents the annealing temperature (°C), and the vertical axis represents the contact resistivity ( ⁇ cm 2 ) of the electrode 18. From this graph, it can be seen that the contact resistivity is lower when the annealing temperature is 830 to 900°C than when the annealing temperature is 600 to 800°C. Thus, if the electrode contains Nb and thermal annealing is performed at an annealing temperature of 830 to 900°C, the electrode 18 diffuses into the barrier layer 16, thereby reducing the contact resistivity.
• the first alloy layer 20 has a region that diffuses into the barrier layer 16 to a depth of more than half the thickness of the barrier layer 16, and therefore the contact resistance of the electrode 18 is low. Furthermore, obtaining an electrode 18 with low contact resistance simply requires performing thermal annealing, which helps to prevent the manufacturing process from becoming too complicated.
• Embodiment 2 is similar to the first embodiment, but differs in that the center of the electrode does not diffuse into the barrier layer to a depth of more than half the thickness of the barrier layer when viewed from a direction perpendicular to the semiconductor substrate.
• a method for manufacturing a semiconductor device 20 according to the second embodiment will now be described.
• the method for manufacturing the semiconductor device 20 is the same as in the first embodiment up to the step of forming the electrode as shown in Figure 4.
• the layer structure of the electrode 38 is the same as in the first embodiment, and is assumed to be, for example, a laminate of Ta/Al/Ni/Au/Nb.
• a resist 44 is formed to cover the peripheral portion 48 of the electrode 38 as shown in Figure 9.
• the Nb in the central portion 46 of the electrode 38 is etched by reactive dry etching using a fluorine-based gas such as SF6 or CF4. At this time, the Nb may be completely removed or may be partially left.
• the resist 44 is removed. Removal methods include dry ashing and methods using a resist removal chemical.
• thermal annealing is performed in the same manner as in embodiment 1 to obtain the semiconductor device 20 shown in Figure 8.
• Thermal annealing results in a layer structure consisting of a first alloy layer 40 and a second alloy layer 42 in the peripheral region 48, which contains a sufficient amount of Nb.
• the first alloy layer 40 diffuses into the barrier layer 36, thereby reducing the contact resistance of the electrode 38.

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