WO2025199848A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置

Info

Publication number
WO2025199848A1
WO2025199848A1 PCT/CN2024/084315 CN2024084315W WO2025199848A1 WO 2025199848 A1 WO2025199848 A1 WO 2025199848A1 CN 2024084315 W CN2024084315 W CN 2024084315W WO 2025199848 A1 WO2025199848 A1 WO 2025199848A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
hollow portions
hollow
orthographic projection
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/084315
Other languages
English (en)
French (fr)
Other versions
WO2025199848A9 (zh
Inventor
谢涛峰
于池
胡静
何帆
徐光华
魏玉龙
胡明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202480000621.1A priority Critical patent/CN121040243A/zh
Priority to PCT/CN2024/084315 priority patent/WO2025199848A1/zh
Publication of WO2025199848A1 publication Critical patent/WO2025199848A1/zh
Publication of WO2025199848A9 publication Critical patent/WO2025199848A9/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/82—Interconnections, e.g. terminals

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device.
  • OLED Organic light-emitting diodes
  • QLED quantum-dot light-emitting diodes
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the substrate further includes a hole area
  • the peripheral area includes a winding area located between the hole area and the display area; and the plurality of first traces and the compensation plate are both located in the winding area.
  • the hollow structure has at least one first hollow edge, the extension direction of the at least one first hollow edge is parallel to the extension direction of at least one first line among the multiple first lines, and the orthographic projection of the at least one first hollow edge on the substrate is located within the orthographic projection range of the at least one first line on the substrate.
  • the multiple first routing lines are alternately arranged in a first gate metal layer and a second gate metal layer, the second gate metal layer is located on a side of the first gate metal layer away from the substrate, and adjacent first routing lines in the multiple first routing lines do not overlap in their orthographic projections on the substrate; the compensation plate is located in the bottom shading metal layer, and the bottom shading metal layer is located on a side of the first gate metal layer close to the substrate.
  • the multiple first traces include: multiple straight trace segments extending in the same direction; the hollow structure of the compensation plate includes: multiple first hollow portions; at least one first hollow portion among the multiple first hollow portions has a first edge, and the extension direction of the first edge is parallel to the extension direction of the multiple straight trace segments; a first edge of a single first hollow portion is located within the orthographic projection range of a straight trace segment on the substrate.
  • the at least one first hollow portion has a rectangular projection on the substrate, and the at least one first hollow portion also has a second edge, the extension direction of the second edge is perpendicular to the extension direction of the first edge, and the orthographic projection of the second edge on the substrate overlaps with the orthographic projection of at least two of the multiple straight line segments on the substrate.
  • the plurality of first hollow portions are arranged in an array along an extension direction of the plurality of straight line segments, and adjacent first hollow portions are aligned in the extension direction of the plurality of straight line segments.
  • the plurality of first hollow portions are arranged in an array along an extension direction of the plurality of straight line segments, and in the extension direction of the plurality of straight line segments, at least two adjacent first hollow portions are staggered.
  • the multiple first hollow portions arranged along the extension direction of the multiple straight line segments form a row of first hollow portions
  • the row of first hollow portions includes: a third group of hollow portions and a fourth group of hollow portions that are alternately arranged, the multiple first hollow portions in the third group of hollow portions are staggered, and the multiple first hollow portions in the fourth group of hollow portions are staggered; at least one first hollow portion in the third group of hollow portions is aligned with at least one first hollow portion in the fourth group of hollow portions.
  • the multiple first hollow portions arranged along the extension direction of the multiple straight line segments form a row of first hollow portions
  • the row of first hollow portions includes: multiple fifth groups of hollow portions arranged in sequence, the multiple first hollow portions within the fifth groups of hollow portions are staggered, and adjacent fifth groups of hollow portions are aligned.
  • the multiple first routing lines include: multiple arc routing segments extending in the same direction;
  • the hollow structure of the compensation plate includes: multiple second hollow portions; the multiple second hollow portions are arranged along the extension direction of the multiple arc routing segments; at least one second hollow portion among the multiple second hollow portions has a third edge, the extension direction of the third edge is parallel to the extension direction of the multiple arc routing segments, and the third edge of a single second hollow portion is located within the orthographic projection range of an arc routing segment on the substrate.
  • the hollow structure of the compensation plate includes: at least one third hollow portion; the at least one third hollow portion extends along at least a portion of the edge of the hole area; the length of the first routing line that overlaps with the orthographic projection of the at least one third hollow portion on the substrate is greater than the length of the first routing line that does not overlap with the orthographic projection of the at least one third hollow portion on the substrate.
  • At least a portion of an edge of the at least one third hollow portion has a step shape in the orthographic projection of the substrate;
  • the step shape includes: a plurality of step structures connected in sequence, each step structure including a first step and a second step connected to each other; the first step and the second step are straight line segments with different extension directions;
  • the orthographic projection of the first step of each step structure on the substrate is located within the orthographic projection range of a first line on the substrate, and the orthographic projection of the second step on the substrate overlaps with the orthographic projections of at least two adjacent first lines on the substrate.
  • the step shape further includes: a step connecting segment connecting adjacent step structures, and the step connecting segment is an arc segment.
  • this embodiment provides a display device including the display substrate as described above.
  • FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG2 is a schematic diagram of the grid lines in FIG1 ;
  • 3B is another partial cross-sectional schematic diagram of the display region of the display substrate according to at least one embodiment of the present disclosure
  • FIG4 is a schematic partial cross-sectional view along the Q-Q' direction in FIG2;
  • FIG. 5 is a schematic diagram showing the positions of a first straight connecting segment of a gate connecting trace and a plurality of first hollow portions of a compensation plate according to at least one embodiment of the present disclosure
  • FIG6A is a partial enlarged schematic diagram of area S1 in FIG1 ;
  • FIG6C is a schematic diagram of the compensation plate in FIG6A ;
  • FIG. 7 is a schematic diagram illustrating another position of the first straight connecting segment of the gate connecting trace and the plurality of first hollow portions of the compensation plate according to at least one embodiment of the present disclosure
  • FIG. 8 is a schematic diagram illustrating another position of the first straight connecting segment of the gate connecting trace and the plurality of first hollow portions of the compensation plate according to at least one embodiment of the present disclosure
  • FIG. 9 is a schematic diagram illustrating another position of the first straight connecting segment of the gate connecting trace and the plurality of first hollow portions of the compensation plate according to at least one embodiment of the present disclosure
  • FIG10B is a schematic diagram of a first straight line connection segment of a plurality of gate connection lines in FIG10A;
  • FIG11A is a partial enlarged schematic diagram of area S2 in FIG1 ;
  • FIG11B is a schematic diagram of multiple arc-shaped connecting segments in FIG11A;
  • FIG11C is a schematic diagram of the compensation plate in FIG11A ;
  • FIG12 is a schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure.
  • FIG13A is a partial schematic diagram of an edge of a third hollow portion according to at least one embodiment of the present disclosure.
  • FIG13B is another partial schematic diagram of the edge of the third hollow portion according to at least one embodiment of the present disclosure.
  • FIG14 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure.
  • FIG15 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure.
  • FIG16 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure.
  • FIG17 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure.
  • FIG18 is another schematic diagram of gate connection routing in the winding area according to at least one embodiment of the present disclosure.
  • FIG19 is a schematic diagram showing the positions of the broken line connection segment of the gate connection trace and the first hollow portion of the compensation plate according to at least one embodiment of the present disclosure
  • the orthographic projection of A includes the orthographic projection of B
  • the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the “shape of A” mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.
  • This embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first wirings, and a compensation plate.
  • the substrate comprises a display area and a peripheral area located on at least one side of the display area.
  • the plurality of sub-pixels are arranged on one side of the substrate and are located in the display area.
  • the plurality of first wirings are located in the peripheral area and are electrically connected to the plurality of sub-pixels.
  • the compensation plate is located in the peripheral area, and at least one insulating layer is provided between the compensation plate and the plurality of first wirings.
  • the orthographic projection of the compensation plate on the substrate partially overlaps with the orthographic projection of the plurality of first wirings on the substrate.
  • the compensation plate has a hollow structure, and the orthographic projection of the hollow structure on the substrate partially overlaps with the orthographic projection of at least one first wiring on the substrate.
  • the hollow structure of the compensation plate can be located within the compensation plate, for example, and can include multiple openings or slots located independently within the compensation plate.
  • the edges of the hollow structure may not be connected to the outer edge of the compensation plate.
  • the hollow structure can be located at the outer edge of the compensation plate, such that at least a portion of the edge of the hollow structure can be connected to the outer edge of the compensation plate.
  • the edge of the hollow structure can serve as part of the outer edge of the compensation plate.
  • the outer edge of the compensation plate in this example can be irregularly shaped.
  • the display substrate provided in this embodiment can perform capacitance compensation on the first routing line by providing a compensation plate that overlaps with the orthographic projection of the first routing line on the substrate, thereby achieving load compensation for the first routing line; moreover, the compensation plate has a hollow structure, and by providing the hollow structure, the overlapping area between multiple first routing lines and the orthographic projection of the compensation plate on the substrate can be adjusted, thereby achieving differentiated load compensation for different first routing lines.
  • the substrate may further include an aperture region.
  • the peripheral region may include a wiring region located between the aperture region and the display region.
  • the plurality of first traces and the compensation plate may be located in the wiring region. In this example, by providing the compensation plate in the wiring region, load compensation can be provided for the first traces that bypass the aperture region, thereby reducing signal load differences caused by the aperture region.
  • the hollow structure may have at least one first hollow edge, at least one first The direction in which the hollow edge extends is parallel to the direction in which the at least one first trace extends, and the orthographic projection of the at least one first hollow edge on the substrate can be located within the orthographic projection of the at least one first trace on the substrate.
  • the orthographic projection of the first trace on the substrate to overlap the orthographic projection of the first hollow edge of the hollow structure on the substrate, the effect of the hollow edge on the film formation of the upper insulating layer, which in turn affects the presence of residual material (remaining) or poor routing in the upper conductive layer, can be reduced.
  • the orthographic projection of the first hollow portion on the substrate may be annular or another shape.
  • the orthographic projections of the linear trace segments of the first trace on the substrate overlap the orthographic projections of the first edges of the first hollow portions on the substrate, it is possible to mitigate the problem of the edges of the hollow structure affecting the conductive layer above, resulting in residual material or poor routing.
  • the hollow structure of the compensation plate may include: at least one third hollow portion; the at least one third hollow portion may extend along at least a portion of the edge of the hole area.
  • the length of the first routing line that overlaps with the orthographic projection of the at least one third hollow portion on the substrate may be greater than the length of the first routing line that does not overlap with the orthographic projection of the at least one third hollow portion on the substrate.
  • the orthographic projection of the third hollow portion on the substrate may be an arc-shaped hollow groove provided in the compensation plate.
  • the third hollow portion may be an annular hollow groove. In this example, by providing a third hollow portion extending along the edge of the hole area, differentiated load compensation for multiple first routing lines can be achieved.
  • the orthographic projection of at least a portion of the edge of at least one third hollow portion on the substrate may be in the shape of a step.
  • the step shape may include: a plurality of step structures connected in sequence, each step structure may include a first step and a second step connected to each other; the first step and the second step are straight line segments extending in different directions.
  • the orthographic projection of the first step of each step structure on the substrate may be located within the orthographic projection range of a first routing line on the substrate, and the orthographic projection of the second step on the substrate may overlap with the orthographic projections of at least two adjacent first routing lines on the substrate.
  • the first hollow edge of the hollow structure may include the first step of multiple step structures.
  • this example can achieve differentiated load compensation for multiple first routing lines, and can also improve the situation where the edge of the hollow structure affects the presence of material residue or poor routing in the conductive layer above.
  • FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG2 is a schematic diagram of a gate line in FIG1.
  • the display substrate may include: an aperture area A2, a display area A1 located on at least one side of the aperture area A2, and a peripheral area BB located on at least one side of the display area A1.
  • Peripheral area BB may include: a winding area B5 located between the aperture area A2 and the display area A1; a first peripheral area B1 and a fourth peripheral area B4 located on either side of the display area A1 along the second direction Y; and a second peripheral area B2 and a third peripheral area B3 located on either side of the display area A1 along the first direction X.
  • the first peripheral area B1 may be connected to the second peripheral area B2 and the third peripheral area B3 and connected to the display area A1; the fourth peripheral area B4 may be connected to the second peripheral area B2 and the third peripheral area B3 and connected to the display area A1.
  • the first peripheral area B1, the second peripheral area B2, the third peripheral area B3, and the fourth peripheral area B4 may be connected to surround the display area A1.
  • the first peripheral region B1 may be the lower frame region of the display substrate
  • the second peripheral region B2 may be the left frame region of the display substrate
  • the third peripheral region B3 may be the right frame region of the display substrate
  • the fourth peripheral region B4 may be the upper frame region of the display substrate.
  • this embodiment is not limited to this.
  • no sub-pixels are set in the hole area A2, and the hole area A2 is not used for display; in other words, the hole area A2 can be a non-display area.
  • No sub-pixels can be set in the winding area B5, and the winding area B5 can be not used for display.
  • the orthographic projection of the hole area A2 may be circular.
  • the diameter of the hole area A2 may range from 6 mm to 20 mm, such as approximately 12 mm.
  • this embodiment is not limited thereto.
  • the orthographic projection of the hole area A2 may be rectangular, rounded rectangular, elliptical, semicircular, pentagonal, hexagonal, etc.
  • the edge of the hole area A2 can be the inner edge of the winding area B5, and the outer edge of the winding area B5 can be connected to the display area A1.
  • the orthographic projection shape of the hole area A2 can be circular, and the orthographic projection shape of the winding area B5 can be an annular ring.
  • this embodiment is not limited to this.
  • the orthographic projection shape of the winding area can match the shape of the hole area; for example, the orthographic projection shape of the hole area is rectangular, and the orthographic projection shape of the winding area can be a rectangular ring; or, the orthographic projection shape of the hole area is elliptical, and the orthographic projection shape of the winding area can be an elliptical ring.
  • the hole area A2 can be located in the middle of the display area A1, so that the display area A1 surrounds the hole area A2.
  • this embodiment is not limited to this.
  • the hole area can be adjacent to the upper edge or lower edge of the display area, so that the display area surrounds at least the left and right sides of the hole area.
  • the display area A1 may include: multiple gate lines and multiple data lines.
  • the multiple gate lines may extend along a first direction X and be arranged along a second direction Y; the multiple data lines may extend along the second direction Y and be arranged along the first direction X.
  • the orthographic projections of the multiple gate lines and the multiple data lines on the substrate may intersect to form multiple sub-pixel regions, with a sub-pixel PX disposed in each sub-pixel region.
  • the multiple data lines are electrically connected to the multiple sub-pixels PX and may be configured to provide data signals to the multiple sub-pixels PX.
  • the multiple gate lines are electrically connected to the multiple sub-pixels PX and may be configured to provide gate drive signals to the multiple sub-pixels PX.
  • the plurality of gate lines may include: a plurality of first-class gate lines 311 and a plurality of second-class gate lines 312.
  • Each gate line may connect a plurality of sub-pixels arranged along the first direction X. Since the aperture area A2 does not have sub-pixels, the number of sub-pixels connected to at least one first-class gate line 311 may be less than the number of sub-pixels connected to at least one second-class gate line 312. The signal load of at least one first-class gate line 311 may be less than the signal load of at least one second-class gate line 312. Number load.
  • the plurality of second-type gate lines 312 may extend along the first direction X and be arranged along the second direction Y.
  • the plurality of second-type gate lines 312 may be divided into two groups arranged along the second direction Y, and the plurality of first-type gate lines 311 may be located between the two groups of second-type gate lines 312 in the second direction Y.
  • a plurality of first-type gate lines 311 are interrupted by the aperture area A2 in the first direction X.
  • the first-type gate lines 311 may include a first gate extension 311-1 and a second gate extension 311-2 located in the display area A1.
  • the first gate extension 311-1 and the second gate extension 311-2 may be connected by a gate connection trace 33 located in the winding area B5.
  • the gate connection trace 33 may be arranged along the aperture area A2.
  • the plurality of data lines may include: a plurality of first-type data lines 321 and a plurality of second-type data lines 322.
  • Each data line may connect to a plurality of sub-pixels arranged along the second direction Y. Since no sub-pixels are provided in the aperture area A2, the number of sub-pixels connected to the at least one first-type data line 321 may be smaller than the number of sub-pixels connected to the at least one second-type data line 322, and the signal load of the at least one first-type data line 321 may be smaller than the signal load of the at least one second-type data line 322.
  • first data connection segment 321-1 and the second data connection segment 321-2 of the first type data line 321, and the data connection trace 34 can be an integrated structure connected to each other; or, the first data connection segment 321-1 and the second data connection segment 321-2 can be located in the same conductive layer, and the conductive layer where the data connection trace 34 is located can be different from the conductive layer where the first data connection segment 321-1 is located.
  • a pixel unit of the display area A1 may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light).
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.
  • a sub-pixel PX may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit.
  • the pixel circuit may include multiple transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • T refers to a thin film transistor
  • C refers to a capacitor
  • the number before T represents the number of thin film transistors in the circuit
  • the number before C represents the number of capacitors in the circuit.
  • the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.
  • the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield.
  • the shape of the light-emitting elements of a sub-pixel can be rectangular, rhombus, pentagonal, or hexagonal.
  • the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern.
  • this embodiment is not limited to this.
  • the light-emitting element can be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc.
  • the light-emitting element can be an OLED, and the light-emitting element can emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit.
  • the color of the light emitted by the light-emitting element can be determined according to needs.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element can be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • Figure 3A is a schematic partial cross-sectional view of a display region of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 3A illustrates the structure of a sub-pixel in the display region as an example.
  • the multiple pixel transistors in the pixel circuit can be of different transistor types, such as low-temperature polysilicon thin-film transistors and oxide thin-film transistors.
  • the display area of the display substrate may include: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate 10.
  • the circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor.
  • the light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels.
  • the display substrate may further include: a touch structure layer located on a side of the encapsulation structure layer away from the substrate.
  • the touch structure layer may include at least one touch conductive layer.
  • the circuit structure layer 12 of the display area may include: a bottom shielding metal layer (BSM) arranged on the substrate 10, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source and drain metal layer, and a second source and drain metal layer.
  • BSM bottom shielding metal layer
  • the side of the second source/drain metal layer away from the substrate 10 may be provided with a ninth insulating layer 109.
  • the seventh insulating layer 107 may also be referred to as a passivation layer
  • the eighth insulating layer 108 may also be referred to as a first planarization layer
  • the ninth insulating layer 109 may also be referred to as a second planarization layer.
  • the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, the sixth insulating layer 106, and the seventh insulating layer 107 may be inorganic insulating layers, and the eighth insulating layer 108 and the ninth insulating layer 109 may be organic insulating layers.
  • this embodiment is not limited to this.
  • a buffer layer may be provided on the side of the bottom light-shielding metal layer close to the substrate. The buffer layer may prevent harmful substances in the substrate from invading the interior of the display substrate and may also increase the adhesion of the film layer in the display substrate to the substrate.
  • the bottom light-shielding metal layer of the display area may include at least a light-shielding block 25.
  • the light-shielding block 25 may be configured to at least partially cover the active layer of the transistor in the pixel circuit to prevent external light from affecting the transistor's performance.
  • the light-shielding block 25 may be electrically connected to the constant voltage signal line in the peripheral area.
  • the light-shielding block 25 may be configured to receive a first power supply signal.
  • the first semiconductor layer in the display area may include at least a first active layer 210 of the first transistor 21.
  • the second semiconductor layer may include at least the second active layer 220 of the second transistor 22.
  • the third gate metal layer may include at least the second gate 223 of the second transistor 22.
  • the orthographic projection of the second gate 223 of the second transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10.
  • the first source-drain metal layer may include at least a first source 211 and a first drain 212 of the first transistor 21, and a second source 221 and a second drain 222 of the second transistor 22.
  • the sixth insulating layer 106 may have a plurality of pixel vias (e.g., a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area.
  • the sixth insulating layer 106, the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102 within the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210; and the sixth insulating layer 106, the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102 within the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210.
  • the sixth insulating layer 106 and the fifth insulating layer 105 within the third and fourth pixel vias can be removed, exposing at least portions of the surfaces of both ends of the second active layer 220.
  • the first source electrode 211 of the first transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain electrode 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via.
  • the second source electrode 221 of the second transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain electrode 222 of the second transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via.
  • the second source-drain metal layer can include at least a first transition electrode 241.
  • the first transition electrode 241 can be electrically connected to the first drain electrode 212 of the first transistor 21 of the pixel circuit through a fifth pixel via defined through the eighth and seventh insulating layers 108 and 107.
  • the first transition electrode 241 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.
  • the light emitting structure layer 13 may include: a pixel definition layer 134 and a plurality of light emitting elements.
  • each light emitting element may include: a stacked first electrode 131, an organic light emitting layer 132, and a second electrode 133.
  • the first electrode 131 of the light emitting element may be an anode.
  • the first electrode 131 may be disposed on the ninth insulating layer 109 and electrically connected to the first transfer electrode 241 through the sixth pixel via hole provided in the ninth insulating layer 109.
  • the pixel definition layer 134 is provided on the first electrode 131 and the ninth insulating layer 109.
  • the pixel definition layer 134 may be provided with a plurality of pixel openings, and one pixel opening may expose at least a portion of the surface of a corresponding first electrode 131.
  • the organic light emitting layer 132 At least a portion of the first electrode 131 may be disposed within a pixel opening and connected to the corresponding first electrode 131.
  • the second electrode 133 may be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.
  • the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL).
  • EML emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • HBL hole blocking layer
  • EBL electron blocking layer
  • EIL electron injection layer
  • ETL electron transport layer
  • the light-emitting layers of light-emitting elements of different colors may be different.
  • a red light-emitting element includes a red light-emitting layer
  • a green light-emitting element includes a green light-emitting layer
  • a blue light-emitting element includes a blue light-emitting layer.
  • the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer
  • the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer.
  • any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be produced by a single process (a single evaporation process or a single inkjet printing process), and isolation can be achieved by means of a surface step difference of the formed film layer or by surface treatment.
  • any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated.
  • the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.
  • FMM fine metal mask
  • Open Mask open mask
  • the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143.
  • the first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like.
  • the second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to prevent external moisture from entering the light-emitting element.
  • the second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display substrate and relieve stress in the first and third encapsulation layers 141 and 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this.
  • the encapsulation structure layer may have a five-layer stacked structure: inorganic/organic/inorganic/organic/inorganic/inorganic.
  • Figure 3B is another partial cross-sectional schematic diagram of the display region of a display substrate according to at least one embodiment of the present disclosure.
  • the multiple pixel transistors in the pixel circuit can be of the same transistor type, for example, all low-temperature polysilicon thin-film transistors.
  • Figure 3B illustrates an example of a first transistor 21 and a capacitor 23 included in each sub-pixel.
  • the circuit structure layer 12 in the display area may include: a bottom light-shielding metal layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, disposed on the substrate 10.
  • a first insulating layer 101 may be disposed between the bottom light-shielding metal layer and the first semiconductor layer
  • a second insulating layer 102 may be disposed between the first semiconductor layer and the first gate metal layer
  • a third insulating layer 103 may be disposed between the first gate metal layer and the second gate metal layer
  • a fourth insulating layer 104 may be disposed between the second gate metal layer and the first source-drain metal layer
  • a seventh insulating layer 107 and an eighth insulating layer 108 may be disposed between the first source-drain metal layer and the second source-drain metal layer
  • a ninth insulating layer 109 may be disposed on the side of the second source-drain metal layer away from the substrate 10.
  • the eighth insulating layer 108 and the ninth insulating layer 109 may be organic insulating layers, and the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 may be inorganic insulating layers.
  • the remaining structures of the display area of the display substrate of this example can be referred to the description of the embodiment shown in FIG3A , and therefore will not be described again here.
  • the pixel circuit may include: eight pixel transistors (ie, first to eighth pixel transistors) and a storage capacitor.
  • the second pixel transistor may be an oxide thin film transistor
  • the first pixel transistor
  • the third to eighth pixel transistors may be low-temperature polysilicon thin film transistors.
  • the gate of the third pixel transistor is electrically connected to the first node, the first electrode of the third pixel transistor is electrically connected to the second node, and the second electrode of the third pixel transistor is electrically connected to the third node.
  • the gate of the fourth pixel transistor is electrically connected to the first scan line, the first electrode of the fourth pixel transistor is electrically connected to the data line, and the second electrode of the fourth pixel transistor is electrically connected to the second node.
  • the gate of the second pixel transistor is electrically connected to the second scan line, the first electrode of the second pixel transistor is electrically connected to the third node, and the second electrode of the second pixel transistor is electrically connected to the first node.
  • the gate of the seventh pixel transistor is electrically connected to the second reset control line, the first electrode of the seventh pixel transistor is electrically connected to the second initial signal line, and the second electrode of the seventh pixel transistor is electrically connected to the fourth node.
  • the seventh pixel transistor can be configured to reset the fourth node.
  • the gate of the eighth pixel transistor is electrically connected to the second reset control line, the first electrode of the eighth pixel transistor is electrically connected to the third initial signal line, and the second electrode of the eighth pixel transistor is electrically connected to the second node.
  • the eighth pixel transistor can be configured to reset the second node.
  • the first electrode of the storage capacitor is electrically connected to the first node, and the second electrode of the storage capacitor is electrically connected to the first power line.
  • multiple gate lines can be located in the first gate metal layer and the second gate metal layer, and multiple data lines can be located in the first source/drain metal layer and the second source/drain metal layer.
  • the multiple gate lines can include: multiple first scan lines, multiple second scan lines, multiple light emission control lines, multiple first reset control lines, and multiple second reset control lines; wherein the multiple first scan lines and the multiple first reset control lines can be located in the first gate metal layer, and the multiple second scan lines, the multiple light emission control lines, and the multiple second reset control lines can be located in the second gate metal layer.
  • multiple gate connection lines located in the winding area can be alternately arranged in the first gate metal layer and the second gate metal layer.
  • the gate connection line connected to the first scan line can be located in the first gate metal layer
  • the gate connection line connected to the first reset control line can be located in the first gate metal layer
  • the gate connection line connected to the second scan line can be located in the second gate metal layer
  • the gate connection line connected to the light emitting control line can be located in the second gate metal layer
  • the gate connection line connected to the second reset control line can be located in the second gate metal layer.
  • Multiple data connection lines located in the winding area can be alternately arranged in the first source and drain metal layer and the second source and drain metal layer.
  • this embodiment is not limited to this.
  • the plurality of first routing lines located in the winding area may include: a first group of first routing lines that bypass the aperture area A2 from one side of the aperture area A2, and a second group of first routing lines that bypass the aperture area A2 from the other side of the aperture area A2.
  • the plurality of first routing lines located in the winding area may include: a plurality of gate connection routing lines 33.
  • the aperture area A2 may have a first centerline, which may pass through the center point of the aperture area A2 and extend along the first direction X.
  • the first group of first routing lines may include: a plurality of gate connection routing lines 33 located on one side of the first centerline in the second direction Y, for example, a plurality of gate connection routing lines 33 bypassing the upper side of the aperture area A2; the second group of first routing lines may include: a plurality of gate connection routing lines 33 located on the opposite side of the first centerline in the second direction Y, for example, a plurality of gate connection routing lines bypassing the lower side of the aperture area A2.
  • FIG4 is a schematic partial cross-sectional view along the Q-Q' direction in FIG2 .
  • the plurality of gate connection traces 33 located in the winding area B5 may include: a gate connection trace 33a located in the first gate metal layer and a gate connection trace 33b located in the second gate metal layer.
  • the plurality of gate connection traces 33a and the plurality of gate connection traces 33b may be arranged alternately, and the orthographic projections of adjacent gate connection traces 33a and 33b on the substrate 10 may not overlap.
  • the plurality of data connection traces 34 in the winding area B5 may include: a data connection trace 34a located in the first source/drain metal layer and a data connection trace 34b located in the second source/drain metal layer.
  • the orthographic projections of adjacent data connection traces 34a and 34b on the substrate 10 may not overlap.
  • the winding area B5 may be provided with a compensation plate 36.
  • the compensation plate 36 may be configured to receive a constant voltage signal, such as a first power signal provided by a first power line, or a second power signal provided by a second power line.
  • the compensation plate 36 may be located in the bottom light-shielding metal layer, and the orthographic projection of the compensation plate 36 on the substrate 10 may at least partially overlap with the orthographic projections of the plurality of gate connection traces 33a and 33b on the substrate 10.
  • the first straight connection segments 331 of the plurality of gate connection traces 33 may extend along the first direction X and be arranged sequentially along the second direction Y.
  • the plurality of first straight connection segments 331 may be located in the same conductive layer (e.g., the first gate metal layer or the second gate metal layer), or may be arranged alternately in the first gate metal layer and the second gate metal layer. This embodiment is not limited to this.
  • the hollow structure of the compensation plate may include multiple first hollow portions 41.
  • the multiple first hollow portions 41 may be arranged in an array along a first direction X and a second direction Y.
  • a row of first hollow portions may include multiple first hollow portions 41 arranged along the first direction X
  • a column of first hollow portions may include multiple first hollow portions 41 arranged along the second direction Y.
  • a row of first hollow portions may be aligned along the first direction X.
  • a column of first hollow portions may be aligned along the second direction Y.
  • the first hollow portion 41 may be an opening provided on the compensation plate.
  • the orthographic projection of the first hollow portion 41 on the substrate may be a rectangle.
  • the first hollow portion 41 may have first edges 411 and 412 disposed parallel to each other, and second edges 413 and 414 disposed parallel to each other.
  • the first edge 411, the second edge 413, the first edge 412, and the second edge 414 may be connected in sequence.
  • the extension direction of the first edge 411 may be perpendicular to the extension direction of the second edge 413.
  • the extension direction of the first edges 411 and 412 may be parallel to the extension direction of the plurality of first straight line connecting segments 331, and the extension direction of the second edges 413 and 414 may be perpendicular to the extension direction of the plurality of first straight line connecting segments 331.
  • the orthographic projection of the first edge 411 of the first hollow portion 41 onto the substrate may be located within the orthographic projection of one first linear connecting segment 331 onto the substrate, and the orthographic projection of the first edge 412 onto the substrate may be located within the orthographic projection of another first linear connecting segment 331 onto the substrate.
  • the orthographic projection of the first edge 411 onto the substrate may be located at the middle position of the orthographic projection of one first linear connecting segment 331 onto the substrate along the second direction Y.
  • the orthographic projection of the first edge 412 onto the substrate may be located at the middle position of the orthographic projection of another first linear connecting segment 331 onto the substrate along the second direction Y.
  • the orthographic projection of the first edge 411 onto the substrate may coincide with the midline of the orthographic projection of one first linear connecting segment 331 onto the substrate along the second direction Y.
  • the orthographic projection of the first edge 412 onto the substrate may coincide with the midline of the orthographic projection of another first linear connecting segment 331 onto the substrate along the second direction Y.
  • the first straight line connecting segment 331 where the orthographic projection of the first edge 411 on the substrate is located may not be adjacent to the first straight line connecting segment 331 where the orthographic projection of the first edge 412 on the substrate is located, and at least one first straight line connecting segment (for example, two first straight line connecting segments) may be set between the two first straight line connecting segments 331.
  • the orthographic projections of the second edges 413 and 414 of the first hollow portion 41 on the substrate may overlap with the orthographic projections of multiple first linear connecting segments 331 (e.g., four or three first linear connecting segments 331) on the substrate.
  • the second edges 413 and 414 may have the same length, and the length of the second edge 413 may be greater than the width of at least two first linear connecting segments 331.
  • the length of the first edge 411 may be the same as or different from the length of the second edge 413. This embodiment is not limited to this.
  • the orthographic projection of a first straight line connecting segment 331 on the substrate may cover the orthographic projection of the first edge 411 of multiple first hollow portions 41 in a row of first hollow portions on the substrate, or may cover the orthographic projection of the first edge 412 of multiple first hollow portions 41 in a row of first hollow portions on the substrate.
  • Figure 6A is a partially enlarged schematic diagram of region S1 in Figure 1.
  • Figure 6B is a schematic diagram of the first straight connecting segments of the plurality of gate connection traces in Figure 6A.
  • Figure 6C is a schematic diagram of the compensation plate in Figure 6A.
  • Figures 6A to 6C illustrate the partial overlap of the first straight connecting segments of the gate connection traces and the compensation plate.
  • the first straight connection segment 331a of the gate connection trace 33a located in the first gate metal layer can extend along the first direction X
  • the first straight connection segment 331b of the gate connection trace 33b located in the second gate metal layer can extend along the first direction X
  • the first straight connection segments 331a of the plurality of gate connection traces 33a and the first straight connection segments 331b of the plurality of gate connection traces 33b can be alternately arranged along the second direction Y.
  • the orthographic projections of the first straight connection segments 331a and 331b on the substrate can have no overlap.
  • the line widths of the first straight connection segments 331a and 331b can be the same.
  • the orthographic projection of the first edge 411 (or 412) of the first hollow portion 41 on the substrate can be located within the orthographic projection range of a first straight line segment 331a (or 331b) on the substrate.
  • the orthographic projection of the second edge 413 (or 414) of the first hollow portion 41 on the substrate can overlap with the orthographic projections of multiple first straight line segments (for example, four or three first straight line segments) on the substrate.
  • the length of the second edge 413 (or 414) can be greater than the line width of at least two first straight line segments.
  • FIG7 is another schematic diagram of the positions of the first straight connecting section of the gate connection line and the multiple first hollow portions of the compensation plate of at least one embodiment of the present disclosure.
  • the compensation plate may have multiple first hollow portions 41.
  • the multiple first hollow portions 41 may be arranged in an array along the first direction X and the second direction Y.
  • the multiple first hollow portions 41 may be aligned in the second direction Y; along the first direction X, at least two adjacent first hollow portions 41 may be staggered.
  • the adjacent multiple first hollow portions 41 (such as six first hollow portions) in a row of first hollow portions may be arranged in a stepped manner.
  • each first hollow portion 41 may have a center line passing through a center point and extending along the first direction X, and the center lines of the adjacent six first hollow portions 41 in a row of first hollow portions may be arranged in sequence along the second direction Y, and the minimum distance between the center lines of any two adjacent first hollow portions 41 may be the same.
  • This embodiment is not limited to this.
  • the orthographic projection of the first hollow portion 41 on the substrate can be rectangular.
  • the first edges 411 and 412 of the first hollow portion 41 extend parallel to the first direction X, and the orthographic projections of the first edges 411 and 412 on the substrate can be located within the orthographic projections of two different first straight line connecting segments 331 on the substrate.
  • the second edges 413 and 414 of the first hollow portion 41 extend parallel to the second direction Y, and the orthographic projections of the second edges 413 and 414 on the substrate overlap with the orthographic projections of multiple (e.g., four) first straight line connecting segments 331 on the substrate.
  • the loads of the plurality of first straight line connection segments can be made the same after compensation by the compensation plate, thereby achieving differentiated load compensation for the plurality of gate connection lines.
  • FIG8 is another schematic diagram of the positions of the first straight connecting section of the gate connection trace and the multiple first hollow portions of the compensation plate according to at least one embodiment of the present disclosure.
  • the multiple first hollow portions 41 of the compensation plate can be arranged along the first direction X and the second direction Y.
  • the multiple first hollow portions 41 can be aligned along the second direction Y.
  • the multiple first hollow portions X can be staggered in the first direction X.
  • a row of first hollow portions can include: a first group of hollow portions 41a and a second group of hollow portions 41b arranged alternately along the first direction X.
  • the number of first hollow portions 41 included in the first group of hollow portions 41a and the second group of hollow portions 41b can be the same.
  • the number of first hollow portions included in the first group of hollow portions 41a and the second group of hollow portions 41b can be different.
  • the number of first hollow portions included in the first group of hollow portions 41a can be greater than the number of first hollow portions included in the second group of hollow portions 41b.
  • the first group of hollow portions 41 a may include multiple first hollow portions 41 (e.g., three first hollow portions) aligned along the first direction X; the second group of hollow portions 41 b may include multiple first hollow portions 41 (e.g., three first hollow portions) aligned along the first direction X. Center lines of the multiple first hollow portions 41 in the first group of hollow portions 41 a parallel to the first direction X may coincide, and center lines of the multiple first hollow portions 41 in the second group of hollow portions 41 b parallel to the first direction X may coincide.
  • the first group of hollow portions 41a and the second group of hollow portions 41b may be staggered in the first direction X.
  • the center line of the first group of hollow portions 41a parallel to the first direction X may be located on one side of the center line of the second group of hollow portions 41b parallel to the first direction X in the second direction Y.
  • the overlapping area of the orthographic projection of the first straight connection segment 331 of the multiple gate connection lines 33 on the substrate and the orthographic projection of the compensation plate on the substrate can be different.
  • the overlapping area of the first straight connection segment (for example, the first straight connection segment 331-1) that overlaps with the orthographic projection of both the first group of hollow portions 41a and the second group of hollow portions 41b on the substrate and the compensation plate can be smaller than the overlapping area of the first straight connection segment (for example, the first straight connection segment 331-2 or 331-3) that overlaps only with the orthographic projection of the first group of hollow portions 41a or the second group of hollow portions 41b on the substrate and the compensation plate.
  • the compensation capacitance of the compensation plate for the first straight connection segment 331-1 can be smaller than the compensation capacitance for the first straight connection segment 331-2 or 331-3. In this way, the compensation plate can focus on signal compensation for the first straight connection segments 331-2 and 331-3, achieving differentiated compensation for different gate connection lines.
  • the orthographic projection relationship between the edge of a single first hollow portion and the first straight line connecting segment can be referred to the description of the aforementioned embodiment, so it will not be repeated here.
  • Figure 9 is another schematic diagram of the positions of the first straight connecting segment of the gate connection trace and the multiple first hollow portions of the compensation plate according to at least one embodiment of the present disclosure.
  • the multiple first hollow portions 41 of the compensation plate can be arranged along the first direction X and the second direction Y.
  • the multiple first hollow portions 41 can be aligned along the second direction Y.
  • the multiple first hollow portions 41 can be staggered in the first direction X.
  • a row of first hollow portions can include: a third group of hollow portions 41c and a fourth group of hollow portions 41d, arranged alternately along the first direction X.
  • the third group of hollow portions 41c and the fourth group of hollow portions 41d can include the same number of first hollow portions 41.
  • this embodiment is not limited to this.
  • the third group of hollow portions 41c and the fourth group of hollow portions 41d can include different numbers of first hollow portions.
  • the number of first hollow portions included in the third group of hollow portions 41c can be greater than the number of first hollow portions included in the fourth group of hollow portions 41d.
  • the third group of hollow portions 41 c may include multiple first hollow portions 41 (e.g., three first hollow portions) staggered along the first direction X
  • the fourth group of hollow portions 41 d may include multiple first hollow portions 41 (e.g., three first hollow portions) staggered along the first direction X.
  • the centerlines of the multiple first hollow portions 41 in the third group of hollow portions 41 c parallel to the first direction X may be arranged sequentially in a direction opposite to the second direction Y, and the minimum distance between the centerlines of any two adjacent first hollow portions 41 in the third group of hollow portions 41 c parallel to the first direction X may be the same.
  • the centerlines of the multiple first hollow portions 41 in the fourth group of hollow portions 41 d parallel to the first direction X may be arranged sequentially along the second direction Y.
  • the minimum distance between the centerlines of any two adjacent first hollow portions 41 in the fourth group of hollow portions 41 d parallel to the first direction X may be the same.
  • At least one first hollow portion in the third group of hollow portions 41 c and at least one first hollow portion in the fourth group of hollow portions 41 d may be aligned in the first direction X.
  • adjacent hollow portions in the third group 41 c and the fourth group 41 d may be symmetrically arranged about a midline thereof parallel to the second direction Y.
  • this embodiment is not limited thereto.
  • the overlapping areas of the orthographic projections of the first straight connecting segments 331 of the plurality of gate connecting traces 33 on the substrate and the orthographic projections of the compensation plate on the substrate can be different.
  • the overlapping area of the first straight connecting segment (e.g., first straight connecting segment 331-5 or 331-6) that overlaps with the orthographic projections of all first hollow portions of the third group of hollow portions 41c and the fourth group of hollow portions 41d on the substrate and the compensation plate can be greater than the overlapping area of the first straight connecting segment (e.g., first straight connecting segment 331-4) that overlaps with only the orthographic projections of some first hollow portions of the first group of hollow portions 41a and the second group of hollow portions 41b on the substrate and the compensation plate.
  • the compensation capacitance of the compensation plate for the first straight connecting segment 331-4 can be greater than the compensation capacitance for the first straight connecting segments 331-5 or 331-6. In this way, the compensation plate can focus on signal compensation for the first straight connecting segment 331-4, achieving differentiated compensation for different gate connecting traces.
  • the orthographic projection relationship between the edge of a single first hollow portion and the first straight line connecting segment can be referred to the description of the aforementioned embodiment, so it will not be repeated here.
  • FIG10A is another partially enlarged schematic diagram of the region S1 in FIG1.
  • FIG10B is a schematic diagram of the plurality of gate connection paths in FIG10A.
  • FIG10A to FIG10C are schematic diagrams showing the partial overlap of the first straight connecting section of the gate connection line and the compensation plate.
  • FIG10C is a schematic diagram showing the first straight connecting section of the gate connection line and the compensation plate.
  • FIG10A to FIG10C are schematic diagrams showing the partial overlap of the first straight connecting section of the gate connection line and the compensation plate.
  • the compensation plate 36 can be located in the bottom light-shielding metal layer.
  • the compensation plate 36 can have a plurality of first hollow portions 41 arranged in an array along the first direction X and the second direction Y.
  • the plurality of first hollow portions 41 can include a fifth group of hollow portions 41e arranged in an array along the first direction X and the second direction Y.
  • the plurality of first hollow portions 41 can be aligned in the second direction Y and staggered in the first direction X.
  • the fifth group of hollow portions 41e may include: six first hollow portions 41 staggered along the first direction X.
  • the center lines of the six first hollow portions 41 in the fifth group of hollow portions 41e parallel to the first direction X may be arranged sequentially along the second direction Y, and the minimum distance between the center lines of any two adjacent first hollow portions 41 parallel to the first direction X may be the same.
  • Adjacent hollow portions 41e in the fifth group of hollow portions arranged along the first direction X may be aligned in the first direction X.
  • the first first hollow portion in the fifth group of hollow portions 41e and the first first hollow portion in the adjacent fifth hollow portion 41e in the first direction X may be aligned in the first direction X.
  • the remaining positional relationships between the first hollow portions and the first straight connecting segments in this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.
  • the overlapping area of the orthographic projection of the plurality of first straight line connection segments and the compensation plate on the substrate can be adjusted, thereby achieving differentiated compensation for the plurality of gate connection lines.
  • Figure 11A is a partially enlarged schematic diagram of region S2 in Figure 1 .
  • Figure 11B is a schematic diagram of multiple arcuate connecting segments in Figure 11A .
  • Figure 11C is a schematic diagram of the compensation plate in Figure 11A .
  • the multiple arcuate connecting segments of the first routing lines may include: multiple arcuate connecting segments 333 of the gate connecting routing lines 33 .
  • the curved connecting segments 333 of the multiple gate connection traces 33 can extend along the curved edge of the hole area B5.
  • the multiple curved connecting segments 333 can be located in the same conductive layer (e.g., the first gate metal layer or the second gate metal layer), or can be arranged alternately in the first gate metal layer and the second gate metal layer.
  • the curved connecting segment 333a of the gate connection trace 33a located in the first gate metal layer can extend along the edge of the hole area B5
  • the curved connecting segment 333b of the gate connection trace 33b located in the second gate metal layer can extend along the edge of the hole area B5.
  • the curved connecting segments 333a of the multiple gate connection traces 33a and the curved connecting segments 333b of the multiple gate connection traces 33b can be arranged alternately in a direction away from the hole area B5.
  • the orthographic projections of the curved connecting segments 333a and 333b on the substrate can not overlap.
  • the line widths of the curved connecting segments 333a and 333b can be the same.
  • the arc-shaped connecting segment 333a or 333b may be an arc segment with the center of the hole area B5 as the center of the circle.
  • the compensating plate 36 may include a plurality of second hollow portions 42, which may be arranged along the extension direction of the arcuate connecting segments 333a and 33b.
  • the plurality of second hollow portions 42 may be arranged in a row along the extension direction of the arcuate connecting segments 333a and 333b, and the plurality of rows of second hollow portions may be arranged in a direction away from the aperture area B5.
  • the spacing between adjacent second hollow portions 42 in a row of second hollow portions near the aperture area B5 may be smaller than the spacing between adjacent second hollow portions 42 in a row of second hollow portions away from the aperture area B5.
  • the plurality of second hollow portions 42 may be arranged radially from the center of the aperture area A2.
  • the orthographic projection of the second hollow portion 42 onto the substrate can be rectangular.
  • the second hollow portion 42 can have parallel third edges 421 and 422, and parallel fourth edges 423 and 424.
  • the third edges 421 and 422 can extend parallel to the directions of the arcuate connecting segments 333a and 333b, while the fourth edges 423 and 424 can extend perpendicular to the directions of the arcuate connecting segments 333a and 333b.
  • the orthographic projection of the third edge 421 (or 422) onto the substrate can be within the orthographic projection of one arcuate connecting segment 333a (or 333b) onto the substrate.
  • the orthographic projection of the fourth edge 423 (or 424) onto the substrate can overlap with the orthographic projections of multiple arcuate connecting segments (e.g., three or four arcuate connecting segments) onto the substrate.
  • the length of the fourth edge 423 (or 424) can be greater than the line width of at least two of the arcuate connecting segments.
  • the arrangement direction of the plurality of second hollow portions 42 can change with the arc angle of the arc-shaped connecting segment to ensure It is proved that the orthographic projection of the third edge of the second hollow portion 42 on the substrate can be located within the orthographic projection range of the arc-shaped connecting segment on the substrate.
  • This example provides multiple second hollow portions arranged along the extension direction of the arc-shaped connecting segments, and the orthographic projections of the multiple arc-shaped connecting segments on the substrate can cover the orthographic projections of the third edges of the multiple second hollow portions on the substrate.
  • This can improve the impact of the boundary position of the compensation plate (e.g., the edge position of the second hollow portion) on the upper inorganic film layer and conductive layer, and can prevent material residue and poor routing in the upper conductive layer (e.g., the first source and drain metal layer).
  • the remaining description of the compensation plate of this example can be referred to the description of the previous embodiment, and will not be repeated here.
  • Figure 12 is a schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure.
  • the dashed line within winding area B5 in Figure 12 divides winding area B5 into a first region near aperture area A2 and a second region farther from aperture area A2.
  • the first region houses the curved connecting segments of gate connection traces 33 within winding area B5, while the second region houses the first and second straight connecting segments of gate connection traces 33.
  • the hole area A2 may have a first center line O1 extending along a first direction X and a second center line O2 extending along a second direction Y.
  • the first center line O1 and the second center line O2 may divide the winding area B5 into four regions (e.g., an upper left region, an upper right region, a lower left region, and a lower right region).
  • the plurality of gate connection traces may include: a first group of gate connection traces located on one side of the first center line O1 in the second direction Y, and a second group of gate connection traces located on the opposite side of the first center line O1 in the second direction Y.
  • first group of gate connection traces and the second group of gate connection traces may be symmetrically arranged about the first center line O1.
  • first group of first traces that bypass the hole area A2 from one side may include a first group of gate connection traces
  • the second group of first traces that bypass the hole area A2 from the other side may include a second group of gate connection traces.
  • the compensation plate 36 located in the winding area B5 may have a third hollow portion 43a located in the upper left region and a third hollow portion 43b located in the lower right region.
  • the orthographic projection of the third hollow portion 43a on the substrate may overlap with the orthographic projection of the first group of gate connection traces on the substrate, and the orthographic projection of the third hollow portion 43b on the substrate may overlap with the orthographic projection of the second group of gate connection traces on the substrate.
  • the third hollow portions 43a and 43b overlap with the orthographic projections of the multiple gate connection traces disposed near the aperture area A2 on the substrate, but may not overlap with the orthographic projections of the multiple gate connection traces disposed away from the area B5 on the substrate.
  • the lengths of the multiple gate connection traces disposed near the aperture area A2 may be greater than the lengths of the multiple gate connection traces disposed away from the aperture area A2.
  • the capacitance compensation for the longer gate connection traces can be reduced, while the capacitance compensation for the shorter gate connection traces can be increased, so that the loads of the multiple gate connection traces remain the same after compensation.
  • the third hollow portions 43a and 43b can both be arcuate hollow grooves extending along the edge of the aperture area A2.
  • the structure of the third hollow portion 43a is used as an example for illustration.
  • the third hollow portion 43a can have a fifth edge 431, a sixth edge 432, a seventh edge 433, and an eighth edge 434.
  • the fifth edge 431, the seventh edge 433, the sixth edge 432, and the eighth edge 433 can be connected in sequence.
  • the fifth edge 431 and the sixth edge 432 can extend in the same direction, for example, along the direction in which the multiple arcuate connecting segments extend.
  • the orthographic projections of the fifth edge 431 and the sixth edge 432 on the substrate can at least partially overlap with the orthographic projections of the multiple arcuate connecting segments on the substrate.
  • the orthographic projection of one arcuate connecting segment on the substrate can overlap the orthographic projection of the fifth edge 431 (or the sixth edge 432) on the substrate.
  • the seventh edge 433 and the eighth edge 434 can extend in a direction perpendicular to the direction in which the arcuate connecting segments extend.
  • the extension line of the seventh edge 433 or the eighth edge 434 may pass through the intersection of the first center line O1 and the second center line O2.
  • this embodiment is not limited thereto.
  • FIG13A is a partial schematic diagram of the edge of the third hollow portion of at least one embodiment of the present disclosure.
  • the orthographic projection of at least part of the edge of the third hollow portion on the substrate may be in the shape of a step.
  • the orthographic projection of the seventh edge 433 and the eighth edge 434 of the third hollow portion 43a on the substrate may be in the shape of a step.
  • the step shape may include: a plurality of step structures 430 connected in sequence.
  • Each step structure 430 may include a first stage 430-1 and a second stage 430-2 connected to each other.
  • the first stage 430-1 and the second stage 430-2 are straight line segments with different extension directions.
  • the first stage 430-1 and the second stage 430-2 are straight line segments with different extension directions.
  • An extending direction of the first stage 430 - 1 may be perpendicular to an extending direction of the second stage 430 - 2 .
  • the extension direction of the first terrace stage 430-1 can be parallel to the extension direction of a local segment (e.g., a straight segment or an arcuate segment) of a gate connection trace.
  • the orthographic projection of the first terrace stage 430-1 on the substrate can be located within the orthographic projection of a gate connection trace 33 (e.g., the arcuate segment 333 of the gate connection trace 33) on the substrate.
  • the orthographic projection of the second terrace stage 430-2 on the substrate can overlap with the orthographic projections of at least two adjacent gate connection traces 33 on the substrate.
  • the orthographic projections of the first terrace stage 430-1 of adjacent stepped structures on the substrate can be located within the orthographic projections of two different gate connection traces on the substrate.
  • the edge configuration of the third hollow portion in this example not only facilitates differentiated compensation of the compensation plate for different gate connection traces, but also reduces the impact of the compensation plate's boundary position (e.g., the edge position of the third hollow portion) on the underlying inorganic film layer and conductive layer (e.g., the first source/drain metal layer), thereby preventing material residue in the conductive layer and poor routing.
  • Figure 13B is another partial schematic diagram of the edge of the third hollow portion of at least one embodiment of the present disclosure.
  • at least a portion of the edge of the third hollow portion can have a stepped shape when projected onto the substrate.
  • the seventh edge 433 and the eighth edge 434 of the third hollow portion 43a can have a stepped shape when projected onto the substrate.
  • This stepped shape can include: a plurality of step structures 430 connected in sequence. Adjacent step structures 430 can be connected by step connecting segments 430-3. Step connecting segments 430-3 can be arc segments.
  • Each step structure 430 can include a first step 430-1 and a second step 430-2 connected to each other. The first step 430-1 and the second step 430-2 are straight line segments extending in different directions.
  • the direction of extension of the first step 430-1 can be perpendicular to the direction of extension of the second step 430-2.
  • at least a portion of the edge of the third hollow portion can have a circular arc gradient boundary.
  • the edge arrangement of the third hollow portion in this example not only facilitates the differential compensation of the compensation plate for different gate connection traces, but also reduces the impact of the compensation plate's boundary position (e.g., the edge position of the third hollow portion) on the overlying inorganic film layer and conductive layer (e.g., the first source/drain metal layer), thereby preventing material residue in the conductive layer and poor trace alignment.
  • the edges of this example please refer to the description of the aforementioned embodiment, and will not be repeated here.
  • Figure 14 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure.
  • the compensation plate 36 in winding area B5 can have third hollow portions 43a and 43c located in the upper left region, and third hollow portions 43b and 43d located in the lower right region.
  • the orthographic projections of the third hollow portions 43a and 43c on the substrate overlap with the orthographic projections of the first group of gate connection traces on the substrate, while the orthographic projections of the third hollow portions 43b and 43d on the substrate overlap with the orthographic projections of the second group of gate connection traces on the substrate.
  • the edge arrangement of the third hollow portion in this example not only facilitates differentiated compensation of the compensation plate for different gate connection traces, but also mitigates the impact of the compensation plate's boundary (e.g., the edge of the third hollow portion) on the underlying inorganic film layer and conductive layer (e.g., the first source/drain metal layer), thereby preventing residual conductive layer material and poor traceability.
  • the remaining structure of the third hollow portion in this example can be found in the description of the preceding embodiment, and will not be further elaborated here.
  • FIG15 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure.
  • the compensation plate 36 in winding area B5 may have third hollow portions 43a and 43c located in the upper left region, and third hollow portions 43e and 43f located in the lower left region.
  • the orthographic projections of the third hollow portions 43a and 43c on the substrate overlap with the orthographic projections of the first group of gate connection traces on the substrate, while the orthographic projections of the third hollow portions 43e and 43f on the substrate overlap with the orthographic projections of the second group of gate connection traces on the substrate.
  • the third hollow portions 43a, 43c, 43e, and 43f may all be arc-shaped hollow grooves extending along the edge of the hole area A2.
  • the third hollow portion 43c may be located on a side of the third hollow portion 43a away from the hole area A2.
  • the third hollow portion 43f can be located on a side of the third hollow portion 43e away from the hole area A2.
  • the length of the third hollow portion 43c can be less than that of the third hollow portion 43a, and the length of the third hollow portion 43f can be less than that of the third hollow portion 43e.
  • the third hollow portions 43a and 43e can be substantially symmetrical about the first centerline O1
  • the third hollow portions 43c and 43f can be substantially symmetrical about the first centerline O1.
  • this embodiment is not limited to this.
  • FIG16 is another schematic diagram of a compensation plate in a winding area according to at least one embodiment of the present disclosure.
  • the compensation plate 36 in winding area B5 may include third hollow portions 43a and 43c in the upper left region, third hollow portions 43e and 43f in the lower left region, third hollow portions 43g and 43h in the upper right region, and third hollow portions 43b and 43d in the lower right region.
  • the third hollow portions 43a, 43b, 43c, 43d, 43e, 43f, 43g, and 43h can all be arc-shaped hollow grooves extending along the edge of the aperture area A2.
  • the third hollow portion 43c can be located on the side of the third hollow portion 43a away from the aperture area A2
  • the third hollow portion 43f can be located on the side of the third hollow portion 43e away from the aperture area A2
  • the third hollow portion 43d can be located on the side of the third hollow portion 43b away from the aperture area A2
  • the third hollow portion 43h can be located on the side of the third hollow portion 43g away from the aperture area B5.
  • the third hollow portions 43a and 43e can be approximately symmetrical about the first centerline O1
  • the third hollow portions 43g and 43a can be approximately symmetrical about the second centerline O2.
  • this embodiment is not limited to this.
  • the edge arrangement of the third hollow portion in this example not only facilitates differentiated compensation of the compensation plate for different gate connection traces, but also mitigates the impact of the compensation plate's boundary (e.g., the edge of the third hollow portion) on the underlying inorganic film layer and conductive layer (e.g., the first source/drain metal layer), thereby preventing residual conductive layer material and poor traceability.
  • the remaining structure of the third hollow portion in this example can be found in the description of the preceding embodiment, and will not be further elaborated here.
  • the third hollow portions 43a, 43g, 43b, and 43e may be connected to form an annular hollow groove to reduce the load compensation for multiple gate connection lines near the hole area A2.
  • the third hollow portions 43c, 43h, 43d, and 43f may be connected to form an annular hollow groove to reduce the load compensation for multiple gate connection lines near the hole area A2.
  • the edge shape of the compensation plate near the hole area can adopt a stepped boundary as shown in FIG13A, or an arc gradient boundary as shown in FIG13B.
  • Differential compensation can be achieved for different gate connection lines by setting the edge of the compensation plate, and the influence of the boundary position of the compensation plate (such as the edge position of the third hollow portion) on the upper inorganic film layer and the conductive layer (such as the first source and drain metal layer) can be improved, which can prevent the conductive layer material residue and the line from being out of alignment.
  • the rest of the structure of the compensation plate of this example can be referred to the description of the above embodiment, so it will not be described again here.
  • FIG18 is another schematic diagram of the gate connection routing of the winding area of at least one embodiment of the present disclosure.
  • the gate connection routing 33 of the winding area B5 may include: a first straight connection segment 331, a second straight connection segment 332, and a folded line connection segment 334.
  • the folded line connection segment 334 may be connected between the first straight line connection segment 331 and the second straight line connection segment 332.
  • the folded line connection segment 334 may include a plurality of sub-straight line segments extending in different extension directions.
  • FIG19 is a schematic diagram illustrating the positions of the zigzag connecting segments of the gate connection traces and the first hollow portion of the compensation plate in at least one embodiment of the present disclosure.
  • the multiple straight line segments of the multiple first traces of this example may include: multiple first straight line connecting segments 331 extending in the same direction, multiple second straight line connecting segments 332 extending in the same direction, and multiple sub-straight line segments extending in the same direction of the multiple zigzag connecting segments 334.
  • the hollow structure of the compensation plate may include multiple first hollow portions 41.
  • the multiple first hollow portions 41 may be arranged in an array along the extension direction of the multiple sub-straight line segments of the multiple zigzag connecting segments 334.
  • the orthographic projections of the edges of the first hollow portion 41 that extend in the same direction as the sub-straight segments of the fold-line connecting segment 334 (e.g., first edges 411 and 412) on the substrate can be located within the orthographic projections of the corresponding sub-straight segments on the substrate.
  • the orthographic projections of the edges of the first hollow portion 41 that extend perpendicular to the sub-straight segments (e.g., second edges 413 and 414) on the substrate can overlap with the orthographic projections of multiple sub-straight segments on the substrate.
  • FIG20 is another schematic diagram of the positions of the zigzag connection segment of the gate connection trace and the first hollow portion of the compensation plate of at least one embodiment of the present disclosure.
  • the hollow structure of the compensation plate may include a plurality of first hollow portions 41.
  • the plurality of first hollow portions 41 may be arranged divergently along the direction of the radial line passing through the center point of the hole area.
  • the center lines of the plurality of first hollow portions 41 arranged in a direction away from the hole area A2 may overlap and be perpendicular to the extension direction of the sub-straight line segments of the plurality of zigzag connection segments 334.
  • the remaining description of the compensation plate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • the hollow structure of the compensation plate may include multiple first hollow portions, and the orthographic projections of the straight routing segments on the substrate may cover portions of the edges of the first hollow portions. If the first routing line located in the winding area has both straight routing segments and curved routing segments, the hollow structure of the compensation plate may include multiple first hollow portions and multiple second hollow portions, or may include multiple first hollow portions and at least one third hollow portion.
  • the orthographic projections of the straight routing segments on the substrate may cover portions of the edges of the first hollow portion, and the orthographic projections of the curved routing segments on the substrate may cover portions of the edges of the second or third hollow portions. This embodiment is not limited to this.
  • the film layer structure of the display substrate may be as shown in FIG3A , where the compensation plate may be located in the third gate metal layer.
  • the compensation plate located in the third gate metal layer is arranged to overlap with the orthographic projections of gate connection traces located in the first gate metal layer and the second gate metal layer on the substrate, thereby providing load compensation for first-category gate lines connected to different gate connection traces.
  • the compensation plate located in the third gate metal layer may be arranged to overlap with the orthographic projections of data connection traces located in the first source/drain metal layer and the second source/drain metal layer on the substrate, thereby providing load compensation for first-category data lines connected to different data connection traces.
  • the peripheral area may also include: a first corner area (for example, also called a lower left corner area) connected between the first peripheral area and the second peripheral area, a first peripheral area connected between the first peripheral area and the third peripheral area, and a second peripheral area connected between the first peripheral area and the third peripheral area.
  • the orthographic projections of the traces located in the bottom light-shielding metal layer in the first corner region and the second corner region on the substrate may not overlap with the orthographic projections of the traces located in the first gate metal layer and the second gate metal layer in the same region on the substrate.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板，包括：衬底(10)、多个子像素(PX)、多条第一走线以及补偿极板(36)。衬底(10)包括显示区域(A1)和位于显示区域(A1)至少一侧的周边区域。多个子像素(PX)设置在衬底(10)的一侧且位于显示区域(A1)。多条第一走线位于周边区域，并与多个子像素(PX)电连接。补偿极板(36)位于周边区域，补偿极板(36)与多条第一走线之间设置有至少一个绝缘层。补偿极板(36)在衬底(10)的正投影与多条第一走线在衬底(10)的正投影部分交叠。补偿极板(36)具有镂空结构，镂空结构在衬底(10)的正投影与至少一条第一走线在衬底(10)的正投影部分交叠。

Description

显示基板及显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及显示装置。
一方面，本实施例提供一种显示基板，包括：衬底、多个子像素、多条第一走线以及补偿极板。衬底包括显示区域和位于显示区域至少一侧的周边区域。多个子像素设置在衬底的一侧且位于显示区域。多条第一走线位于周边区域，并与所述多个子像素电连接。补偿极板位于周边区域，补偿极板与多条第一走线之间设置有至少一个绝缘层。补偿极板在衬底的正投影与多条第一走线在衬底的正投影部分交叠。补偿极板具有镂空结构，镂空结构在衬底的正投影与多条第一走线中的至少一条第一走线在衬底的正投影部分交叠。
在一些示例性实施方式中，所述衬底还包括：孔区，所述周边区域包括位于所述孔区和所述显示区域之间的绕线区；所述多条第一走线和所述补偿极板均位于所述绕线区。
在一些示例性实施方式中，所述镂空结构具有至少一条第一镂空边缘，所述至少一条第一镂空边缘的延伸方向平行于所述多条第一走线中的至少一条第一走线的延伸方向，所述至少一条第一镂空边缘在所述衬底的正投影位于所述至少一条第一走线在所述衬底的正投影范围内。
在一些示例性实施方式中，所述补偿极板位于所述多条第一走线靠近所述衬底的一侧。
在一些示例性实施方式中，所述多条第一走线交替设置在第一栅金属层和第二栅金属层，所述第二栅金属层位于所述第一栅金属层远离所述衬底的一侧，所述多条第一走线中的相邻第一走线在所述衬底的正投影没有交叠；所述补偿极板位于底部遮光金属层，所述底部遮光金属层位于所述第一栅金属层靠近所述衬底的一侧。
在一些示例性实施方式中，所述多条第一走线包括：沿同一方向延伸的多条直线走线段；所述补偿极板的镂空结构包括：多个第一镂空部；所述多个第一镂空部中的至少一个第一镂空部具有第一边缘，所述第一边缘的延伸方向平行于所述多条直线走线段的延伸方向；单个第一镂空部的一条第一边缘在所述衬底的正投影位于一条直线走线段在所述衬底的正投影范围内。
在一些示例性实施方式中，所述至少一个第一镂空部在所述衬底的正投影为矩形，所述至少一个第一镂空部还具有第二边缘，所述第二边缘的延伸方向垂直于所述第一边缘的延伸方向，所述第二边缘在所述衬底的正投影与所述多条直线走线段中的至少两条直线走线段在所述衬底的正投影部分交叠。
在一些示例性实施方式中，所述多个第一镂空部沿着所述多条直线走线段的延伸方向阵列排布，且在所述多条直线走线段的延伸方向上，相邻第一镂空部对齐设置。
在一些示例性实施方式中，所述多个第一镂空部沿着所述多条直线走线段的延伸方向阵列排布，且在所述多条直线走线段的延伸方向上，至少两个相邻第一镂空部错位设置。
在一些示例性实施方式中，沿着所述多条直线走线段的延伸方向排布的多个第一镂空部为一行第一镂空部，所述一行第一镂空部包括：交替设置的第一组镂空部和第二组镂空部，所述第一组镂空部内的多个第一镂空部对齐设置，所述第二组镂空部内的多个第一镂空部对齐设置，所述第一组镂空部和所述第二组镂空部错位设置。
在一些示例性实施方式中，沿着所述多条直线走线段的延伸方向排布的多个第一镂空部为一行第一镂空部，所述一行第一镂空部包括：交替设置的第三组镂空部和第四组镂空部，所述第三组镂空部内的多个第一镂空部错位设置，所述第四组镂空部内的多个第一镂空部错位设置；所述第三组镂空部内的至少一个第一镂空部与所述第四组镂空部内的至少一个第一镂空部对齐设置。
在一些示例性实施方式中，沿着所述多条直线走线段的延伸方向排布的多个第一镂空部为一行第一镂空部，所述一行第一镂空部包括：依次设置的多个第五组镂空部，所述第五组镂空部内的多个第一镂空部错位设置，相邻第五组镂空部对齐设置。
在一些示例性实施方式中，所述多条第一走线包括：延伸方向相同的多条弧线走线段；所述补偿极板的镂空结构包括：多个第二镂空部；所述多个第二镂空部沿着所述多条弧线走线段的延伸方向排布；所述多个第二镂空部中的至少一个第二镂空部具有第三边缘，所述第三边缘的延伸方向平行于所述多条弧线走线段的延伸方向，单个第二镂空部的所述第三边缘在所述衬底的正投影位于一条弧线走线段在所述衬底的正投影范围内。
在一些示例性实施方式中，所述补偿极板的镂空结构包括：至少一个第三镂空部；所述至少一个第三镂空部沿着所述孔区的至少部分边缘延伸；与所述至少一个第三镂空部在所述衬底的正投影存在交叠的第一走线的长度，大于没有与所述至少一个第三镂空部在所述衬底的正投影存在交叠的第一走线的长度。
在一些示例性实施方式中，所述多条第一走线包括：从所述孔区的一侧绕过所述孔区的第一组第一走线、以及从所述孔区的另一侧绕过所述孔区的第二组第一走线；所述补偿极板的镂空结构包括：与所述第一组第一走线在所述衬底的正投影存在交叠的至少一个第三镂空部、以及与所述第二组第一走线在所述衬底的正投影存在交叠的至少一个第三镂空部。
在一些示例性实施方式中，所述至少一个第三镂空部的至少部分边缘在所述衬底的正投影为台阶形状；所述台阶形状包括：依次连接的多个台阶结构，每个台阶结构包括相互连接的第一台阶段和第二台阶段；所述第一台阶段和所述第二台阶段为延伸方向不同的直线段；每个台阶结构的所述第一台阶段在所述衬底的正投影位于一条第一走线在所述衬底的正投影范围内，所述第二台阶段在所述衬底的正投影与至少两条相邻第一走线在所述衬底的正投影存在交叠。
在一些示例性实施方式中，所述台阶形状还包括：连接相邻台阶结构的台阶连接段，所述台阶连接段为弧线段。
另一方面，本实施例提供一种显示装置，包括如上所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。
图1为本公开至少一实施例的显示基板的示意图；
图2为图1中的栅线的示意图；
图3A为本公开至少一实施例的显示基板的显示区域的局部剖面示意图；
图3B为本公开至少一实施例的显示基板的显示区域的另一局部剖面示意图；
图4为图2中沿Q-Q’方向的局部剖面示意图；
图5为本公开至少一实施例的栅连接走线的第一直线连接段与补偿极板的多个第一镂空部的位置示意图；
图6A为图1中区域S1的局部放大示意图；
图6B为图6A中多条栅连接走线的第一直线连接段的示意图；
图6C为图6A中补偿极板的示意图；
图7为本公开至少一实施例的栅连接走线的第一直线连接段与补偿极板的多个第一镂空部的另一位置示意图；
图8为本公开至少一实施例的栅连接走线的第一直线连接段与补偿极板的多个第一镂空部的另一位置示意图；
图9为本公开至少一实施例的栅连接走线的第一直线连接段与补偿极板的多个第一镂空部的另一位置示意图；
图10A为图1中区域S1的另一局部放大示意图；
图10B为图10A中多条栅连接走线的第一直线连接段的示意图；
图10C为图10A中补偿极板的示意图；
图11A为图1中区域S2的局部放大示意图；
图11B为图11A中多条弧形连接段的示意图；
图11C为图11A中补偿极板的示意图；
图12为本公开至少一实施例的绕线区的补偿极板示意图；
图13A为本公开至少一实施例的第三镂空部的边缘局部示意图；
图13B为本公开至少一实施例的第三镂空部的边缘的另一局部示意图；
图14为本公开至少一实施例的绕线区的补偿极板的另一示意图；
图15为本公开至少一实施例的绕线区的补偿极板的另一示意图；
图16为本公开至少一实施例的绕线区的补偿极板的另一示意图；
图17为本公开至少一实施例的绕线区的补偿极板的另一示意图；
图18为本公开至少一实施例的绕线区的栅连接走线的另一示意图；
图19为本公开至少一实施例的栅连接走线的折线连接段与补偿极板的第一镂空部的位置示意图；
图20为本公开至少一实施例的栅连接走线的折线连接段与补偿极板的第一镂空部的 另一位置示意图；
图21为本公开至少一实施例的显示装置的示意图。
详述
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，例如包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，例如包括85°以上且95°以下的角度的状态。
在本说明书中，圆形、椭圆形、三角形、矩形、梯形、五边形或六边形等并非严格意 义上的，可以是近似圆形、近似椭圆形、近似三角形、近似矩形、近似梯形、近似五边形或近似六边形等，可以存在公差导致的一些小变形，例如可以存在导角、弧边以及变形等。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“相同”是指数值相差10％以内的情况，例如包括数值相差5％以内的情况。
在本公开中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。本公开中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
本公开中，“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。本公开所说的“A的形状”是指A在衬底的正投影的形状。
随着显示技术的发展，全面屏和窄边框的需求越来越大。为了不损失拍照的效果，显示基板需要进行特殊设计，以满足后置摄像头露出的目的。其中，显示区通孔(AA hole)设计是全面屏的主要解决方案之一。由于在显示区通孔没有设置子像素，原本经过显示区通孔的走线需要绕过显示区通孔来连接显示区通孔两侧的子像素，因此，针对传输同种信号的走线，绕过显示区通孔的走线的信号负载(loading)与不需要绕过显示区通孔的走线的信号负载会产生差异，从而造成显示不良(Mura)等情况。
本实施例提供一种显示基板，包括：衬底、多个子像素、多条第一走线以及补偿极板。衬底包括显示区域和位于显示区域至少一侧的周边区域。多个子像素设置在衬底的一侧且位于显示区域。多条第一走线位于周边区域，并与所述多个子像素电连接。补偿极板位于周边区域，补偿极板与多条第一走线之间设置有至少一个绝缘层。补偿极板在衬底的正投影与多条第一走线在衬底的正投影部分交叠。补偿极板具有镂空结构，镂空结构在衬底的正投影与至少一条第一走线在衬底的正投影部分交叠。
在一些示例中，补偿极板在衬底的正投影可以覆盖至少一条第一走线在衬底的正投影；或者，补偿极板在衬底的正投影与多条第一走线中的每条第一走线在衬底的正投影均部分交叠。补偿极板的镂空结构在衬底的正投影与一条或多条第一走线在衬底的正投影部分交叠。补偿极板的镂空结构在衬底的正投影可以与至少一条第一走线在衬底的正投影没有交叠。
在一些示例中，补偿极板的镂空结构可以位于补偿极板内部，例如可以包括位于补偿极板内部且独立设置的多个开口或开槽。镂空结构的边缘与补偿极板的外边缘可以没有连通。在另一些示例中，镂空结构可以位于补偿极板的外边缘处，使得镂空结构的至少部分边缘可以与补偿极板的外边缘连通，例如，镂空结构的边缘可以作为补偿极板的外边缘的一部分。本示例的补偿极板的外边缘可以为非规则形状。
本实施例提供的显示基板，通过设置与第一走线在衬底的正投影存在交叠的补偿极板，可以对第一走线进行电容补偿，以实现对第一走线的负载补偿；而且，补偿极板具有镂空结构，通过设置镂空结构可以调节多条第一走线与补偿极板在衬底的正投影的交叠面积，从而实现对不同第一走线进行差异化的负载补偿。
在一些示例性实施方式中，衬底还可以包括：孔区。周边区域可以包括位于孔区和显示区域之间的绕线区，多条第一走线和补偿极板可以均位于绕线区。本示例中，通过在绕线区设置补偿极板，可以对绕过孔区的第一走线进行负载补偿，改善由于孔区所导致的走线信号负载差异。
在一些示例性实施方式中，镂空结构可以具有至少一条第一镂空边缘，至少一条第一 镂空边缘的延伸方向平行于至少一条第一走线的延伸方向，至少一条第一镂空边缘在衬底的正投影可以位于所述至少一条第一走线在衬底的正投影范围内。本示例中，通过设置第一走线在衬底的正投影覆盖镂空结构的第一镂空边缘在衬底的正投影，可以改善镂空结构的边缘影响上方绝缘层成膜效果，进而影响上方导电层存在材料残留(Remain)或走线不良的情况。
在一些示例性实施方式中，多条第一走线可以包括：沿同一方向延伸的多条直线走线段。补偿极板的镂空结构可以包括多个第一镂空部。至少一个第一镂空部可以具有第一边缘，第一边缘的延伸方向可以平行于多条直线走线段的延伸方向；单个第一镂空部的第一边缘在衬底的正投影可以位于一条直线走线段在衬底的正投影范围内。在本示例中，镂空结构的第一镂空边缘可以包括多个第一镂空部的第一边缘。在一些示例中，第一镂空部可以为设置在补偿极板的开口。例如，第一镂空部在衬底的正投影可以为矩形。然而，本实施例对此并不限定。例如，第一镂空部在衬底的正投影可以为环形或其他形状。本示例通过设置多个第一镂空部，且第一走线的直线走线段在衬底的正投影可以覆盖第一镂空部的第一边缘在衬底的正投影，可以改善镂空结构的边缘影响上方导电层存在材料残留或走线不良的情况。
在一些示例性实施方式中，多个第一走线可以包括：延伸方向相同的多条弧线走线段。补偿极板的镂空结构可以包括多个第二镂空部。多个第二镂空部可以沿着多条弧线走线段的延伸方向排布。至少一个第二镂空部可以具有第三边缘，第三边缘的延伸方向可以平行于多条弧线走线段的延伸方向，单个第二镂空部的第三边缘在衬底的正投影可以位于一条弧线走线段在衬底的正投影范围内。本示例中，镂空结构的第一镂空边缘可以包括多个第二镂空部的第三边缘。在一些示例中，第二镂空部可以为设置在镂空极板的开口。例如，第二镂空部在衬底的正投影可以为矩形。然而，本实施例对此并不限定。例如，第二镂空部在衬底的正投影可以为环形或其他形状。本示例通过设置多个第二镂空部，且第一走线的弧线走线段在衬底的正投影可以覆盖第二镂空部的第三边缘在衬底的正投影，可以改善镂空结构的边缘影响上方导电层存在材料残留或走线不良的情况。
在一些示例性实施方式中，补偿极板的镂空结构可以包括：至少一个第三镂空部；所述至少一个第三镂空部可以沿着孔区的至少部分边缘延伸。与所述至少一个第三镂空部在衬底的正投影存在交叠的第一走线的长度，可以大于没有与所述至少一个第三镂空部在衬底的正投影存在交叠的第一走线的长度。在一些示例中，第三镂空部在衬底的正投影可以为设置在补偿极板的弧形镂空槽。然而，本实施例对此并不限定。例如，第三镂空部可以为环形镂空槽。本示例通过设置沿着孔区边缘延伸的第三镂空部，可以实现对多条第一走线的差异化负载补偿。
在一些示例性实施方式中，至少一个第三镂空部的至少部分边缘在衬底的正投影可以为台阶形状。台阶形状可以包括：依次连接的多个台阶结构，每个台阶结构可以包括相互连接的第一台阶段和第二台阶段；第一台阶段和第二台阶段为延伸方向不同的直线段。每个台阶结构的第一台阶段在衬底的正投影可以位于一条第一走线在衬底的正投影范围内，第二台阶段在衬底的正投影可以与至少两条相邻第一走线在衬底的正投影存在交叠。在本示例中，镂空结构的第一镂空边缘可以包括多个台阶结构的第一台阶段。本示例通过设置沿着孔区边缘延伸的第三镂空部的部分边缘为台阶形状，可以实现对多条第一走线的差异化负载补偿，而且可以改善镂空结构的边缘影响上方导电层存在材料残留或走线不良的情况。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示基板的示意图。图2为图1中的栅线的示意图。在 一些示例中，如图1和图2所示，显示基板可以包括：孔区A2、位于孔区A2至少一侧的显示区域A1、以及位于显示区域A1至少一侧的周边区域BB。周边区域BB可以包括：位于孔区A2和显示区域A1之间的绕线区B5、沿第二方向Y位于显示区域A1两侧的第一周边区域B1和第四周边区域B4、沿第一方向X位于显示区域A1两侧的第二周边区域B2和第三周边区域B3。第一周边区域B1可以与第二周边区域B2和第三周边区域B3连通，并与显示区域A1连接；第四周边区域B4可以与第二周边区域B2和第三周边区域B3连通，并与显示区域A1连接。第一周边区域B1、第二周边区域B2、第三周边区域B3和第四周边区域B4连通后可以围绕显示区域A1。例如，第一周边区域B1可以为显示基板的下边框区域，第二周边区域B2可以为显示基板的左边框区域，第三周边区域B3可以为显示基板的右边框区域，第四周边区域B4可以为显示基板的上边框区域。然而，本实施例对此并不限定。
在一些示例中，孔区A2内没有设置子像素，孔区A2不用于显示；换言之，孔区A2可以为非显示区域。绕线区B5内可以没有设置子像素，绕线区B5可以不用于显示。
在一些示例中，孔区A2的正投影形状可以为圆形，例如，孔区A2的直径范围可以为6毫米至20毫米，比如可以约为12毫米。然而，本实施例对此并不限定。在另一些示例中，孔区A2的正投影形状可以为矩形、圆角矩形、椭圆形、半圆形、五边形或六边形等。
在一些示例中，孔区A2的边缘可以为绕线区B5的内边缘，绕线区B5的外边缘可以与显示区域A1连接。例如，孔区A2的正投影形状可以为圆形，绕线区B5的正投影形状可以为圆环形。然而，本实施例对此并不限定。在另一些示例中，绕线区的正投影形状可以匹配孔区的形状；例如，孔区的正投影形状为矩形，绕线区的正投影形状可以为矩形环；或者，孔区的正投影形状为椭圆形，绕线区的正投影形状可以为椭圆环。
在一些示例中，孔区A2可以位于显示区域A1的中间位置，使得显示区域A1可以围绕在孔区A2的四周。然而，本实施例对此并不限定。在另一些示例中，孔区可以邻近显示区域的上边缘或下边缘，使得显示区域可以至少围绕孔区的左侧和右侧。
在一些示例中，显示区域A1可以包括组成像素阵列的多个子像素PX，多个子像素PX可以被配置为显示动态图片或静止图像。例如，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在一些示例中，显示区域A1可以包括：多条栅线以及多条数据线。多条栅线可以沿第一方向X延伸，并沿第二方向Y排布；多条数据线可以沿第二方向Y延伸，并沿第一方向X排布。多条栅线和多条数据线在衬底的正投影可以交叉形成多个子像素区域，每个子像素区域内设置一个子像素PX。多条数据线与多个子像素PX电连接，多条数据线可以配置为向多个子像素PX提供数据信号。多条栅线与多个子像素PX电连接，多条栅线可以配置为向多个子像素PX提供栅极驱动信号。例如，栅极驱动信号可以包括扫描信号，或者可以包括扫描信号和发光控制信号，或者可以包括扫描信号、复位控制信号和发光控制信号。在一些示例中，第二方向Y可以是显示区域A1内数据线的延伸方向；第一方向X可以是显示区域A1内栅线的延伸方向。第一方向X与第二方向Y可以相互交叉，例如可以相互垂直。
在一些示例中，多条栅线可以包括：多条第一类栅线311和多条第二类栅线312。每条栅线可以连接沿第一方向X排布的多个子像素。由于孔区A2没有设置子像素，因此，至少一条第一类栅线311连接的子像素的数目可以小于至少一条第二类栅线312连接的子像素的数目。至少一条第一类栅线311的信号负载可以小于至少一条第二类栅线312的信 号负载。
在一些示例中，多条第二类栅线312可以沿第一方向X延伸，并沿第二方向Y排布。例如，多条第二类栅线312可以分为沿第二方向Y设置的两组，多条第一类栅线311可以在第二方向Y上位于两组第二类栅线312之间。
在一些示例中，如图2所示，多条第一类栅线311在第一方向X上被孔区A2截断。第一类栅线311可以包括：位于显示区域A1的第一栅延伸段311-1和第二栅延伸段311-2。第一栅延伸段311-1和第二栅延伸段311-2可以通过位于绕线区B5的栅连接走线33连接。栅连接走线33可以沿孔区A2绕线设置。
在一些示例中，第一类栅线311的第一栅延伸段311-1和第二栅延伸段311-2、以及栅连接走线33可以为相互连接的一体结构；或者，第一栅延伸段311-1和第二栅延伸段311-2可以位于相同导电层，栅连接走线33所在的导电层可以不同于第一栅延伸段311-1所在的导电层。
在一些示例中，位于绕线区B5的至少一条栅连接走线33可以包括：第一直线连接段331、第二直线连接段332以及弧形连接段333。第一直线连接段331和第二直线连接段332可以沿第一方向X延伸，并沿第一方向X位于孔区A2的两侧。弧形连接段333可以连接在第一直线连接段331和第二直线连接段332之间。第一直线连接段331可以与第一栅延伸段311-1连接，第二直线连接段332可以与第二栅延伸段311-2连接。例如，第一直线连接段331、第二直线连接段332以及弧形连接段333可以为相互连接的一体结构。
在一些示例中，多条数据线可以包括：多条第一类数据线321和多条第二类数据线322。每条数据线可以连接沿第二方向Y排布的多个子像素。由于孔区A2没有设置子像素，因此，至少一条第一类数据线321连接的子像素的数目可以小于至少一条第二类数据线322连接的子像素的数目，所述至少一条第一类数据线321的信号负载可以小于所述至少一条第二类数据线322的信号负载。
在一些示例中，多条第二类数据线322可以沿第二方向Y延伸，并沿第一方向X排布。例如，多条第二类数据322可以分为沿第一方向X设置的两组，多条第一类数据线321可以在第一方向X上位于两组第二类数据线322之间。
在一些示例中，多条第一类数据线321在第二方向Y上被孔区A2截断。第一类数据线321可以包括：位于显示区域A1的第一数据连接段321-1和第二数据连接段321-2。第一数据连接段321-1和第二数据连接段321-2可以通过位于绕线区B5的数据连接走线34连接。数据连接走线34可以沿孔区A2绕线设置。
在一些示例中，第一类数据线321的第一数据连接段321-1和第二数据连接段321-2、以及数据连接走线34可以为相互连接的一体结构；或者，第一数据连接段321-1和第二数据连接段321-2可以位于相同导电层，数据连接走线34所在的导电层可以不同于第一数据连接段321-1所在的导电层。
在一些示例中，显示区域A1的一个像素单元可以包括三个子像素，三个子像素可以分别为出射第一颜色光(例如，红光)的第一子像素、出射第二颜色光(例如，绿光)的第二子像素和出射第三颜色光(例如，蓝光)的第三子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素可以分别为出射红光的子像素、出射绿光的子像素、出射蓝光的子像素和出射白光的子像素。又如，一个像素单元可以包括四个子像素，四个子像素可以包括一个出射红光的子像素、一个出射蓝光的子像素、以及两个出射绿光的子像素。
在一些示例中，一个子像素PX可以包括：像素电路以及与像素电路电连接的发光元件。像素电路可以包括多个晶体管和至少一个电容。例如，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。在一些示例中，像素电路中的多个晶体管可以包括P型晶体管和N型晶体管。在另一些示例中，像素电路中的多个晶体管可以为P型晶体管或者可以为N型晶体管，像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。
在一些示例中，子像素的发光元件的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素的发光元件可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素的发光元件可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diode)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
图3A为本公开至少一实施例的显示基板的显示区域的局部剖面示意图。图3A中以显示区域的一个子像素的结构为例进行示意。本示例中，像素电路中的多个像素晶体管的晶体管类型可以不同，例如可以包括低温多晶硅薄膜晶体管和氧化物薄膜晶体管。
在一些示例中，如图3A所示，在垂直于显示基板的方向上，显示基板的显示区域可以包括：衬底10、以及依次设置在衬底10上的电路结构层12、发光结构层13、以及封装结构层14。电路结构层12可以至少包括：多个子像素的像素电路，每个子像素的像素电路可以包括多个晶体管和至少一个电容。发光结构层13可以至少包括：多个子像素的发光元件。在另一些示例中，显示基板还可以包括：位于封装结构层远离衬底一侧的触控结构层。例如，触控结构层可以包括至少一个触控导电层。
在一些示例中，图3A中以每个子像素包括的一个第一晶体管21、一个第二晶体管22以及一个电容23为例进行示意。第一晶体管21和第二晶体管22的晶体管类型可以不同。其中，第一晶体管21可以为低温多晶硅薄膜晶体管，第二晶体管22可以为氧化物薄膜晶体管。或者，第一晶体管21可以为氧化物薄膜晶体管，第二晶体管22可以为低温多晶硅薄膜晶体管。
在一些示例中，显示区域的电路结构层12可以包括：设置在衬底10上的底部遮光金属层(BSM，Bottom Shielding Metal)、第一半导体层、第一栅金属层、第二栅金属层、第二半导体层、第三栅金属层、第一源漏金属层以及第二源漏金属层。底部遮光金属层与第一半导体层之间可以设置有第一绝缘层101，第一绝缘层101还可以称为缓冲层；第一半导体层和第一栅金属层之间可以设置有第二绝缘层102，第一栅金属层和第二栅金属层之间可以设置有第三绝缘层103；第二栅金属层和第二半导体层之间可以设置有第四绝缘层104；第二半导体层和第三栅金属层之间可以设置有第五绝缘层105；第二绝缘层102至第五绝缘层105还可以称为栅绝缘层；第三栅金属层和第一源漏金属层之间可以设置有第六绝缘层106，第六绝缘层106还可以称为层间绝缘层；第一源漏金属层和第二源漏金属层之间可以设置有第七绝缘层107和第八绝缘层108，第八绝缘层108可以位于第七绝 缘层107远离衬底10的一侧；第二源漏金属层远离衬底10的一侧可以设置有第九绝缘层109。第七绝缘层107还可以称为钝化层，第八绝缘层108还可以称为第一平坦层，第九绝缘层109还可以称为第二平坦层。其中，第一绝缘层101、第二绝缘层102、第三绝缘层103、第四绝缘层104、第五绝缘层105、第六绝缘层106和第七绝缘层107可以为无机绝缘层，第八绝缘层108和第九绝缘层109可以为有机绝缘层。然而，本实施例对此并不限定。在另一些示例中，底部遮光金属层靠近衬底一侧还可以设置缓冲层，缓冲层可以防止衬底中的有害物质侵入显示基板的内部，还可以增加显示基板中的膜层在衬底上的附着力。另一些示例中，第一源漏金属层和第二源漏金属层之间可以省略第七绝缘层，第一源漏金属层和第二源漏金属层之间可以仅设置第八绝缘层。
在一些示例中，如图3A所示，显示区域的底部遮光金属层可以至少包括：遮光块25。遮光块25可以被配置为至少部分覆盖像素电路的晶体管的有源层，以避免外部光线对晶体管的性能产生影响。例如，遮光块25可以与周边区域的恒压信号线电连接，比如遮光块25可以配置为接收第一电源信号。显示区域的第一半导体层可以至少包括：第一晶体管21的第一有源层210。第一晶体管21的第一有源层210可以包括：第一区2101、第二区2102以及位于第一区2101和第二区2102之间的沟道区2100。第一栅金属层可以至少包括：第一晶体管21的第一栅极213、以及电容23的第一极板231。第一晶体管21的第一栅极213在衬底10的正投影可以覆盖第一有源层210的沟道区2100在衬底10的正投影。第二栅金属层可以至少包括：电容23的第二极板232。电容23的第二极板232和第一极板231在衬底10的正投影可以至少部分交叠，例如，两者可以重合。第二半导体层可以至少包括：第二晶体管22的第二有源层220。第三栅金属层可以至少包括：第二晶体管22的第二栅极223。第二晶体管22的第二栅极223在衬底10的正投影与第二有源层220在衬底10的正投影可以部分交叠。
在一些示例中，如图3A所示，第一源漏金属层可以至少包括：第一晶体管21的第一源极211和第一漏极212、第二晶体管22的第二源极221和第二漏极222。第六绝缘层106在显示区域可以开设有多个像素过孔(例如，包括第一像素过孔、第二像素过孔、第三像素过孔和第四像素过孔)，第一像素过孔内的第六绝缘层106、第五绝缘层105、第四绝缘层104、第三绝缘层103和第二绝缘层102可以被去掉，暴露出第一有源层210的第一区2101的至少部分表面；第二像素过孔内的第六绝缘层106、第五绝缘层105、第四绝缘层104、第三绝缘层103和第二绝缘层102可以被去掉，暴露出第一有源层210的第二区2102的至少部分表面。第三像素过孔和第四像素过孔内的第六绝缘层106和第五绝缘层105可以被去掉，暴露出第二有源层220的两端的至少部分表面。第一晶体管21的第一源极211可以通过第一像素过孔与第一有源层210的第一区2101电连接，第一漏极212可以通过第二像素过孔与第一有源层210的第二区2102电连接。第二晶体管22的第二源极221可以通过第三像素过孔与第二有源层220的一端电连接，第二晶体管22的第二漏极222可以通过第四像素过孔与第二有源层220的另一端电连接。第二源漏金属层可以至少包括：第一转接电极241。第一转接电极241可以通过第八绝缘层108和第七绝缘层107开设的第五像素过孔与像素电路的第一晶体管21的第一漏极212电连接。本示例可以通过第一转接电极241实现像素电路与发光元件之间的电连接。
在一些示例中，如图3A所示，发光结构层13可以包括：像素定义层134和多个发光元件。例如，每个发光元件可以包括：叠设的第一电极131、有机发光层132和第二电极133。发光元件的第一电极131可以为阳极，第一电极131可以设置在第九绝缘层109上，并通过第九绝缘层109开设的第六像素过孔，与第一转接电极241电连接。像素定义层134设置在第一电极131和第九绝缘层109上，像素定义层134可以开设有多个像素开口，一个像素开口可以暴露出对应的一个第一电极131的至少部分表面。有机发光层132 的至少部分可以设置在一个像素开口内，并与对应的第一电极131连接。第二电极133可以设置在有机发光层132上，并与有机发光层132连接。有机发光层132在第一电极131和第二电极133的驱动下可以出射相应颜色的光线。
在一些示例中，发光元件的有机发光层132可以包括发光层(EML，Emitting Layer)，以及包括空穴注入层(HIL，Hole Injection Layer)、空穴传输层(HTL，Hole Transport Layer)、空穴阻挡层(HBL，Hole Block Layer)、电子阻挡层(EBL，Electron Block Layer)、电子注入层(EIL，Electron Injection Layer)、电子传输层(ETL，Electron Transport Layer)中的一个或多个膜层。在第一电极131和第二电极133的电压驱动下，可以利用有机材料的发光特性根据需要的灰度发光。
在一些示例中，不同颜色的发光元件的发光层可以不同。例如，红色发光元件包括红色发光层，绿色发光元件包括绿色发光层，蓝色发光元件包括蓝色发光层。为了降低工艺难度和提升良率，位于发光层一侧的空穴注入层和空穴传输层可以采用共通层，位于发光层另一侧的电子注入层和电子传输层可以采用共通层。在一些示例中，空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以通过一次工艺(一次蒸镀工艺或一次喷墨打印工艺)制作，并通过形成的膜层表面段差或者通过表面处理等手段实现隔离。例如，相邻子像素对应的空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以是隔离的。在一些示例中，有机发光层可以通过采用精细金属掩模版(FMM，Fine Metal Mask)或者开放式掩膜版(Open Mask)蒸镀制备形成，或者采用喷墨工艺制备形成。
在一些示例中，如图3A所示，封装结构层14可以包括叠设的第一封装层141、第二封装层142和第三封装层143。其中，第一封装层141和第三封装层143可以采用无机材料，例如氮化硅、氧化硅、氮氧化硅等，无机材料的致密性高，可以防止水、氧等的侵入。第二封装层142可以设置在第一封装层141和第三封装层143之间，以保证外界水汽无法进入发光元件。第二封装层142可以采用有机材料，例如，可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，或者可以为高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一封装层141和第三封装层143的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。然而，本实施例对此并不限定。例如，封装结构层可以采用无机/有机/无机/有机/无机的五层叠设结构。
图3B为本公开至少一实施例的显示基板的显示区域的另一局部剖面示意图。本示例中，像素电路中的多个像素晶体管的晶体管类型可以相同，例如可以均为低温多晶硅薄膜晶体管。图3B中以每个子像素包括的一个第一晶体管21和一个电容23为例进行示意。
在一些示例中，如图3B所示，显示区域的电路结构层12可以包括：设置在衬底10上的底部遮光金属层、第一半导体层、第一栅金属层、第二栅金属层、第一源漏金属层以及第二源漏金属层。底部遮光金属层和第一半导体层之间可以设置第一绝缘层101，第一半导体层和第一栅金属层之间可以设置第二绝缘层102，第一栅金属层和第二栅金属层之间可以设置第三绝缘层103，第二栅金属层和第一源漏金属层之间可以设置第四绝缘层104，第一源漏金属层和第二源漏金属层之间可以设置第七绝缘层107和第八绝缘层108，第二源漏金属层远离衬底10的一侧可以设置第九绝缘层109。第八绝缘层108和第九绝缘层109可以为有机绝缘层，第一绝缘层101、第二绝缘层102、第三绝缘层103和第四绝缘层104可以为无机绝缘层。关于本示例的显示基板的显示区域的其余结构可以参照图3A所示实施例的描述，故于此不再赘述。
在一些示例中，像素电路可以包括：八个像素晶体管(即第一像素晶体管至第八像素晶体管)以及一个存储电容。第二像素晶体管可以为氧化物薄膜晶体管，第一像素晶体管、 第三像素晶体管至第八像素晶体管可以为低温多晶硅薄膜晶体管。
在一些示例中，第三像素晶体管的栅极与第一节点电连接，第三像素晶体管的第一极与第二节点电连接，第三像素晶体管的第二极与第三节点电连接。第四像素晶体管的栅极与第一扫描线电连接，第四像素晶体管的第一极与数据线电连接，第四像素晶体管的第二极与第二节点电连接。第二像素晶体管的栅极与第二扫描线电连接，第二像素晶体管的第一极与第三节点电连接，第二像素晶体管的第二极与第一节点电连接。第五像素晶体管的栅极与发光控制线电连接，第五像素晶体管的第一极与第一电源线电连接，第五像素晶体管的第二极与第二节点电连接。第六像素晶体管的栅极与发光控制线电连接，第六像素晶体管的第一极与第三节点电连接，第六像素晶体管的第二极与第四节点电连接。第一像素晶体管的栅极与第一复位控制线电连接，第一像素晶体管的第一极与第一初始信号线电连接，第一像素晶体管的第二极与第三节点电连接。第一像素晶体管可以配置为对第三节点进行复位。第七像素晶体管的栅极与第二复位控制线电连接，第七像素晶体管的第一极与第二初始信号线电连接，第七像素晶体管的第二极与第四节点电连接。第七像素晶体管可以配置为对第四节点进行复位。第八像素晶体管的栅极与第二复位控制线电连接，第八像素晶体管的第一极与第三初始信号线电连接，第八像素晶体管的第二极与第二节点电连接。第八像素晶体管可以配置为对第二节点进行复位。存储电容的第一电极与第一节点电连接，存储电容的第二电极与第一电源线电连接。
在一些示例中，以图3A所示的显示基板的膜层结构为例，多条栅线可以位于第一栅金属层和第二栅金属层，多条数据线可以位于第一源漏金属层和第二源漏金属层。例如，多条栅线可以包括：多条第一扫描线、多条第二扫描线、多条发光控制线、多条第一复位控制线和多条第二复位控制线；其中，多条第一扫描线和多条第一复位控制线可以设置在第一栅金属层，多条第二扫描线、多条发光控制线和多条第二复位控制线可以设置在第二栅金属层。
在一些示例中，位于绕线区的多条栅连接走线可以交替排布在第一栅金属层和第二栅金属层。例如，与第一扫描线连接的栅连接走线可以位于第一栅金属层，与第一复位控制线连接的栅连接走线可以位于第一栅金属层，与第二扫描线连接的栅连接走线可以位于第二栅金属层，与发光控制线连接的栅连接走线可以位于第二栅金属层，与第二复位控制线连接的栅连接走线可以位于第二栅金属层。位于绕线区的多条数据连接线可以交替排布在第一源漏金属层和第二源漏金属层。然而，本实施例对此并不限定。
在一些示例中，位于绕线区的多条第一走线可以包括：从孔区A2的一侧绕过孔区A2的第一组第一走线、以及从孔区A2的另一侧绕过孔区A2的第二组第一走线。例如，位于绕线区的多条第一走线可以包括：多条栅连接走线33。孔区A2可以具有第一中心线，第一中心线可以经过孔区A2的中心点且沿第一方向X延伸。第一组第一走线可以包括：位于第一中心线在第二方向Y一侧的多条栅连接走线33，比如，从孔区A2上侧绕过的多条栅连接走线33；第二组第一走线可以包括：位于第一中心线在第二方向Y的反方向一侧的多条栅连接走线33，比如，从孔区A2下侧绕过的多条栅连接走线。
图4为图2中沿Q-Q’方向的局部剖面示意图。在一些示例中，如图2和图4所示，位于绕线区B5的多条栅连接走线33可以包括：位于第一栅金属层的栅连接走线33a和位于第二栅金属层的栅连接走线33b。多条栅连接走线33a和多条栅连接走线33b可以交替排布，且相邻的栅连接走线33a和33b在衬底10的正投影可以没有交叠。绕线区B5的多条数据连接走线34可以包括：位于第一源漏金属层的数据连接走线34a和位于第二源漏金属层的数据连接走线34b。相邻的数据连接走线34a和34b在衬底10的正投影可以没有交叠。
在一些示例中，绕线区B5可以设置有补偿极板36。补偿极板36可以配置为接收恒压信号，比如第一电源线提供的第一电源信号，或者第二电源线提供的第二电源信号。补偿极板36可以位于底部遮光金属层，补偿极板36在衬底10的正投影可以与多条栅连接走线33a和33b在衬底10的正投影至少部分交叠。例如，补偿极板36在衬底10的正投影可以覆盖一部分栅连接走线在衬底10的正投影，且与另一部分栅连接走线在衬底10的正投影可以部分交叠；或者，补偿极板36在衬底10的正投影与所有栅连接走线在衬底10的正投影可以均部分交叠。本示例通过在底部遮光金属层设置补偿极板36，可以对绕线区B5内位于第一栅金属层和第二栅金属层的栅连接走线进行电容补偿，从而对栅连接走线所连接的第一类栅线进行负载补偿，使得补偿后的第一类栅线的负载和第二类栅线的负载可以大致相同，进而保证显示效果。
在一些示例中，绕线区B5可以设置一个补偿极板36。补偿极板36在衬底的正投影可以为具有镂空结构的圆环状。补偿极板36的外边缘可以与绕线区B5的边缘形状大致相同。本示例通过设置大面积的补偿极板，可以避免在底部遮光金属层设置细线，从而防止底部遮光金属层对上方导电层的走线产生影响。
在一些示例中，补偿极板36可以具有镂空结构，镂空结构在衬底的正投影与至少一条栅连接走线在衬底的正投影可以部分交叠。本示例通过设置镂空结构，可以避免大面积的补偿极板导致的膜层剥落(peeling)问题；而且通过设置镂空结构，可以调节补偿极板与不同栅连接走线的交叠面积，从而有利于针对不同栅连接走线进行差异化电容补偿。然而，在补偿极板的边缘位置(比如镂空结构的边缘位置)，补偿极板上方的无机膜层的成膜效果会变差，例如产生窄缝或凹陷位置，使得无机膜层上方的导电层会存在残留(Remain)情况，容易导致走线不良等，进而影响显示基板的显示效果。例如，以图3B所示的显示基板的膜层结构为例，补偿极板可以位于底部遮光金属层，多条栅连接走线可以位于第一栅金属层和第二栅金属层，补偿极板的边缘位置上方的无机绝缘层(例如包括第一绝缘层101、第二绝缘层102、第三绝缘层103和第四绝缘层104)的成膜效果会变差，从而引起第一源漏金属层在补偿极板的边缘位置对应的区域容易产生金属残留、走线不良等情况。本示例通过对补偿极板的镂空结构进行设计，利用第一栅金属层和第二栅金属层对补偿极板的镂空结构的部分边缘进行覆盖，可以改善在补偿极板的镂空结构的边缘位置上方的导电膜层存在的金属残留或走线不良情况。
图5为本公开至少一实施例的栅连接走线的第一直线连接段与补偿极板的多个第一镂空部的位置示意图。在本示例中，补偿极板的镂空结构可以具有多个第一镂空部；多条第一走线的多条直线走线段可以包括：多条栅连接走线的第一直线连接段和第二直线连接段。图5以第一直线连接段与第一镂空部的位置关系为例进行说明，关于第二直线连接段与第一镂空部的位置关系可以参照第一直线连接部与第一镂空部的位置关系，故于此不再赘述。
在一些示例中，如图5所示，多条栅连接走线33的第一直线连接段331可以沿第一方向X延伸，并沿第二方向Y依次排布。多条第一直线连接段331可以位于同一导电层(比如，第一栅金属层或第二栅金属层)，或者可以交替排布在第一栅金属层和第二栅金属层。本实施例对此并不限定。
在一些示例中，如图5所示，补偿极板的镂空结构可以具有多个第一镂空部41。多个第一镂空部41可以沿第一方向X和第二方向Y阵列排布。本示例的一行第一镂空部可以包括沿第一方向X排布的多个第一镂空部41，一列第一镂空部可以包括沿第二方向Y排布的多个第一镂空部41。一行第一镂空部可以沿第一方向X对齐排布。一列第一镂空部可以沿第二方向Y对齐排布。
在一些示例中，第一镂空部41可以为补偿极板上设置的开口。第一镂空部41在衬底的正投影可以为矩形。第一镂空部41可以具有相互平行设置的第一边缘411和412、相互平行设置的第二边缘413和414。第一边缘411、第二边缘413、第一边缘412和第二边缘414可以依次连接。第一边缘411的延伸方向可以垂直于第二边缘413的延伸方向。第一边缘411和412的延伸方向可以平行于多条第一直线连接段331的延伸方向，第二边缘413和414的延伸方向可以垂直于多条第一直线连接段331的延伸方向。
在一些示例中，第一镂空部41的第一边缘411在衬底的正投影可以位于一条第一直线连接段331在衬底的正投影范围内，第一边缘412在衬底的正投影可以位于另一条第一直线连接段331在衬底的正投影范围内。在一些示例中，第一边缘411在衬底的正投影可以位于一条第一直线连接段331在衬底的正投影沿第二方向Y的中间位置。第一边缘412在衬底的正投影可以位于另一条第一直线连接段331在衬底的正投影沿第二方向Y的中间位置。比如，第一边缘411在衬底的正投影可以与一条第一直线连接段331在衬底的正投影沿第二方向Y的中线重合。第一边缘412在衬底的正投影可以与另一条第一直线连接段331在衬底的正投影沿第二方向Y的中线重合。
在一些示例中，第一边缘411在衬底的正投影所在的第一直线连接段331，与第一边缘412在衬底的正投影所在的第一直线连接段331可以没有相邻，这两条第一直线连接段331之间可以设置至少一条第一直线连接段(例如两条第一直线连接段)。
在一些示例中，第一镂空部41的第二边缘413和414在衬底的正投影可以与多条第一直线连接段331(例如，四条或三条第一直线连接段331)在衬底的正投影部分交叠。第二边缘413和414的长度相同，第二边缘413的长度可以大于至少两条第一直线连接段331的线宽。第一边缘411的长度可以与第二边缘413的长度相同，或者不同。本实施例对此并不限定。
在些示例中，一条第一直线连接段331在衬底的正投影可以覆盖一行第一镂空部中多个第一镂空部41的第一边缘411在衬底的正投影，或者，可以覆盖一行第一镂空部中多个第一镂空部41的第一边缘412在衬底的正投影。
本示例的第一镂空部的设置方式，可以改善补偿极板的边界位置(例如第一镂空部的边缘位置)对上方无机膜层和导电层(例如第一源漏金属层)的影响，可以防止导电层的材料残留和走线不良。
图6A为图1中区域S1的局部放大示意图。图6B为图6A中多条栅连接走线的第一直线连接段的示意图。图6C为图6A中补偿极板的示意图。图6A至图6C示意了栅连接走线的第一直线连接段与补偿极板的局部交叠示意图。
在一些示例中，如图6A至图6C所示，位于第一栅金属层的栅连接走线33a的第一直线连接段331a可以沿第一方向X延伸，位于第二栅金属层的栅连接走线33b的第一直线连接段331b可以沿第一方向X延伸。多条栅连接走线33a的第一直线连接段331a和多条栅连接走线33b的第一直线连接段331b可以沿第二方向Y交替排布。第一直线连接段331a和331b在衬底的正投影可以没有交叠。第一直线连接段331a和331b的线宽可以相同。
在一些示例中，补偿极板36可以位于底部遮光金属层。补偿极板36可以具有沿第一方向X和第二方向Y阵列排布的多个第一镂空部41。多个第一镂空部41可以沿第一方向X和第二方向Y对齐排布。
在一些示例中，第一镂空部41在衬底的正投影可以为矩形。第一镂空部41可以具有平行设置的第一边缘411和412、以及平行设置的第二边缘413和414。第一边缘411和 412可以沿第一方向X延伸。第一边缘411和412的延伸方向与第一直线连接段331a和331b的延伸方向相同。第二边缘413和414的延伸方向可以垂直于第一直线连接段331a和331b的延伸方向。第一镂空部41的第一边缘411(或412)在衬底的正投影可以位于一条第一直线连接段331a(或331b)在衬底的正投影范围内。第一镂空部41的第二边缘413(或414)在衬底的正投影可以与多条第一直线连接段(例如，四条或三条第一直线连接段)在衬底的正投影存在交叠。第二边缘413(或414)的长度可以大于至少两条第一直线连接段的线宽。
本示例通过设置沿第一直线连接段的延伸方向阵列排布的多个第一镂空部，且多条第一直线延伸段在衬底的正投影可以覆盖多个第一镂空部的第一边缘在衬底的正投影，可以改善补偿极板的边界位置(例如第一镂空部的边缘位置)对上方无机膜层和导电层的影响，可以防止上方导电层(例如第一源漏金属层)的材料残留和走线不良。
图7为本公开至少一实施例的栅连接走线的第一直线连接段与补偿极板的多个第一镂空部的另一位置示意图。在一些示例中，如图7所示，补偿极板可以具有多个第一镂空部41。多个第一镂空部41可以沿第一方向X和第二方向Y阵列排布。多个第一镂空部41可以在第二方向Y上对齐设置；沿第一方向X上，至少两个相邻第一镂空部41可以错位设置。例如，一行第一镂空部中的相邻多个第一镂空部41(比如六个第一镂空部)可以呈阶梯状排布。比如，每个第一镂空部41可以具有经过中心点且沿第一方向X延伸的中心线，一行第一镂空部中的相邻六个第一镂空部41的中心线可以沿第二方向Y依次排布，任两个相邻第一镂空部41的中心线之间的最小距离可以相同。本实施例对此并不限定。
在一些示例中，如图7所示，第一镂空部41在衬底的正投影可以为矩形。第一镂空部41的第一边缘411和412的延伸方向平行于第一方向X，第一边缘411和412在衬底的正投影可以位于两条不同的第一直线连接段331在衬底的正投影范围内。第一镂空部41的第二边缘413和414的延伸方向可以平行于第二方向Y，第二边缘413和414在衬底的正投影与多条(例如四条)第一直线连接段331在衬底的正投影存在交叠。
本示例通过对多个第一镂空部进行错位设置，可以使得经过补偿极板的补偿之后，多条第一直线连接段的负载可以相同，从而实现对多条栅连接走线的差异化负载补偿。
图8为本公开至少一实施例的栅连接走线的第一直线连接段与补偿极板的多个第一镂空部的另一位置示意图。在一些示例中，如图8所示，补偿极板的多个第一镂空部41可以沿第一方向X和第二方向Y排布。多个第一镂空部41可以沿第二方向Y对齐排布。多个第一镂空部X可以在第一方向X错位排布。一行第一镂空部可以包括：沿第一方向X交替设置的第一组镂空部41a和第二组镂空部41b，第一组镂空部41a和第二组镂空部41b所包括的第一镂空部41的数目可以相同。然而，本实施例对此并不限定。例如，第一组镂空部41a和第二组镂空部41b所包括的第一镂空部的数目可以不同。比如，第一组镂空部41a所包括的第一镂空部的数目可以大于第二组镂空部41b所包括的第一镂空部的数目。
在一些示例中，第一组镂空部41a可以包括沿第一方向X对齐设置的多个第一镂空部41(比如三个第一镂空部)；第二组镂空部41b可以包括沿第一方向X对齐设置的多个第一镂空部41(比如三个第一镂空部)。第一组镂空部41a内的多个第一镂空部41的平行于第一方向X的中心线可以重合，第二组镂空部41b内的多个第一镂空部41的平行于第一方向X的中心线可以重合。
在一些示例中，第一组镂空部41a和第二组镂空部41b在第一方向X上可以错位排 布。例如，第一组镂空部41a的平行于第一方向X的中心线，可以位于第二组镂空部41b的平行于第一方向X的中心线在第二方向Y的一侧。
本示例中，多条栅连接走线33的第一直线连接段331在衬底的正投影与补偿极板在衬底的正投影的交叠面积可以不同。在一些示例中，与第一组镂空部41a和第二组镂空部41b在衬底的正投影均存在交叠的第一直线连接段(例如，第一直线连接段331-1)与补偿极板的交叠面积，可以小于仅与第一组镂空部41a或第二组镂空部41b在衬底的正投影存在交叠的第一直线连接段(例如，第一直线连接段331-2或331-3)与补偿极板的交叠面积。补偿极板对第一直线连接段331-1的补偿电容可以小于对第一直线连接段331-2或331-3的补偿电容。如此一来，补偿极板可以着重对第一直线连接段331-2和331-3进行信号补偿，实现对不同栅连接走线进行差异化补偿。本示例中单个第一镂空部的边缘与第一直线连接段的正投影关系可以参照前述实施例的描述，故于此不再赘述。
图9为本公开至少一实施例的栅连接走线的第一直线连接段与补偿极板的多个第一镂空部的另一位置示意图。在一些示例中，如图9所示，补偿极板的多个第一镂空部41可以沿第一方向X和第二方向Y排布。多个第一镂空部41可以沿第二方向Y对齐排布。多个第一镂空部41可以在第一方向X错位排布。一行第一镂空部可以包括：沿第一方向X交替设置的第三组镂空部41c和第四组镂空部41d。第三组镂空部41c和第四组镂空部41d所包括的第一镂空部41的数目可以相同。然而，本实施例对此并不限定。例如，第三组镂空部41c和第四组镂空部41d所包括的第一镂空部的数目可以不同。比如，第三组镂空部41c所包括的第一镂空部的数目可以大于第四组镂空部41d所包括的第一镂空部的数目。
在一些示例中，第三组镂空部41c可以包括沿第一方向X错位排布的多个第一镂空部41(比如三个第一镂空部)，第四组镂空部41d可以包括沿第一方向X错位排布的多个第一镂空部41(比如三个第一镂空部)。第三组镂空部41c内的多个第一镂空部41的平行于第一方向X的中心线可以沿第二方向Y的反方向依次设置，第三组镂空部41c内任两个相邻第一镂空部41的平行于第一方向X的中心线之间的最小距离可以相同。第四组镂空部41d内的多个第一镂空部41的平行于第一方向X的中心线可以沿第二方向Y依次设置。第四组镂空部41d内任两个相邻第一镂空部41的平行于第一方向X的中心线之间的最小距离可以相同。
在一些示例中，第三组镂空部41c内的至少一个第一镂空部和第四组镂空部41d内的至少一个第一镂空部可以在第一方向X上对齐设置。例如，相邻的第三组镂空部41c和第四组镂空部41d可以关于两者的平行于第二方向Y的中线对称设置。然而，本实施例对此并不限定。
本示例中，多条栅连接走线33的第一直线连接段331在衬底的正投影与补偿极板在衬底的正投影的交叠面积可以不同。在一些示例中，与第三组镂空部41c和第四组镂空部41d的全部第一镂空部在衬底的正投影均存在交叠的第一直线连接段(例如，第一直线连接段331-5或331-6)与补偿极板的交叠面积，可以大于仅与第一组镂空部41a和第二组镂空部41b的部分第一镂空部在衬底的正投影存在交叠的第一直线连接段(例如，第一直线连接段331-4)与补偿极板的交叠面积。补偿极板对第一直线连接段331-4的补偿电容可以大于对第一直线连接段331-5或331-6的补偿电容。如此一来，补偿极板可以着重对第一直线连接段331-4进行信号补偿，实现对不同栅连接走线进行差异化补偿。本示例中单个第一镂空部的边缘与第一直线连接段的正投影关系可以参照前述实施例的描述，故于此不再赘述。
图10A为图1中区域S1的另一局部放大示意图。图10B为图10A中多条栅连接走 线的第一直线连接段的示意图。图10C为图10A中补偿极板的示意图。图10A至图10C示意了栅连接走线的第一直线连接段与补偿极板的局部交叠示意图。
在一些示例中，补偿极板36可以位于底部遮光金属层。补偿极板36可以具有沿第一方向X和第二方向Y阵列排布的多个第一镂空部41。多个第一镂空部41可以包括：沿第一方向X和第二方向Y阵列排布的多个第五组镂空部41e。其中，多个第一镂空部41可以沿第二方向Y对齐排布，并沿第一方向X错位排布。
在一些示例中，第五组镂空部41e可以包括：沿第一方向X错位设置的六个第一镂空部41。第五组镂空部41e内的六个第一镂空部41的平行于第一方向X的中心线可以沿第二方向Y依次设置，且任两个相邻第一镂空部41的平行于第一方向X的中心线之间的最小距离可以相同。沿第一方向X排布的相邻第五组镂空部41e可以在第一方向X上对齐排布。例如，第五组镂空部41e内的第一个第一镂空部与第一方向X上相邻第五镂空部41e内的第一个第一镂空部可以在第一方向X上对齐排布。关于本示例的第一镂空部与第一直线连接段的其余位置关系可以参照前述实施例的描述，故于此不再赘述。
本示例通过将多个第一镂空部沿第一直线连接段的延伸方向进行错位设置，可以调整多条第一直线连接段与补偿极板在衬底的正投影的交叠面积，从而实现对多条栅连接走线的差异化补偿。
图11A为图1中区域S2的局部放大示意图。图11B为图11A中多条弧形连接段的示意图。图11C为图11A中补偿极板的示意图。在本示例中，多条第一走线的弧线走线段可以包括：多条栅连接走线33的弧形连接段333。
在一些示例中，如图11A至图11C所示，多条栅连接走线33的弧形连接段333可以沿着孔区B5的弧形边缘延伸。多条弧形连接段333可以位于同一导电层(比如，第一栅金属层或第二栅金属层)，或者可以交替排布在第一栅金属层和第二栅金属层。例如，位于第一栅金属层的栅连接走线33a的弧形连接段333a可以沿孔区B5的边缘延伸，位于第二栅金属层的栅连接走线33b的弧形连接段333b可以沿孔区B5的边缘延伸。多条栅连接走线33a的弧形连接段333a和多条栅连接走线33b的弧形连接段333b可以沿远离孔区B5的方向交替排布。弧形连接段333a和333b在衬底的正投影可以没有交叠。弧形连接段333a和333b的线宽可以相同。例如，弧形连接段333a或333b可以为以孔区B5的中心为圆心的弧线段。
在一些示例中，补偿极板36可以包括：多个第二镂空部42，多个第二镂空部42可以沿着弧形连接段333a和33b的延伸方向排布。例如，多个第二镂空部42可以沿着弧形连接段333a和333b的延伸方向排布为一行，多行第二镂空部可以沿着远离孔区B5的方向排布。靠近孔区B5的一行第二镂空部内相邻第二镂空部42的间距可以小于远离孔区B5的一行第二镂空部内相邻第二镂空部42的间距。例如，多个第二镂空部42可以按照以孔区A2的中心呈放射状方式排布。
在一些示例中，第二镂空部42在衬底的正投影可以为矩形。第二镂空部42可以具有平行设置的第三边缘421和422、以及平行设置的第四边缘423和424。第三边缘421和422的延伸方向可以平行于弧形连接段333a和333b的延伸方向，第四边缘423和424的延伸方向可以垂直于弧形连接段333a和333b的延伸方向。第三边缘421(或422)在衬底的正投影可以位于一条弧形连接段333a(或333b)在衬底的正投影范围内。第四边缘423(或424)在衬底的正投影可以与多条弧形连接段(例如三条或四条弧形连接段)在衬底的正投影存在交叠。第四边缘423(或424)的长度可以大于至少两条弧形连接段的线宽。多个第二镂空部42的排布方向可以跟随弧形连接段的圆弧角度变化而变化，以保 证第二镂空部42的第三边缘在衬底的正投影可以位于弧形连接段在衬底的正投影范围内。
本示例通过设置沿弧形连接段的延伸方向排布的多个第二镂空部，且多条弧形连接段在衬底的正投影可以覆盖多个第二镂空部的第三边缘在衬底的正投影，可以改善补偿极板的边界位置(例如第二镂空部的边缘位置)对上方无机膜层和导电层的影响，可以防止上方导电层(例如第一源漏金属层)的材料残留和走线不良。关于本示例的补偿极板的其余说明可以参照前述实施例的描述，故于此不再赘述。
图12为本公开至少一实施例的绕线区的补偿极板示意图。图12中绕线区B5内的虚线将绕线区B5划分为靠近孔区A2的第一区域和远离孔区A2的第二区域，其中，第一区域为绕线区B5内的栅连接走线33的弧形连接段的设置区域，第二区域为栅连接走线33的第一直线连接段和第二直线连接段的设置区域。
在一些示例中，如图12所示，孔区A2可以具有沿第一方向X延伸的第一中心线O1、沿第二方向Y延伸的第二中心线O2。第一中心线O1和第二中心线O2可以将绕线区B5划分为四个区域(比如称为左上区域、右上区域、左下区域和右下区域)。多条栅连接走线可以包括：位于第一中心线O1在第二方向Y一侧的第一组栅连接走线、以及位于第一中心线O1在第二方向Y的反方向一侧的第二组栅连接走线。例如，第一组栅连接走线和第二组栅连接走线可以关于第一中心线O1对称设置。本示例中，从孔区A2的一侧绕过孔区A2的第一组第一走线可以包括第一组栅连接走线，从孔区A2的另一侧绕过孔区A2的第二组第一走线可以包括第二组栅连接走线。
在一些示例中，如图12所示，位于绕线区B5的补偿极板36可以具有位于左上区域的第三镂空部43a和位于右下区域的第三镂空部43b。第三镂空部43a在衬底的正投影与第一组栅连接走线在衬底的正投影可以存在交叠，第三镂空部43b在衬底的正投影与第二组栅连接走线在衬底的正投影可以存在交叠。
在一些示例中，第三镂空部43a和43b均与靠近孔区A2设置多条栅极连接走线在衬底的正投影存在交叠，与远离区域B5设置的多条栅极连接走线在衬底的正投影可以没有交叠。靠近孔区A2设置的多条栅连接走线的长度可以大于远离孔区A2设置的多条栅连接走线的长度。本示例通过在靠近孔区A2设置第三镂空部，可以减少对长度较大的栅连接走线的电容补偿，增加对长度较短的栅连接走线的电容补偿，以便于使得多条栅连接走线在补偿之后的负载保持相同。
在一些示例中，第三镂空部43a和43b可以均为沿孔区A2边缘延伸的弧形镂空槽。以第三镂空部43a的结构为例进行说明。第三镂空部43a可以具有第五边缘431、第六边缘432、第七边缘433和第八边缘434。第五边缘431、第七边缘433、第六边缘432和第八边缘433可以依次连接。第五边缘431和第六边缘432的延伸方向可以相同，例如可以沿多条弧形连接段的延伸方向延伸。第五边缘431和第六边缘432在衬底的正投影可以与多条弧形连接段在衬底的正投影至少部分交叠。例如，一条弧形连接段在衬底的正投影可以覆盖第五边缘431(或第六边缘432)在衬底的正投影。第七边缘433和第八边缘434的延伸方向可以垂直于弧形连接段的延伸方向。例如，第七边缘433或第八边缘434的延伸线可以经过第一中心线O1和第二中心线O2的交点。然而，本实施例对此并不限定。
图13A为本公开至少一实施例的第三镂空部的边缘局部示意图。在一些示例中，第三镂空部的至少部分边缘在衬底的正投影可以为台阶形状。例如，第三镂空部43a的第七边缘433和第八边缘434在衬底的正投影可以为台阶形状。台阶形状可以包括：依次连接的多个台阶结构430。每个台阶结构430可以包括相互连接的第一台阶段430-1和第二台阶段430-2。第一台阶段430-1和第二台阶段430-2为延伸方向不同的直线段。例如，第 一台阶段430-1的延伸方向可以垂直于第二台阶段430-2的延伸方向。
在一些示例中，第一台阶段430-1的延伸方向可以平行于栅连接走线的局部线段(例如直线连接段或弧形连接段)的延伸方向。第一台阶段430-1在衬底的正投影可以位于一条栅连接走线33(例如栅连接走线33的弧形连接段333)在衬底的正投影范围内。第二台阶段430-2在衬底的正投影可以与至少两条相邻栅连接走线33在衬底的正投影存在交叠。例如，相邻台阶结构的第一台阶段430-1在衬底的正投影可以位于不同的两条栅连接走线在衬底的正投影范围内。然而，本实施例对此并不限定。本示例的第三镂空部的边缘设置方式，不仅可以有利于补偿极板对不同栅连接走线实现差异化补偿，而且可以改善补偿极板的边界位置(例如第三镂空部的边缘位置)对上方无机膜层和导电层(例如，第一源漏金属层)的影响，可以防止导电层的材料残留和走线不良。
图13B为本公开至少一实施例的第三镂空部的边缘的另一局部示意图。在一些示例中，第三镂空部的至少部分边缘在衬底的正投影可以为台阶形状。例如，第三镂空部43a的第七边缘433和第八边缘434在衬底的正投影可以为台阶形状。台阶形状可以包括：依次连接的多个台阶结构430。相邻台阶结构430之间可以通过台阶连接段430-3连接。台阶连接段430-3可以为弧线段。每个台阶结构430可以包括相互连接的第一台阶段430-1和第二台阶段430-2。第一台阶段430-1和第二台阶段430-2为延伸方向不同的直线段。例如，第一台阶段430-1的延伸方向可以垂直于第二台阶段430-2的延伸方向。本示例的第三镂空部的至少部分边缘可以为圆弧渐变边界。本示例的第三镂空部的边缘设置方式，不仅可以有利于补偿极板对不同栅连接走线实现差异化补偿，而且可以改善补偿极板的边界位置(例如第三镂空部的边缘位置)对上方无机膜层和导电层(例如，第一源漏金属层)的影响，可以防止导电层的材料残留和走线不良。关于本示例的边缘的其他说明可以参照前述实施例的描述，故于此不再赘述。
图14为本公开至少一实施例的绕线区的补偿极板的另一示意图。在一些示例中，如图14所示，位于绕线区B5的补偿极板36可以具有位于左上区域的第三镂空部43a和43c、以及位于右下区域的第三镂空部43b和43d。第三镂空部43a和43c在衬底的正投影与第一组栅连接走线在衬底的正投影存在交叠，第三镂空部43b和43d在衬底的正投影与第二组栅连接走线在衬底的正投影存在交叠。
在一些示例中，如图14所示，第三镂空部43a、43b、43c和43d可以均为沿孔区A2边缘延伸的弧形镂空槽。第三镂空部43c可以位于第三镂空部43a远离孔区A2的一侧，第三镂空部43d可以位于第三镂空部43b远离孔区A2的一侧。第三镂空部43c的长度可以小于第三镂空部43a的长度，第三镂空部43d的长度可以小于第三镂空部43b的长度。
本示例的第三镂空部的边缘设置方式，不仅可以有利于补偿极板对不同栅连接走线实现差异化补偿，而且可以改善补偿极板的边界位置(例如第三镂空部的边缘位置)对上方无机膜层和导电层(例如，第一源漏金属层)的影响，可以防止导电层的材料残留和走线不良。关于本示例的第三镂空部的其余结构可以参照前述实施例的描述，故于此不再赘述。
图15为本公开至少一实施例的绕线区的补偿极板的另一示意图。在一些示例中，如图15所示，位于绕线区B5的补偿极板36可以具有位于左上区域的第三镂空部43a和43c、以及位于左下区域的第三镂空部43e和43f。第三镂空部43a和43c在衬底的正投影与第一组栅连接走线在衬底的正投影存在交叠，第三镂空部43e和43f在衬底的正投影与第二组栅连接走线在衬底的正投影存在交叠。
在一些示例中，如图15所示，第三镂空部43a、43c、43e和43f可以均为沿孔区A2边缘延伸的弧形镂空槽。第三镂空部43c可以位于第三镂空部43a远离孔区A2的一侧， 第三镂空部43f可以位于第三镂空部43e远离孔区A2的一侧。第三镂空部43c的长度可以小于第三镂空部43a的长度，第三镂空部43f的长度可以小于第三镂空部43e的长度。例如，第三镂空部43a和43e可以关于第一中心线O1大致对称，第三镂空部43c和43f可以关于第一中心线O1大致对称。然而，本实施例对此并不限定。
本示例的第三镂空部的边缘设置方式，不仅可以有利于补偿极板对不同栅连接走线实现差异化补偿，而且可以改善补偿极板的边界位置(例如第三镂空部的边缘位置)对上方无机膜层和导电层(例如，第一源漏金属层)的影响，可以防止导电层的材料残留和走线不良。关于本示例的第三镂空部的其余结构可以参照前述实施例的描述，故于此不再赘述。
图16为本公开至少一实施例的绕线区的补偿极板的另一示意图。在一些示例中，如图16所示，位于绕线区B5的补偿极板36可以具有位于左上区域的第三镂空部43a和43c、位于左下区域的第三镂空部43e和43f、位于右上区域的第三镂空部43g和43h、位于右下区域的第三镂空部43b和43d。第三镂空部43a、43c、43g和43h在衬底的正投影与第一组栅连接走线在衬底的正投影存在交叠，第三镂空部43e、43f、43b和43d在衬底的正投影与第二组栅连接走线在衬底的正投影存在交叠。
在一些示例中，如图16所示，第三镂空部43a、43b、43c、43d、43e、43f、43g和43h可以均为沿孔区A2边缘延伸的弧形镂空槽。第三镂空部43c可以位于第三镂空部43a远离孔区A2的一侧，第三镂空部43f可以位于第三镂空部43e远离孔区A2的一侧，第三镂空部43d可以位于第三镂空部43b远离孔区A2的一侧，第三镂空部43h可以位于第三镂空部43g远离孔区B5的一侧。例如，第三镂空部43a和43e可以关于第一中心线O1大致对称，第三镂空部43g和43a可以关于第二中心线O2大致对称。然而，本实施例对此并不限定。
本示例的第三镂空部的边缘设置方式，不仅可以有利于补偿极板对不同栅连接走线实现差异化补偿，而且可以改善补偿极板的边界位置(例如第三镂空部的边缘位置)对上方无机膜层和导电层(例如，第一源漏金属层)的影响，可以防止导电层的材料残留和走线不良。关于本示例的第三镂空部的其余结构可以参照前述实施例的描述，故于此不再赘述。
在另一些示例中，第三镂空部43a、43g、43b和43e可以连通形成环形镂空槽，以减少对靠近孔区A2的多条栅连接走线的负载补偿。在另一些示例中，第三镂空部43c、43h、43d和43f可以连通形成环形镂空槽，以减少对靠近孔区A2的多条栅连接走线的负载补偿。
图17为本公开至少一实施例的绕线区的补偿极板的另一示意图。在一些示例中，如图17所示，位于绕线区B5的补偿极板36可以具有位于左上区域的第三镂空部43i、位于右下区域的第三镂空部43j。第三镂空部43i和43j可以与补偿极板36靠近孔区A2的边缘连通。第三镂空部43i和43j的边缘可以为补偿极板36的边缘的一部分。例如，第三镂空部43i和43j没有独立设置在补偿极板36的内部，而是设置在补偿极板36靠近孔区A2的边界位置，使得补偿极板36的边界位置可以形成向远离孔区A2一侧凹陷的凹口。如此一来，补偿极板与靠近孔区设置的栅连接走线在衬底的正投影的交叠面积，可以小于补偿极板与远离孔区设置的栅连接走线在衬底的正投影的交叠面积，从而增加对远离孔区设置的栅连接走线的负载补偿。
在一些示例中，补偿极板靠近孔区的边缘形状可以采用如图13A所示的台阶状边界，或者，如图13B所示的圆弧渐变边界。通过补偿极板的边缘设置对不同栅连接走线实现差异化补偿，而且可以改善补偿极板的边界位置(例如第三镂空部的边缘位置)对上方无机膜层和导电层(例如，第一源漏金属层)的影响，可以防止导电层的材料残留和走线不 良。关于本示例的补偿极板的其余结构可以参照前述实施例的描述，故于此不再赘述。
图18为本公开至少一实施例的绕线区的栅连接走线的另一示意图。在一些示例中，如图18所示，绕线区B5的栅连接走线33可以包括：第一直线连接段331、第二直线连接段332以及折线连接段334。折线连接段334可以连接在第一直线连接段331和第二直线连接段332之间。折线连接段334可以包括沿不同延伸方向延伸的多条子直线段连接形成。关于本示例的栅连接走线的其他说明可以参照前述实施例的描述，故于此不再赘述。
图19为本公开至少一实施例的栅连接走线的折线连接段与补偿极板的第一镂空部的位置示意图。在一些示例中，如图19所示，本示例的多条第一走线的多条直线走线段可以包括：延伸方向相同的多条第一直线连接段331、延伸方向相同的多条第二直线连接段332、多条折线连接段334的延伸方向相同的多条子直线段。补偿极板的镂空结构可以包括多个第一镂空部41。多个第一镂空部41可以沿多条折线连接段334的多条子直线段的延伸方向阵列排布。第一镂空部41的与折线连接段334的子直线段的延伸方向相同的边缘(例如第一边缘411和412)在衬底的正投影可以位于对应的子直线段在衬底的正投影范围内，第一镂空部41的与子直线段的延伸方向垂直的边缘(例如第二边缘413和414)在衬底的正投影可以与多条子直线段在衬底的正投影存在交叠。关于本示例的补偿极板的其余说明可以参照前述实施例的描述，故于此不再赘述。
图20为本公开至少一实施例的栅连接走线的折线连接段与补偿极板的第一镂空部的另一位置示意图。在一些示例中，如图20所示，补偿极板的镂空结构可以包括多个第一镂空部41。多个第一镂空部41可以沿着经过孔区的中心点的放射线的方向进行发散排布。例如，沿着远离孔区A2的方向排布的多个第一镂空部41的中心线可以重合并垂直于多条折线连接段334的子直线段的延伸方向。关于本示例的补偿极板的其余说明可以参照前述实施例的描述，故于此不再赘述。
在一些示例中，在位于绕线区的第一走线仅具有直线走线段，则补偿极板的镂空结构可以包括多个第一镂空部，直线走线段在衬底的正投影可以覆盖第一镂空部的部分边缘；在位于绕线区的第一走线具有直线走线段和弧线走线段，则补偿极板的镂空结构可以包括多个第一镂空部和多个第二镂空部，或者，镂空结构可以包括多个第一镂空部和至少一个第三镂空部；其中，直线走线段在衬底的正投影可以覆盖第一镂空部的部分边缘，弧线走线段在衬底的正投影可以覆盖第二镂空部或第三镂空部的部分边缘。本实施例对此并不限定。
在另一些示例中，绕线区可以设置多个补偿极板。例如，按照第一中心线O1和第二中心线O2可以将绕线区B5为四个区域，所述四个区域中的每个区域可以设置一个补偿极板，相邻区域内的补偿极板可以独立设置。或者，可以在按照第一中心线(或第二中心线)划分的两个区域中的每个区域内独立设置一个补偿极板。每个补偿极板的镂空结构可以如前述实施例的描述，故于此不再赘述。
在另一些示例中，显示基板的膜层结构可以如图3A所示，补偿极板可以位于第三栅金属层，位于第三栅金属层的补偿极板通过与位于第一栅金属层和第二栅金属层的栅连接走线在衬底的正投影交叠设置，来对不同栅连接走线所连接的第一类栅线进行负载补偿。或者，位于第三栅金属层的补偿极板通过与位于第一源漏金属层和第二源漏金属层的数据连接走线在衬底的正投影交叠设置，来对不同数据连接走线所连接的第一类数据线进行负载补偿。
在另一些示例中，周边区域还可以包括：连接在第一周边区域和第二周边区域之间的第一拐角区域(例如还可以称为左下拐角区域)、连接在第一周边区域和第三周边区域之 间的第二拐角区域(例如还可以称为右下拐角区域)。第一拐角区域和第二拐角区域内位于底部遮光金属层的走线在衬底的正投影与该区域内位于第一栅金属层和第二栅金属层的走线在衬底的正投影可以没有交叠。换言之，在第一拐角区域和第二拐角区域内，底部遮光金属层的走线可以避开第一栅金属层和第二栅金属层的走线设置，以避免由于底部遮光金属层的边界引发上方无机层不平坦，带来导电层的材料残留和走线不良等情况。
图21为本公开至少一实施例的显示装置的示意图。在一些示例中，如图21所示，显示面板910可以为OLED显示面板。显示装置91可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (18)

  1. 一种显示基板，包括：
    衬底，包括显示区域和位于所述显示区域至少一侧的周边区域；
    多个子像素，设置在所述衬底的一侧且位于所述显示区域；
    多条第一走线，位于所述周边区域，所述多条第一走线与所述多个子像素电连接；
    补偿极板，位于所述周边区域，所述补偿极板与所述多条第一走线之间设置有至少一个绝缘层；所述补偿极板在所述衬底的正投影与所述多条第一走线在所述衬底的正投影部分交叠；所述补偿极板具有镂空结构，所述镂空结构在所述衬底的正投影与所述多条第一走线中的至少一条第一走线在所述衬底的正投影部分交叠。
  2. 根据权利要求1所述的显示基板，其中，所述衬底还包括：孔区，所述周边区域包括位于所述孔区和所述显示区域之间的绕线区；所述多条第一走线和所述补偿极板均位于所述绕线区。
  3. 根据权利要求1或2所述的显示基板，其中，所述镂空结构具有至少一条第一镂空边缘，所述至少一条第一镂空边缘的延伸方向平行于所述多条第一走线中的至少一条第一走线的延伸方向，所述至少一条第一镂空边缘在所述衬底的正投影位于所述至少一条第一走线在所述衬底的正投影范围内。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述补偿极板位于所述多条第一走线靠近所述衬底的一侧。
  5. 根据权利要求4所述的显示基板，其中，所述多条第一走线交替设置在第一栅金属层和第二栅金属层，所述第二栅金属层位于所述第一栅金属层远离所述衬底的一侧，所述多条第一走线中的相邻第一走线在所述衬底的正投影没有交叠；
    所述补偿极板位于底部遮光金属层，所述底部遮光金属层位于所述第一栅金属层靠近所述衬底的一侧。
  6. 根据权利要求1至5中任一项所述的显示基板，其中，所述多条第一走线包括：沿同一方向延伸的多条直线走线段；
    所述补偿极板的镂空结构包括：多个第一镂空部；
    所述多个第一镂空部中的至少一个第一镂空部具有第一边缘，所述第一边缘的延伸方向平行于所述多条直线走线段的延伸方向；单个第一镂空部的一条第一边缘在所述衬底的正投影位于一条直线走线段在所述衬底的正投影范围内。
  7. 根据权利要求6所述的显示基板，其中，所述至少一个第一镂空部在所述衬底的正投影为矩形，所述至少一个第一镂空部还具有第二边缘，所述第二边缘的延伸方向垂直于所述第一边缘的延伸方向，所述第二边缘在所述衬底的正投影与所述多条直线走线段中的至少两条直线走线段在所述衬底的正投影部分交叠。
  8. 根据权利要求6所述的显示基板，其中，所述多个第一镂空部沿着所述多条直线走线段的延伸方向阵列排布，且在所述多条直线走线段的延伸方向上，相邻第一镂空部对齐设置。
  9. 根据权利要求6所述的显示基板，其中，所述多个第一镂空部沿着所述多条直线走线段的延伸方向阵列排布，且在所述多条直线走线段的延伸方向上，至少两个相邻第一镂空部错位设置。
  10. 根据权利要求9所述的显示基板，其中，沿着所述多条直线走线段的延伸方向排布的多个第一镂空部为一行第一镂空部，所述一行第一镂空部包括：交替设置的第一组镂空部和第二组镂空部，所述第一组镂空部内的多个第一镂空部对齐设置，所述第二组镂空部内的多个第一镂空部对齐设置，所述第一组镂空部和所述第二组镂空部错位设置。
  11. 根据权利要求9所述的显示基板，其中，沿着所述多条直线走线段的延伸方向排布的多个第一镂空部为一行第一镂空部，所述一行第一镂空部包括：交替设置的第三组镂空部和第四组镂空部，所述第三组镂空部内的多个第一镂空部错位设置，所述第四组镂空部内的多个第一镂空部错位设置；所述第三组镂空部内的至少一个第一镂空部与所述第四组镂空部内的至少一个第一镂空部对齐设置。
  12. 根据权利要求9所述的显示基板，其中，沿着所述多条直线走线段的延伸方向排布的多个第一镂空部为一行第一镂空部，所述一行第一镂空部包括：依次设置的多个第五组镂空部，所述第五组镂空部内的多个第一镂空部错位设置，相邻第五组镂空部对齐设置。
  13. 根据权利要求1至5中任一项所述的显示基板，其中，所述多条第一走线包括：延伸方向相同的多条弧线走线段；
    所述补偿极板的镂空结构包括：多个第二镂空部；所述多个第二镂空部沿着所述多条弧线走线段的延伸方向排布；
    所述多个第二镂空部中的至少一个第二镂空部具有第三边缘，所述第三边缘的延伸方向平行于所述多条弧线走线段的延伸方向，单个第二镂空部的所述第三边缘在所述衬底的正投影位于一条弧线走线段在所述衬底的正投影范围内。
  14. 根据权利要求2所述的显示基板，其中，所述补偿极板的镂空结构包括：至少一个第三镂空部；所述至少一个第三镂空部沿着所述孔区的至少部分边缘延伸；
    与所述至少一个第三镂空部在所述衬底的正投影存在交叠的第一走线的长度，大于没有与所述至少一个第三镂空部在所述衬底的正投影存在交叠的第一走线的长度。
  15. 根据权利要求14所述的显示基板，其中，所述多条第一走线包括：从所述孔区的一侧绕过所述孔区的第一组第一走线、以及从所述孔区的另一侧绕过所述孔区的第二组第一走线；
    所述补偿极板的镂空结构包括：与所述第一组第一走线在所述衬底的正投影存在交叠的至少一个第三镂空部、以及与所述第二组第一走线在所述衬底的正投影存在交叠的至少一个第三镂空部。
  16. 根据权利要求14所述的显示基板，其中，所述至少一个第三镂空部的至少部分边缘在所述衬底的正投影为台阶形状；所述台阶形状包括：依次连接的多个台阶结构，每个台阶结构包括相互连接的第一台阶段和第二台阶段；所述第一台阶段和所述第二台阶段为延伸方向不同的直线段；
    每个台阶结构的所述第一台阶段在所述衬底的正投影位于一条第一走线在所述衬底的正投影范围内，所述第二台阶段在所述衬底的正投影与至少两条相邻第一走线在所述衬底的正投影存在交叠。
  17. 根据权利要求16所述显示基板，其中，所述台阶形状还包括：连接相邻台阶结构的台阶连接段，所述台阶连接段为弧线段。
  18. 一种显示装置，包括如权利要求1至17中任一项所述的显示基板。
PCT/CN2024/084315 2024-03-28 2024-03-28 显示基板及显示装置 Pending WO2025199848A1 (zh)

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JP2011017816A (ja) * 2009-07-08 2011-01-27 Sharp Corp データ線駆動回路および表示装置
CN111477672A (zh) * 2020-05-20 2020-07-31 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示面板和显示装置
CN113376911A (zh) * 2018-12-03 2021-09-10 厦门天马微电子有限公司 显示面板和显示装置
CN113383381A (zh) * 2019-04-04 2021-09-10 深圳市柔宇科技股份有限公司 显示面板和显示装置
WO2021243875A1 (zh) * 2020-06-05 2021-12-09 京东方科技集团股份有限公司 显示基板以及显示装置
CN115880998A (zh) * 2022-12-12 2023-03-31 武汉华星光电半导体显示技术有限公司 显示面板和显示装置

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JP2011017816A (ja) * 2009-07-08 2011-01-27 Sharp Corp データ線駆動回路および表示装置
CN113376911A (zh) * 2018-12-03 2021-09-10 厦门天马微电子有限公司 显示面板和显示装置
CN113383381A (zh) * 2019-04-04 2021-09-10 深圳市柔宇科技股份有限公司 显示面板和显示装置
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