Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

Definitions

• This disclosure relates to a Doherty amplifier.
• Patent Document 1 discloses a Doherty amplifier including a first output circuit that transmits a first signal output from a carrier amplifier and a second output circuit that transmits a second signal output from a peak amplifier.
• the second output circuit includes a high-pass circuit to cancel the influence of the parasitic capacitance of the peak amplifier.
• This disclosure has been made to solve the above-mentioned problems, and aims to obtain a Doherty amplifier that can achieve wider bandwidth characteristics than the Doherty amplifier disclosed in Patent Document 1.
• the Doherty amplifier disclosed herein includes a first output circuit having a first transmission line for transmitting a first signal output from a carrier amplifier and outputting the first signal after transmission via the first transmission line to a load, and a second output circuit having a second transmission line for transmitting a second signal output from a peak amplifier and outputting the second signal after transmission via the second transmission line to the load.
• the first transmission line includes a first T-type circuit having one end connected to the output side of the carrier amplifier and the other end connected to the load, and a first capacitor having one end connected to the other end of the first T-type circuit and the other end grounded.
• the second transmission line includes a second T-type circuit having one end connected to the output side of the peak amplifier, a second capacitor having one end connected to the other end of the second T-type circuit and the other end connected to the load, and a third capacitor having one end connected to the other end of the second T-type circuit and the other end grounded.
• FIG. 1 is a configuration diagram showing a Doherty amplifier according to a first embodiment.
• 2 is a configuration diagram showing the inside of a first output circuit 6 and a second output circuit 7.
• FIG. 2A and 2B are circuit diagrams showing a first output circuit 6 and a second output circuit 7, respectively.
• 3A and 3B are circuit diagrams showing a first output circuit 6 and a second output circuit 7 to which parasitic capacitances C s1 , C s2 , etc. are added.
• FIG. 1 is a circuit diagram showing a circuit in which the characteristic impedances Z 1 , Z 2 , and Z 3 are replaced by lumped parameter networks.
• FIG. 1 is a circuit diagram showing a circuit in which the characteristic impedances Z 1 , Z 2 , and Z 3 are replaced by lumped parameter networks.
• FIG. 10 is a circuit diagram showing that the first output circuit 6 and the second output circuit 7 are realized by two T-type matching circuits and lumped constant networks C m , C 3 , and C a .
• FIG. 10 is an explanatory diagram showing a simulation result of mismatch on the first transmission line side during saturation.
• FIG. 10 is an explanatory diagram showing a simulation result of mismatch on the second transmission line side during saturation.
• FIG. 10 is an explanatory diagram showing a simulation result of mismatch on the first transmission line side during backoff.
• FIG. 10 is an explanatory diagram showing simulation results of saturated output power of a Doherty amplifier.
• FIG. 10 is an explanatory diagram showing a simulation result of the saturation efficiency of the Doherty amplifier.
• FIG. 10 is an explanatory diagram showing a simulation result of the saturation efficiency of the Doherty amplifier.
• 10 is an explanatory diagram showing a simulation result of the back-off efficiency of the Doherty amplifier.
• 10 is an explanatory diagram showing the correspondence relationship between the capacitance C3 of the second capacitor 22, the characteristic impedance Z3 , and the phase ⁇ 3 .
• FIG. FIG. 10 is an explanatory diagram showing a simulation result of mismatch on the first transmission line side during saturation.
• FIG. 10 is an explanatory diagram showing a simulation result of mismatch on the second transmission line side during saturation.
• FIG. 10 is an explanatory diagram showing a simulation result of loss in a Doherty amplifier when saturated.
• FIG. 10 is an explanatory diagram showing a simulation result of mismatch on the first transmission line side during backoff.
• FIG. 10 is an explanatory diagram showing a simulation result of loss in a Doherty amplifier during backoff.
• FIG. 10 is an explanatory diagram showing simulation results of saturated output power of a Doherty amplifier.
• FIG. 10 is an explanatory diagram showing a simulation result of the saturation efficiency of the Doherty amplifier.
• FIG. 10 is an explanatory diagram showing a simulation result of the back-off efficiency of the Doherty amplifier.
• FIG. 1 is a configuration diagram showing a Doherty amplifier according to a first embodiment.
• the Doherty amplifier shown in FIG. 1 includes a distributor 1, a first input circuit 2, a second input circuit 3, a carrier amplifier 4, a peak amplifier 5, a first output circuit 6, a second output circuit 7, and a combining point 8.
• the divider 1 divides the power of an input signal to be amplified.
• the signal distributed to the carrier amplifier 4 side will be referred to as a first signal
• the signal distributed to the peak amplifier 5 side will be referred to as a second signal.
• the distributor 1 outputs a first signal to a first input circuit 2 and outputs a second signal to a second input circuit 3 .
• the first input circuit 2 delays the first signal output from the distributor 1 and outputs the delayed first signal to the carrier amplifier 4 .
• the second input circuit 3 delays the second signal output from the distributor 1 and outputs the delayed second signal to the peak amplifier 5 .
• the carrier amplifier 4 includes an input matching circuit 4a and a first transistor 4b.
• the carrier amplifier 4 receives the first signal delayed by the first input circuit 2 as the signal to be amplified.
• the carrier amplifier 4 operates, for example, with a class A bias or a class AB bias, amplifies the first signal delayed by the first input circuit 2, and outputs the amplified first signal to the first output circuit 6.
• the input matching circuit 4a matches the impedance on the input side of the first transistor 4b.
• the first transistor 4b is realized by, for example, a FET (Field Effect Transistor).
• the first transistor 4 b amplifies the first signal delayed by the first input circuit 2 .
• the peak amplifier 5 includes an input matching circuit 5a and a second transistor 5b.
• the peak amplifier 5 receives the second signal delayed by the second input circuit 3 as the signal to be amplified.
• the peak amplifier 5 operates, for example, with a class C bias, amplifies the second signal delayed by the second input circuit 3 , and outputs the amplified second signal to the second output circuit 7 .
• the input matching circuit 5a matches the impedance on the input side of the second transistor 5b.
• the second transistor 5b is realized by, for example, a FET.
• the second transistor 5 b amplifies the second signal delayed by the second input circuit 3 .
• the first output circuit 6 has a first transmission line for transmitting the first signal output from the carrier amplifier 4 .
• the first output circuit 6 outputs the first signal transmitted through the first transmission line to a combining point 8 .
• the second output circuit 7 has a second transmission line for transmitting the second signal output from the peak amplifier 5 .
• the second output circuit 7 outputs the second signal after transmission through the second transmission line to a combining point 8 .
• the output side of the first output circuit 6, the output side of the second output circuit 7, and the input side of the load 9 are connected.
• the load 9 is driven by the signal after amplification by the Doherty amplifier.
• FIG. 2 is a diagram showing the internal configuration of each of the first output circuit 6 and the second output circuit 7.
• the first output circuit 6 includes a first T-type circuit 11 and a first capacitor 12 as a first transmission line.
• the first T-type circuit 11 is, for example, a high-pass circuit, and includes a transmission line 11a, a transmission line 11b, and a transmission line 11c.
• One end of the first T-type circuit 11 is connected to the output side of the carrier amplifier 4 .
• the other end of the first T-type circuit 11 is connected to one end of the first capacitor 12 and the combining point 8 .
• the first T-type circuit 11 blocks the passage of low-frequency signals contained in the first signal output from the carrier amplifier 4 and passes high-frequency signals contained in the first signal.
• One end of the transmission line 11 a is connected to the output side of the carrier amplifier 4 .
• the other end of the transmission line 11a is connected to one end of the transmission line 11b and one end of the transmission line 11c.
• the characteristic impedance of the transmission line 11a is Z A
• the phase of the transmission line 11a is ⁇ A.
• One end of the transmission line 11b is connected to the other end of the transmission line 11a and one end of the transmission line 11c.
• the other end of the transmission line 11 b is connected to one end of the first capacitor 12 and the combining point 8 .
• the characteristic impedance of the transmission line 11b is ZB
• the phase of the transmission line 11b is ⁇ B .
• One end of the transmission line 11c is connected to the other end of the transmission line 11a and one end of the transmission line 11b.
• the other end of the transmission line 11c is grounded.
• the characteristic impedance of the transmission line 11c is ZC
• the phase of the transmission line 11c is ⁇ C .
• One end of the first capacitor 12 is connected to the other end of the transmission line 11 b and the combining point 8 .
• the other end of the first capacitor 12 is grounded.
• the capacitance of the first capacitor 12 is C m .
• the second output circuit 7 includes a second T-type circuit 21, a second capacitor 22, and a third capacitor 23 as a second transmission line.
• the second T-type circuit 21 is, for example, a high-pass circuit, and includes a transmission line 21a, a transmission line 21b, and a transmission line 21c.
• One end of the second T-type circuit 21 is connected to the output side of the peak amplifier 5 .
• the other end of the second T-type circuit 21 is connected to one end of the second capacitor 22 and one end of the third capacitor 23 .
• the second T-type circuit 21 blocks the passage of low-frequency signals contained in the second signal output from the peak amplifier 5 and passes high-frequency signals contained in the second signal.
• One end of the transmission line 21 a is connected to the output side of the peak amplifier 5 .
• the other end of the transmission line 21a is connected to one end of the transmission line 21b and one end of the transmission line 21c.
• the characteristic impedance of the transmission line 21a is ZD
• the phase of the transmission line 21a is ⁇ D .
• One end of the transmission line 21b is connected to the other end of the transmission line 21a and one end of the transmission line 21c.
• the other end of the transmission line 21b is connected to one end of the second capacitor 22 and one end of the third capacitor 23, respectively.
• the characteristic impedance of the transmission line 21b is Z E and the phase of the transmission line 21b is ⁇ E.
• One end of the transmission line 21c is connected to the other end of the transmission line 21a and one end of the transmission line 21b.
• the other end of the transmission line 21c is grounded.
• the characteristic impedance of the transmission line 21c is ZF
• the phase of the transmission line 21c is ⁇ F .
• One end of the second capacitor 22 is connected to the other end of the transmission line 21 b and one end of the third capacitor 23 .
• the other end of the second capacitor 22 is connected to the combining point 8 .
• the second capacitor 22 has a capacitance C3 .
• One end of the third capacitor 23 is connected to the other end of the transmission line 21 b and one end of the second capacitor 22 .
• the other end of the third capacitor 23 is grounded.
• the capacitance of the third capacitor 23 is Ca.
• the equivalent electrical length of the second transmission line is ⁇ 20 degrees
• the difference in phase between the signal to be amplified by the carrier amplifier 4 and the signal to be amplified by the peak amplifier 5 is 90 degrees + 20 degrees.
• the divider 1 divides the power of the input signal.
• the divider 1 outputs a first signal, which is one of the divided signals, to the carrier amplifier 4 side, and outputs a second signal, which is the other of the divided signals, to the peak amplifier 5 side.
• the first input circuit 2 receives the first signal from the distributor 1 , it delays the first signal and outputs the delayed first signal to the carrier amplifier 4 .
• the second input circuit 3 receives the second signal from the distributor 1 , it delays the second signal and outputs the delayed second signal to the peak amplifier 5 .
• the carrier amplifier 4 amplifies the first signal delayed by the first input circuit 2 and outputs the amplified first signal to the first output circuit 6 .
• the peak amplifier 5 amplifies the second signal delayed by the second input circuit 3 and outputs the amplified second signal to the second output circuit 7 .
• the first output circuit 6 transmits the amplified first signal to the combining point 8 .
• the second output circuit 7 receives the amplified second signal from the peak amplifier 5 , it transmits the amplified second signal to the combining point 8 .
• the amplified first signal and the amplified second signal are combined, and the combined signal of the first signal and the second signal is provided to the load 9 .
• the first transistor 4b of the carrier amplifier 4 has a parasitic capacitance Cs1
• the second transistor 5b of the peak amplifier 5 has a parasitic capacitance Cs2 .
• These parasitic capacitances C s1 and C s2 affect the operation of the Doherty amplifier, and as a result, the frequency characteristics of the efficiency during back-off operation or the frequency characteristics of the saturation efficiency may become narrow.
• the first output circuit 6 includes a first T-type circuit 11 and a first capacitor 12
• the second output circuit 7 includes a second T-type circuit 21, a second capacitor 22, and a third capacitor 23.
• the first output circuit 6 is represented by a circuit having a characteristic impedance of Z 1 and a phase of ⁇ 1
• the second output circuit 7 is represented by a circuit having a characteristic impedance of Z 2 and a phase of ⁇ 2
• FIG. 3 is a circuit diagram showing each of the first output circuit 6 and the second output circuit 7.
• ⁇ 1 90 degrees
• ⁇ 2 90 degrees
• ⁇ 3 ⁇ 90 degrees.
• the characteristic impedance Z1 satisfies the following formula (1)
• the ratio of the characteristic impedance Z2 to the characteristic impedance Z3 is expressed as the following formula (2).
• R L is the resistance of the load 9
• R opt is the optimum load of the first transistor 4b
• ⁇ is the optimum load ratio between the first transistor 4b and the second transistor 5b.
• FIG. 4 is a circuit diagram showing each of the first output circuit 6 and the second output circuit 7 to which parasitic capacitances C s1 , C s2 and the like are added.
• FIG. 5 is a circuit diagram showing a circuit in which the characteristic impedances Z 1 , Z 2 , and Z 3 are replaced by lumped parameter networks.
• FIG. 6 is a circuit diagram showing that the first output circuit 6 and the second output circuit 7 are realized by two T-type matching circuits and lumped constant circuits C m , C 3 , and C a .
• FIG. 7 is an explanatory diagram showing the simulation results of mismatch on the first transmission line side during saturation.
• FIG. 8 is an explanatory diagram showing the simulation results of mismatch on the second transmission line side during saturation. 7 and 8, the horizontal axis represents frequency and the vertical axis represents mismatch.
• the first output circuit 6 includes the first T-type circuit 11 and the first capacitor 12
• the second output circuit 7 includes the second T-type circuit 21, the second capacitor 22, and the third capacitor 23.
• the Doherty amplifier shown in FIG. 1 has improved mismatch bandwidth characteristics during saturation compared to the Doherty amplifier of Patent Document 1.
• FIG. 9 is an explanatory diagram showing the simulation results of mismatch on the first transmission line side during backoff.
• the horizontal axis represents frequency and the vertical axis represents mismatch.
• the first output circuit 6 includes the first T-type circuit 11 and the first capacitor 12
• the second output circuit 7 includes the second T-type circuit 21, the second capacitor 22, and the third capacitor 23.
• the Doherty amplifier shown in FIG. 1 has improved mismatch bandwidth characteristics during backoff compared to the Doherty amplifier of Patent Document 1.
• FIG. 10 is an explanatory diagram showing the simulation results of the saturated output power of the Doherty amplifier.
• FIG. 11 is an explanatory diagram showing the simulation results of the saturation efficiency of the Doherty amplifier.
• FIG. 12 is an explanatory diagram showing the simulation results of the back-off efficiency of the Doherty amplifier.
• 10, 11 and 12 the horizontal axis represents frequency.
• the vertical axis represents saturated output power
• in FIG. 11 the vertical axis represents saturation efficiency
• the vertical axis represents back-off efficiency.
• the Doherty amplifier shown in FIG. 1 achieves wider bandwidths of saturated output power, wider bandwidths of saturation efficiency, and wider bandwidths of back-off efficiency compared to the Doherty amplifier of Patent Document 1.
• the Doherty amplifier is configured to include a first output circuit 6 having a first transmission line for transmitting a first signal output from the carrier amplifier 4 and outputting the first signal after transmission via the first transmission line to the load 9, and a second output circuit 7 having a second transmission line for transmitting a second signal output from the peak amplifier 5 and outputting the second signal after transmission via the second transmission line to the load 9.
• the first transmission line includes a first T-type circuit 11 having one end connected to the output side of the carrier amplifier 4 and the other end connected to the load 9, and a first capacitor 12 having one end connected to the other end of the first T-type circuit 11 and the other end grounded.
• the second transmission line includes a second T-type circuit 21 having one end connected to the output side of the peak amplifier 5, a second capacitor 22 having one end connected to the other end of the second T-type circuit 21 and the other end connected to the load 9, and a third capacitor 23 having one end connected to the other end of the second T-type circuit 21 and the other end grounded. Therefore, the Doherty amplifier can achieve wider bandwidth characteristics than the Doherty amplifier disclosed in Patent Document 1.
• Embodiment 2 In the second embodiment, specific circuit conditions for realizing the wideband characteristics of the Doherty amplifier will be described.
• the characteristic impedance Z 3 and the phase ⁇ 3 are determined by selecting one of the capacitances shown in FIG. 14 as the capacitance C 3 of the second capacitor 22. If the capacitance C3 of the second capacitor 22 is selected to be, for example, 81 fF, the characteristic impedance Z3 becomes 100 ⁇ and the phase ⁇ 3 becomes ⁇ 90 degrees.
• FIG. 14 is an explanatory diagram showing the correspondence relationship between the capacitance C3 of the second capacitor 22, the characteristic impedance Z3 , and the phase ⁇ 3 .
• the circuit of the Doherty amplifier is a modified version of the circuit shown in FIGS. 4 to 6 .
• FIG. 15 is an explanatory diagram showing the simulation results of mismatch on the first transmission line side during saturation.
• FIG. 16 is an explanatory diagram showing the simulation results of mismatch on the second transmission line side during saturation.
• FIG. 17 is an explanatory diagram showing the simulation results of the loss in the Doherty amplifier when saturated.
• the horizontal axis represents frequency and the vertical axis represents mismatch.
• the horizontal axis represents frequency and the vertical axis represents loss.
• the bandwidth characteristics of the mismatch at saturation change when the capacitance C3 of the second capacitor 22 is adjusted.
• the loss at saturation changes when the capacitance C3 of the second capacitor 22 is adjusted.
• FIG. 18 is an explanatory diagram showing the simulation results of mismatch on the first transmission line side during backoff.
• FIG. 19 is an explanatory diagram showing the simulation results of the loss of the Doherty amplifier during backoff.
• the horizontal axis represents frequency and the vertical axis represents mismatch.
• the horizontal axis represents frequency and the vertical axis represents loss.
• the bandwidth characteristics of mismatch during back-off change when the capacitance C3 of the second capacitor 22 is adjusted.
• the loss during back-off changes when the capacitance C3 of the second capacitor 22 is adjusted.
• FIG. 20 is an explanatory diagram showing the simulation results of the saturated output power of the Doherty amplifier.
• FIG. 21 is an explanatory diagram showing the simulation results of the saturation efficiency of the Doherty amplifier.
• FIG. 22 is an explanatory diagram showing the simulation results of the back-off efficiency of the Doherty amplifier.
• 20, 21 and 22 the horizontal axis represents frequency.
• the vertical axis represents saturated output power
• in FIG. 21, the vertical axis represents saturation efficiency
• the vertical axis represents back-off efficiency.
• the bandwidth characteristics of the saturated output power, the bandwidth characteristics of the saturation efficiency, and the bandwidth characteristics of the back-off efficiency are all changed by adjusting the capacitance C3 of the second capacitor 22.
• the capacitance C3 of the second capacitor 22 is selected to be 59 fF, the effect of the wideband characteristics is prominent. 21, the efficiency in the high frequency range is most improved when the capacitance C3 is 59 fF.
• C3 ⁇ 59 fF ( ⁇ 3 ⁇ -110°)
• the effect of improving the efficiency in the high frequency range is not obtained, and it can be seen that the bandwidth is not widened.
• the second embodiment describes a Doherty amplifier in which the capacitance C3 of the second capacitor 22 is adjusted.
• the capacitance C3 of the second capacitor 22 is adjusted.
• the same 59 fF may also be used for the capacitance values of the first capacitor 12 and the third capacitor 23.
• This disclosure is suitable for Doherty amplifiers.

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  • 2024-03-21 JP JP2026501394A patent/JPWO2025196988A1/ja active Pending
  • 2024-03-21 WO PCT/JP2024/010882 patent/WO2025196988A1/ja active Pending

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