Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations

Definitions

• This disclosure relates to a semiconductor device (power semiconductor module).
• Patent Document 1 discloses that three electrode lead terminals are stacked with an insulating resin sheet between them to form a five-layer structure, and that positioning pins are inserted into two lamination holes in the five-layer structure to determine the relative positions of the layers.
• Patent Document 2 discloses an insulating sheet having a first main surface and a second main surface; a plate-shaped first terminal provided opposite the first main surface of the insulating sheet and having a first protrusion that protrudes outward from the first main surface of the insulating sheet; and a plate-shaped second terminal provided opposite the second main surface of the insulating sheet and having a second protrusion that protrudes alongside the first protrusion outward from the second main surface of the insulating sheet, with a first opening provided at the position where the first protrusion intersects with the end of the insulating sheet, where the side surface facing the second protrusion is recessed in a direction away from the second protrusion.
• Patent Document 3 discloses that the main terminals are arranged as protruding parts from the sealing resin body so as to cancel out magnetic fluxes generated when a main current flows, and that the main terminals have opposing parts where the plate surfaces of the main terminals are spaced apart and facing each other, and non-opposing parts where the plate surfaces of the main terminals do not face each other.
• Patent Document 4 discloses that when positioning pins are provided in advance in a mold for resin molding and these are inserted in the order of positive bus bar, insulating paper, and negative bus bar for positioning, by making the guide holes in the insulating paper sufficiently small relative to the guide holes in the positive and negative bus bars and providing steps in the pins according to the diameter of each guide hole, it is possible to ensure positioning accuracy.
• Patent document 5 discloses that a laminate structure is used in which an anode conductor, an insulating sheet, and a cathode conductor are arranged, and an insulating cap is arranged between the anode conductor and the insulating sheet, which has a flange portion to ensure creepage distance and a barrier portion to ensure spatial distance, and that only circular holes of the minimum size necessary to allow the anode conductor to pass through the barrier portion of the insulating cap and the cathode conductor to pass through the barrier portion are drilled, thereby making it possible to increase the inductance reduction effect obtained by bringing opposing currents closer together.
• one approach to reducing inductance is to laminate terminals of different potentials so that they face each other closely, with an insulating layer in between.
• aligning the terminals with the insulating layer is not easy, and there are cases where insulation between the terminals cannot be guaranteed.
• the present disclosure aims to provide a semiconductor device that can ensure insulation between terminals when terminals with different potentials are arranged via an insulating layer.
• One aspect of the present disclosure is a semiconductor device comprising: a first terminal; a second terminal having a portion facing the first terminal and a first opening in a portion not facing the first terminal; a main body portion provided between the facing first and second terminals; and an insulating layer having a first protrusion connected to the main body portion and inserted into the first opening.
• the second terminal may have a first flat portion that faces at least a portion of the first terminal, and a first connecting portion that is bent and connected to the first flat portion.
• the first opening may be provided in the first connection portion.
• a portion of the first flat portion faces the first terminal, a first opening is provided in another portion of the first flat portion that does not face the first terminal, and the first convex portion may be bent from the main body portion and inserted into the first opening.
• the second terminal may further include a second connection portion that is bent and connected to the side of the first flat portion opposite to the side to which the first connection portion is connected, and that has a second opening
• the insulating layer may further include a second protrusion that is connected to the main body portion and inserted into the second opening.
• a portion of the first terminal faces the second terminal
• a second opening is provided in another portion of the first terminal that does not face the second terminal
• the insulating layer may further have a second protrusion connected to the main body and inserted into the second opening.
• the first terminal may have a second flat portion that faces at least a portion of the second terminal, and a third connection portion that is bent and connected to the second flat portion.
• a second opening may be provided in the third connection portion.
• a portion of the second flat portion may face the second terminal, a second opening may be provided in another portion of the second flat portion, and the second convex portion may be bent and inserted into the second opening.
• the first convex portion and the second convex portion may be provided in positions facing each other across the main body portion.
• the first convex portion and the second convex portion may be positioned away from each other across the main body portion.
• the first convex portion may be provided with a return portion.
• the tip of the first protrusion may protrude from the first opening and be bent.
• the length of the first convex portion may be equal to or greater than the thickness of the second terminal.
• the device may further include an insulating circuit board having a first terminal and a second terminal provided on its upper surface, a semiconductor chip provided on the upper surface of the insulating circuit board and electrically connected to the first terminal and the second terminal, and a sealing resin that seals the insulating circuit board and the semiconductor chip.
• This disclosure provides a semiconductor device that can ensure insulation between terminals when terminals with different potentials are arranged via an insulating layer.
• FIG. 1 is a side view of a semiconductor device according to a first embodiment
• FIG. 2 is a plan view of components of the semiconductor device according to the first embodiment
• 3 is a cross-sectional view taken along line AA' in FIG. 2.
• 3 is a cross-sectional view taken along line BB' in FIG. 2.
• FIG. 2 is a side view of a component of the semiconductor device according to the first embodiment.
• FIG. 2 is a side view of a component of the semiconductor device according to the first embodiment.
• FIG. 2 is a plan view of components of the semiconductor device according to the first embodiment.
• FIG. 2 is a plan view of components of the semiconductor device according to the first embodiment.
• FIG. 10 is a plan view of components of a semiconductor device according to a second embodiment.
• FIG. 10 is a plan view of components of a semiconductor device according to a third embodiment.
• FIG. 10 is a plan view of components of a semiconductor device according to a fourth embodiment.
• FIG. 10 is a plan view of components of a semiconductor device according to a fourth embodiment.
• FIG. 13 is a cross-sectional view of a component of a semiconductor device according to a fifth embodiment.
• FIG. 13 is a cross-sectional view of a component of a semiconductor device according to a sixth embodiment.
• 12B is a cross-sectional view taken along line BB' in FIG. 12A.
• FIG. 13 is a cross-sectional view of a component of a semiconductor device according to a seventh embodiment.
• FIG. 13 is a plan view of a component of a semiconductor device according to an eighth embodiment.
• FIG. 15 is a cross-sectional view taken along line AA' in FIG. 14.
• 15 is a cross-sectional view taken along line BB' in FIG. 14.
• FIG. 13 is a side view of a component of a semiconductor device according to an eighth embodiment.
• FIG. 13 is a plan view of a component of a semiconductor device according to a ninth embodiment.
• FIG. 23 is a plan view of a component of a semiconductor device according to a tenth embodiment.
• FIG. 23 is a plan view of a component of a semiconductor device according to an eleventh embodiment.
• 21 is a cross-sectional view taken along line BB' in FIG. 20.
• top surface and “bottom surface” may be read as “front surface” and “back surface,” respectively.
• first main surface and “second main surface” of each member are main surfaces that face each other; for example, if the “first main surface” is the top surface, the “second main surface” is the bottom surface.
• first main surface and “second main surface” may be read as “one main surface” and “the other main surface,” respectively.
• the semiconductor device according to the first embodiment may be, for example, a so-called "2-in-1" power semiconductor module that constitutes part of a three-phase bridge circuit and has the functions of two power semiconductor elements.
• FIG. 1 is a side view of the semiconductor device according to the first embodiment.
• the left-right direction in FIG. 1 is defined as the X-axis direction
• the leftward direction in FIG. 1 is defined as the positive X-axis direction.
• the frontward and rearward direction in FIG. 1, which is a direction perpendicular to the X-axis direction, is defined as the Y-axis direction
• the frontward direction in FIG. 1 is defined as the positive Y-axis direction.
• the definitions of directions in FIG. 2 and subsequent figures are the same as those in FIG. 1.
• the semiconductor device includes an insulating circuit board 1, power semiconductor elements (semiconductor chips) 2a and 2b mounted on the upper surface of the insulating circuit board 1, and terminals 3 to 5 and 7 mounted on the upper surface of the insulating circuit board 1 and electrically connected to the semiconductor chips 2a and 2b.
• power semiconductor elements semiconductor chips
• terminals 3 to 5 and 7 mounted on the upper surface of the insulating circuit board 1 and electrically connected to the semiconductor chips 2a and 2b.
• the insulating circuit board 1 may be, for example, a direct copper bonding (DCB) board or an activated metal brazing (AMB) board.
• the insulating circuit board 1 includes an insulating plate 11, conductive plates 12a to 12c provided on the upper surface of the insulating plate 11, and a conductive plate 13 provided on the lower surface of the insulating plate 11.
• the insulating plate 11 is composed of, for example, a resin insulating layer using a polymer material or a ceramic plate mainly composed of aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), boron nitride (BN), or the like.
• the conductive plates 12a to 12c and the conductive plate 13 are composed of, for example, a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy.
• a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy.
• the arrangement positions and number of the conductive plates 12a to 12c are not particularly limited.
• the semiconductor chips 2a and 2b are configured using semiconductor substrates such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ), or diamond (C).
• the semiconductor chips 2a and 2b may be field-effect transistors (FETs) such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), static induction (SI) thyristors, gate turn-off (GTO) thyristors, or the like.
• FETs field-effect transistors
• MOSFETs metal-oxide-semiconductor field-effect transistors
• IGBTs insulated-gate bipolar transistors
• SI static induction
• GTO gate turn-off
• the type, placement position, and number of the semiconductor chips 2a and 2b are not particularly limited. In the semiconductor device according to the first embodiment, a case in which the semiconductor chips 2a and
• the first electrode (drain electrode) (not shown) on the underside of semiconductor chip 2a is joined to the upper surface of conductive plate 12a of insulated circuit board 1 with a bonding material (not shown) such as solder or a sintered material.
• the first electrode (drain electrode) (not shown) on the underside of semiconductor chip 2b is joined to the upper surface of conductive plate 12b of insulated circuit board 1 with a bonding material (not shown) such as solder or a sintered material.
• Each of the terminals 3-5, 7 is made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy.
• Each of the terminals 3-5, 7 has a flat plate shape and a first main surface (top surface) and a second main surface (bottom surface). There are no particular restrictions on the placement position, length, width, or thickness of each of the terminals 3-5, 7. Furthermore, there are no particular restrictions on the position or number of bent portions of each of the terminals 3-5, 7.
• Terminal 7 is hidden behind terminal 3, but is joined to conductive plate 12b of insulated circuit board 1 or to another conductive plate (not shown) at the same potential as conductive plate 12b using a joining material (not shown) such as solder or a sintered material.
• the other end of terminal 7 extends beyond the outer edge of insulated circuit board 1.
• Terminal 7 may, for example, constitute a positive terminal, which is an external connection terminal.
• the terminal 4 is joined to the upper surface of the conductive plate 12a of the insulated circuit board 1 with a joining material (not shown), such as solder or a sintered material.
• the other end of the terminal 4 extends beyond the outer edge of the insulated circuit board 1.
• the terminal 4 may constitute, for example, an output terminal, which is an external connection terminal.
• terminal 5 One end of terminal 5 is joined to the upper surface of conductive plate 12a of insulated circuit board 1 with a joining material (not shown), such as solder or a sintered material.
• the other end of terminal 5 is joined to a second electrode (source electrode) (not shown) on the upper surface of semiconductor chip 2b with a joining material (not shown), such as solder or a sintered material.
• source electrode source electrode
• joining material not shown
• terminals or bonding wires connected to third electrodes (gate electrodes) on the upper surfaces of semiconductor chips 2a and 2b are not shown in the illustration.
• Terminal 3 One end of terminal 3 is joined to a second electrode (source electrode) (not shown) on the upper surface of semiconductor chip 2a with a bonding material (not shown), such as solder or a sintered material.
• the other end of terminal 3 is joined to the upper surface of conductive plate 12c of insulating circuit board 1 with a bonding material (not shown), such as solder or a sintered material, and extends further outward than the outer edge of insulating circuit board 1.
• Terminal 3 may, for example, constitute a negative terminal, which is an external connection terminal.
• terminals 3 and 5 are terminals to which different potentials are applied (different electrode terminals).
• semiconductor chips 2a and 2b are turned on and off, currents flow in opposite directions through terminals 3 and 5, and mutual inductance reduces wiring inductance at the opposing portions of terminals 3 and 5. Because wiring inductance between different electrode terminals within a power semiconductor module affects switching loss, it is important to reduce inductance values. In particular, devices such as SiC and GaN enable high-speed switching, making it necessary to reduce the inductance of power semiconductor modules.
• One effective method for reducing inductance is to closely arrange (laminate) different electrode terminals within a power semiconductor module.
• the insulating layer 6 is composed of, for example, a sheet-like insulating material (insulating sheet).
• the insulating layer 6 can be made of insulating paper or a highly insulating and heat-resistant material such as polyimide or polyamide. Other materials that can be used include epoxy resin and polyphenylene sulfide (PPS) resin.
• the thickness of the insulating layer 6 is, for example, but not limited to, approximately 0.1 mm to 1.5 mm. From the perspective of reducing inductance, the thickness of the insulating layer 6 is preferably approximately 0.1 mm to 1.0 mm, and more preferably approximately 0.1 mm to 0.5 mm. The thickness of the insulating layer 6 corresponds to the opposing distance between terminals 3 and 5. The thinner the insulating layer 6, the smaller the opposing distance between terminals 3 and 5, which reduces wiring inductance.
• sealing resin 8 is provided to seal the insulating circuit board 1 and semiconductor chips 2a, 2b, etc.
• the sealing resin 8 is made of a resin material such as epoxy.
• the sealing resin 8 may be formed by transfer molding without a case.
• the sealing resin 8 may include a resin case and resin filled inside the case by potting.
• the external shape of the sealing resin 8 is not limited to a roughly rectangular parallelepiped shape, and may be any of a variety of three-dimensional shapes.
• Terminals 3 and 7 protrude from a common side surface of the sealing resin 8 and extend in one direction.
• Terminal 4 protrudes from the side surface of the sealing resin 8 opposite the side surface from which terminals 3 and 7 protrude, and extends in the opposite direction to terminals 3 and 7.
• the portions of terminals 3, 4, and 7 protruding from the sealing resin 8 may be provided with bent portions. At least one of terminals 3, 4, and 7 may protrude from the top surface of the sealing resin 8.
• Figure 2 is a plan view of the terminals 3 and insulating layer 6, which are components of the semiconductor device according to the first embodiment.
• Figure 3A is a cross-sectional view of the terminals 3, 5 and insulating layer 6 taken along line A-A' in Figure 2.
• Figure 3B is a cross-sectional view of the terminals 3, 5 and insulating layer 6 taken along line B-B' in Figure 2.
• Figure 4 is a side view of the terminals 3, 5 and insulating layer 6 as viewed in the negative direction of the X-axis.
• Figure 5 is a side view of the terminals 3, 5 and insulating layer 6 as viewed in the positive direction of the X-axis.
• Figures 2 to 5 show the terminal 3 in Figure 1 from one end of the terminal 3 that is bonded to the semiconductor chip 2a to the portion that is bonded to the conductive plate 12c, and omit the portion of the terminal 3 that protrudes from the sealing resin 8 on the other end side.
• the components of the terminal 3 from one end that is bonded to the semiconductor chip 2a to the portion that is bonded to the conductive plate 12c and the components that constitute the external connection terminal that protrudes from the sealing resin 8 may be separate components and electrically connected to each other.
• terminal 3 has a flat portion 31, connection portions 32a to 32c that are bent (folded) downward and connected to flat portion 31, and connection portions 33a and 33b that are bent downward and connected to the flat portion 31 on the side opposite to connection portions 32a to 32c.
• the flat portion 31 has a generally rectangular planar shape, but is not limited to this. A portion of the lower surface of the flat portion 31 faces the upper surface of the terminal 5 via the insulating layer 6.
• connection portions 32a to 32c are spaced apart from each other in the Y-axis direction and extend parallel to the X-axis direction. Just as the underside of the connection portion 32a is bonded to the semiconductor chip 2a shown in FIG. 1, the undersides of the connection portions 32b and 32c may be bonded to a semiconductor chip (not shown).
• An opening 34a is formed between the connection portions 32a and 32b on the underside of the flat portion 31.
• An opening 34b is formed between the connection portions 32a and 32b on the underside of the flat portion 31.
• the openings 34a and 34b have a width W1.
• the semiconductor device according to the first embodiment illustrates a case in which three connection portions 32a to 32c are provided, but the device may have only two connection portions (e.g., connection portions 32a and 32b), or may have four or more connection portions.
• Connection portions 33a and 33b are positioned opposite connection portions 32a and 32b across flat portion 31. Connection portions 33a and 33b are spaced apart from each other in the Y-axis direction and extend parallel to the X-axis direction. The lower surfaces of connection portions 33a and 33b are joined to conductive plate 12c shown in FIG. 1. An opening 35 is formed between connection portions 33a and 32b on the lower side of flat portion 31. Opening 35 has a width W3.
• the semiconductor device according to the first embodiment has two connection portions 33a and 33b, but may have three or more connection portions.
• FIG. 6 is a plan view of terminal 5.
• terminal 5 includes flat portion 51 and connection portions 52a to 52c that are bent downward and connected to flat portion 51.
• flat portion 51 has a generally rectangular planar shape, but is not limited to this.
• the upper surface of flat portion 51 faces the lower surface of flat portion 31 of terminal 3 via insulating layer 6.
• the lower surface of flat portion 51 is bonded to semiconductor chip 2b shown in FIG. 1. Multiple semiconductor chips similar to semiconductor chip 2b may be bonded to the lower surface of flat portion 51.
• connection portions 52a to 52c are spaced apart from one another in the Y-axis direction and extend parallel to the X-axis direction.
• An insulating layer 6 is disposed above the connection portions 52a to 52c.
• the lower surfaces of the connection portions 52a to 52c are bonded to the conductive plate 12a shown in FIG. 1.
• the semiconductor device according to the first embodiment is illustrated as having three connection portions 52a to 52c, but it may also have only one connection portion (e.g., connection portion 52a), only two connection portions (e.g., connection portions 52a and 52b), or four or more connection portions.
• Figure 7 is a plan view of the insulating layer 6.
• the insulating layer 6 comprises a main body portion 61, a protrusion portion 62 connected to the main body portion 61, and a protrusion portion 63 connected to the side of the main body portion 61 opposite to the side to which the protrusion portion 62 is connected. Note that it is sufficient if at least one of the protrusion portion 62 and the protrusion portion 63 is provided; neither the protrusion portion 62 nor the protrusion portion 63 needs to be provided.
• the main body 61 has an approximately rectangular planar shape, but is not limited to this. As shown in Figures 2 to 5, the main body 61 is arranged so as to be sandwiched between the upper surface of the flat portion 51 of the terminal 5 and the lower surface of the flat portion 31 of the terminal 3. The planar size of the main body 61 is larger than the planar sizes of the flat portion 51 of the terminal 5 and the flat portion 31 of the terminal 3. The main body 61 ensures a creepage distance between the terminals 5 and 3.
• Figure 3A illustrates an example in which both ends of the main body 61 in the X-axis direction are in contact with the connection portions 32a, 33a of the terminal 3, but both or either end of the main body 61 in the X-axis direction may be separated from the connection portions 32a, 33a of the terminal 3.
• the convex portion 62 of the insulating layer 6 is located opposite the convex portion 63 across the main body portion 61.
• the convex portion 62 has a length L1 in the X-axis direction and a width W2 in the Y-axis direction.
• the convex portion 63 has a length L2 in the X-axis direction and a width W4 in the Y-axis direction.
• the length L1 of the convex portion 62 may be the same as or different from the length L2 of the convex portion 63.
• the width W2 of the convex portion 62 may be the same as or different from the width W4 of the convex portion 63.
• the protrusion 62 is inserted into the opening 34a of the terminal 3.
• the insulating layer 6 is fixed to the terminal 3, preventing or reducing misalignment between the terminal 3 and the insulating layer 6. If the length L1 of the protrusion 62 is equal to or greater than the thickness T1 of the terminal 3, the insulating layer 6 is less likely to come off the terminal 3. If the length L1 of the protrusion 62 is longer than the thickness T1 of the terminal 3, the tip of the protrusion 62 can be bent to make the insulating layer 6 less likely to come off the terminal 3.
• the length L1 of the protrusion 62 may be less than the thickness T1 of the terminal 3, and the protrusion 62 may be inserted up to a portion of the opening 34a.
• the semiconductor device according to the first embodiment illustrates a case in which the length L1 of the protrusion 62 is longer than the thickness T1 of the terminal 3, and the protrusion 62 protrudes outward beyond the terminal 3 through the opening 34a.
• the width W2 of the protrusion 62 is equal to or smaller than the width W1 of the opening 34a so that it can be inserted into the opening 34a.
• the width W2 of the protrusion 62 is illustrated as being the same as the width W1 of the opening 34a, but the width W2 of the protrusion 62 may also be narrower than the width W1 of the opening 34a.
• the protrusion 63 is inserted into the opening 35 of the terminal 3.
• the insulating layer 6 is fixed to the terminal 3, preventing or reducing misalignment between the terminal 3 and the insulating layer 6. If the length L2 of the protrusion 63 is equal to or greater than the thickness T1 of the terminal 3, the insulating layer 6 is less likely to come off the terminal 3. If the length L2 of the protrusion 63 is longer than the thickness T1 of the terminal 3, the tip of the protrusion 63 can be bent to make the insulating layer 6 less likely to come off the terminal 3.
• the length L2 of the protrusion 63 may be less than the thickness T1 of the terminal 3, and the protrusion 63 may be inserted partially into the opening 35.
• the semiconductor device according to the first embodiment illustrates a case in which the length L2 of the protrusion 63 is longer than the thickness T1 of the terminal 3, and the protrusion 63 protrudes outward beyond the terminal 3 through the opening 35.
• the width W4 of the protrusion 63 is equal to or smaller than the width W3 of the opening 35 so that the protrusion 63 can be inserted into the opening 35.
• the width W4 of the protrusion 63 is illustrated as being the same as the width W3 of the opening 35, but the width W4 of the protrusion 63 may also be narrower than the width W3 of the opening 35.
• a manufacturing method for the semiconductor device according to the first embodiment will be described.
• the semiconductor chips 2a and 2b and the terminals 3 to 5 and 7 are bonded to the upper surface of the insulating circuit board 1 shown in FIG. 1 using a bonding material such as solder or a sintered material.
• a bonding material such as solder or a sintered material.
• an insulating layer 6 is sandwiched between the terminals 3 and 5, the terminals 3 and 5 are closely arranged, and the protrusions 62 and 63 of the insulating layer 6 are inserted into the openings 34a and 35 of the terminal 3 for alignment.
• the insulating circuit board 1, the semiconductor chips 2a and 2b, and the terminals 3 to 5 and 7 are electrically connected using bonding wires (not shown) or the like.
• the insulating circuit board 1 and the semiconductor chips 2a and 2b are encapsulated in a sealing resin 8 by transfer molding or the like. This completes the semiconductor device according to the first embodiment.
• the convex portion 62 of the insulating layer 6 is inserted into the opening 34b of the terminal 3, and the convex portion 63 of the insulating layer 6 is inserted into the opening 35 of the terminal 3.
• Example> an example of the semiconductor device according to the first embodiment will be described along with a first comparative example and a second comparative example.
• the example of the semiconductor device according to the first embodiment was fabricated by soldering a semiconductor chip (rated at 1200 V) onto an insulating circuit board, joining different electrode terminals, etc., and then sealing with resin.
• insulating paper was used as the insulating layer between terminals, the distance between terminals was 0.38 mm, and the inductance ratio between terminals was 0.79.
• the inductance ratio is expressed as a ratio where a distance between terminals of 1 mm is 1.
• the first comparative example primary molding was performed with an insulating layer placed between the different electrode terminals.
• polyphenylene sulfide (PPS) was used as the insulating layer between the terminals, the distance between the terminals was 1.5 mm, and the inductance ratio between the terminals was 1.
• PPS polyphenylene sulfide
• an insulating layer was fixed between the different electrode terminals using positioning pins.
• insulating paper was used as the insulating layer between the terminals, the distance between the terminals was 0.38 mm, and the inductance ratio between the terminals was 0.79.
• Other manufacturing conditions for the second comparative example were the same as those for the example of the semiconductor device according to the first embodiment.
• Partial discharge evaluation was performed after thermal cycling for each of the example, first comparative example, and second comparative example of the semiconductor device according to the first embodiment fabricated as described above.
• the thermal cycle conditions consisted of a cycle of alternating between -40°C and 125°C, with partial discharge evaluation performed every 500 cycles.
• the partial discharge evaluation involved gradually applying a voltage up to 2.5 kV, and if the discharge charge after 60 seconds was 1 pC or less, it was determined that no partial discharge was observed.
• Second Embodiment 8 is a plan view of the terminal 3 and insulating layer 6, which are components of the semiconductor device according to the second embodiment.
• the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 2 in that the protruding portion 62 of the insulating layer 6 is not opposed to the protruding portion 63 across the main body portion 61 but is positioned offset from it.
• the protruding portion 62 is inserted into an opening 34b formed between the connecting portions 32b and 32c of the terminal 3.
• the other configuration of the semiconductor device according to the second embodiment is substantially the same as that of the semiconductor device according to the first embodiment, and therefore a repeated description will be omitted.
• the protrusion 62 of the insulating layer 6 may be positioned offset from the protrusion 63 across the main body 61, rather than facing it.
• the protrusion 62 of the insulating layer 6 is inserted into the opening 34b of the terminal 3, and the protrusion 63 of the insulating layer 6 is inserted into the opening 35 of the terminal 3, thereby fixing the insulating layer 6 to the terminal 3. This facilitates alignment of the terminal 3 and the insulating layer 6, ensuring insulation between the terminals 3 and 5.
• the protrusion 62 of the insulating layer 6 is positioned offset from the protrusion 63 across the main body 61, rather than facing it, and is inserted into the opening 34b of the terminal 3, misalignment between the terminal 3 and the insulating layer 6 can be further reduced.
• (Third embodiment) 9 is a plan view of the terminal 3 and the insulating layer 6, which are components of the semiconductor device according to the third embodiment.
• the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 2 in that a protrusion 62x is further provided in the insulating layer 6 in parallel with the protrusion 62.
• the protrusion 62x is inserted into an opening 34b formed between the connection portions 32b and 32c of the terminal 3.
• the other configuration of the semiconductor device according to the third embodiment is substantially the same as that of the semiconductor device according to the first embodiment, and therefore a duplicated description will be omitted.
• a protrusion 62x may be further provided on the insulating layer 6 in parallel with the protrusion 62.
• the protrusions 62, 62x are inserted into the openings 34a, 34b of the terminal 3, and the protrusion 63 is inserted into the opening 35 of the terminal 3, thereby fixing the insulating layer 6 to the terminal 3.
• the insulating layer 6 is further provided with a protrusion 62x in parallel with the protrusion 62 and is inserted into the opening 34b of the terminal 3, thereby further reducing misalignment between the terminal 3 and the insulating layer 6.
• FIG. 10A is a plan view of an insulating layer 6, which is a component of a semiconductor device according to a fourth embodiment.
• the semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 7 in that return portions 62a, 63a are provided on the protruding portions 62, 63 of the insulating layer 6.
• the width W5 of the return portion 62a is wider than the width W2 of the protruding portion 62.
• the width W6 of the return portion 63a is wider than the width W4 of the protruding portion 63. Note that only one of the return portions 62a, 63a of the protruding portions 62, 63 of the insulating layer 6 may be provided.
• FIG. 10B is a plan view of the terminal 3 and insulating layer 6, which are components of the semiconductor device according to the fourth embodiment.
• the convex portion 62 of the insulating layer 6 is inserted into the opening 34a of the terminal 3.
• the return portion 62a at the tip of the convex portion 62 is located outside the outer edge of the flat portion 31 of the terminal 3.
• the convex portion 63 of the insulating layer 6 is inserted into the opening 35 of the terminal 3.
• the return portion 63a at the tip of the convex portion 63 is located outside the outer edge of the flat portion 31 of the terminal 3.
• the other configuration of the semiconductor device according to the fourth embodiment is substantially the same as that of the semiconductor device according to the first embodiment, so repeated explanations will be omitted.
• the protrusions 62, 63 of the insulating layer 6 may be provided with return portions 62a, 63a.
• the protrusion 62 is inserted into the opening 34a of the terminal 3, and the protrusion 63 is inserted into the opening 35 of the terminal 3, thereby fixing the insulating layer 6 to the terminal 3.
• This makes it easier to align the terminal 3 and the insulating layer 6, and ensures insulation between the terminals 3, 5.
• the protrusions 62, 63 of the insulating layer 6 are provided with return portions 62a, 63a, the insulating layer 6 is less likely to come off the terminal 3.
• FIG. 11 is a cross-sectional view of the terminals 3 and 5 and the insulating layer 6, which are components of the semiconductor device according to the fifth embodiment, corresponding to the cross-sectional position of the semiconductor device according to the first embodiment shown in FIG. 3B.
• the semiconductor device according to the fifth embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 3B in that the lower sides of the openings 34a and 35 formed in the terminal 3 are closed.
• a sidewall 32d is provided below the opening 34a.
• the sidewall 32d is connected between the connecting portions 32a and 32b shown in FIG. 2.
• a sidewall 33c is provided below the opening 35.
• the sidewall 33c is connected between the connecting portions 33a and 33b shown in FIG. 2.
• Other configurations of the semiconductor device according to the fifth embodiment are substantially similar to those of the semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.
• the lower sides of the openings 34a, 35 formed in the terminal 3 may be closed. Even in this case, the insulating layer 6 is fixed to the terminal 3 by inserting the protrusion 62 into the opening 34a of the terminal 3 and the protrusion 63 into the opening 35 of the terminal 3, which makes it easier to align the terminal 3 and the insulating layer 6 and ensures insulation between the terminals 3, 5.
• Sixth Embodiment 12A is a plan view of the terminal 3 and insulating layer 6, which are components of the semiconductor device according to the sixth embodiment.
• the cross section of the terminals 3, 5 and insulating layer 6 taken along line A-A' in FIG. 12A is the same as FIG. 3A.
• FIG. 12B is a cross section of the terminals 3, 5 and insulating layer 6 taken along line B-B' in FIG. 12A.
• the semiconductor device according to the sixth embodiment differs from the semiconductor device according to the first embodiment shown in FIGS. 2 and 3B in that openings 34x, 34y, and 35x that penetrate in the Z-axis direction are provided in the flat portion 31 of the terminal 3.
• a portion of the flat portion 31 of terminal 3 faces the flat portion 51 of terminal 5 via the main body portion 61 of insulating layer 6. Openings 34x, 34y, and 35x are provided in the other portion of the flat portion 31 of terminal 3 that does not face the flat portion 51 of terminal 5.
• the protruding portion 62 of insulating layer 6 is bent upward at a right angle from the main body portion 61 and inserted into opening 34x.
• the protruding portion 63 of insulating layer 6 is bent upward at a right angle from the main body portion 61 and inserted into opening 35x.
• the opening 34y into which the protrusion 62 of the insulating layer 6 is not inserted may not be present.
• the protrusion 62 of the insulating layer 6 may be positioned offset from the protrusion 63 across the main body 61, rather than facing it, and inserted into the opening 34y.
• the other configuration of the semiconductor device according to the sixth embodiment is substantially the same as that of the semiconductor device according to the first embodiment, and therefore a redundant description will be omitted.
• openings 34x, 35x penetrating in the Z-axis direction may be provided in the flat portion 31 of the terminal 3, and the protruding portions 62, 63 of the insulating layer 6 may be bent and inserted into the openings 34x, 35x.
• the insulating layer 6 is fixed to the terminal 3, making it easy to align the terminal 3 and the insulating layer 6, and ensuring insulation between the terminals 3, 5.
• the protruding portions 62, 63 of the insulating layer 6 are bent and inserted into the openings 34x, 35x, misalignment between the terminal 3 and the insulating layer 6 in the X-axis and Y-axis directions can be further reduced.
• Seventh Embodiment 13 is a cross-sectional view of the terminals 3 and 5 and the insulating layer 6, which are components of the semiconductor device according to the seventh embodiment, corresponding to the cross-sectional position of the semiconductor device according to the first embodiment shown in FIG. 3B.
• the semiconductor device according to the seventh embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 3B in that the protruding tip portions are inserted into the openings 34a and 35 of the protruding portions 62 and 63 of the insulating layer 6 and are bent. Note that only one tip portion of the protruding portions 62 and 63 of the insulating layer 6 may be bent.
• Other configurations of the semiconductor device according to the seventh embodiment are substantially similar to those of the semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.
• the protrusions 62 and 63 of the insulating layer 6 may be inserted into the openings 34a and 35, with the protruding tip portions bent. Even in this case, the insulating layer 6 is fixed to the terminal 3 by inserting the protrusion 62 into the opening 34a of the terminal 3 and the protrusion 63 into the opening 35 of the terminal 3, making it easier to align the terminal 3 and the insulating layer 6 and ensuring insulation between the terminals 3 and 5. Furthermore, because the tip portions of the protrusions 62 and 63 of the insulating layer 6 are bent, the insulating layer 6 is less likely to come off the terminal 3.
• Fig. 14 is a plan view of the terminals 3 and insulating layer 6, which are components of the semiconductor device according to the eighth embodiment.
• Fig. 15 is a cross-sectional view of the terminals 3, 5 and insulating layer 6 taken along line A-A' in Fig. 14.
• Fig. 16 is a cross-sectional view of the terminals 3, 5 and insulating layer 6 taken along line B-B' in Fig. 14.
• Fig. 17 is a side view of the terminals 3, 5 and insulating layer 6 as viewed in the positive direction of the X-axis.
• the semiconductor device according to the eighth embodiment differs from the semiconductor device according to the first embodiment shown in Figures 2 to 5 in that the protrusion 62 of the insulating layer 6 is inserted into the opening 34a of one terminal 3, and the protrusion 63 of the insulating layer 6 is inserted into the opening 53a of the other terminal 5.
• Terminals 3 and 5 are arranged on the upper surface of the insulated circuit board 1 shown in Figure 1 and are electrically connected to the semiconductor chips 2a and 2b. There are no particular restrictions on the arrangement position, length, width, or thickness of each of the terminals 3 and 5. There are also no particular restrictions on the position or number of bent portions of each of the terminals 3 and 5.
• One of the terminals 3 and 5 may constitute a positive terminal that is an external connection terminal, and the other of the terminals 3 and 5 may constitute a negative terminal that is also an external connection terminal.
• the terminals 3 and 5 are arranged closely (laminated) so as to face each other with the insulating layer 6 interposed therebetween.
• the terminals 3 and 5 are different electrode terminals to which different potentials are applied, and currents flow in opposite directions through the terminals 3 and 5.
• the terminal 3 has a flat portion 31, connection portions 32a to 32c that are bent downward and connected to the flat portion 31, and a connection portion 33 that is bent upward and connected to the flat portion 31 on the side opposite to the side to which connection portions 32a to 32c are connected.
• the shapes of the flat portion 31 and connection portions 32a to 32c are the same as those of the flat portion 31 and connection portions 32a to 32c shown in Figures 2 to 5.
• An opening 34a is provided between connection portions 32a and 32b on the lower side of the flat portion 31.
• An opening 34b is provided between connection portions 32b and 32c on the lower side of the flat portion 31.
• connection portion 33 is provided so as to extend in the Z-axis direction. No opening is provided in the connection portion 33.
• the upper end of the connection portion 33 may protrude from the upper surface of the sealing resin 8 (see Figure 1).
• Terminal 5 has a flat portion 51, a connection portion 52 bent downward and connected to flat portion 51, and a connection portion 53 bent upward and connected to the flat portion 51 on the side opposite to the side to which connection portion 52 is connected.
• the shape of flat portion 51 is the same as the shape of flat portion 51 shown in Figures 2 to 5.
• Flat portion 51 is arranged so as to face a part of flat portion 31 of terminal 3 with insulating layer 6 interposed between them.
• Connection portion 52 may be divided into three portions, similar to connection portions 52a to 52c shown in Figures 2 to 5.
• connection portion 53 is arranged to extend in the Z-axis direction, parallel to the connection portion 33 of the terminal 3. As shown in Figures 14, 16, and 17, the connection portion 53 has openings 53a and 53b that penetrate in the X-axis direction. Note that the opening 53b does not necessarily have to be provided. The upper end of the connection portion 53 may protrude from the upper surface of the sealing resin 8 (see Figure 1).
• the shape of the insulating layer 6 is the same as that of the insulating layer 6 shown in Figure 7.
• the insulating layer 6 comprises a main body portion 61, a protrusion portion 62 connected to the main body portion 61, and a protrusion portion 63 connected to the side of the main body portion 61 opposite to the side to which the protrusion portion 62 is connected.
• the protrusion portion 62 of the insulating layer 6 is inserted into the opening 34a of the terminal 3.
• the protrusion portion 63 of the insulating layer 6 is inserted into the opening 53a of the terminal 5.
• the relationship between the length L1 of the protrusion 62 and the thickness T1 of the terminal 3 is the same as in the semiconductor device of the first embodiment. If the length L2 of the protrusion 63 is equal to or greater than the thickness T2 of the terminal 5, the insulating layer 6 will be less likely to come off the terminal 5. If the length L2 of the protrusion 63 is longer than the thickness T2 of the terminal 5, the tip of the protrusion 63 can be bent to make the insulating layer 6 even less likely to come off the terminal 5. The length L2 of the protrusion 63 may be less than the thickness T2 of the terminal 5, and the protrusion 63 may be inserted up to a portion of the opening 53a.
• the other configuration of the semiconductor device of the eighth embodiment is substantially the same as that of the semiconductor device of the first embodiment, so repeated explanations will be omitted.
• the protrusion 62 of the insulating layer 6 may be inserted into the opening 34a of one terminal 3, and the protrusion 63 of the insulating layer 6 may be inserted into the opening 53a of the other terminal 5.
• the insulating layer 6 is fixed to both terminals 3 and 5, making it easier to align both terminals 3 and 5 with the insulating layer 6, and ensuring insulation between the terminals 3 and 5.
• Ninth Embodiment 18 is a plan view of the terminals 3 and 5 and the insulating layer 6, which are components of the semiconductor device according to the ninth embodiment.
• the semiconductor device according to the ninth embodiment differs from the semiconductor device according to the eighth embodiment shown in FIG. 14 in that the protruding portion 62 of the insulating layer 6 is not opposed to the protruding portion 63 across the main body portion 61 but is positioned offset from it.
• the protruding portion 62 is inserted into an opening 34b formed between the connecting portions 32b and 32c of the terminal 3.
• the other configuration of the semiconductor device according to the ninth embodiment is substantially the same as that of the semiconductor device according to the eighth embodiment, and therefore, a redundant description will be omitted.
• the protrusion 62 of the insulating layer 6 may be positioned offset from the protrusion 63 across the main body 61.
• the protrusion 62 of the insulating layer 6 is inserted into the opening 34b of the terminal 3, and the protrusion 63 of the insulating layer 6 is inserted into the opening 53a of the terminal 5, and the insulating layer 6 is fixed to both the terminals 3 and 5. This facilitates alignment of both the terminals 3 and 5 with the insulating layer 6, ensuring insulation between the terminals 3 and 5.
• the protrusion 62 of the insulating layer 6 is positioned offset from the protrusion 63 across the main body 61, and is inserted into the opening 34b of the terminal 3, further reducing misalignment between the terminals 3 and 5 and the insulating layer 6.
• Tenth Embodiment 19 is a plan view of the terminals 3 and 5 and the insulating layer 6, which are components of the semiconductor device according to the tenth embodiment.
• the semiconductor device according to the tenth embodiment differs from the semiconductor device according to the eighth embodiment shown in FIG. 14 in that the protruding portions 62 and 63 of the insulating layer 6 are provided with return portions 62a and 63a. Note that only one of the return portions 62a and 63a of the protruding portions 62 and 63 of the insulating layer 6 may be provided.
• the other configuration of the semiconductor device according to the tenth embodiment is substantially the same as that of the semiconductor device according to the eighth embodiment, and therefore, a duplicated description will be omitted.
• the protrusions 62, 63 of the insulating layer 6 may be provided with return portions 62a, 63a.
• the protrusion 62 of the insulating layer 6 is inserted into the opening 34b of the terminal 3, and the protrusion 63 of the insulating layer 6 is inserted into the opening 53a of the terminal 5, and the insulating layer 6 is fixed to both the terminals 3, 5.
• the return portions 62a, 63a are provided on the protrusions 62, 63 of the insulating layer 6, making it more difficult for the insulating layer 6 to come off both the terminals 3, 5.
• FIG. 20 is a plan view of the terminals 3, 5 and insulating layer 6, which are components of the semiconductor device according to the eleventh embodiment.
• the cross section taken along line A-A' in Fig. 20 is similar to Fig. 15.
• Fig. 21 is a cross section of the terminals 3, 5 and insulating layer 6 taken along line B-B' in Fig. 20.
• the semiconductor device according to the eleventh embodiment differs from the semiconductor device according to the eighth embodiment shown in Figures 14 and 16 in that openings 34x and 34y that penetrate in the Z-axis direction are provided in the portion of the flat portion 31 of the terminal 3 that does not face the terminal 5, and openings 53x that penetrate in the Z-axis direction are provided in the portion of the flat portion 51 of the terminal 5 that does not face the terminal 3.
• the protrusion 62 of the insulating layer 6 is bent upward at a right angle from the main body 61 and inserted into the opening 34x.
• the protrusion 63 of the insulating layer 6 is bent downward at a right angle from the main body 61 and inserted into the opening 53x.
• the opening 34y into which the protrusion 62 of the insulating layer 6 is not inserted does not have to be present.
• the protrusion 62 of the insulating layer 6 may be positioned offset from the protrusion 63 across the main body 61, rather than facing it, and inserted into the opening 34y.
• the other configuration of the semiconductor device according to the eleventh embodiment is substantially the same as that of the semiconductor device according to the eighth embodiment, and therefore redundant description will be omitted.
• an opening 34x penetrating in the Z-axis direction may be provided in the flat portion 31 of the terminal 3
• an opening 53x penetrating in the Z-axis direction may be provided in the flat portion 51 of the terminal 5
• the protrusions 62, 63 of the insulating layer 6 may be bent and inserted into the openings 34x, 53x.
• the insulating layer 6 is fixed to the terminals 3, 5, making it easy to align the terminals 3, 5 and the insulating layer 6, ensuring insulation between the terminals 3, 5.
• a protrusion 62x may be further provided on the insulating layer 6, and the protrusion 62x may be inserted into the opening 34b, as in the semiconductor device according to the third embodiment shown in FIG. 9. Furthermore, in the semiconductor device according to the eighth embodiment shown in FIGS. 14 to 17, the tips of the protrusions 62, 63 on the insulating layer 6 may be bent, as in the semiconductor device according to the seventh embodiment shown in FIG. 13.

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