Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies

Definitions

• a semiconductor device has been proposed that can reduce leakage current by providing a P- layer that connects a P layer (FLR) provided at a fixed pitch at the edge termination portion and a P- layer 10a with a lower impurity concentration than the P layer and a depth smaller than that of the P layer (see, for example, Patent Document 1 below).
• FLR P layer
• the termination region includes the first semiconductor layer, a first semiconductor region of a second conductivity type including a plurality of first small regions of a second conductivity type spaced apart from one another on the surface layer of the first semiconductor layer, and a third semiconductor region of a second conductivity type that is lower in concentration than the first small regions and whose surface on the semiconductor substrate side is shallower than the surface of the first small regions on the semiconductor substrate side, between the second semiconductor region and the first small regions closest to the active region and between the first small regions, from the end of the second semiconductor region to a predetermined number of the first small regions, and in the first semiconductor layer, a fourth semiconductor region of a first conductivity type between the surface of the first semiconductor layer and the third semiconductor region.
• an inter-FLR low-concentration p-type layer (third semiconductor region of second conductivity type) in a form that connects between the FLRs (first small regions of second conductivity type)
• sufficient surface charge resistance can be ensured even if the dimensions of each FLR in the FLR structure vary, and edge breakdown voltage can be stabilized.
• breakdown voltage can be stably ensured without performing SiC etching or high-acceleration ion implantation in the edge termination region, and by not using SiC etching or high-acceleration ion implantation, manufacturing costs can be reduced.
• FIG. 1 is a cross-sectional view showing an edge termination structure of a silicon carbide semiconductor device according to an embodiment.
• FIG. 2 is a cross-sectional view showing an active structure of the silicon carbide semiconductor device according to the embodiment.
• FIG. 3 is a graph showing concentration distribution in the depth direction of the p-type layer of the silicon carbide semiconductor device according to the embodiment.
• FIG. 4 is a graph showing variations in FLR dimensions and changes in edge breakdown voltage due to edge surface charges in conventional silicon carbide semiconductor devices.
• FIG. 5 is a graph showing variations in FLR dimensions and changes in edge breakdown voltage due to edge surface charges in silicon carbide semiconductor devices according to the embodiment.
• FIG. 6 is a cross-sectional view showing the electric field distribution in a conventional silicon carbide semiconductor device.
• the semiconductor device is characterized in that, in the above disclosure, the fourth semiconductor region is provided from the surface of the first semiconductor layer to the surface of the third semiconductor region on the surface side of the first semiconductor layer, and the thickness of the fourth semiconductor region is smaller than the thickness of the second sub-region of the first sub-region.
• the semiconductor device in the above disclosure, is characterized in that the first small region has an impurity concentration of 5 ⁇ 1019 cm -3 or more and 2 ⁇ 1020 cm -3 or less in the second small region of the central region, an impurity concentration of 1 ⁇ 1016 cm -3 or more and 5 ⁇ 1019 cm -3 or less in the third small region of the central region, and an impurity concentration of 1 ⁇ 1016 cm -3 or more and 5 ⁇ 1019 cm -3 or less in the inner region and the outer region.
• the semiconductor device according to the present disclosure in the above disclosure, is characterized in that the width of the central region of the first small region is wider than the width of the inner region or the outer region in a direction parallel to the surface of the first semiconductor layer.
• the semiconductor device is characterized in that in the above disclosure, the width of the inner region and the width of the outer region of the first small region are 3% or more and 20% or less of the width of the first small region provided closest to the active region.
• the semiconductor device according to the present disclosure is characterized in that in the above disclosure, the surface of the first semiconductor region and the surface of the second semiconductor region are the same as the surface of the first semiconductor layer.
• the semiconductor device is characterized in that, in the above disclosure, the width of the multiple first small regions narrows and the spacing between the first small regions widens from the active region side toward the chip end, the width of the first small regions on the surface of the first semiconductor layer is 6.0 ⁇ m or more at the side closest to the active region and 2.0 ⁇ m or less at the side closest to the chip end, the width of the first small regions is less than the width of the first small regions adjacent to the active region side, the spacing between the first small regions on the surface of the first semiconductor layer is 2.0 ⁇ m or less at the side closest to the active region and 3.0 ⁇ m or more at the side closest to the chip end, the spacing between the first small regions is greater than the spacing between the first small regions adjacent to the active region side, and there are 10 or more first small regions.
• the semiconductor device is characterized in that, in the above disclosure, the impurity concentration of the third semiconductor region has a maximum value on the semiconductor substrate side from the surface side of the first semiconductor layer, the maximum value being higher than the impurity concentration of the first semiconductor layer and not more than 2 x 1017 cm -3 , and the impurity concentration of the third semiconductor region is lower than the impurity concentration of the first small region in a region deeper than the position where the first small region has the maximum impurity concentration.
• the semiconductor device is characterized in that, in the above disclosure, the end of the third semiconductor region on the chip end side is closer to the chip end side than the first part from the active region where the spacing between the first small regions is 1.5 ⁇ m or more or the width of the first small regions is 3.0 ⁇ m or less.
• an edge termination region is provided that surrounds the periphery of an active region through which current flows when the device is on and has a breakdown voltage structure.
• the breakdown voltage structure is fabricated by forming a p-type structure on the surface of an n-type substrate.
• a semiconductor element using silicon carbide (SiC) as a semiconductor material hereinafter referred to as a silicon carbide semiconductor device
• a spatially modulated JTE (Junction Termination Extension) structure, an FLR structure, or a structure that combines these structures is mainly used.
• the edge termination region's breakdown voltage structure has the role of making the edge breakdown voltage equal to or greater than that of the active region by mitigating electric field concentration at the edge of the active region. This reduces the risk of thermal breakdown of the chip by allowing dielectric breakdown to occur in the active region, which has a larger area than the edge termination region, and also reduces the effect of charge accumulated on the surface of the edge termination region, stabilizing the breakdown voltage.
• the spatially modulated JTE structure uses a patterned p-type region (JTE) to form a structural concentration distribution and prevent electric field concentration.
• the FLR structure disperses the electric field by arranging the p-type region in a ring shape when viewed from the surface, thereby achieving a breakdown voltage. Furthermore, a structure in which an FLR is placed closer to the active region and combined with a JTE to cover it is also conceivable.
• the spatially modulated JTE structure can reduce the effects of dimensional variations and surface charges in the edge termination region, it requires multiple ion implantations in addition to the active region formation process, resulting in high manufacturing costs.
• SiC where impurities do not easily diffuse, etching of the surface SiC or ion implantation at high acceleration energy is required to ensure a depth equivalent to that of the active region, which also leads to increased manufacturing costs.
• the FLR structure requires only one ion implantation and can be formed simultaneously with the p-type region of the active region, so manufacturing costs are relatively low, but there is a large fluctuation in breakdown voltage due to dimensional variations and edge surface charges.
• a structure that combines an FLR formed simultaneously with the active region and a JTE can stabilize the breakdown voltage while limiting the number of ion implantations to one, but the high cost required to ensure the depth remains an issue.
• an FLR structure is adopted, and since ion implantation is required only once and it is possible to form the active region together with the p-type region at the same time, manufacturing costs are relatively low, and furthermore, a semiconductor device is provided that reduces fluctuations in breakdown voltage due to dimensional variations and edge surface charges.
• the semiconductor device according to the present disclosure is configured using a wide band gap semiconductor.
• a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example.
• Fig. 1 is a cross-sectional view showing a structure from an edge termination region to an active region of a silicon carbide semiconductor device according to an embodiment.
• Fig. 2 is a cross-sectional view showing a structure of an active region of a silicon carbide semiconductor device according to an embodiment.
• a silicon carbide semiconductor device 70 comprises an active region 50 and an edge termination region 60 surrounding the active region 50 in a semiconductor substrate made of silicon carbide (hereinafter referred to as a silicon carbide substrate (semiconductor substrate (semiconductor chip))).
• the active region 50 is a region through which current flows in the on state.
• the edge termination region 60 is a region that relieves the electric field on the front surface side of the substrate in the drift region and maintains a breakdown voltage.
• a gate insulating film 11 is formed along the inner wall of the trench 25 on the bottom and side walls of the trench 25, and a gate electrode 13 is formed inside the gate insulating film 11 in the trench 25.
• the gate electrode 13 is insulated from the n ⁇ type drift region 2 and the p type base region 5 by the gate insulating film 11. A part of the gate electrode 13 may protrude from above the trench 25 (the side where a source electrode 16 described later is provided) toward the source electrode 16.
• An upper p + type partial region (first semiconductor region of second conductivity type) 4a is provided in the surface layer of the opposite side (first main surface side of the silicon carbide base) of the n - type drift region 2 with respect to the n + type silicon carbide substrate 1 side.
• the upper p + type partial region 4a is provided, for example, between the trenches 25.
• a lower p + type partial region 4b that contacts the bottom of the upper p + type partial region 4a is provided in the n - type drift region 2.
• a p + type region 26 is provided at the bottom of the trench 25.
• the p + type region 26 that contacts the bottom of the trench 25 is provided at a position facing the bottom of the trench 25 in the depth direction (direction from the source electrode 16 to the back electrode).
• the upper p + type partial region 4a and the lower p + type partial region 4b between the trenches 25 are combined to form the p + type partial region 4.
• the width of the p + type region 26 is equal to or wider than the width of the trench 25.
• the width of the lower p + type partial region 4b is equal to or wider than the width of the upper p + type partial region 4a.
• the bottom of the trench 25 may reach the p + type region 26, or may be located within the n - type drift region 2 sandwiched between the p type base region 5 and the p + type region 26.
• n ++ type source region 7 and p ++ type contact region 6 are selectively provided on the first main surface side of the silicon carbide substrate within the p type base region 5.
• the n ++ type source region 7 and the p ++ type contact region 6 are in contact with each other.
• the lower p + type partial region 4b, the upper p + type partial region 4a, and the p ++ type contact region 6 extend to the end of the active region 50.
• the end of the lower p + type partial region 4b is preferably located 3.0 ⁇ m or more closer to the active region 50 than the ends of the upper p + type partial region 4a and the p ++ type contact region 6.
• the interlayer insulating film 14 is provided on the entire surface of the first main surface side of the silicon carbide substrate so as to cover the gate electrode 13 embedded in the trench 25.
• the source electrode 16 contacts the n ++ type source region 7 and the p ++ type contact region 6 through a contact hole opened in the interlayer insulating film 14.
• the source electrode 16 is electrically insulated from the gate electrode 13 by the interlayer insulating film 14.
• a source electrode pad (not shown) is provided on the source electrode 16.
• a barrier metal 15 for preventing diffusion of metal atoms from the source electrode 16 to the gate electrode 13 side may be provided between the source electrode 16 and the interlayer insulating film 14.
• a polyimide (not shown) functioning as a protective film is provided on the surface of the silicon carbide semiconductor device 70.
• FIG. 1 only two MOS gate (insulating gate made of metal-oxide film-semiconductor) structures are illustrated in the active region 50, but more MOS gate structures may be arranged in parallel.
• edge termination region 60 the above-mentioned n ⁇ type drift region 2 is also provided on the front surface of n + type silicon carbide substrate 1 .
• the edge termination region 60 is provided with an FLR structure (second semiconductor region of second conductivity type) 30.
• an n ++ type (p ++ type) channel stopper region (not shown) functioning as a channel stopper is provided on the surface of the n ⁇ type drift region 2 outside the FLR structure 30 (chip end side).
• a high breakdown voltage in the lateral direction is maintained by a pn junction between the FLR structure 30 and the n ⁇ type drift region 2.
• the edge termination region 60 is covered with a field oxide film (not shown), and an HTO film (not shown) and an interlayer insulating film (not shown) are deposited in this order on the field oxide film.
• the FLR structure 30 has a plurality of p-type FLRs (first small regions of a second conductivity type) 31 arranged on the first main surface side of the silicon carbide substrate.
• a high-concentration p-type FLR region 32 which is a shallow and highly-concentrated region, is provided in the center of the surface side of the FLR 31.

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