WO2025134202A1 - 光半導体装置 - Google Patents

光半導体装置 Download PDF

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Publication number
WO2025134202A1
WO2025134202A1 PCT/JP2023/045330 JP2023045330W WO2025134202A1 WO 2025134202 A1 WO2025134202 A1 WO 2025134202A1 JP 2023045330 W JP2023045330 W JP 2023045330W WO 2025134202 A1 WO2025134202 A1 WO 2025134202A1
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WIPO (PCT)
Prior art keywords
electrode
pad electrode
optical semiconductor
insulating film
capacitance
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PCT/JP2023/045330
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English (en)
French (fr)
Japanese (ja)
Inventor
真也 奥田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2025564641A priority Critical patent/JPWO2025134202A1/ja
Priority to PCT/JP2023/045330 priority patent/WO2025134202A1/ja
Publication of WO2025134202A1 publication Critical patent/WO2025134202A1/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers

Definitions

  • This disclosure relates to optical semiconductor devices.
  • An Electro Absorption Modulated Laser is a device that integrates a semiconductor laser and an optical modulator, which absorbs part of the incident light when an electric field is applied, on the same semiconductor substrate. Compared to direct modulation methods that directly modulate the light intensity, there is less degradation of the signal waveform, making high-speed, long-distance optical fiber transmission possible.
  • Patent Document 1 discloses a technique for providing multiple mesh holes in the pad electrode as a technique for reducing the capacitance of the pad electrode. This makes it possible to reduce the effective area of the pad electrode while still ensuring the contact area.
  • the present disclosure aims to provide an optical semiconductor device that can reduce the capacitance of the pad electrode in order to solve the above-mentioned problems.
  • the first aspect of the present disclosure is A semiconductor substrate; an optical semiconductor element formed on the semiconductor substrate; a pad electrode formed on the optical semiconductor element and electrically connected to an upper surface electrode of the optical semiconductor element; Equipped with the pad electrode has a first electrode formed on the optical semiconductor element via an insulating film, and a second electrode formed on the first electrode;
  • An optical semiconductor device having a mesh-like groove or a plurality of holes in a top view, the mesh-like groove or holes penetrating the insulating film from the front surface of the first electrode toward the rear surface of the semiconductor substrate. It is preferable that:
  • the second aspect is as follows: A semiconductor substrate; an optical semiconductor element formed on the semiconductor substrate; a pad electrode formed on the optical semiconductor element via an insulating film and electrically connected to an upper surface electrode of the optical semiconductor element; Equipped with It is desirable for the optical semiconductor device to have a mesh-like groove or a plurality of holes in a top view that penetrate the insulating film from the surface of the insulating film formed under the pad electrode toward the back surface of the semiconductor substrate.
  • FIG. 1 is a top view of an optical semiconductor device according to a first embodiment of the present disclosure
  • 2 is a cross-sectional view taken along line AA of FIG. 1, showing a cross section of a mesa stripe.
  • 2 is a cross-sectional view taken along line B-B of FIG. 1, showing a cross section of the semiconductor laser.
  • 2 is a cross-sectional view taken along the line CC in FIG. 1, showing a cross section of the optical modulator.
  • FIG. 4 is a schematic diagram for calculating the capacitance of a pad electrode according to the first embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram for calculating the capacitance of a pad electrode in a general prior art.
  • FIG. 1 is a schematic diagram for calculating the capacitance of a pad electrode in Patent Document 1.
  • 11 is a cross-section of an optical modulator according to a second embodiment of the present disclosure.
  • 13 is a schematic diagram for calculating the capacitance of a pad electrode according to a second embodiment of the present disclosure.
  • FIG. 11 is a cross-section of an optical modulator according to a third embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram for calculating the capacitance of a pad electrode according to a third embodiment of the present disclosure.
  • FIG. 11 is a top view of an optical semiconductor device according to a fourth embodiment of the present disclosure.
  • 11 is a cross section of an optical modulator according to a fourth embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram for calculating the capacitance of a pad electrode according to a fourth disclosed embodiment. 13 is a cross-section of an optical modulator according to a fifth embodiment of the present disclosure. FIG. 13 is a schematic diagram for calculating the capacitance of a pad electrode according to a fifth embodiment of the present disclosure.
  • FIG. 2 is a top view of an optical semiconductor device 1 according to a modified example of the first embodiment of the present disclosure. This is a cross section taken along line DD in FIG.
  • First embodiment 1 is a top view of an optical semiconductor device 1 according to a first embodiment of the present disclosure.
  • the direction of the optical axis of a laser beam emitted by a semiconductor laser 2 is defined as the z-direction.
  • the thickness direction of stacked semiconductor layers is defined as the y-direction.
  • the direction perpendicular to the z-direction and the y-direction is defined as the x-direction.
  • a semiconductor laser 2 and an optical modulator 4 are integrated on an InP substrate 9 (not shown).
  • the semiconductor laser 2 is, for example, a distributed feedback laser.
  • the wavelength band of the laser light is not limited, but the 1.3 ⁇ m band and the 1.55 ⁇ m band are used in the long wavelength bands for optical communications.
  • An anode electrode 5 is formed on the surface of the semiconductor laser 2.
  • the optical modulator 4 is an electroabsorption type modulator.
  • An anode electrode 6 is formed on the upper surface of the optical modulator 4.
  • the anode electrode 6 is electrically connected to a pad electrode 7 via a wire bonding metal 28 (not shown).
  • the optical modulator 4 absorbs and modulates the laser light emitted from the semiconductor laser 2.
  • the semiconductor laser 2 and the optical modulator 4 are separated by a separation section 3.
  • FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1, showing a cross section of mesa stripe 8.
  • the mesa stripe 8 is formed across the semiconductor laser 2, the separator 3, and the optical modulator 4.
  • the mesa stripe 8 has a waveguide that propagates the light generated by the semiconductor laser 2 to the optical modulator 4.
  • the mesa stripe 8 in the semiconductor laser 2 region has an n-type guide layer 10, an i-type active layer 11, a diffraction grating 13, a p-type guide layer 14, a p-type cladding layer 15 of InP, and a p-type contact layer 16, which are stacked in this order on an InP substrate 9.
  • the n-type guide layer 10, the i-type active layer 11, the diffraction grating 13, and the p-type guide layer 14 are made of III-V group mixed crystal semiconductors such as InAlGaAs and InGaAsP.
  • the p-type contact layer 16 is made of InGaAs or the like.
  • the i-type active layer 11 has a multiple quantum well (MQW) structure.
  • An insulating film 17 and an anode electrode 5 are formed on the p-type contact layer 16 in the semiconductor laser 2 region.
  • An opening is provided in the insulating film 17, and the anode electrode 5 is electrically connected to the p-type contact layer 16 through the opening.
  • the anode electrode 5 includes an anode first electrode 18 connected to the p-type contact layer 16, and an anode second electrode 19 formed on the anode first electrode 18.
  • the anode first electrode 18 not only enhances adhesion to the p-type contact layer 16, but also serves as a barrier metal that prevents the metal of the anode second electrode 19 from diffusing into the p-type contact layer 16.
  • the anode first electrode 18 and the anode second electrode 19 are made of Ti, Au, or the like.
  • the mesa stripe 8 in the optical modulator 4 region comprises an n-type guide layer 10, an i-type light absorbing layer 12, a p-type guide layer 14, a p-type cladding layer 15, and a p-type contact layer 16, which are stacked in this order on an InP substrate 9.
  • the i-type light absorbing layer 12 is an MQW structure using a III-V group mixed crystal semiconductor such as InAlGaAs or InGaAsP.
  • An insulating film 17 and an anode electrode 6 are formed on the p-type contact layer 16 in the optical modulator 4 region.
  • An opening is provided in the insulating film 17, and the anode electrode 6 is electrically connected to the p-type contact layer 16 through the opening.
  • the anode electrode 6 includes a first anode electrode 18 and a second anode electrode 19.
  • a cathode electrode 20 is provided on the entire or part of the back surface of the InP substrate 9.
  • the cathode electrode 20 includes a first cathode electrode 21 and a second cathode electrode 22.
  • the first cathode electrode 21 not only enhances adhesion to the InP substrate 9, but also serves as a barrier metal that prevents the metal of the second cathode electrode 22 from diffusing into the InP substrate 9.
  • the first cathode electrode 21 and the second cathode electrode 22 are made of AuGe, Au, or the like.
  • the structure of the mesa stripe 8 in the separation section 3 region is the same as that of the mesa stripe 8 in the optical modulator 4 region, except that an insulating film 17 is formed on the p-type cladding layer 15.
  • the insulating film 17 is formed between the p-type contact layer 16 in the semiconductor laser 2 region and the p-type contact layer 16 in the optical modulator 4 region. This electrically insulates the semiconductor laser 2 from the optical modulator 4.
  • FIG. 3 is a cross-sectional view taken along line B-B in FIG. 1, showing a cross section of the semiconductor laser 2.
  • the ridge structure 23 of the semiconductor laser 2 is provided on an InP substrate 9.
  • an n-type guide layer 10, an i-type active layer 11, a diffraction grating 13, and a p-type guide layer 14 are formed.
  • the semiconductor burying layer 24 buries the sides of the ridge structure 23.
  • Semiconductor burying layer 24 is made of Fe-doped semi-insulating InP or the like.
  • the sides of the mesa stripe 8, including the ridge structure 23 and the semiconductor buried layer 24, are covered with an insulating film 17.
  • FIG. 4 is a cross-sectional view taken along line C-C in FIG. 1, showing a cross-section of the optical modulator 4.
  • the ridge structure 23 is provided on an InP substrate 9.
  • an n-type guide layer 10, an i-type light absorption layer 12, and a p-type guide layer 14 are formed.
  • the sides of the ridge structure 23 are buried with a semiconductor burying layer 24.
  • the anode electrode 6 on the mesa stripe 8 is extended to the surface of the p-type contact layer 16 in a portion not including the mesa stripe 8, and serves as the pad electrode 7. This takes into consideration the fact that the width of the mesa stripe 8 of the optical modulator 4 must be narrowed to reduce capacitance, and therefore the width of the anode electrode 6 formed on the mesa stripe 8 must also be narrowed.
  • the pad electrode 7 is used to input a modulated signal to the optical modulator 4. It is also used in EML characteristic inspections using probe contacts, and in wire bonding to mount the EML chip on optical transmission devices such as transceivers. The area of the pad electrode 7 is secured in consideration of the ease of these operations.
  • the capacitance of the optical modulator 4 is the sum of the capacitance of the mesa stripe 8 of the optical modulator 4 and the capacitance of the pad electrode 7.
  • the capacitance of the optical modulator 4 is the sum of the capacitance of the mesa stripe 8 of the optical modulator 4 and the capacitance of the pad electrode 7.
  • mesh-like grooves 25 are provided in the pad electrode 7 and the insulating film 17 formed below the pad electrode 7 when viewed from above. This is based on the finding of the present disclosure that the capacitance of the pad electrode 7 can be reduced by providing an area occupied by air with a low dielectric constant below the pad electrode 7 and below the pad electrode 7.
  • FIG. 5 is a schematic diagram for calculating the capacitance of the pad electrode 7 according to the first embodiment of the present disclosure.
  • a simplified structure as shown in FIG. 5 was considered. That is, the structure is composed of metal 28, pad electrode 7, insulating film 17, i-type light absorbing layer 12, and cathode electrode 20. Note that metal 28 is assumed to be the wire used in the above-mentioned wire bonding.
  • each component is as follows: metal 28 1.0 ⁇ m, pad electrode 7 2.5 ⁇ m, insulating film 17 1.5 ⁇ m, i-type light absorbing layer 12 0.5 ⁇ m, and cathode electrode 20 1.0 ⁇ m.
  • the size of the metal 28, i-type light absorbing layer 12, and cathode electrode 20 when viewed from the top is 50 ⁇ m x 50 ⁇ m.
  • the pad electrode 7 and insulating film 17 are 50 ⁇ m x 50 ⁇ m, but a groove 25 with a width of 10 ⁇ m is provided.
  • the pad electrode 7 and insulating film 17 are configured with nine 10 ⁇ m x 10 ⁇ m pillars lined up. Note that the width here refers to the width when viewed from the side of the optical semiconductor device 1.
  • the surrounding environment including the groove 25 is air, the relative dielectric constant of the i-type light absorbing layer 12 is 12.25, and the relative dielectric constant of the insulating film 17 is 2.28.
  • the capacitance of the pad electrode 7 disclosed herein was approximately 19.9 fF.
  • Figure 6 is a schematic diagram for calculating the capacitance of the pad electrode 7 in a typical conventional technique.
  • the conventional technique neither the pad electrode 7 nor the insulating film 17 is mesh-shaped. Therefore, the shape and relative dielectric constant of each component are the same as in Figure 5, except that the pad electrode 7 and insulating film 17 do not have grooves 25.
  • the capacitance of the pad electrode 7 was approximately 39.2 [fF]. From this result, it is clear that the capacitance of the pad electrode 7 is greater in the conventional technique than in the present disclosure.
  • FIG. 7 is a schematic diagram for calculating the capacitance of the pad electrode 7 in Patent Document 1.
  • the insulating film 17 is not mesh-shaped. Therefore, except for the fact that the insulating film 17 does not have grooves 25, the shape and relative dielectric constant of each component are the same as in FIG. 5. As a result of the calculation, the capacitance was approximately 24.2 [fF]. Since the insulating film 17 is a material with a higher dielectric constant than air, it can be said that the capacitance of the pad electrode 7 in Patent Document 1 is larger than that of the present disclosure.
  • the lower layer of the pad electrode 7 is an insulating film 17, but even if any semiconductor layer is used, the capacitance will be larger than that disclosed in this disclosure. This is because the relative dielectric constant of the semiconductor material is higher than that of air.
  • a mesh-like groove 25 is provided in a top view that penetrates from the surface of the pad electrode 7 through the insulating film 17. This allows an area occupied by air, which has a low dielectric constant, to be provided in the insulating film 17, making it possible to reduce the electrostatic capacitance of the pad electrode 7.
  • a current is injected from the anode electrode 5 of the semiconductor laser 2 to the cathode electrode 20, causing electrons and holes to recombine and emit light.
  • the light generated is reflected by the diffraction grating 13 and travels back and forth within the semiconductor laser 2. During the travel, stimulated emission occurs, amplifying the light intensity. When a certain threshold is reached, laser oscillation occurs, and laser light is emitted from the semiconductor laser 2 toward the optical modulator 4.
  • the optical modulator 4 a negative voltage is applied from the anode electrode 6 to the cathode electrode 20 via the pad electrode 7. Then, the absorption spectrum of the i-type optical absorption layer 12 changes due to the quantum confined Stark effect, and optical absorption occurs. In other words, the intensity of the laser light emitted from the optical modulator 4 is modulated according to the voltage value applied to the optical modulator 4. The modulated laser light is emitted to the outside of the optical semiconductor device 1 and is used as signal light in optical communications, etc.
  • the n-type guide layer 10 is crystal-grown on the surface of the InP substrate 9 by MOCVD (metal organic chemical vapor deposition).
  • MOCVD metal organic chemical vapor deposition
  • the target semiconductor layers are crystal-grown by MOCVD in the regions of the semiconductor laser 2, the separator 3, and the optical modulator 4.
  • dry etching is performed using a SiO2 mask to pattern the i-type active layer 11, the i-type light absorption layer 12, the diffraction grating 13, and the p-type guide layer 14.
  • a SiO 2 mask is formed on the surface of the p-type guide layer 14, and a ridge structure 23 is patterned by dry etching. After that, a semiconductor buried layer 24 is crystal-grown on the side surface of the ridge structure 23. After removing the SiO 2 mask, a p-type cladding layer 15 and a p-type contact layer 16 are crystal-grown in sequence on the surfaces of the semiconductor buried layer 24 and the ridge structure 23. Next, a SiO 2 mask is formed on the surface of the p-type contact layer 16, and a mesa stripe 8 is patterned by dry etching. Next, the p-type contact layer 16 on the separation section 3 is removed by wet etching using a photoresist mask. Next, an insulating film 17 such as SiO 2 is formed on the surfaces of the semiconductor laser 2, separation section 3, and optical modulator 4 by plasma CVD or the like.
  • an opening is formed in the insulating film 17 by combining photolithography technology with etching technology using hydrofluoric acid or the like. These techniques are also used to form a groove 25 in the insulating film 17 below the pad electrode 7.
  • the anode first electrode 18 and the anode second electrode 19 are formed in the regions where the anode electrodes 5 and 6 are to be formed.
  • the formation method is electron beam deposition, plating, or the like. Unnecessary parts are lifted off together with the photoresist film.
  • the pad electrode 7 is also formed at the same time as the anode electrodes 5 and 6.
  • the photoresist film in the region where the pad electrode 7 is to be formed is patterned into a mesh shape, so that grooves 25 can be provided in the anode first electrode 18 and the anode second electrode 19.
  • the optical semiconductor device 1 of this embodiment is manufactured by the above steps.
  • the manufacturing method is not limited to this.
  • the above description shows a case where the p-type cladding layer 15 and the p-type contact layer 16 are formed simultaneously in each region of the semiconductor laser 2, the separation section 3, and the optical modulator 4, but each may be formed in a separate process.
  • the materials of the n-type guide layer 10, the i-type active layer 11, the i-type light absorption layer 12, the diffraction grating 13, and the p-type guide layer 14 are not limited to III-V mixed crystal semiconductors, and other semiconductor materials may be used. Although the i-type active layer 11 and the i-type light absorption layer 12 have an MQW structure, they may have a single quantum well structure or may not have a quantum well structure.
  • the type of substrate is not limited to InP.
  • the width of the mesa stripe 8 is uniform in each of the semiconductor laser 2, the separator 3, and the optical modulator 4 regions, but the width does not have to be uniform.
  • FIG. 2 shows a case where the mesa stripes 8 of the separation unit 3 and the optical modulator 4 have the same structure, but they do not necessarily have to be the same.
  • FIG. 2 shows an example where the diffraction grating 13 is formed on the i-type active layer 11, but the diffraction grating 13 may be formed below the i-type active layer 11.
  • the semiconductor laser 2, separation unit 3, and optical modulator 4 have the same structure except for the i-type active layer 11, diffraction grating 13, and i-type optical absorption layer 12, but they do not necessarily have to be the same.
  • the semiconductor laser 2 and the optical modulator 4 have a buried structure, but they may have a ridge structure or another structure.
  • the optical modulator 4 is not limited to a high mesa structure, and may have a buried waveguide or low mesa ridge structure.
  • FIG. 13 is a cross-section of an optical modulator 4 according to embodiment 4 of the present disclosure.
  • the cross-section shown here is the same as that shown in FIG. 4 of embodiment 1.
  • the shield electrode 26 includes an anode first electrode 18 connected to the p-type contact layer 16, and an anode second electrode 19 formed on the anode first electrode 18.
  • the capacitance reduction effect is greater as the width of the shield electrode 26 in a side view increases. However, it should be noted that in order to ensure insulation, the shield electrode 26 cannot come into contact with the pad electrode 7 and the insulating film 17.
  • FIG. 14 is a schematic diagram for calculating the capacitance of the pad electrode 7 according to the fourth embodiment of the present disclosure.
  • the width of the shield electrode 26 is set to 6 ⁇ m and the thickness to 2.5 ⁇ m.
  • the shapes and relative dielectric constants of the other components are set to the same as those in FIG. 5 of the first embodiment.
  • the capacitance of the pad electrode 7 was approximately 14.5 fF. It is clear from this result that the capacitance of the pad electrode 7 can be reduced compared to the first embodiment.
  • the optical semiconductor device 1 of this embodiment will be described. Note that only the changes from embodiment 1 will be described here. For example, only the area of the shield electrode 26 is patterned with a photoresist film, and the first anode electrode 18 and the second anode electrode 19 are formed in the area that will become the pad electrode 7 and the shield electrode 26 using electron beam evaporation, plating, etc. Furthermore, by repeatedly lifting off the unnecessary parts together with the photoresist film, the pad electrode 7 and the shield electrode 26 of the desired thickness can be formed simultaneously.
  • Fifth embodiment 15 is a cross-section of an optical modulator 4 according to a fifth embodiment of the present disclosure.
  • the cross-section shown here is the same as that shown in FIG. 4 of the first embodiment.
  • the pad electrode 7 is uniform.
  • a groove 25 penetrates from the surface of the insulating film 17 to the back surface of the n-type guide layer 10.
  • the contact properties of the pad electrode 7 can be improved compared to embodiment 3.
  • FIG. 16 is a schematic diagram for calculating the capacitance of the pad electrode 7 according to the fifth embodiment of the present disclosure.
  • the shape and relative dielectric constant of each component are the same as those of the third embodiment, except that the pad electrode 7 does not have a groove 25.
  • the capacitance of the pad electrode 7 is approximately 16.2 fF.
  • the capacitance is larger than that of the third embodiment, the capacitance of the pad electrode 7 can be made smaller than that of the general prior art shown in FIG. 6 and that of Patent Document 1 shown in FIG. 7. This is the effect of providing a groove 25 that penetrates from the surface of the insulating film 17 to the underside of the i-type light absorbing layer 12.
  • the optical semiconductor device 1 of this embodiment will be described. Note that only the changes from embodiment 3 will be described here.
  • the portion that will become the groove 25 is covered with a photoresist film. Dry etching is then performed to form the groove 25 and expose the top of the insulating film 17.
  • the anode first electrode 18 and the anode second electrode 19 are formed in the region of the pad electrode 7 using electron beam evaporation, plating, etc. By lifting off the unnecessary portions together with the photoresist film, a uniform pad electrode 7 can be formed on the mesh-shaped insulating film 17.
  • the present disclosure is not limited to the above-described embodiments, and various modifications can be made in the implementation stage without departing from the spirit of the disclosure.
  • the present disclosure is not limited to EMLs, and can be applied to optical semiconductor devices having pad electrodes for applying an electric field or injecting a current to optical semiconductor elements such as directly modulated semiconductor lasers, Mach-Zehnder type optical modulators, optical resonators, and optical phase shifters.
  • the various embodiments may be implemented in appropriate combination, in which case the combined effects can be obtained.
  • Fig. 17 is a top view of an optical semiconductor device 1 according to a modified example of the first embodiment of the present disclosure.
  • a plurality of holes 30 that are mesh-like when viewed from above are formed. Even in this case, a region occupied by air with a low dielectric constant can be provided below the pad electrode 7, and the same effect as described above can be obtained.
  • Fig. 18 is a cross section taken along the line D-D in Fig. 17.
  • a plurality of holes 30 are provided that penetrate the pad electrode 7 and the insulating film 17.
  • the pad electrode 7 is referred to as a first electrode
  • the metal 28 is referred to as a second electrode
  • the pad electrode has a first electrode and a second electrode.
  • the anode electrode 6 is referred to as an upper electrode.
  • Optical semiconductor device 1 Optical semiconductor device, 2 Semiconductor laser, 3 Isolation section, 4 Optical modulator (optical semiconductor element), 5 Anode electrode, 6 Anode electrode (upper electrode), 7 Pad electrode, 8 Mesa stripe, 9 InP substrate (semiconductor substrate), 10 n-type guide layer, 11 i-type active layer, 12 i-type light absorption layer, 13 Diffraction grating, 14 p-type guide layer, 15 p-type cladding layer, 16 p-type contact layer, 17 Insulating film, 18 Anode first electrode, 19 Anode second electrode, 20 Cathode electrode, 21 Cathode first electrode, 22 Cathode second electrode, 23 Ridge structure, 24 Semiconductor buried layer, 25 Groove, 26 Shield electrode, 27 Pad electrode, 28 Metal, 30 Hole

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)
  • Optical Modulation, Optical Deflection, Nonlinear Optics, Optical Demodulation, Optical Logic Elements (AREA)
PCT/JP2023/045330 2023-12-18 2023-12-18 光半導体装置 Pending WO2025134202A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02181987A (ja) * 1989-01-06 1990-07-16 Nec Corp 半導体レーザ
JP2003324233A (ja) * 2002-04-26 2003-11-14 Fuji Xerox Co Ltd 表面発光型半導体レーザ素子およびその製造方法
JP2008084891A (ja) * 2006-09-25 2008-04-10 Fujitsu Ltd 光半導体素子及びその製造方法
JP2010182973A (ja) * 2009-02-06 2010-08-19 Sony Corp 半導体素子
JP2012023065A (ja) * 2010-07-12 2012-02-02 Nippon Telegr & Teleph Corp <Ntt> 半導体素子

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02181987A (ja) * 1989-01-06 1990-07-16 Nec Corp 半導体レーザ
JP2003324233A (ja) * 2002-04-26 2003-11-14 Fuji Xerox Co Ltd 表面発光型半導体レーザ素子およびその製造方法
JP2008084891A (ja) * 2006-09-25 2008-04-10 Fujitsu Ltd 光半導体素子及びその製造方法
JP2010182973A (ja) * 2009-02-06 2010-08-19 Sony Corp 半導体素子
JP2012023065A (ja) * 2010-07-12 2012-02-02 Nippon Telegr & Teleph Corp <Ntt> 半導体素子

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