WO2025089009A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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WO2025089009A1
WO2025089009A1 PCT/JP2024/035494 JP2024035494W WO2025089009A1 WO 2025089009 A1 WO2025089009 A1 WO 2025089009A1 JP 2024035494 W JP2024035494 W JP 2024035494W WO 2025089009 A1 WO2025089009 A1 WO 2025089009A1
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trench
gate
semiconductor device
region
forming
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French (fr)
Japanese (ja)
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源宜 窪内
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Publication of WO2025089009A1 publication Critical patent/WO2025089009A1/ja
Priority to US19/334,947 priority patent/US20260020271A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/415—Insulated-gate bipolar transistors [IGBT] having edge termination structures
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/161—IGBT having built-in components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/417—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/418—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
  • Patent Document 1 JP 2019-110288 A
  • the step of forming a barrier region of the second conductivity type at the bottom of the trench may cause variations in the threshold voltage.
  • a method for manufacturing a semiconductor device comprising the steps of forming a plurality of trenches on a front surface of a semiconductor substrate, forming an implantation mask in a first of the plurality of trenches, and injecting a dopant of a second conductivity type into the second trench to form a trench bottom portion at the bottom of a second trench among the plurality of trenches in which the implantation mask is not formed, wherein, in the step of injecting the dopant, the dopant of the second conductivity type is also implanted into a first mesa portion adjacent to the first trench and a second mesa portion adjacent to the second trench.
  • a third trench may be formed between the first trench and the second trench, and in the step of forming the implantation mask, the implantation mask may be formed in the third trench, and in the step of injecting the dopant, the second conductivity type dopant may also be implanted into the first mesa portion adjacent to the third trench.
  • the method for manufacturing a semiconductor device may further include a step of diffusing the dopant, and may further include forming the trench bottom portion at the bottom of the third trench.
  • the upper surface of the implantation mask may be located at the same position as the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate, or at a position deeper than the front surface of the semiconductor substrate.
  • a method for manufacturing a semiconductor device comprising the steps of forming a plurality of trenches on a front surface of a semiconductor substrate, forming an implantation mask in a first of the plurality of trenches, and injecting a dopant of a second conductivity type into the second trench to form a trench bottom portion at the bottom of a second trench of the plurality of trenches in which the implantation mask is not formed, wherein in the step of forming the implantation mask, a mask is also formed on the top surface of a first mesa portion adjacent to the first trench and on the top surface of a second mesa portion adjacent to the second trench.
  • a third trench may be formed between the first trench and the second trench, and in the step of forming the implantation mask, the implantation mask may be further formed in the third trench and on the upper surface of the first mesa portion adjacent to the third trench.
  • the method for manufacturing a semiconductor device may further include a step of diffusing the dopant, and may further include forming the trench bottom portion at the bottom of the third trench.
  • the implantation mask may be formed such that an end of the implantation mask in the trench arrangement direction is aligned with the sidewall of the second trench.
  • a method for manufacturing a semiconductor device comprising the steps of forming a trench etch mask on a front surface of a semiconductor substrate, forming a plurality of trenches on the front surface of the semiconductor substrate using the trench etch mask, forming an implantation mask in a first of the plurality of trenches, and injecting a dopant of a second conductivity type into the second trench using the trench etch mask and the implantation mask to form a trench bottom portion at the bottom of a second trench where the implantation mask is not formed.
  • the step of forming the plurality of trenches may further include forming a third trench between the first trench and the second trench, and the step of forming the implantation mask may further include forming the implantation mask in the third trench.
  • the method for manufacturing a semiconductor device may further include a step of diffusing the dopant, and may further include forming the trench bottom portion at the bottom of the third trench.
  • the thickness of the trench etch mask may be 0.3 ⁇ m or more and 1 ⁇ m or less.
  • a method for manufacturing a semiconductor device comprising the steps of forming a plurality of trenches on the front surface of a semiconductor substrate, forming an implantation mask in a first region in which a first trench of the plurality of trenches is formed, implanting a second conductivity type dopant into a second trench of the plurality of trenches and a second mesa portion adjacent to the second trench in a second region in which the implantation mask is not formed, to form a trench bottom portion at the bottom of the second trench, removing the implantation mask from the first region, implanting a second conductivity type dopant into a first mesa portion adjacent to the first trench in the first region, and implanting a second conductivity type dopant into the second mesa portion.
  • a third trench may be formed between the first trench and the second trench, in the step of forming the implantation mask, the implantation mask may be formed in the third trench in the first region, and in the first base implantation step, the second conductivity type dopant may also be implanted into the first mesa portion adjacent to the third trench.
  • the method for manufacturing a semiconductor device may further include a step of diffusing the dopant, and may further include forming the trench bottom portion at the bottom of the third trench.
  • the dose of the second base implantation step may be smaller than the dose of the first base implantation step.
  • the dose of the dopant implanted in the second mesa portion may be equal to the dose of the dopant implanted in the first mesa portion.
  • a semiconductor device in a fifth aspect of the present invention, includes a plurality of trench portions including a first trench portion and a second trench portion, and a trench bottom portion of a second conductivity type provided at the bottom of the second trench portion, and the first trench portion not provided with the trench bottom portion is a dummy trench portion or a dummy gate trench portion.
  • a semiconductor device in a sixth aspect of the present invention, includes a plurality of trench portions including a first trench portion and a second trench portion, a trench bottom portion of a second conductivity type provided at the bottom of the second trench portion, a first gate runner connected to the first trench portion not provided with the trench bottom portion, and a second gate runner different from the first gate runner connected to the second trench portion.
  • a third trench portion is provided between the first trench portion and the second trench portion, and the trench bottom portion is provided at the bottom of the third trench portion, and the third trench portion may be the dummy trench portion or the dummy gate trench portion.
  • a third trench portion may be provided between the first trench portion and the second trench portion, the trench bottom portion may be provided at the bottom of the third trench portion, and the third trench portion may be connected to the first gate runner.
  • a third trench portion may be provided between the first trench portion and the second trench portion, and the trench bottom portion may be provided at the bottom of the third trench portion.
  • the semiconductor device may include a first gate runner connected to the third trench portion, and a second gate runner different from the first gate runner connected to the second trench portion.
  • the first gate runner and the second gate runner may be connected to different gate pads.
  • the first gate runner and the second gate runner may have different gate wiring resistances.
  • the second trench portion adjacent to the first trench portion may be the dummy trench portion or the dummy gate trench portion.
  • the first trench portion adjacent to the second trench portion may be a dummy trench portion or a dummy gate trench portion.
  • FIG. 1 is a diagram illustrating an example of a top surface of a semiconductor device 100 according to a first embodiment.
  • FIG. 2 is a diagram showing an example of a cross section taken along line aa' in FIG.
  • FIG. 2B is an enlarged view of area A in FIG. 2A.
  • 2A to 2C are diagrams illustrating an example of a manufacturing method of the semiconductor device 100 according to the first embodiment.
  • 2A to 2C are diagrams illustrating an example of a manufacturing method of the semiconductor device 100 according to the first embodiment.
  • 10A to 10C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment.
  • 10A to 10C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment.
  • 10A to 10C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment.
  • 10A to 10C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment.
  • 10A to 10C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment.
  • 10A to 10C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment.
  • 10A to 10C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment.
  • FIG. 11 is a diagram showing an example of a cross section of a semiconductor device 200 according to a second embodiment.
  • FIG. 11 is a diagram showing an example of a cross section of a semiconductor device 300 according to a third embodiment.
  • FIG. 13 is a diagram showing an example of a cross section of a semiconductor device 400 according to a fourth embodiment.
  • 10A to 10C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment.
  • 10A to 10C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment.
  • 10A to 10C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment.
  • 10A to 10C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment.
  • FIG. 11 is a diagram showing another example of a cross section of the semiconductor device 200 according to the second embodiment.
  • FIG. 11 is a diagram showing another example of a cross section of the semiconductor device 300 according to the third embodiment.
  • FIG. 13 is a diagram showing another example of a cross section of the semiconductor device 400 according to the fourth embodiment.
  • top or bottom one side in a direction parallel to the depth direction of a semiconductor substrate
  • top or bottom one side in a direction parallel to the depth direction of a semiconductor substrate
  • back the other side
  • the front side one side in a direction parallel to the depth direction of a semiconductor substrate
  • front side one side in a direction parallel to the depth direction of a semiconductor substrate
  • back side one side in a direction parallel to the depth direction of a semiconductor substrate
  • front side one side
  • back side is referred to as the back side.
  • the directions of "top” and “bottom” are not limited to the direction of gravity or the directions when the semiconductor device is mounted.
  • the orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction.
  • the Z-axis does not limit the height direction relative to the ground.
  • the +Z-axis direction and the -Z-axis direction are opposite directions.
  • the Z-axis direction is described without indicating positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.
  • the orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis.
  • the axis perpendicular to the front and back surfaces of the semiconductor substrate is referred to as the Z-axis.
  • the direction of the Z-axis may be referred to as the depth direction.
  • the direction parallel to the front and back surfaces of the semiconductor substrate, including the X-axis and Y-axis may be referred to as the horizontal direction.
  • the conductivity type of a doped region doped with impurities is described as P type or N type.
  • impurities may particularly mean either N type donors or P type acceptors, and may be described as dopants.
  • doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor that exhibits N type conductivity or a semiconductor that exhibits P type conductivity.
  • the doping concentration means the concentration of the donor or the concentration of the acceptor in a thermal equilibrium state.
  • the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge.
  • the donor concentration is N D and the acceptor concentration is N A
  • the net doping concentration at any position is N D -N A.
  • Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves.
  • the VOH defect which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons.
  • chemical concentration refers to the concentration of an impurity that is measured regardless of the state of electrical activation.
  • the chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS).
  • SIMS secondary ion mass spectrometry
  • the above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV method).
  • the carrier concentration measured by spreading resistance measurement (SR method) may be taken as the net doping concentration.
  • the carrier concentration measured by the CV method or SR method may be taken as a value in a thermal equilibrium state.
  • the carrier concentration in that region may be taken as the donor concentration.
  • the carrier concentration in that region may be taken as the acceptor concentration.
  • the peak value may be taken as the concentration of the donor, acceptor or net doping in the region.
  • the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping.
  • the carrier concentration measured by the SR method may be lower than the donor or acceptor concentration.
  • the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.
  • the donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor.
  • the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor is about 99% of the chemical concentration.
  • the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.
  • FIG. 1 is a diagram showing an example of the top surface of a semiconductor device 100 according to the first embodiment.
  • FIG. 1 the positions of each component projected onto the front surface of a semiconductor substrate are shown.
  • FIG. 1 only some of the components of the semiconductor device 100 are shown, and some components are omitted.
  • the semiconductor device 100 includes a semiconductor substrate.
  • top view simply refers to a view from the front surface of the semiconductor substrate.
  • the semiconductor substrate in this example has two sets of edges that face each other when viewed from the top. In FIG. 1, the X-axis and Y-axis are parallel to one of the edges. The Z-axis is perpendicular to the front surface of the semiconductor substrate.
  • the semiconductor substrate has an active portion 160.
  • the active portion 160 is a region through which a main current flows in the depth direction between the front and back surfaces of the semiconductor substrate when the semiconductor device 100 is in operation.
  • the active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT.
  • the active section 160 may further be provided with a diode section including a diode element such as a free wheel diode (FWD).
  • the transistor section 70 has a gate structure having an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film periodically arranged on the front surface side of the semiconductor substrate.
  • the semiconductor device 100 may have one or more pads above the semiconductor substrate.
  • the semiconductor device 100 may have pads such as a gate pad, an anode pad, a cathode pad, and a current detection pad.
  • Each pad is disposed near an edge. The vicinity of an edge refers to the region between the edge and the emitter electrode in a top view.
  • each pad may be connected to an external circuit via wiring such as a wire.
  • a gate potential is applied to the gate pad.
  • the gate pad is electrically connected to the conductive portion of the gate trench portion of the active portion 160.
  • the semiconductor device 100 includes a gate runner 47 that electrically connects the gate pad and the gate trench portion.
  • the gate runner 47 is disposed between the active portion 160 and the edge of the semiconductor substrate when viewed from above.
  • the gate runner 47 surrounds the active portion 160 when viewed from above.
  • the area surrounded by the gate runner 47 when viewed from above may be the active portion 160.
  • the gate runner 47 is composed of either or both of a semiconductor gate runner 48 and a gate metal layer 50.
  • the gate runner 47 comprises a semiconductor gate runner 48 and a gate metal layer 50.
  • the semiconductor gate runner 48 is disposed above the semiconductor substrate.
  • the semiconductor gate runner 48 may be formed of a polycrystalline semiconductor such as polysilicon doped with impurities.
  • the semiconductor gate runner 48 is electrically connected to a gate conductive portion provided inside the gate trench portion via a gate insulating film.
  • the semiconductor device 100 of this example has a breakdown voltage structure portion 190 provided on the outer periphery of the active portion 160.
  • the breakdown voltage structure portion 190 of this example is disposed between the gate runner 47 and the edge.
  • the breakdown voltage structure portion 190 reduces electric field concentration on the front surface side of the semiconductor substrate.
  • the breakdown voltage structure 190 may further include at least one of a field plate 94 and a resurf, which are arranged in a ring shape surrounding the active section 160.
  • the field plate 94 in this example may be made of the same material as the gate metal layer 50 or the emitter electrode 52 and/or polysilicon doped with impurities. In this example, the structure of the breakdown voltage structure 190 other than the field plate 94 will not be described.
  • the semiconductor device 100 may also include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that operates in the same manner as a transistor portion provided in the active portion 160.
  • a temperature sensor not shown
  • a current detector not shown
  • the semiconductor device 100 includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided on the front surface side of a semiconductor substrate.
  • the gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.
  • the semiconductor device 100 of this example also includes a gate metal layer 50 and an emitter electrode 52 provided above the front surface of the semiconductor substrate.
  • the gate metal layer 50 and the emitter electrode 52 are provided separately from each other.
  • the gate metal layer 50 and the emitter electrode 52 are electrically insulated.
  • An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 50 and the front surface of the semiconductor substrate, but is omitted in FIG. 1.
  • contact holes 49, 54, and 56 are provided through the interlayer insulating film. In FIG. 1, each contact hole is hatched with diagonal lines.
  • the emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15.
  • the emitter electrode 52 is electrically connected to the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate by contact holes 54.
  • the emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 by a contact hole 56.
  • a connection portion made of a conductive material, such as polysilicon doped with impurities, may be provided between the emitter electrode 52 and the dummy conductive portion.
  • the connection portion may be provided on the front surface of the semiconductor substrate via an insulating film, such as a dummy insulating film, of the dummy trench portion 30.
  • the gate metal layer 50 is electrically connected to the semiconductor gate runner 48 by a contact hole 49.
  • the semiconductor gate runner 48 may be formed of polysilicon doped with impurities or the like.
  • the semiconductor gate runner 48 connects to the gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate.
  • the semiconductor gate runner 48 is not electrically connected to the dummy conductive portion in the dummy trench portion 30 and the emitter electrode 52. If the semiconductor gate runner 48 and the gate conductive portion are not connected, or if the semiconductor gate runner 48 is not provided, the gate metal layer 50 may be directly connected to the gate conductive portion by the contact hole 49.
  • the semiconductor gate runner 48 and the emitter electrode 52 are electrically isolated by an insulating material such as an interlayer insulating film and an oxide film.
  • the semiconductor gate runner 48 is provided from below the contact hole 49 to the tip 41 of the gate trench portion 40.
  • the gate conductive portion is exposed on the front surface of the semiconductor substrate and is connected to the semiconductor gate runner 48.
  • the emitter electrode 52 and the gate metal layer 50 are formed of a conductive material containing metal.
  • they are formed of aluminum or an alloy mainly composed of aluminum (for example, an aluminum-silicon alloy, etc.).
  • Each electrode may have a barrier metal formed of titanium, a titanium compound, etc. under the region formed of aluminum, etc.
  • each electrode is the emitter electrode 52 and the gate metal layer 50.
  • Each electrode may have a plug formed of tungsten or the like in the contact hole.
  • the plug may have a barrier metal on the side that contacts the semiconductor substrate, with tungsten embedded so as to contact the barrier metal, and may be formed of aluminum or the like on the tungsten.
  • the well region 11 overlaps with the gate runner 47, extends around the periphery of the active portion 160, and is provided in a ring shape when viewed from above.
  • the well region 11 also extends to a predetermined width in an area where it does not overlap with the gate runner 47, and is provided in a ring shape when viewed from above.
  • the well region 11 is provided away from the end of the contact hole 54 in the Y-axis direction toward the gate runner 47.
  • the well region 11 is a region of the second conductivity type that has a higher doping concentration than the base region 14.
  • the gate runner 47 is electrically insulated from the well region 11.
  • the base region 14 is P type
  • the well region 11 is P+ type.
  • the well region 11 is formed from the front surface of the semiconductor substrate to a position deeper than the lower end of the base region 14.
  • the base region 14 is provided in contact with the well region 11. Therefore, the well region 11 is electrically connected to the emitter electrode 52.
  • the transistor section 70 has multiple trench sections arranged in the arrangement direction.
  • the transistor section 70 has one or more gate trench sections 40 arranged along the arrangement direction.
  • the gate trench portion 40 in this example may have two straight portions 39 (portions of the trench that are straight along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two straight portions 39.
  • At least a portion of the tip 41 may be curved when viewed from above.
  • the tip 41 connects the ends of the two straight portions 39 in the Y-axis direction to the semiconductor gate runner 48, and functions as a gate electrode to the gate trench portion 40.
  • electric field concentration at the end can be alleviated more effectively than if it were completed at the straight portion 39.
  • the transistor section 70 may have one or more gate trench sections 40 and one or more dummy trench sections 30 arranged alternately along the arrangement direction.
  • the dummy trench sections 30 are arranged between the respective straight line sections 39 of the gate trench sections 40.
  • One dummy trench section 30 may be arranged between each straight line section 39, or multiple dummy trench sections 30 may be arranged.
  • FIG. 1 two dummy trench sections 30 are arranged between the straight line sections 39, but this is merely an example and is not limited to this.
  • a dummy trench portion 30 does not have to be provided, and a gate trench portion 40 may be provided. With this structure, the electron current from the emitter region 12 can be increased, thereby reducing the on-voltage.
  • the dummy trench portion 30 may have a linear shape extending in the extension direction, and may have a linear portion 29 and a tip portion 31, similar to the gate trench portion 40.
  • the semiconductor device 100 shown in FIG. 1 has only dummy trench portions 30 having tip portions 31 arranged therein, but in other examples, the semiconductor device 100 may include linear dummy trench portions 30 that do not have tip portions 31.
  • the diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30.
  • the ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottoms of each trench portion in the depth direction are covered by the well region 11.
  • the trench portion provided at the ends in the X-axis direction may be covered by the well region 11. This can alleviate electric field concentration at the bottoms of each trench portion.
  • a mesa portion refers to a region inside the semiconductor substrate that is sandwiched between the trench portions.
  • the depth position of the mesa portion is from the front surface of the semiconductor substrate to the bottom of the trench portion.
  • the mesa portion is sandwiched between adjacent trench portions in the X-axis direction, and is provided on the front surface of the semiconductor substrate, extending in the extension direction (Y-axis direction) along the trenches.
  • Each mesa portion has a base region 14.
  • at least one of an emitter region 12 of a first conductivity type and a contact region 15 of a second conductivity type may be provided in a region sandwiched between the base regions 14 in a top view.
  • the emitter region 12 is N+ type
  • the contact region 15 is P+ type.
  • the emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate in the depth direction.
  • the mesa portion has an emitter region 12 exposed on the front surface of the semiconductor substrate.
  • the emitter region 12 is provided in contact with the gate trench portion 40.
  • the mesa portion in contact with the gate trench portion 40 has a contact region 15 exposed on the front surface of the semiconductor substrate.
  • the contact regions 15 and emitter regions 12 in the mesa portion are each provided from one trench portion to the other trench portion in the X-axis direction.
  • the contact regions 15 and emitter regions 12 in the mesa portion are alternately arranged along the extension direction of the trench portion (Y-axis direction).
  • the contact region 15 and emitter region 12 of the mesa portion may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion.
  • the emitter region 12 is provided in a region that contacts the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.
  • a contact hole 54 is provided above each mesa portion.
  • the contact holes 54 are arranged in a region sandwiched between the base regions 14 in the extension direction (Y-axis direction). In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12.
  • the contact holes 54 may be arranged in the center in the arrangement direction of the mesa portions (X-axis direction).
  • FIG. 2A is a diagram showing an example of the a-a' cross section in FIG. 1.
  • FIG. 2B is an enlarged view of region A in FIG. 2A.
  • the a-a' cross section is an XZ plane passing through the emitter region 12, the contact region 15, the base region 14, the gate trench portion 40, and the dummy trench portion 30.
  • the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.
  • the breakdown voltage structure 190 may have a guard ring 92.
  • the guard ring 92 is a P-type region that contacts the front surface 21 of the semiconductor substrate 10.
  • the guard ring 92 is electrically connected to the field plate 94.
  • contact holes are drawn in the interlayer insulating film 38 to show the electrical connection between the guard ring 92 and the field plate 94, but this does not necessarily indicate that there are contact holes on the a-a' cross section.
  • the interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10.
  • the interlayer insulating film 38 is an insulating film such as silicate glass doped with impurities such as boron or phosphorus.
  • the interlayer insulating film 38 may be in contact with the front surface 21, or another film such as an oxide film may be provided between the interlayer insulating film 38 and the front surface 21.
  • the interlayer insulating film 38 has a contact hole 54 as described in FIG. 1.
  • the emitter electrode 52 is provided on the front surface 21 of the semiconductor substrate 10 and on the upper surface of the interlayer insulating film 38.
  • the emitter electrode 52 is electrically connected to the front surface 21 through a contact hole 54 in the interlayer insulating film 38.
  • a plug and/or barrier metal such as tungsten (W) may be provided inside the contact hole 54.
  • a P++ type plug region (not shown) having a higher doping concentration than the contact region 15 may be provided under the contact hole in which the plug and/or barrier metal is provided.
  • the plug region improves the contact resistance between the barrier metal and the P type region including the well region 11, the base region 14, and the contact region 15. Improving the contact resistance between the barrier metal and the contact region 15 improves the latch-up resistance.
  • the collector electrode 24 is provided on the rear surface 23 of the semiconductor substrate 10.
  • the emitter electrode 52 and the collector electrode 24 are formed of a material containing a metal or a laminate film thereof.
  • the semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc.
  • the semiconductor substrate 10 in this example is a silicon substrate.
  • the semiconductor substrate 10 has a drift region 18 of a first conductivity type.
  • the drift region 18 is N-type.
  • the drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being provided.
  • the accumulation region 16 is a region in which the same dopant as the drift region 18 accumulates at a higher concentration than the drift region 18.
  • the doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18.
  • the accumulation region 16 is N-type.
  • dopants for the accumulation region 16 include arsenic (As), phosphorus (P), and antimony (Sb).
  • the accumulation region 16 in this example may be provided between the base region 14 and a trench bottom portion 75 described below.
  • the upper end of the accumulation region 16 in this example contacts the base region 14, and the lower end contacts the trench bottom portion 75.
  • a drift region 18 may be interposed between the lower end of the accumulation region 16 and the upper end of the trench bottom portion 75.
  • an emitter region 12 is provided in contact with the front surface 21 of the semiconductor substrate 10.
  • the emitter region 12 is provided in contact with the gate trench portion 40.
  • the doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. Examples of dopants for the emitter region 12 include arsenic (As), phosphorus (P), and antimony (Sb).
  • a buffer region 20 of a first conductivity type may be provided below the drift region 18.
  • the buffer region 20 is N-type.
  • the doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18.
  • a collector region 22 is provided below the buffer region 20.
  • the collector region 22 is P+ type, for example.
  • the buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22.
  • the semiconductor substrate 10 is provided with a gate trench portion 40 and a dummy trench portion 30.
  • the gate trench portion 40 and the dummy trench portion 30 are provided so as to penetrate from the front surface 21 through the base region 14 and the accumulation region 16 to reach the drift region 18.
  • the trench portion penetrating the doping region is not limited to being manufactured in the order of forming the doping region and then the trench portion.
  • the trench portion penetrating the doping region also includes being manufactured in the order of forming the trench portion and then forming the doping region between the trench portions.
  • the gate trench portion 40 has a gate trench provided on the front surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44.
  • the gate insulating film 42 is provided to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed of an oxide film or a nitride film.
  • the gate conductive portion 44 is provided so as to fill the inside of the gate trench more inward than the gate insulating film 42.
  • the upper surface of the gate conductive portion 44 may be in the same XY plane as the front surface 21.
  • the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10.
  • the gate conductive portion 44 is formed of polysilicon doped with impurities, etc.
  • the gate conductive portion 44 may be provided longer than the base region 14 in the depth direction.
  • the gate trench portion 40 is covered by an interlayer insulating film 38 on the front surface 21.
  • a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40 in the XZ cross section.
  • the dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the front surface 21 of the semiconductor substrate 10.
  • the dummy insulating film 32 is provided to cover the inner wall of the dummy trench.
  • the dummy insulating film 32 may be formed of an oxide film or a nitride film.
  • the dummy conductive portion 34 is provided so as to fill the inside of the dummy trench more inward than the dummy insulating film 32.
  • the upper surface of the dummy conductive portion 34 may be in the same XY plane as the front surface 21.
  • the dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.
  • the dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.
  • the gate trench portion 40 and the dummy trench portion 30 in this example are covered by an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10.
  • the bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in the XZ cross section).
  • a P-type trench bottom portion 75 is provided at the bottom of the trench portion.
  • the trench bottom portion 75 is provided below the accumulation region 16.
  • the lower end of the trench bottom portion 75 may be located below the bottom of the gate trench portion 40.
  • the trench bottom portion 75 may cover the bottom of the gate trench portion 40.
  • the trench bottom portion 75 may be an electrically floating layer.
  • a floating layer refers to a layer that is not electrically connected to any electrode, such as the emitter electrode 52.
  • Providing the trench bottom portion 75 improves the turn-on characteristics of the transistor portion 70.
  • Providing the trench bottom portion 75 also alleviates electric field concentration at the bottom of the gate trench portion 40, improving the avalanche resistance.
  • the transistor section 70 may have an electron passing region 76 in which no trench bottom section 75 is provided when viewed from above.
  • the electron passing region 76 may have an accumulation region 16.
  • the accumulation region 16 may not be provided.
  • the trench bottom section 75 may be an electrically floating layer provided closer to the center of the active section 160 than the electron passing region 76.
  • the trench bottom section 75 may also have a region in contact with the well region 11, provided closer to the voltage-resistant structure section 190 than the electron passing region 76.
  • the electron passage region 76 separates the trench bottom portion 75 on the central side of the active portion 160 from the well region 11, which is fixed at the emitter potential, and electrically floats it, so that when the transistor portion 70 is conductive, electrons can flow through the trench bottom portion 75 on the central side of the active portion 160. Also, when the transistor portion 70 is conductive, electrons can flow through the electron passage region 76.
  • FIGS. 3A and 3B are diagrams showing an example of a method for manufacturing the semiconductor device 100 according to the first embodiment.
  • the process related to the formation of the trench bottom portion 75 is mainly described, and the other processes are not described.
  • a trench etch mask 60 is formed on the front surface 21 of the semiconductor substrate 10, and multiple trenches are formed by etching using the trench etch mask 60.
  • the trenches are formed by etching to a depth that reaches the region that will become the drift region 18 (the region that will remain without other doping regions being provided in the subsequent doping region formation process).
  • an oxide film having a thickness of 50 nm to 200 nm is formed.
  • the trench etch mask 60 may be removed before the oxide film is formed.
  • An implantation mask 62 is formed in those trenches that do not have a trench bottom portion 75 formed at their bottom.
  • the implantation mask 62 is a resist mask.
  • first trenches those trenches that do not have a trench bottom portion 75 formed at their bottom
  • second trenches those trenches that have a trench bottom portion 75 formed at their bottom.
  • the upper surface of the implantation mask 62 is provided in the Z-axis direction at the same position as the front surface 21 of the semiconductor substrate 10 or at a position deeper than the front surface 21 of the semiconductor substrate 10.
  • the implantation mask 62 in this example is not provided on the mesa portion, but only in the first trench.
  • a P-type dopant is ion-implanted to form trench bottom portion 75.
  • the dopant is ion-implanted vertically from above the multiple trenches toward the bottom of the trench portion.
  • the dose amount may be adjusted as appropriate to achieve a predetermined doping concentration.
  • One example of the P-type dopant is boron (B).
  • the P-type dopant is implanted into the second trench where the implantation mask 62 is not formed. Furthermore, the P-type dopant is also implanted into the mesa portion where the implantation mask 62 is not formed.
  • the mesa portion adjacent to the first trench may be referred to as the first mesa portion
  • the mesa portion adjacent to the second trench may be referred to as the second mesa portion.
  • the side of the first trench may be regarded as the first mesa portion
  • the side of the second trench may be regarded as the second mesa portion.
  • the P-type dopant is also implanted into the first mesa portion and the second mesa portion.
  • the implantation depth of the P-type dopant in the first mesa portion and the second mesa portion is indicated by a dashed line.
  • step S150 the oxide film is removed from the side walls and mesa portions of the multiple trenches, and then in step S160, an oxide film is formed on the side walls of the multiple trenches.
  • This oxide film becomes the dummy insulating film 32 and the gate insulating film 42.
  • the multiple trenches whose side walls are covered with the dummy insulating film 32 and the gate insulating film 42 are filled with polysilicon doped with impurities to form the dummy conductive portion 34 and the gate conductive portion 44, respectively.
  • Excess polysilicon deposited on the front surface 21 of the semiconductor substrate 10 is removed by etching, and the dummy trench portion 30 and the gate trench portion 40 are formed.
  • step S170 dopants for forming the base region 14 and the like are ion-implanted into the front surface 21 of the semiconductor substrate 10, and then a doped region is formed by thermal diffusion.
  • the P-type dopant implanted into the bottom of the second trench in step S140 diffuses in the trench arrangement direction (X-axis direction), forming a trench bottom portion 75 that extends in the trench arrangement direction (X-axis direction) across multiple second trenches.
  • doped regions such as the base region 14, emitter region 12, contact region 15, and accumulation region 16 are also formed.
  • step S140 a P-type dopant is injected into the mesa portion.
  • the P-type dopant is injected evenly into the first mesa portion and the second mesa portion. Therefore, even after the doping region formation process in step S170, the dose amount of the P-type dopant injected into the first mesa portion and the second mesa portion is uniform, and the doping concentration of the base region 14 is uniform. Therefore, regardless of whether a trench bottom portion 75 is provided at the bottom, the threshold voltage of the mesa portion in contact with the gate trench portion 40 can be made uniform.
  • FIGS. 4A and 4B are diagrams showing another example of a method for manufacturing the semiconductor device 100 according to the first embodiment. This example differs from the example of FIGS. 3A and 3B in the process of forming the implantation mask 62. Here, the differences from the example of FIGS. 3A and 3B will be mainly described, and a description of the common processes will be omitted.
  • Steps S200 to S220 are the same as steps S100 to S120 in FIG. 3A.
  • an implantation mask 62 is formed in a trench (i.e., a first trench) that does not have a trench bottom portion 75 at its bottom, on the top surface of a mesa portion (i.e., a first mesa portion) adjacent to the first trench, and on the top surface of a mesa portion (i.e., a second mesa portion) adjacent to a trench (i.e., a second trench) that has a trench bottom portion 75 at its bottom.
  • the implantation mask 62 is formed so that its end in the trench arrangement direction (X-axis direction) is aligned with the sidewall of the second trench.
  • the upper end of the trench sidewall is the point where it intersects with the front surface 21 of the semiconductor substrate 10
  • the implantation mask 62 being aligned with the trench sidewall means that the end of the implantation mask 62 is located at the upper end of the trench sidewall in the trench arrangement direction (X-axis direction).
  • the implantation mask 62 in this example is provided so as to cover not only the inside of the first trench, but also both the first mesa portion and the second mesa portion.
  • a P-type dopant is ion-implanted to form trench bottom portion 75.
  • the dopant is ion-implanted vertically from above the multiple trenches toward the bottom of the trench portion.
  • the dose amount may be adjusted appropriately to achieve a predetermined doping concentration.
  • One example of the P-type dopant is boron (B).
  • the P-type dopant is implanted into the second trench where the implantation mask 62 is not formed. However, the P-type dopant is not implanted into the mesa portion where the implantation mask 62 is formed. That is, in this example, the P-type dopant is implanted only into the second trench.
  • steps S250 to S270 the oxide film is removed from the sidewalls of the multiple trenches, and then the dummy trench portion 30, the gate trench portion 40, and the doping region are formed. However, since this is the same as steps S150 to S170, a description thereof will be omitted.
  • step S240 the P-type dopant is injected only into the second trench, and not into either the first or second mesa portion. Therefore, prior to the doping region formation process of step S270, the P-type dopant is not injected into any of the mesa portions, and in the doping region formation process of step S270, the P-type dopant is injected evenly into the first and second mesa portions. Therefore, the doping concentration of the base region 14 is uniform in both mesa portions, and therefore the threshold voltages of the mesa portions in contact with the gate trench portion 40 can be made uniform, regardless of whether a trench bottom portion 75 is provided at the bottom.
  • FIGS. 5A and 5B are diagrams showing another example of a method for manufacturing a semiconductor device 100 according to the first embodiment. This example differs from the example shown in FIGS. 3A and 3B in the process of forming a trench etch mask 60. Here, the differences from the example shown in FIGS. 3A and 3B will be mainly described, and a description of the common processes will be omitted.
  • a trench etch mask 60 is formed on the front surface 21 of the semiconductor substrate 10, and multiple trenches are formed by etching using the trench etch mask 60.
  • the thickness T of the trench etch mask 60 is 0.3 ⁇ m or more and 1 ⁇ m or less.
  • the thickness T of the trench etch mask 60 in this example is greater than the thickness of the trench etch mask 60 used in the example shown in Figures 3A and 3B.
  • a P-type dopant is ion-implanted to form trench bottom portion 75 using trench etch mask 60 and implantation mask 62.
  • the P-type dopant is implanted into the second trench where implantation mask 62 is not formed.
  • the P-type dopant is not implanted into the mesa portion where trench etch mask 60 remains. That is, in this example, the P-type dopant is implanted only into the second trench.
  • step S350 the trench etch mask 60 provided on the top surface of the mesa portion and the oxide film provided on the side walls of the multiple trenches are removed.
  • steps S350 to S370 the dummy trench portion 30, the gate trench portion 40, and the doping region are formed, but since these steps are common to steps S160 to S170, their explanation will be omitted.
  • the trench etch mask 60 formed thick in step S300 is also used in the trench bottom portion 75 formation process in step S340, so the P-type dopant is only implanted into the second trench, and not into the mesa portion. Therefore, no P-type dopant is implanted into any of the mesa portions prior to the doping region formation process in step S370, and the P-type dopant is uniformly implanted into the mesa portions in the doping region formation process in step S370. Therefore, the doping concentration of the base region 14 is uniform in all mesa portions, so that the threshold voltages of the mesa portions in contact with the gate trench portion 40 can be made uniform regardless of whether or not a trench bottom portion 75 is provided at the bottom.
  • the trench etch mask 60 can have a sufficient thickness to be usable as an implantation mask even after etching.
  • FIGS. 6A to 6C are diagrams showing another example of a method for manufacturing the semiconductor device 100 according to the first embodiment. This example differs from the example shown in FIGS. 3A and 3B in the process of forming the doping region. Here, the differences from the example shown in FIGS. 3A and 3B will be mainly described, and a description of the common processes will be omitted.
  • Step S400 is the same as step S100 in FIG. 3A.
  • an implantation mask 62 is formed in a first region R1 in which a trench (i.e., a first trench) that does not have a trench bottom portion 75 formed at its bottom is formed.
  • the implantation mask 62 in this example may be provided only in the first trench, or may be provided in the first trench and on a mesa portion adjacent to the first trench in the first region R1 (i.e., a first mesa portion).
  • a P-type dopant is ion-implanted in the second region R2 where the implantation mask 62 is not formed to form the trench bottom portion 75.
  • the P-type dopant is implanted in the second region R2 into the second trench where the implantation mask 62 is not formed and into the mesa portion adjacent to the second trench (i.e., the second mesa portion).
  • the implantation depth of the P-type dopant in the first mesa portion and the second mesa portion is indicated by a dashed line.
  • steps S450 to S460 the oxide film is removed from the sidewalls of the multiple trenches, and then the dummy trench portion 30, the gate trench portion 40, and the doping region are formed. However, since this is common to steps S160 to S170, the description will be omitted.
  • step S462 a P-type dopant is injected into the first mesa portion adjacent to the first trench in the first region R1 to form the base region 14.
  • step S464 a P-type dopant is injected into the second mesa portion to form the base region 14.
  • step S464 the dose of P-type dopant implanted into the second mesa portion of the second region R2 is smaller than the dose of P-type dopant implanted into the first mesa portion of the first region R1 in step S462.
  • the dose of P-type dopant implanted into the second mesa portion i.e., the total dose of P-type dopant implanted into the second mesa portion in steps S440 and S464, is equal to the dose of P-type dopant implanted into the first mesa portion. Note that either of the P-type dopant implantation processes in steps S462 and S464 may be performed first.
  • step S470 dopants for forming emitter regions 12 and the like are ion-implanted into the front surface 21 of the semiconductor substrate 10, and then doped regions are formed by thermal diffusion.
  • the P-type dopant implanted into the bottom of the second trench in step S440 diffuses in the trench arrangement direction (X-axis direction), forming trench bottom portions 75 that extend in the trench arrangement direction (X-axis direction) across multiple second trenches.
  • doped regions such as the base region 14, emitter region 12, contact region 15, and accumulation region 16 are also formed.
  • step S440 a P-type dopant is implanted into the second mesa portion of the second region R2.
  • the doses of P-type dopant implanted into the first mesa portion and the second mesa portion become uniform, and the doping concentration of the base region 14 becomes uniform. Therefore, regardless of whether a trench bottom portion 75 is provided at the bottom, the threshold voltages of the mesa portions in contact with the gate trench portion 40 can be made uniform.
  • FIG. 7A is a diagram showing an example of a cross section of a semiconductor device 200 according to a second embodiment.
  • common reference numerals are used to designate components common to the semiconductor device 100, and the following description focuses on the differences from the semiconductor device 100.
  • the semiconductor device 200 of this example has a plurality of trench portions including a gate trench portion 40 and a dummy trench portion 30.
  • a trench portion that does not have a trench bottom portion 75 at its bottom may be referred to as a first trench portion
  • a trench portion that has a trench bottom portion 75 at its bottom may be referred to as a second trench portion.
  • FIG. 7A shows a schematic diagram of the connection between the trench portion and the electrode of the semiconductor device 200 of this example.
  • a region in which a plurality of first trench portions without trench bottom portions 75 are continuously arranged and a region in which a plurality of second trench portions with trench bottom portions 75 are continuously arranged are alternately arranged in the trench arrangement direction (X-axis direction).
  • the region in which a plurality of first trench portions are continuously arranged constitutes an electron passage region 76.
  • the trench bottom portions 75 are arranged to extend in the trench arrangement direction (X-axis direction) across the plurality of continuously arranged second trench portions.
  • the first trench portions arranged in series are dummy trench portions 30 that are set to the emitter potential.
  • the mesa portion (i.e., the second mesa portion) adjacent to the trench in which the trench bottom portion 75 is formed i.e., the second trench
  • the mesa portion (i.e., the first mesa portion) adjacent to the trench in which the trench bottom portion 75 is not formed i.e., the first trench) is covered with the implantation mask 62.
  • the dose of P-type dopant implanted in the first mesa portion is less than the dose of P-type dopant implanted in the second mesa portion, and there is a possibility that the threshold voltage of the first mesa portion is lower than the threshold voltage of the second mesa portion.
  • the first trench portion is a dummy trench portion 30 that is not connected to the gate pad G.
  • the gate trench portion 40 by making only the trench portion that is not in contact with the first mesa portion the gate trench portion 40, it is possible to align the threshold voltages of the mesa portions in contact with the gate trench portion 40.
  • the second trench portion is a gate trench portion 40 set to the gate potential or a dummy trench portion 30 set to the emitter potential.
  • the second trench portion may also include a dummy gate trench portion 45 shown in FIG. 7C.
  • the dummy gate trench portion 45 refers to a trench portion that is set to the gate potential and is not in contact with the emitter region 12.
  • the gate trench portion 40 is electrically connected to the gate pad G via a gate runner 47 or the like.
  • the P-type dopant implanted on the side of the second trench portion may diffuse to the side of the first trench portion (first mesa portion) where the P-type dopant is not implanted, thereby decreasing the doping concentration of the base region 14 of the second mesa portion. Therefore, the second mesa portion between the first trench portion and the second trench portion may have a lower threshold voltage than the second mesa portion between the second trench portions. Therefore, the second trench portion adjacent to the first trench portion may be a dummy trench portion 30 or a dummy gate trench portion 45.
  • the emitter region 12 may be provided in the second mesa portion on the side of the adjacent second trench portion to operate the second trench portion as a gate trench portion 40, and the emitter region 12 may not be provided in the second mesa portion on the side of the adjacent first trench portion.
  • the second trench portion may be a gate trench portion 40 having the emitter region 12 in the second mesa portions on both sides.
  • FIG. 7B is a diagram showing an example of a cross section of a semiconductor device 300 according to Example 3.
  • common reference numerals are used to designate components common to the semiconductor device 100, and differences will be mainly described.
  • FIG. 7B shows a schematic diagram of the connection between the trench portion and the electrodes of the semiconductor device 300 of this example.
  • the multiple first trench portions arranged continuously in the trench arrangement direction (X-axis direction) have their gate trench portions 40 connected to gate pad G1 via gate runner 47-1
  • the multiple second trench portions arranged continuously in the trench arrangement direction (X-axis direction) have their gate trench portions 40 connected to gate pad G2 via gate runner 47-2.
  • the dummy trench portions 30 are connected to the emitter electrode 52 and are set to the emitter potential.
  • the dose of P-type dopant implanted into the mesa portion (i.e., the first mesa portion) adjacent to the trench in which the trench bottom portion 75 is not formed (i.e., the first trench) is different from the dose of P-type dopant implanted into the mesa portion (i.e., the second mesa portion) adjacent to the trench in which the trench bottom portion 75 is formed (i.e., the second trench).
  • the gate trench portions 40 of the multiple first trench portions and the multiple second trench portions are connected to different gate pads via different gate runners. This allows the gate pads G1 and G2 to send signals at different timings depending on the difference in threshold voltage, thereby aligning the on/off timing of the first trench portions and the multiple second trench portions.
  • the first gate runner 47-1 and the second gate runner 47-2 may have different gate wiring resistances.
  • the first gate runner 47-1 and the second gate runner 47-2 may have resistors with different resistance values inserted in the middle of the path, may be made of materials with different resistances, or may have different cross-sectional areas.
  • the signal transmission speed to the first trench portion and the second trench portion differs depending on the gate wiring resistance of the gate runner 47-1 and the second gate runner 47-2, so that the on/off timing of the first trench portion and the multiple second trench portions can be aligned.
  • the second trench portion adjacent to the first trench portion may be a dummy trench portion 30 or a dummy gate trench portion 45, or may be a gate trench portion 40 if the concentration difference between the adjacent base regions 14 is small.
  • the other second trench portions may include a dummy gate trench portion 45.
  • the P-type dopant implanted on the side of the second trench portion may diffuse to the side of the first trench portion (first mesa portion) where the P-type dopant is not implanted, and the concentration of the base region 14 of the first mesa portion may increase.
  • the threshold voltage may be higher in the first mesa portion between the first trench portion and the second trench portion than in the one mesa portion between the first trench portions. Therefore, the first trench portion adjacent to the second trench portion may be the dummy trench portion 30 or the dummy gate trench portion 45.
  • the emitter region 12 may be provided in the first mesa portion on the side of the adjacent first trench portion to operate the first trench portion as the gate trench portion 40, and the emitter region 12 may not be provided in the first mesa portion on the side of the adjacent second trench portion.
  • the first trench portion may be a gate trench portion 40 having an emitter region 12 in the first mesa portions on both sides.
  • the other first trench portions may include a dummy gate trench portion 45.
  • FIG. 7C is a diagram showing an example of a cross section of a semiconductor device 400 according to Example 4.
  • common reference numerals are used to designate components common to the semiconductor device 100, and differences will be mainly described.
  • FIG. 7C shows a schematic diagram of the connection between the trench portions and electrodes of the semiconductor device 400 of this example.
  • the dummy gate trench portions 45 of the multiple first trench portions arranged continuously in the trench arrangement direction (X-axis direction) and the gate trench portions 40 of the multiple second trench portions arranged continuously in the trench arrangement direction (X-axis direction) are connected to the gate pad G via the gate runner 47.
  • the dummy gate trench portion 45 refers to a trench portion that is set to a gate potential and is not in contact with the emitter region 12.
  • the dummy trench portion 30 is connected to the emitter electrode 52 and is set to an emitter potential.
  • the dose of P-type dopant implanted into the mesa portion (i.e., the first mesa portion) adjacent to the trench in which the trench bottom portion 75 is not formed (i.e., the first trench) is different from the dose of P-type dopant implanted into the mesa portion (i.e., the second mesa portion) adjacent to the trench in which the trench bottom portion 75 is formed (i.e., the second trench).
  • the dummy gate trench portions 45 of the multiple first trench portions and the gate trench portions 40 of the multiple second trench portions are connected to a gate pad via a gate runner. Since the first trench portion is a dummy gate trench portion 45 that is not in contact with the emitter region 12, even if the base region 14 forms an inversion channel, electrons do not conduct from the front surface 21. Since the second trench portion is a gate trench portion 40 that has an emitter region 12, the base region 14 forms an inversion channel and electrons conduct from the front surface 21. As described above, by making only the trench portion that is not in contact with the first mesa portion into the gate trench portion 40, the threshold voltage of the mesa portion in contact with the gate trench portion 40 can be made uniform.
  • the contact region 15 is provided in place of the emitter region 12 in contact with the dummy gate trench portion 45, but this is not limited thereto.
  • the contact region 15 may be not formed but may be the base region 14.
  • the emitter region 12 may not be formed adjacent to the dummy trench portion 30 of the first trench portion.
  • the second trench portion adjacent to the first trench portion may be the dummy trench portion 30 or the dummy gate trench portion 45, or may be the gate trench portion 40 if the concentration difference between the adjacent base regions 14 is small.
  • the other second trench portions may include the dummy gate trench portion 45.
  • the present invention also applies to cases in which the diffusion width of the P-type impurities is different. Even in cases in which the diffusion of the P-type impurities is narrow and not connected to each other, and the trench bottom portions 75 are formed discretely, the above invention can be applied in the same way to align the threshold values of each mesa portion.
  • the threshold value of each mesa portion can be made uniform by treating the trench portion (sometimes called the third trench portion) as being similar to the first trench portion.
  • FIG. 8A is a diagram showing an example of a manufacturing method for the semiconductor device 100 according to the first embodiment when a third trench is included.
  • changes related to the third trench from the process shown in FIGS. 3A and 3B are mainly described, and descriptions of other processes are omitted.
  • an oxide film having a thickness of 50 nm to 200 nm is formed on the third trench 73, similar to the first and second trenches.
  • the trench etch mask 60 may be removed before the oxide film is formed.
  • an implantation mask 62 is formed in the third trench 73, similar to the first trench.
  • the implantation mask 62 in this example is a resist mask.
  • the upper surface of the implantation mask 62 is provided in the Z-axis direction at the same position as the front surface 21 of the semiconductor substrate 10 or at a position deeper than the front surface 21 of the semiconductor substrate 10.
  • the implantation mask 62 in this example is not provided on the mesa portion, but only in the first trench and the third trench 73.
  • a P-type dopant is ion-implanted to form a trench bottom portion 75.
  • the P-type dopant is implanted into the second trench where the implantation mask 62 is not formed. Furthermore, the P-type dopant is also implanted into the mesa portion where the implantation mask 62 is not formed.
  • the mesa portion adjacent to the first trench and the third trench 73 may be referred to as the first mesa portion
  • the mesa portion adjacent to the second trench may be referred to as the second mesa portion.
  • the third trench 73 side may be regarded as the first mesa portion, and the second trench side may be regarded as the second mesa portion.
  • the P-type dopant is also implanted into the first mesa portion and the second mesa portion.
  • the implantation depth of the P-type dopant in the first mesa portion and the second mesa portion is indicated by a dashed line.
  • dummy trench portions 30 and gate trench portions 40 may be formed in multiple trenches including the third trench 73 as shown in FIG. 3B.
  • step S170 dopants for forming the base region 14 and the like are ion-implanted into the front surface 21 of the semiconductor substrate 10, and then a doping region is formed by thermal diffusion.
  • the P-type dopant implanted in the bottom of the second trench in step S140 diffuses in the trench arrangement direction (X-axis direction), forming a trench bottom portion 75 that extends in the trench arrangement direction (X-axis direction) across multiple second trenches, and at this time, a trench bottom portion 75 is also formed at the bottom of the third trench 73.
  • two third trenches are provided and formed as a gate trench portion 40 and a dummy trench portion 30, but three or more may be provided, and if only one is provided, it may be formed as a gate trench portion 40 or as a dummy trench portion 30.
  • FIG. 8B is a diagram showing another example of a method for manufacturing the semiconductor device 100 according to the first embodiment when a third trench is included.
  • changes related to the third trench from the process shown in FIGS. 4A and 4B are mainly described, and descriptions of other processes are omitted.
  • an implantation mask 62 is formed in the trenches (i.e., the first trench and the third trench 73) into which the P-type dopant is not implanted to form the trench bottom portion 75 at the bottom, on the top surface of the mesa portion (i.e., the first mesa portion) adjacent to the first trench, and on the top surface of the mesa portion (i.e., the second mesa portion and the first mesa portion) adjacent to the trench (i.e., the second trench) into which the P-type dopant is implanted to form the trench bottom portion 75 at the bottom.
  • a P-type dopant is ion-implanted to form trench bottom portion 75.
  • the P-type dopant is implanted into the second trench where implantation mask 62 is not formed. However, the P-type dopant is not implanted into the mesa portion where implantation mask 62 is formed. That is, in this example, the P-type dopant is implanted only into the second trench.
  • dummy trench portions 30 and gate trench portions 40 may be formed in multiple trenches including the third trench 73 as shown in FIG. 4B.
  • step S270 dopants for forming the base region 14 and the like are ion-implanted into the front surface 21 of the semiconductor substrate 10, and then a doping region is formed by thermal diffusion.
  • the P-type dopant implanted in the bottom of the second trench in step S240 diffuses in the trench arrangement direction (X-axis direction), forming a trench bottom portion 75 that extends in the trench arrangement direction (X-axis direction) across multiple second trenches, and at this time, a trench bottom portion 75 is also formed at the bottom of the third trench 73.
  • two third trenches are provided and formed as a gate trench portion 40 and a dummy trench portion 30, but three or more may be provided, and if only one is provided, it may be formed as a gate trench portion 40 or as a dummy trench portion 30.
  • FIG. 8C is a diagram showing another example of a method for manufacturing the semiconductor device 100 according to the first embodiment when a third trench is included.
  • the changes related to the third trench from the process shown in FIGS. 5A and 5B are mainly described, and the other processes are not described.
  • step S330 an implantation mask 62 is formed inside the third trench 73 and the first trench.
  • a P-type dopant is ion-implanted to form trench bottom portion 75 using trench etch mask 60 and implantation mask 62.
  • the P-type dopant is implanted into the second trench where implantation mask 62 is not formed.
  • the P-type dopant is not implanted into the mesa portion where trench etch mask 60 remains. That is, in this example, the P-type dopant is implanted only into the second trench, and is not implanted into the first mesa portion, the second mesa portion, the first trench, or the third trench 73.
  • dummy trench portions 30 and gate trench portions 40 may be formed in multiple trenches including the third trench 73 as shown in FIG. 5B.
  • step S370 dopants for forming the base region 14 and the like are ion-implanted into the front surface 21 of the semiconductor substrate 10, and then a doping region is formed by thermal diffusion.
  • the P-type dopant implanted in the bottom of the second trench in step S340 diffuses in the trench arrangement direction (X-axis direction), forming a trench bottom portion 75 that extends in the trench arrangement direction (X-axis direction) across multiple second trenches, and at this time, a trench bottom portion 75 is also formed at the bottom of the third trench 73.
  • two third trenches are provided and formed as a gate trench portion 40 and a dummy trench portion 30, but three or more may be provided, and if only one is provided, it may be formed as a gate trench portion 40 or as a dummy trench portion 30.
  • FIG. 8D is a diagram showing another example of a method for manufacturing the semiconductor device 100 according to the first embodiment when a third trench is included.
  • the changes related to the third trench from the process shown in FIGS. 6A to 6C are mainly described, and the description of other processes is omitted.
  • step S430 an implantation mask 62 is formed in the third trench 73, inside the first trench, and on the first mesa portion in the first region R1.
  • a P-type dopant is ion-implanted into the second region R2 to form a trench bottom portion 75.
  • steps S450 and S460 a dummy trench portion 30 and a gate trench portion 40 may be formed in a plurality of trenches including the third trench 73 as shown in FIG. 6B.
  • step S462 a P-type dopant is implanted into the first mesa portion adjacent to the first trench and the third trench in the first region R1 to form a base region 14.
  • step S464 a P-type dopant is injected into the second mesa portion adjacent to the second trench in the second region R2 to form the base region 14.
  • step S470 a doping region is formed by thermal diffusion.
  • the P-type dopant injected into the bottom of the second trench in step S440 diffuses in the trench arrangement direction (X-axis direction), and a trench bottom portion 75 is formed that extends in the trench arrangement direction (X-axis direction) across multiple second trenches, and at this time, a trench bottom portion 75 is also formed at the bottom of the third trench 73. Note that in FIG.
  • two third trenches are provided and formed as a gate trench portion 40 and a dummy trench portion 30, but three or more may be provided, and if only one is provided, it may be formed as a gate trench portion 40 or a dummy trench portion 30.
  • FIG. 9A is a diagram showing an example of a cross section of a semiconductor device 200 according to a second embodiment having a third trench portion.
  • changes related to the third trench portion from the semiconductor device shown in FIG. 7A are described, and descriptions of other structures are omitted.
  • the trench portion located at the end of trench bottom portion 75 was the second trench.
  • the trench portion located at the end of trench bottom portion 75 is the third trench 73, and ion implantation to form trench bottom portion 75 is not performed on the adjacent first mesa portion.
  • the third trench 73 is formed as a dummy trench portion 30, no channel is formed in the first mesa portion adjacent to the third trench 73, and no deviation in threshold voltage between the conductive mesa portions occurs.
  • two third trenches 73 are provided, but three or more may be provided, or only one may be provided.
  • FIG. 9B is a diagram showing an example of a cross section of a semiconductor device 300 according to Example 3 having a third trench portion.
  • changes related to the third trench portion from the semiconductor device shown in FIG. 7B are explained, and explanations of other structures are omitted.
  • the trench portion located at the end of the trench bottom portion 75 was the second trench.
  • the trench portion located at the end of the trench bottom portion 75 is the third trench 73, and ion implantation to form the trench bottom portion 75 is not performed on the adjacent first mesa portion.
  • the third trench 73 is formed as the gate trench portion 40, but is connected to the gate runner 47-1 like the first trench of the electron passage region 76. In the first mesa portion adjacent to the third trench 73, there is no shift in the timing of turning on and/or off the gate of each of the other mesa portions.
  • the third trench 73 may also be formed as a dummy trench portion 30, and in this case, no channel is formed in the first mesa portion adjacent to the third trench 73, and there is no shift in the threshold of each of the conductive mesa portions.
  • the gate trench portion 40 formed from the third trench 73 may be connected to the first gate runner 47-1, and the other first trench portion may not be connected to the first gate runner 47-1 or the second gate runner 47-2.
  • two third trenches 73 are provided, but three or more may be provided, and if only one is provided, it may be formed as a gate trench portion 40 or as a dummy trench portion 30.
  • FIG. 9C is a diagram showing an example of a cross section of a semiconductor device 400 according to a fourth embodiment having a third trench portion.
  • changes related to the third trench portion from the semiconductor device shown in FIG. 7C are explained, and explanations of other structures are omitted.
  • the trench portion located at the end of the trench bottom portion 75 was the second trench.
  • the trench portion located at the end of the trench bottom portion 75 is the third trench 73, and ion implantation to form the trench bottom portion 75 is not performed on the adjacent first mesa portion.
  • the third trench 73 is also formed as a dummy gate trench portion 45, so the channel formed in the first mesa portion adjacent to the third trench 73 is not connected to the emitter region 12 and electrons are not conducted. Therefore, there is no shift in the threshold of each conductive mesa portion.
  • the third trench 73 may also be formed as a dummy trench portion 30, and in this case, there is also no channel formed in the first mesa portion adjacent to the third trench 73, and there is no shift in the threshold of each conductive mesa portion.
  • two third trenches 73 are provided, but three or more may be provided, and when only one is provided, it may be formed as a dummy gate trench portion 45 or as a dummy trench portion 30. Note that in the semiconductor devices 200 and 300 according to Examples 2 and 3, the third trench 73 may be formed as a dummy gate trench portion 45.

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109033A (ja) * 2008-10-29 2010-05-13 Renesas Technology Corp 半導体装置およびその製造方法
JP2014060387A (ja) * 2012-08-21 2014-04-03 Rohm Co Ltd 半導体装置
US20160336394A1 (en) * 2015-05-14 2016-11-17 Alpha And Omega Semiconductor Incorporated New dual-gate trench igbt with buried floating p-type shield
WO2019159391A1 (ja) * 2018-02-14 2019-08-22 富士電機株式会社 半導体装置
WO2023140254A1 (ja) * 2022-01-20 2023-07-27 富士電機株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109033A (ja) * 2008-10-29 2010-05-13 Renesas Technology Corp 半導体装置およびその製造方法
JP2014060387A (ja) * 2012-08-21 2014-04-03 Rohm Co Ltd 半導体装置
US20160336394A1 (en) * 2015-05-14 2016-11-17 Alpha And Omega Semiconductor Incorporated New dual-gate trench igbt with buried floating p-type shield
WO2019159391A1 (ja) * 2018-02-14 2019-08-22 富士電機株式会社 半導体装置
WO2023140254A1 (ja) * 2022-01-20 2023-07-27 富士電機株式会社 半導体装置

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