WO2025050596A1 - 半导体器件及其制造方法、电子设备 - Google Patents

半导体器件及其制造方法、电子设备 Download PDF

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Publication number
WO2025050596A1
WO2025050596A1 PCT/CN2024/075856 CN2024075856W WO2025050596A1 WO 2025050596 A1 WO2025050596 A1 WO 2025050596A1 CN 2024075856 W CN2024075856 W CN 2024075856W WO 2025050596 A1 WO2025050596 A1 WO 2025050596A1
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Prior art keywords
buffer layer
relaxed buffer
substrate
layer
relaxed
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English (en)
French (fr)
Inventor
王海玲
王祥升
宋艳鹏
刘晓萌
王桂磊
赵超
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the embodiments of the present application relate to but are not limited to the field of design and manufacturing of semiconductor devices, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device.
  • DRAM Dynamic Random Access Memory
  • the capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively.
  • the transistor is the switch that controls the charging and discharging of the capacitor.
  • the SiGe layer epitaxially grown on the Si substrate will produce strain due to the lattice mismatch.
  • the strain will be released after the Si/SiGe multilayer stacking, resulting in an increase in defects in the channel formed by the Si layer, causing device degradation and seriously affecting the performance of DRAM.
  • An embodiment of the present application provides a semiconductor device, the semiconductor device comprising:
  • a plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to the substrate and distributed periodically; each layer includes a plurality of columns of memory cells;
  • a relaxed buffer layer is located between the substrate and the memory cell.
  • a lattice constant of the relaxed buffer layer in a relaxed state is different from a lattice constant of the substrate.
  • the relaxed buffer layer may include a first relaxed buffer layer and a second relaxed buffer layer, the first relaxed buffer layer is located between the substrate and the second relaxed buffer layer, and the second relaxed buffer layer is located between the first relaxed buffer layer and the memory cell;
  • the lattice constant of the first relaxed buffer layer changes, and the lattice constant of the second relaxed buffer layer remains unchanged;
  • Dislocations are present in both the first relaxed buffer layer and the second relaxed buffer layer, and a dislocation density in the first relaxed buffer layer is greater than a dislocation density in the second relaxed buffer layer.
  • the first relaxed buffer layer is a film layer in which strain is completely relaxed at least in a region on a side away from the substrate.
  • the material of the substrate may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide and indium phosphide.
  • the material of the relaxed buffer layer may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.
  • the memory cell includes a transistor, and the transistor includes a semiconductor column; the main material of the semiconductor column can be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.
  • the material of the substrate and the main material of the semiconductor pillar may both be silicon, and the material of the relaxed buffer layer may be silicon germanium.
  • the material of the substrate may be silicon
  • the material of the relaxed buffer layer may be selected from any one or more of gallium arsenide, aluminum gallium arsenide and indium gallium arsenide
  • the main material of the semiconductor column may be gallium arsenide or indium gallium arsenide.
  • the semiconductor device may further include an isolation layer, wherein the isolation layer is located between the relaxed buffer layer and the memory cell and is configured to isolate the relaxed buffer layer from the memory cell.
  • the transistor may further include a gate electrode surrounding at least a portion of a sidewall of the semiconductor pillar.
  • the semiconductor pillar may extend along a first direction parallel to the substrate.
  • the memory cell may further include a capacitor connected to the transistor in the same memory cell.
  • the semiconductor device may further include: a plurality of bit lines extending in a direction perpendicular to the substrate.
  • the transistors of two columns of memory cells that are located in different layers and adjacent to each other along the first direction may be connected to the same bit line.
  • the semiconductor device may further include: a plurality of word lines extending along a second direction parallel to the substrate.
  • the transistors of a column of the memory cells located in the same layer and arranged along the second direction may be connected to the same word line.
  • the embodiment of the present application also provides a method for manufacturing a semiconductor device, wherein the semiconductor device comprises a plurality of memory cells and a relaxed buffer layer; the plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to a substrate and distributed periodically, and the memory cells comprise transistors;
  • the method for manufacturing the semiconductor device comprises:
  • the plurality of memory cells are formed on a side of the relaxed buffer layer away from the substrate.
  • forming the relaxed buffer layer on the substrate and making the relaxed buffer layer a relaxed film layer may include:
  • a first relaxed buffer layer is grown on one side of the substrate by an epitaxial process; wherein the lattice constant of the first relaxed buffer layer changes along a direction away from the substrate, the first relaxed buffer layer has dislocations, and the first relaxed buffer layer has a plurality of dislocations.
  • the region of the buffer layer away from the substrate is a film layer in which strain is completely relaxed;
  • a second relaxed buffer layer is grown on a side of the first relaxed buffer layer away from the substrate using an epitaxial process, and the lattice structure of the second relaxed buffer layer is consistent with the lattice structure of the first relaxed buffer layer away from the substrate; the first relaxed buffer layer and the second relaxed buffer layer constitute the relaxed buffer layer.
  • forming the plurality of memory cells on a side of the relaxed buffer layer away from the substrate may include:
  • the semiconductor layers and the sacrificial layers are alternately grown on the side of the isolation layer away from the substrate by using an epitaxial process, so as to obtain a stacked structure consisting of alternating semiconductor layers and sacrificial layers.
  • the lattice constant of the relaxed buffer layer in a relaxed state is different from the lattice constant of the substrate, and the lattice constant of the relaxed buffer layer in a relaxed state is between the lattice constants of the sacrificial layer and the semiconductor layer.
  • forming the plurality of storage units may further include: after obtaining the stacking structure,
  • a patterning process is performed on the semiconductor layer in the stacked structure so that the semiconductor layer forms a semiconductor column of the transistor, and a gate electrode is formed on at least a portion of the sidewall of the semiconductor column.
  • the semiconductor column and the gate electrode constitute the transistor.
  • the method for manufacturing the semiconductor device may further include: forming a capacitor connected to the transistor, wherein the transistor and the capacitor connected thereto constitute the storage unit.
  • An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided in the above embodiment of the present application.
  • FIG1A is a schematic longitudinal cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application.
  • FIG. 1B is a top view of the semiconductor device shown in FIG. 1A ;
  • FIG2 is a process flow chart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application
  • 3A is a schematic longitudinal cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application after a first relaxed buffer layer is formed;
  • FIG3B is a top view of the semiconductor device shown in FIG3A ;
  • FIG4 is a schematic longitudinal cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application after CMP is performed on the surface of the first relaxed buffer layer;
  • FIG. 5A is a longitudinal section of a semiconductor device provided by an exemplary embodiment of the present application after forming a second relaxed buffer layer.
  • FIG5B is a top view of the semiconductor device shown in FIG5A ;
  • 6A is a schematic longitudinal cross-sectional view of a semiconductor device after a stacked structure is formed, provided by an exemplary embodiment of the present application;
  • FIG6B is a top view of the semiconductor device shown in FIG6A ;
  • FIG. 7A is a schematic longitudinal cross-sectional view of a semiconductor device after forming a semiconductor column provided by an exemplary embodiment of the present application;
  • FIG7B is a top view of the semiconductor device shown in FIG7A ;
  • FIG. 8A is a schematic longitudinal cross-sectional view of a semiconductor device after a bit line is formed, provided by an exemplary embodiment of the present application;
  • FIG8B is a top view of the semiconductor device shown in FIG8A;
  • FIG. 9A is a schematic longitudinal cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application after a sacrificial layer is removed;
  • FIG9B is a top view of the semiconductor device shown in FIG9A ;
  • FIG10A is a schematic longitudinal cross-sectional view of a semiconductor device after word lines are formed, provided by an exemplary embodiment of the present application;
  • FIG10B is a top view of the semiconductor device shown in FIG10A ;
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate component, or the internal communication of two components.
  • installed should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate component, or the internal communication of two components.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • a channel region refers to a region where current mainly flows.
  • the first electrode region may be a drain electrode and the second electrode region may be a source electrode, or the first electrode region may be a source electrode and the second electrode region may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in the present application, unless otherwise specified, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection or “connection” includes situations where constituent elements are connected together through an element having some electrical function, such as an electrical signal connection (coupled connection, such as coupled to), or a physical direct connection.
  • element having some electrical function there is no particular limitation on “element having some electrical function” as long as it can transfer electrical signals between connected constituent elements.
  • Examples of “element having some electrical function” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°.
  • perpendicular means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.
  • film and “layer” can be interchanged.
  • semiconductor layer can sometimes be replaced by “semiconductor film”.
  • insulating film can sometimes be replaced by “insulating layer”.
  • a and B are arranged in the same layer in this application means that A and B are distributed on the same horizontal plane, or although not on the same horizontal plane, they are in different areas of the same support surface.
  • a and B are formed simultaneously by subjecting the same film layer to the same patterning process.
  • a and B are an integrated structure
  • a film layer patterned on a film layer to form a connection is an integrated structure.
  • a and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be exactly the same.
  • the epitaxially grown Si 1-x Ge x layer on the Si substrate will produce strain due to lattice mismatch.
  • the critical thickness decreases exponentially. According to theoretical calculations, the critical thickness of relaxation of Si 0.8 Ge 0.2 layer directly grown on Si substrate is about 15nm, and the critical thickness of metastable state is about 250nm, while the critical thickness of relaxation of Si 0.7 Ge 0.3 layer is only about 8nm, and the critical thickness of metastable state is about 100nm.
  • An embodiment of the present application provides a semiconductor device.
  • FIG1A is a schematic longitudinal cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application
  • FIG1B is a top view of the semiconductor device shown in FIG1A .
  • the semiconductor device includes:
  • a plurality of memory cells 110 are distributed in different layers, stacked along a direction perpendicular to the substrate 10 and distributed periodically; Each layer includes a plurality of columns of memory cells 110 , the memory cells 110 include transistors 90 , and the transistors 90 include semiconductor pillars 41 ;
  • the relaxed buffer layer 20 is a relaxed film layer and is located between the substrate 10 and the memory cell 110 .
  • the semiconductor device of the embodiment of the present application introduces a relaxed buffer layer between the substrate and the storage unit, which can reduce the lattice mismatch between the substrate and the epitaxial stack structure (such as the Si/SiGe stack structure) during the manufacturing process of the semiconductor device, thereby reducing the strain accumulation in the epitaxial stack structure. Under the same conditions, the number of layers that can be stacked in the epitaxial stack structure can be increased.
  • the introduction of the relaxed buffer layer can increase the tensile strain in the channel region of the transistor, which can improve the electron mobility in the channel region and further increase the operating speed of the transistor (eg, switching speed).
  • the introduction of the relaxed buffer layer can reduce the strain accumulation of the epitaxial sacrificial layer (for example, the SiGe epitaxial sacrificial layer) in the epitaxial stack structure during the manufacturing process of the semiconductor device, so that under the same conditions, the critical thickness of the epitaxial sacrificial layer increases, thereby obtaining a thicker epitaxial sacrificial layer, which can reduce the process difficulty of 3D semiconductor device processing.
  • the epitaxial sacrificial layer for example, the SiGe epitaxial sacrificial layer
  • the semiconductor pillars 41 of the transistors of the plurality of memory cells 110 located in the same layer may be formed by the same semiconductor layer 40 ;
  • the semiconductor layer 40 and the relaxed buffer layer 20 are both epitaxial layers grown epitaxially on the substrate.
  • the lattice constant of the relaxed buffer layer in a relaxed state is different from the lattice constant of the substrate.
  • the lattice constant of the relaxed buffer layer in a relaxed state is greater than the lattice constant of the substrate; if the material of the substrate is germanium and the material of the relaxed buffer layer is silicon, the lattice constant of the relaxed buffer layer in a relaxed state is less than the lattice constant of the substrate.
  • the relaxed buffer layer 20 may include a first relaxed buffer layer 21 and a second relaxed buffer layer 22 , wherein the first relaxed buffer layer 21 is located between the substrate and the second relaxed buffer layer 22 , and the second relaxed buffer layer 22 is located between the first relaxed buffer layer 21 and the memory cell 110 ;
  • the lattice constant of the first relaxed buffer layer 21 changes, and the lattice constant of the second relaxed buffer layer 22 remains unchanged;
  • Both the first relaxed buffer layer 21 and the second relaxed buffer layer 22 have dislocations therein, and the dislocation density in the first relaxed buffer layer 21 is greater than the dislocation density in the second relaxed buffer layer 22 .
  • the first relaxed buffer layer is a film layer in which strain is completely relaxed at least in a region on a side away from the substrate.
  • the material of the substrate may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide and indium phosphide.
  • the material of the relaxed buffer layer may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.
  • the material of the semiconductor pillar may include any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.
  • the host material of the semiconductor column can be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.
  • the "host material” here is relative to the doped "guest material”. In order to obtain different resistivities, a small amount of impurity elements are usually doped into the semiconductor material.
  • the semiconductor material is the host material, and the impurity elements doped in the semiconductor material are the guest material.
  • the material of the substrate and the main material of the semiconductor pillar may both be silicon.
  • the material of the relaxed buffer layer may be silicon germanium.
  • the material of the substrate may be silicon
  • the material of the relaxed buffer layer may be selected from any one or two of gallium arsenide, aluminum gallium arsenide and indium gallium arsenide
  • the main material of the semiconductor column may be gallium arsenide or indium gallium arsenic.
  • the semiconductor device may further include an isolation layer 30, which is located between the relaxed buffer layer and the memory cell and is configured to isolate the relaxed buffer layer from the memory cell.
  • an isolation layer 30 is used as the isolation layer 30.
  • the transistor 90 may further include a gate electrode 82 , and the gate electrode 82 surrounds at least a portion of a sidewall of the semiconductor pillar 41 .
  • a transistor 90 includes a first electrode region 42 , a channel region 43 , and a second electrode region 44 in sequence, and a gate electrode 82 surrounds at least a portion of a sidewall of the channel region 43 .
  • surrounding can be understood as partial surrounding or full surrounding.
  • the surrounding can be full surrounding, that is, the entire side wall of the channel region is surrounded by the gate electrode, and the cross-section of the gate electrode after surrounding is a closed ring.
  • the cross-section is intercepted along a direction perpendicular to the substrate and parallel to the second direction.
  • the surrounding can be partial surrounding, that is, part of the side wall of the channel region is surrounded by the gate electrode, and the cross-section after surrounding is not closed, but presents a ring shape.
  • a ring with an opening or two independent semiconductor layers For example, the opposite side surfaces of the channel region are surrounded by the gate electrode, and the cross-section of the gate electrode is a ring with two openings.
  • the semiconductor pillar 41 may extend in a first direction parallel to the substrate 10.
  • the first direction may be an X direction as shown in FIGS. 1A and 1B.
  • the memory cell 110 may further include a capacitor 100 , and the capacitor 100 is connected to the transistor 90 in the same memory cell 110 .
  • the semiconductor device may further include: a plurality of bit lines 70 extending in a direction perpendicular to the substrate 10.
  • the direction perpendicular to the substrate 10 may be the Z direction as shown in Figure 1A.
  • transistors 90 of two columns of memory cells 110 located in different layers and adjacent to each other along the first direction may be connected to the same bit line 70 .
  • the semiconductor device may further include: a plurality of word lines 80 extending along a second direction parallel to the substrate 10.
  • the second direction may be a Y direction as shown in FIG1B .
  • transistors 90 of a column of memory cells 110 located in the same layer and arranged along the second direction may be connected to the same word line 80 .
  • the semiconductor layer can be understood as semiconductor material, where the emphasis is not on its shape and structure but only on its function.
  • spacing can be understood as being separated, and can be achieved by a physical structural disconnection or an electrical characteristic disconnection.
  • the semiconductor layer between the effective channels corresponding to the two transistors is modified to achieve insulation to achieve electrical spacing between the two channels.
  • the electrode material of the gate electrode may be any one or more of the following different types of materials:
  • it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;
  • metal oxides metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide ITO, Metal oxide materials with high conductivity such as indium zinc oxide IZO and indium oxide InO; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN);
  • it can also be polysilicon material; it can also be conductive material doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that embody conductivity, etc.
  • the material of the gate insulating layer may include one or more layers of Low-K and/or High-K dielectric materials, or include two or more regions with different dielectric constants K.
  • the characteristics of the gate insulating layer of the present application will be exemplarily described below.
  • Low-K materials such as silicon oxide.
  • High-K materials such as dielectric materials with a dielectric constant K ⁇ 3.9.
  • oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. may be included.
  • high-K materials may include but are not limited to at least one of the following: hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO 2 ), etc.
  • the above-mentioned memory cell may be a memory cell including a transistor, wherein the transistor may be an access transistor, and the memory cell may further include other components, such as a capacitor in a 1T1C memory cell, or a read transistor and a storage node in a 2T0C memory cell.
  • the material of the dielectric layer may be silicon oxide or a High-K dielectric material, ie, a dielectric material with a dielectric constant K ⁇ 3.9.
  • the High-K dielectric material may include but is not limited to at least one of the following: aluminum oxide (Al 2 O 3 ) and hafnium oxide.
  • the semiconductor device may be a 3D memory, for example, a 3D DRAM or other memory.
  • the 3D memory may be a 1T1C or 2T (containing a read transistor and a write transistor) structure.
  • An embodiment of the present application also provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a plurality of memory cells and a relaxed buffer layer; the plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to a substrate and distributed periodically, and the memory cells include transistors.
  • the semiconductor device provided in the above embodiment of the present application can be obtained through the manufacturing method.
  • FIG. 2 is a process flow chart of a method for manufacturing a semiconductor device provided in an exemplary embodiment of the present application.
  • the method for manufacturing the semiconductor device includes:
  • the plurality of memory cells are formed on a side of the relaxed buffer layer away from the substrate.
  • the manufacturing method of the semiconductor device described in the embodiment of the present application introduces a relaxed buffer layer between the substrate and the storage unit, which can reduce the lattice mismatch between the substrate and the epitaxial stack structure (such as the Si/SiGe stack structure) during the manufacturing process of the semiconductor device, thereby reducing the strain accumulation in the epitaxial stack structure. Under the same conditions, the number of layers that can be stacked in the epitaxial stack structure can be increased.
  • the introduction of the relaxed buffer layer can increase the tensile strain in the channel region of the transistor, which can improve the electron mobility in the channel region and further increase the operating speed of the transistor (eg, switching speed).
  • the introduction of the relaxed buffer layer can reduce the strain accumulation of the epitaxial sacrificial layer (for example, the SiGe epitaxial sacrificial layer) in the epitaxial stack structure during the manufacturing process of the semiconductor device, so that under the same conditions, the critical thickness of the epitaxial sacrificial layer increases, thereby obtaining a thicker epitaxial sacrificial layer, which can reduce the process difficulty of 3D semiconductor device processing.
  • the epitaxial sacrificial layer for example, the SiGe epitaxial sacrificial layer
  • forming the relaxed buffer layer on the substrate and making the relaxed buffer layer a relaxed film layer may include:
  • a first relaxed buffer layer is grown on one side of the substrate by using an epitaxial process; wherein, along the direction from the substrate to the second relaxed buffer layer, the lattice constant of the first relaxed buffer layer is changed, dislocations are present in the first relaxed buffer layer, and a region of the first relaxed buffer layer on a side away from the substrate is a film layer with completely relaxed strain;
  • a second relaxed buffer layer is grown on a side of the first relaxed buffer layer away from the substrate using an epitaxial process, and the lattice structure of the second relaxed buffer layer is consistent with the lattice structure of the first relaxed buffer layer away from the substrate; the first relaxed buffer layer and the second relaxed buffer layer constitute the relaxed buffer layer.
  • forming the plurality of memory cells on a side of the relaxed buffer layer away from the substrate may include:
  • Semiconductor layers and sacrificial layers are alternately grown on a side of the isolation layer away from the substrate by using an epitaxial process, so as to obtain a stacked structure consisting of alternating semiconductor layers and sacrificial layers.
  • the lattice constant of the relaxed buffer layer in a relaxed state is different from the lattice constant of the substrate, and the lattice constant of the relaxed buffer layer in a relaxed state is between the lattice constants of the sacrificial layer and the semiconductor layer.
  • forming the plurality of storage units may further include: after obtaining the stacking structure,
  • a patterning process is performed on the semiconductor layer in the stacked structure so that the semiconductor layer forms a semiconductor column of the transistor, and a gate electrode is formed on at least a portion of the sidewall of the semiconductor column.
  • the semiconductor column and the gate electrode constitute the transistor.
  • the method for manufacturing the semiconductor device may further include: forming a capacitor connected to the transistor, wherein the transistor and the capacitor connected thereto constitute the storage unit.
  • the technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment.
  • the "patterning process” mentioned in this embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology.
  • the "photolithography process” mentioned in this embodiment includes coating of film layers, mask exposure and development, which is a mature preparation process in the relevant technology.
  • Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc.
  • coating can adopt known coating processes
  • etching can adopt known methods, which are not specifically limited here.
  • FIG3A is a schematic longitudinal section diagram of a semiconductor device provided in an exemplary embodiment of the present application after forming a first relaxed buffer layer
  • FIG3B is a top view of the semiconductor device shown in FIG3A
  • FIG4 is a schematic longitudinal section diagram of a semiconductor device provided in an exemplary embodiment of the present application after CMP is performed on the surface of the first relaxed buffer layer
  • FIG5A is a schematic longitudinal section diagram of a semiconductor device provided in an exemplary embodiment of the present application after forming a second relaxed buffer layer
  • FIG5B is a top view of the semiconductor device shown in FIG5A
  • FIG6A is a schematic longitudinal section diagram of a semiconductor device provided in an exemplary embodiment of the present application after forming a stacked structure
  • FIG6B is a top view of the semiconductor device shown in FIG6A
  • FIG7 A is a schematic longitudinal section diagram of a semiconductor device provided by an exemplary embodiment of the present application after forming a semiconductor column
  • Figure 7B is a top view of the semiconductor device shown in Figure 7
  • the method for manufacturing the semiconductor device may include the following process.
  • step S10 may include:
  • S11 providing a substrate 10, and performing surface treatment on the substrate 10, including but not limited to: baking the water vapor on the surface of the substrate 10 at a low temperature, and then heating it to a high temperature and removing impurity elements such as C and O on the surface of the substrate 10 in a H2 atmosphere, so that the surface of the substrate 10 presents a clean and fresh Si atomic layer;
  • S12 epitaxially growing a first relaxed buffer layer 21 on the surface of the surface-treated substrate 10, comprising: firstly growing Si 1-y Ge y with a certain thickness t1 (for example, t1>10 nm) at a certain temperature T1 (for example, T1 ⁇ 600° C.) using polycarbonate active silicon dioxide (DCS) and germanium (GeH 4 ) as precursors, then increasing the temperature to T2 (for example, T1 ⁇ T2 ⁇ 850° C.) and growing Si 1-y Ge y with a certain thickness t2 (for example, t2>100 nm), and then maintaining the temperature T2 for annealing, so that the lattice constant of the Si 1 -y Ge y film on the surface away from the substrate and the nearby surface is substantially close to or reaches the lattice constant of the crystal Si 1-y Ge y , that is, the Si 1-y Ge y surface is
  • the y film is a film layer in which the strain is completely relaxed, and a first
  • the surface of the formed first relaxed buffer layer 21 has many protrusions.
  • the protrusions can be as high as tens of nanometers or even higher.
  • a large number of dislocations (not shown in the figure) can be observed at the Si/Si 1-y Ge y interface through the cross-sectional TEM image of the slice, which are gradually suppressed during the film growth process.
  • the threading dislocation density on the surface of the first relaxed buffer layer 21 is about 1 ⁇ 10 6 /cm 2 to 5 ⁇ 10 7 /cm 2 .
  • step S20 may include:
  • S21 grinding and polishing the surface of the first relaxed buffer layer 21 by using a chemical mechanical polishing (CMP) process, after which the height of the protrusions on the surface of the first relaxed buffer layer 21 can be reduced to within a few nanometers, for example, the surface roughness (RMS) of the surface of the first relaxed buffer layer 21 is less than 2 nm;
  • CMP chemical mechanical polishing
  • step S30 may include: epitaxially growing a Si 1-y Ge y layer of a certain thickness t3 (for example, t3 ⁇ 10 nm) at a certain temperature T3 (T3 ⁇ T2), and growing the Si 1-y Ge y layer completely according to the relaxed Si 1-y Ge y lattice on the surface of the first relaxed buffer layer 21 (i.e., a strain-free Si 1-y Ge y layer) to obtain a second relaxed buffer layer 22, as shown in Figures 5A and 5B; wherein the dislocation density in the second relaxed buffer layer 22 is significantly smaller than the dislocation density in the first relaxed buffer layer 21.
  • t3 for example, t3 ⁇ 10 nm
  • T3 ⁇ T2 certain temperature
  • S40 epitaxially growing a first insulating layer 31 on a side of the second relaxed buffer layer 22 away from the substrate 10, and epitaxially growing a semiconductor layer 40 and a sacrificial layer 50 in an alternating manner on a side of the first insulating layer 31 away from the substrate 10, to obtain a stacked structure consisting of alternatingly stacked semiconductor layers 40 and sacrificial layers 50.
  • step S40 may include:
  • S41 epitaxial growth of the first insulating layer 31, comprising: at a temperature T3, using DCS as a precursor to perform Si epitaxial growth on a side of the second relaxed buffer layer 22 away from the substrate 10, to obtain a first insulating layer 31 formed of a Si epitaxial layer, wherein the thickness of the first insulating layer 31 is t4 (for example, 5 nm ⁇ t4 ⁇ 100 nm); the first insulating layer 31 functions as an isolation layer between the second relaxed buffer layer 22 and the stacked structure for insulation;
  • S42 epitaxial growth of the stacked structure, including: continuing to maintain the temperature at T3, using DCS and GeH4 as precursors to staggered epitaxially grow a superlattice structure of Si1 -xGex ( y ⁇ x) and Si on a side of the first insulating layer 31 away from the substrate 10, to obtain a Si/Si1 - xGex stacked structure; wherein the Si epitaxial layer serves as a semiconductor layer 40 for subsequently forming source/drain electrodes and a channel of the transistor; the Si1 - xGex epitaxial layer is a strained layer, serving as a sacrificial layer 50, as shown in Figures 6A and 6B.
  • the solution of the embodiment of the present application can further increase the number of stacking layers of the Si/SiGe stacked structure, thereby improving the storage density of the 3D semiconductor device.
  • step S50 may include:
  • each first groove 61 extends in a direction perpendicular to the substrate 10 and in a first direction parallel to the substrate 10, and the plurality of first grooves 61 are spaced apart in a second direction parallel to the substrate 10, and the plurality of first grooves 61 space each semiconductor layer 40 into a plurality of semiconductor pillars 41 extending in the first direction and spaced apart in the second direction;
  • each second groove 62 extends in a direction perpendicular to the substrate 10 and in the second direction, and the plurality of second grooves 62 are spaced apart in the first direction;
  • the first direction may be the X direction as shown in FIGS. 7A and 7B
  • the second direction may be the Y direction as shown in FIG. 7B
  • the direction perpendicular to the substrate 10 may be the Z direction as shown in FIG. 7A
  • the first trench 61 and the second trench 62 may expose the first insulating layer 31 , for example, the first trench 61 and the second trench 62 may extend to the surface or the inside of the first insulating layer 31 away from the substrate 10 ;
  • S52 Fill the first trench 61 and the second trench 62 with the second insulating layer 32, as shown in Figure 7A and Figure 7B.
  • the second insulating layer 32 is used to separate two adjacent columns of memory cells along the first direction and to separate memory cells located in different layers.
  • the material of the second insulating layer 32 may be a low-K dielectric material, ie, a dielectric material with a dielectric constant K ⁇ 3.9, including but not limited to silicon oxides such as silicon dioxide (SiO 2 ) or other silicon-containing films, and air (ie, forming an air gap).
  • a dielectric material with a dielectric constant K ⁇ 3.9 including but not limited to silicon oxides such as silicon dioxide (SiO 2 ) or other silicon-containing films, and air (ie, forming an air gap).
  • step S60 may include: etching the patterned stack structure along a direction toward the substrate 10, forming a bit line hole that penetrates each semiconductor pillar 41 of different layers in the patterned stack structure, forming a bit line 70 in the bit line hole, and connecting the bit line 70 to each semiconductor pillar 41, as shown in Figures 8A and 8B.
  • bit line hole there may be one bit line hole between two adjacent second grooves 62 in the first direction; the bit line hole may extend in a direction perpendicular to the substrate 10 and expose the first insulating layer 31.
  • the bit line hole may extend to the surface or interior of the first insulating layer 31 away from the substrate 10, and the formed bit line 70 also extends in a direction perpendicular to the substrate 10.
  • the material of the bit line can be selected from any one or more of other metal materials with similar properties such as tungsten, molybdenum, and cobalt.
  • the bit line can be a single-layer or multi-layer structure, for example, it can be made of titanium (Ti), titanium nitride (TiN), and tungsten (W) formed of a multilayer structure.
  • step S70 may include: defining a photolithography pattern by photolithography, etching away the second insulating layer 32 in the first groove 61, and exposing the sacrificial layer 50 in the patterned stacked structure through the sidewall of the first groove 61; removing the sacrificial layer 50 by a selective etching process; and filling the space vacated after etching away the sacrificial layer 50 and the first groove 61 with the second insulating layer 32, as shown in FIGS. 9A and 9B .
  • a semiconductor column 41 between two adjacent second trenches 62 is subsequently used to form two transistors 90 connected to the same bit line 70.
  • the semiconductor column 41 includes a first electrode region 42, a channel region 43, a second electrode region 44, and a third electrode region 45 in sequence, one of the first electrode region 42 and the second electrode region 412 is used as the source electrode of the transistor, the other is used as the drain electrode of the transistor, and the third electrode region 45 is used as the inner electrode of the capacitor connected to the transistor.
  • the transistor is connected to the bit line 70 through the first electrode region 42, and the transistor is connected to the third electrode region of the capacitor through the second electrode region 44.
  • step S80 may include:
  • S82 depositing a gate insulating layer 81 and a gate electrode 82 on the exposed sidewalls of the channel region 43 in sequence, forming the gate insulating layer 81 and the gate electrode 82 surrounding at least a portion of the sidewalls of the channel region 43, and the semiconductor pillar 41 and the gate electrode 82 constitute a transistor 90;
  • S83 Connect the gate electrodes 82 of multiple transistors located in the same layer and spaced apart along the second direction together to form a word line 80 extending along the second direction, with the gate electrodes 82 of the transistors serving as part of the word line 80, as shown in FIGS. 10A and 10B ; or, separately form a word line 80 extending along the second direction, and connect the gate electrodes 82 of a column of transistors located in the same layer and spaced apart along the second direction to the same word line 80.
  • step S81 may further include: after exposing at least a portion of the sidewall of the channel region 43 of the semiconductor pillar 41 and before performing step S82,
  • a selective etching process is used to remove the second insulating layer 32 between the semiconductor pillars 41 of different layers, exposing the entire sidewall of the channel region 43 of the semiconductor pillar 41;
  • Step S82 may include: sequentially depositing a gate insulating layer 81 and a gate electrode 82 on the entire exposed sidewall surface of the channel region 43 of the semiconductor pillar 41 to form a gate insulating layer 81 and a gate electrode 82 that completely surround the channel region 43 .
  • Step S80 may further include: after step S83,
  • step S90 may include:
  • S92 sequentially depositing a dielectric layer 101 and a fourth electrode layer 102 on the exposed sidewalls of the third electrode region 45 to form the dielectric layer 101 and the fourth electrode layer 102 surrounding at least a portion of the sidewalls of the third electrode region 45.
  • the third electrode region 45, the dielectric layer 101 and the fourth electrode layer 102 constitute a capacitor 100.
  • the fourth electrode layer 102 surrounding the third electrode region 45 serves as an external electrode of the capacitor 100.
  • the transistor 90 and the capacitor 100 constitute a storage unit 110.
  • the semiconductor device shown in FIG. 1B The semiconductor device shown in FIG. 1B .
  • step S91 may further include: after exposing at least a portion of the sidewall of the third electrode region 45 of the semiconductor pillar 41 and before performing step S92,
  • the second insulating layer 32 between the semiconductor pillars 41 of different layers is removed by a selective etching process to expose the entire side wall of the third electrode region 45 of the semiconductor pillar 41;
  • Step S92 may include: sequentially depositing a dielectric layer 101 and a fourth electrode layer 102 on the entire exposed sidewall surface of the third electrode region 45 of the semiconductor pillar 41 to form the dielectric layer 101 and the fourth electrode layer 102 completely surrounding the third electrode region 45 .
  • step S90 may further include: after step S92,
  • S93 fill the gaps between adjacent semiconductor pillars 41 with the second insulating layer 32 , and insulate two adjacent storage cells 110 located in different layers and two adjacent storage cells 110 located in the same layer and spaced apart along the second direction through the second insulating layer 32 .
  • the material of the second insulating layer 32 is not limited to one, that is, the material of the second insulating layer 32 used in each step may be the same or different.
  • An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided in the above embodiment of the present application.
  • the electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc.
  • the storage device may include a memory in a computer, etc., which is not limited here.

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Abstract

一种半导体器件及其制造方法、电子设备，所述半导体器件包括多个存储单元，分布于不同层、沿着垂直于衬底的方向堆叠且周期性分布；每一层包括多列存储单元；弛豫缓冲层，位于所述衬底与所述存储单元之间。

Description

半导体器件及其制造方法、电子设备
本申请要求于2023年9月7日提交中国专利局、申请号为202311153052.8、发明名称为“半导体器件及其制造方法、电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本申请实施例涉及但不限于半导体器件的设计与制造领域，尤指一种半导体器件及其制造方法、电子设备。
背景技术
动态随机存取存储器(Dynamic Random Access Memory,DRAM)是一种常见的系统内存，广泛应用在个人电脑、笔记本和消费电子产品中。传统已知的DRAM有多个重复的“存储单元”，每个存储单元有一个电容器和晶体管。电容器可以存储1位数据，充放电后，电容器存储电荷的多少可以分别对应二进制数据“1”和“0”。晶体管是控制电容器充放电的开关。
为了尽可能降低产品的成本，人们希望在有限的衬底上做出尽可能多的存储单元，3DDRAM的架构和思路应运而生。其中，利用硅/硅锗(Si/SiGe)叠层作为沟道层及牺牲层是实现3D DRAM器件的一种方案。
由于Si和Ge的晶格失配度达4％，在Si衬底上外延生长的SiGe层由于晶格失配会产生应变，应变在Si/SiGe多层堆叠后会释放出来，导致Si层形成的沟道的缺陷增多，引起器件的退化，严重影响DRAM的性能。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制本申请的保护范围。
本申请实施例提供了一种半导体器件，所述半导体器件包括：
多个存储单元，分布于不同层、沿着垂直于衬底的方向堆叠且周期性分布；每一层包括多列存储单元；
弛豫缓冲层，位于所述衬底与所述存储单元之间。
在本申请的示例性实施例中，所述弛豫缓冲层在弛豫状态下的晶格常数不同于所述衬底的晶格常数。
在本申请的示例性实施例中，所述弛豫缓冲层可以包括第一弛豫缓冲层和第二弛豫缓冲层，所述第一弛豫缓冲层位于所述衬底与所述第二弛豫缓冲层之间，所述第二弛豫缓冲层位于所述第一弛豫缓冲层与所述存储单元之间；
沿着远离所述衬底的方向，所述第一弛豫缓冲层的晶格常数是变化的，所述第二弛豫缓冲层的晶格常数是不变的；
所述第一弛豫缓冲层和所述第二弛豫缓冲层中均具有位错，并且所述第一弛豫缓冲层中的位错密度大于所述第二弛豫缓冲层中的位错密度。
在本申请的示例性实施例中，所述第一弛豫缓冲层至少在远离所述衬底的一侧的区域为应变完全弛豫的膜层。
在本申请的示例性实施例中，所述衬底的材料可以选自硅、锗、硅锗、碳化硅、砷化镓、砷化铟和磷化铟中的任意一种或多种。
在本申请的示例性实施例中，所述弛豫缓冲层的材料可以选自硅、锗、硅锗、碳化硅、砷化镓、铝镓砷、铟镓砷、砷化铟和磷化铟中的任意一种或多种。
在本申请的示例性实施例中，所述存储单元包括晶体管，所述晶体管包括半导体柱；所述半导体柱的主体材料可以选自硅、锗、硅锗、碳化硅、砷化镓、铟镓砷、砷化铟和磷化铟中的任意一种或多种。
在本申请的示例性实施例中，所述衬底的材料和所述半导体柱的主体材料可以均为硅，所述弛豫缓冲层的材料可以为硅锗。
在本申请的示例性实施例中，所述衬底的材料可以为硅，所述弛豫缓冲层的材料可以选自砷化镓、铝镓砷和铟镓砷中的任意一种或多种，所述半导体柱的主体材料为砷化镓或铟镓砷。
在本申请的示例性实施例中，所述半导体器件还可以包括隔离层，所述隔离层位于所述弛豫缓冲层与所述存储单元之间，配置为对所述弛豫缓冲层与所述存储单元进行隔离。
在本申请的示例性实施例中，所述晶体管还可以包括栅电极，所述栅电极环绕所述半导体柱的至少部分侧壁。
在本申请的示例性实施例中，所述半导体柱可以沿平行于所述衬底的第一方向延伸。
在本申请的示例性实施例中，所述存储单元还可以包括电容器，所述电容器与同一个所述存储单元中的所述晶体管连接。
在本申请的示例性实施例中，所述半导体器件还可以包括：沿垂直于所述衬底的方向延伸的多条位线。
在本申请的示例性实施例中，位于不同层且沿所述第一方向相邻的两列所述存储单元的所述晶体管可以与同一条位线连接。
在本申请的示例性实施例中，所述半导体器件还可以包括：沿平行于所述衬底的第二方向延伸的多条字线。
在本申请的示例性实施例中，位于同一层且沿所述第二方向排列的一列所述存储单元的所述晶体管可以与同一条字线连接。
本申请实施例还提供一种半导体器件的制造方法，所述半导体器件包括多个存储单元和弛豫缓冲层；所述多个存储单元分布于不同层、沿着垂直于衬底的方向堆叠且周期性分布，所述存储单元包括晶体管；
所述半导体器件的制造方法包括：
在所述衬底上形成所述弛豫缓冲层，并使所述弛豫缓冲层为弛豫的膜层；
在所述弛豫缓冲层远离所述衬底的一侧形成所述多个存储单元。
在本申请的示例性实施例中，在所述衬底上形成所述弛豫缓冲层，并使所述弛豫缓冲层为弛豫的膜层可以包括：
采用外延工艺在所述衬底一侧生长第一弛豫缓冲层；其中，沿着远离所述衬底的方向，所述第一弛豫缓冲层的晶格常数是变化的，所述第一弛豫缓冲层中具有位错，所述第一弛 豫缓冲层的远离所述衬底的一侧的区域为应变完全弛豫的膜层；
采用外延工艺在所述第一弛豫缓冲层的远离所述衬底的一侧生长第二弛豫缓冲层，所述第二弛豫缓冲层的晶格结构与所述第一弛豫缓冲层远离所述衬底的一侧的晶格结构一致；所述第一弛豫缓冲层和所述第二弛豫缓冲层构成所述弛豫缓冲层。
在本申请的示例性实施例中，在所述弛豫缓冲层远离所述衬底的一侧形成所述多个存储单元可以包括：
采用外延工艺在所述弛豫缓冲层远离所述衬底的一侧形成隔离层；
采用外延工艺在所述隔离层远离所述衬底的一侧交替生长半导体层和牺牲层，得到由交替的半导体层和牺牲层构成的堆叠结构。
在本申请的示例性实施例中，所述弛豫缓冲层在弛豫状态下的晶格常数不同于所述衬底的晶格常数，所述弛豫缓冲层在弛豫状态下的晶格常数介于所述牺牲层和所述半导体层的晶格常数。
在本申请的示例性实施例中，形成所述多个存储单元还可以包括：在得到所述堆叠结构之后，
对所述堆叠结构中的半导体层进行图案化工艺，使所述半导体层形成所述晶体管的半导体柱，以及在所述半导体柱的至少部分侧壁上形成栅电极，所述半导体柱和所述栅电极构成所述晶体管。
在本申请的示例性实施例中，所述半导体器件的制造方法还可以包括：形成与所述晶体管连接的电容器，所述晶体管和与其连接的所述电容器构成所述存储单元。
本申请实施例还提供一种电子设备，所述电子设备包括如上本申请实施例提供的所述半导体器件。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得更加清楚，或者通过实施本申请而了解。本申请的目的和优点可通过在说明书以及附图中所特别指出的结构来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1A为本申请示例性实施例提供的一种半导体器件的纵截面示意图；
图1B为图1A所示的半导体器件的俯视图；
图2为本申请示例性实施例提供的一种半导体器件的制造方法的工艺流程图；
图3A为本申请示例性实施例提供的一种半导体器件在形成第一弛豫缓冲层后的纵截面示意图；
图3B为图3A所示的半导体器件的俯视图；
图4为本申请示例性实施例提供的一种半导体器件在对第一弛豫缓冲层表面进行CMP后的纵截面示意图；
图5A为本申请示例性实施例提供的一种半导体器件在形成第二弛豫缓冲层后的纵截 面示意图；
图5B为图5A所示的半导体器件的俯视图；
图6A为本申请示例性实施例提供的一种半导体器件在形成堆叠结构后的纵截面示意图；
图6B为图6A所示的半导体器件的俯视图；
图7A为本申请示例性实施例提供的一种半导体器件在形成半导体柱后的纵截面示意图；
图7B为图7A所示的半导体器件的俯视图；
图8A为本申请示例性实施例提供的一种半导体器件在形成位线后的纵截面示意图；
图8B为图8A所示的半导体器件的俯视图；
图9A为本申请示例性实施例提供的一种半导体器件在去除牺牲层后的纵截面示意图；
图9B为图9A所示的半导体器件的俯视图；
图10A为本申请示例性实施例提供的一种半导体器件在形成字线后的纵截面示意图；
图10B为图10A所示的半导体器件的俯视图；
附图中的各标记符号的含义为：
10-衬底；21-第一弛豫缓冲层；22-第二弛豫缓冲层；30-隔离层；31-第一绝缘层；32-第二绝缘层；40-半导体层；41-半导体柱；42-第一电极区；43-沟道区；44-第二电极区；45-第三电极区；50-牺牲层；61-第一沟槽；62-第二沟槽；70-位线；80-字线；81-栅极绝缘层；82-栅电极；90-晶体管；100-电容器；101-介电质层；102-第四电极层；110-存储单元。
详述
为使本申请的目的、技术方案和优点更加清楚明白，下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
本申请的实施方式并不一定限定附图所示尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本申请的实施方式不局限于附图所示的形状或数值。
本申请中的“第一”、“第二”等序数词是为了避免构成要素的混同而设置，并不表示任何顺序、数量或者重要性。
在本申请中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在公开中说明的词句，根据情况可以适当地更换。
在本申请中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域 的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本申请中，沟道区域是指电流主要流过的区域。
在本申请中，可以是第一电极区为漏电极、第二电极区为源电极，或者可以是第一电极区为源电极、第二电极区为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本申请中，如果不特别说明，“源电极”和“漏电极”可以互相调换。
在本公开中，“电连接”或“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况，比如，电学信号连接(耦合连接，如coupled to)，或物理直接连接。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本申请中，“平行”是指大约平行或几乎平行，比如，两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指大约垂直，比如，两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本申请的一些实施例中，“膜”和“层”可以相互调换。例如，有时可以将“半导体层”换成“半导体膜”。与此同样，有时可以将“绝缘膜”换成“绝缘层”。
本申请所说的“A和B同层设置”是指，A和B在同一个水平面上分布，或者虽然不在一个水平面上，但是均在同一个支撑面上的不同区域。一种实施例为，A和B通过对同一个膜层经同一次图案化工艺同时形成。
本申请实施例中的“A和B为一体式结构”可以是指在微观结构上无明显的断层或间隙等明显的分界界面。一般地，在一个膜层上图案化形成连接的膜层为一体式。比如A和B使用相同的材料形成一个膜层并通过同一次图案化工艺同时形成具有连接关系的结构，或者在A上通过外延的方式直接生长出的B，二者材料可以不完全相同。
在Si衬底上外延生长的Si1-xGex层由于晶格失配会产生应变，当应变超过临界值时就会产生位错，引起应变弛豫，且随着Ge浓度的增加，临界厚度成指数下降。根据理论计算，在Si衬底上直接生长Si0.8Ge0.2层发生弛豫的临界厚度约为15nm，亚稳态的临界厚度约为250nm，而生长Si0.7Ge0.3层发生弛豫的临界厚度仅约为8nm，亚稳态的临界厚度约为100nm。
在以Si/SiGe叠层实现3D DRAM器件的过程中，由于SiGe和Si的选择性刻蚀工艺的要求，Ge浓度不能无限降低，因此为了得到更多的叠层层数，实现更高的集成度，就需要寻求新的方法，以在确保叠层晶体质量的情况下，实现更多层数的Si/Si1-xGex叠层结构。
本申请实施例提供了一种半导体器件。
图1A为本申请示例性实施例提供的一种半导体器件的纵截面示意图；图1B为图1A所示的半导体器件的俯视图。
如图1A和图1B所示，所述半导体器件包括：
多个存储单元110，分布于不同层、沿着垂直于衬底10的方向堆叠且周期性分布； 每一层包括多列存储单元110，存储单元110包括晶体管90，晶体管90包括半导体柱41；
弛豫缓冲层20，弛豫缓冲层20为弛豫的膜层，位于衬底10与存储单元110之间。
本申请实施例的半导体器件在衬底与存储单元之间引入弛豫的弛豫缓冲层，可以在制造半导体器件的过程中降低衬底与外延堆叠结构(例如Si/SiGe的堆叠结构)之间的晶格失配度，进而降低外延堆叠结构中的应变积累，同等条件下，可以增加外延堆叠结构能够堆叠的层数。
另外，弛豫缓冲层的引入可以增加晶体管中沟道区域的张应变，能够提高沟道区域的电子迁移率，可进一步提升晶体管的工作速度(例如，开关速度)。
而且，弛豫缓冲层的引入可以在制造半导体器件的过程中降低外延堆叠结构中的外延牺牲层(例如，SiGe外延牺牲层)的应变积累，使得在同等条件下，外延牺牲层的临界厚度增加，从而可以得到更厚的外延牺牲层，可以降低3D半导体器件加工的工艺难度。
在本申请的示例性实施例中，位于同一层的多个存储单元110的晶体管的半导体柱41可以由同一个半导体层40形成；
半导体层40、弛豫缓冲层20均为在所述衬底上外延生长出的外延层。
在本申请的示例性实施例中，所述弛豫缓冲层在弛豫状态下的晶格常数不同于所述衬底的晶格常数。例如，若所述衬底的材料为硅，所述弛豫缓冲层的材料为硅锗，则所述弛豫缓冲层在弛豫状态下的晶格常数大于所述衬底的晶格常数；若所述衬底的材料为锗，所述弛豫缓冲层的材料为硅，则所述弛豫缓冲层在弛豫状态下的晶格常数小于所述衬底的晶格常数。
在本申请的示例性实施例中，如图1A所示，弛豫缓冲层20可以包括第一弛豫缓冲层21和第二弛豫缓冲层22，第一弛豫缓冲层21位于所述衬底与第二弛豫缓冲层22之间，第二弛豫缓冲层22位于第一弛豫缓冲层21与存储单元110之间；
沿着从衬底10到第二弛豫缓冲层22的方向，第一弛豫缓冲层21的晶格常数是变化的，第二弛豫缓冲层22的晶格常数是不变的；
第一弛豫缓冲层21和第二弛豫缓冲层22中均具有位错，并且第一弛豫缓冲层21中的位错密度大于第二弛豫缓冲层22中的位错密度。
在本申请的示例性实施例中，所述第一弛豫缓冲层至少在远离所述衬底的一侧的区域为应变完全弛豫的膜层。
在本申请的示例性实施例中，所述衬底的材料可以选自硅、锗、硅锗、碳化硅、砷化镓、砷化铟和磷化铟中的任意一种或多种。
在本申请的示例性实施例中，所述弛豫缓冲层的材料可以选自选自硅、锗、硅锗、碳化硅、砷化镓、铝镓砷、铟镓砷、砷化铟和磷化铟中的任意一种或多种。
在本申请的示例性实施例中，所述半导体柱的材料可以包括硅、锗、硅锗、碳化硅、砷化镓、铟镓砷、砷化铟和磷化铟中的任意一种或多种。
在本申请的示例性实施例中，所述半导体柱的主体(Host)材料可以选自硅、锗、硅锗、碳化硅、砷化镓、铟镓砷、砷化铟和磷化铟中的任意一种或多种。这里的“主体材料”是相对于掺杂的“客体材料(Dopant)”来说的，为了获得不同的电阻率，通常在半导体材料中掺杂少量的杂质元素，半导体材料即为主体材料，半导体材料中掺杂的杂质元素即为客体材料。
在本申请的示例性实施例中，所述衬底的材料和所述半导体柱的主体材料可以均为硅， 所述弛豫缓冲层的材料可以为硅锗。
在本申请的示例性实施例中，所述衬底的材料可以为硅，所述弛豫缓冲层的材料可以选自砷化镓、铝镓砷和铟镓砷中的任意一种或两种，所述半导体柱的主体材料可以为砷化镓或铟镓砷。
在本申请的示例性实施例中，所述半导体器件还可以包括隔离层30，隔离层30位于所述弛豫缓冲层与所述存储单元之间，配置为对所述弛豫缓冲层与所述存储单元进行隔离。在如图1所示的半导体器件中，采用第一绝缘层31作为隔离层30。
在本申请的示例性实施例中，如图1A所示，晶体管90还可以包括栅电极82，栅电极82环绕半导体柱41的至少部分侧壁。
在本申请的示例性实施例中，如图1A所示，晶体管90依次包括第一电极区42、沟道区43和第二电极区44，栅电极82环绕沟道区43的至少部分侧壁。
这里，环绕可以理解为部分环绕或全部环绕。一些实施例中，所述环绕可以为全部环绕，即沟道区的整个侧壁被栅电极环绕，环绕后的栅电极的横截面为闭合环形。所述横截面为沿着垂直于衬底并平行于所述第二方向延伸的方向截取。如一些实施例中，所述环绕可以为部分环绕，即沟道区的部分侧壁被栅电极环绕，环绕后的横截面不是闭合的，但是呈现环形状。比如，具有开口的环形或两个独立的半导体层。例如，沟道区的相对的侧表面被栅电极环绕，此时栅电极的横截面为具有两个开口的环形。
在本申请的示例性实施例中，半导体柱41可以沿平行于衬底10的第一方向延伸。所述第一方向可以为如图1A和图1B所示的X方向。
在本申请的示例性实施例中，如图1A所示，存储单元110还可以包括电容器100，电容器100与同一个存储单元110中的晶体管90连接。
在本申请的示例性实施例中，如图1A和图1B所示，所述半导体器件还可以包括：沿垂直于衬底10的方向延伸的多条位线70。垂直于衬底10的方向可以为如图1A所示的Z方向。
在本申请的示例性实施例中，如图1A所示，位于不同层且沿所述第一方向相邻的两列存储单元110的晶体管90可以与同一条位线70连接。
在本申请的示例性实施例中，如图1A和图1B所示，所述半导体器件还可以包括：沿平行于衬底10的第二方向延伸的多条字线80。所述第二方向可以为如图1B所示的Y方向。
在本申请的示例性实施例中，如图1B所示，位于同一层且沿所述第二方向排列的一列存储单元110的晶体管90可以与同一条字线80连接。
半导体层可以理解为半导体材料，该处不强调其形状构造，仅仅强调其功能。
在本申请中，间隔可以理解为分开的、独立的(separated)，可以是物理结构上的断开来实现间隔，还可以是电学特性上的断开。比如，两个晶体管对应的有效沟道之间的半导体层经改性实现绝缘以实现两个沟道之间的电学间隔。
在本申请的示例性实施例中，所述栅电极的电极材料可以是如下不同类型材料中的任意一种或多种：
比如，含有钨、铝、钛、铜、镍、铂、钌、钼、金、铱、铑、钽、钴等金属；可以是含有前述提到的这些金属的金属合金；
还可以是金属氧化物、金属氮化物、金属硅化物、金属碳化物等，如铟锡氧化物ITO、 铟锌氧化物IZO、铟的氧化物InO等导电性较高的金属氧化物材料；比如，氮化钛(TiN)、氮化钽(TaN)、氮化钨(WN)、氮化钛铝(TiAlN)等金属氮化物材料；
当然，还可以是多晶硅材料；还可以是导电材料掺杂半导体材料，比如，导电掺杂后的硅、导电掺杂后的锗、导电掺杂后的硅锗等；体现导电性的其他材料等。
在本申请的示例性实施例中，所述栅极绝缘层的材料可以包含一层或多层Low-K和/或High-K介质材料，或者包含不同介电常数K的两个或多个区域。以下将示例性地说明本申请的栅极绝缘层的特点。
Low-K材料，比如氧化硅。
High-K材料，比如介电常数K≥3.9的介质材料。一些实施例中，可以包括铪、铝、镧、锆等一个或多个的氧化物。示例性地，比如，可以包括但不限于以下至少之一：氧化铪(HfO2)、氧化铝(Al2O3)、铪铝氧化物(HfAlO)、铪镧氧化物(HfLaO)、锆的氧化物(ZrO2)等高K材料。
上述的存储单元可以是包含晶体管的存储单元，所述晶体管可以是存取晶体管，所述存储单元还可以包含其他元器件，如1T1C存储单元中的电容器，或包含2T0C存储单元中的读取晶体管和存储节点。
在本申请的示例性实施例中，所述介电质层的材料可以为氧化硅或High-K介质材料，即介电常数K≥3.9的介质材料。所述High-K介质材料可以包括但不限于以下至少之一：三氧化二铝(Al2O3)、氧化铪。
在本申请的示例性实施例中，所述半导体器件可以为3D存储器，例如，3D DRAM等存储器。所述3D存储器可以为1T1C或2T(含有读晶体管和写晶体管)结构。
本申请实施例还提供一种半导体器件的制造方法，所述半导体器件包括多个存储单元和弛豫缓冲层；所述多个存储单元分布于不同层、沿着垂直于衬底的方向堆叠且周期性分布，所述存储单元包括晶体管。
如上本申请实施例提供的半导体器件可以通过该制造方法得到。
图2为本申请示例性实施例提供的一种半导体器件的制造方法的工艺流程图。
如图2所示，所述半导体器件的制造方法包括：
在所述衬底上形成所述弛豫缓冲层，并使所述弛豫缓冲层为弛豫的膜层；
在所述弛豫缓冲层远离所述衬底的一侧形成所述多个所述存储单元。
本申请实施例的述半导体器件的制造方法在衬底与存储单元之间引入弛豫的弛豫缓冲层，可以在制造半导体器件的过程中降低衬底与外延堆叠结构(例如Si/SiGe的堆叠结构)之间的晶格失配度，进而降低外延堆叠结构中的应变积累，同等条件下，可以增加外延堆叠结构能够堆叠的层数。
另外，弛豫缓冲层的引入可以增加晶体管中沟道区域的张应变，能够提高沟道区域的电子迁移率，可进一步提升晶体管的工作速度(例如，开关速度)。
而且，弛豫缓冲层的引入可以在制造半导体器件的过程中降低外延堆叠结构中的外延牺牲层(例如，SiGe外延牺牲层)的应变积累，使得在同等条件下，外延牺牲层的临界厚度增加，从而可以得到更厚的外延牺牲层，可以降低3D半导体器件加工的工艺难度。
在本申请的示例性实施例中，在所述衬底上形成所述弛豫缓冲层，并使所述弛豫缓冲层为弛豫的膜层可以包括：
采用外延工艺在所述衬底一侧生长第一弛豫缓冲层；其中，沿着从所述衬底到所述第二弛豫缓冲层的方向，所述第一弛豫缓冲层的晶格常数是变化的，所述第一弛豫缓冲层中具有位错，所述第一弛豫缓冲层的远离所述衬底的一侧的区域为应变完全弛豫的膜层；
采用外延工艺在所述第一弛豫缓冲层的远离所述衬底的一侧生长第二弛豫缓冲层，所述第二弛豫缓冲层的晶格结构与所述第一弛豫缓冲层远离所述衬底的一侧的晶格结构一致；所述第一弛豫缓冲层和所述第二弛豫缓冲层构成所述弛豫缓冲层。
在本申请的示例性实施例中，在所述弛豫缓冲层远离所述衬底的一侧形成所述多个存储单元可以包括：
采用外延工艺在所述弛豫缓冲层远离所述衬底的一侧形成隔离层；
采用外延工艺在所述隔离层远离所述衬底的一侧交替生长半导体层和牺牲层，得到由交替的半导体层和牺牲层构成的堆叠结构。
在本申请的示例性实施例中，所述弛豫缓冲层在弛豫状态下的晶格常数不同于所述衬底的晶格常数，所述弛豫缓冲层在弛豫状态下的晶格常数介于所述牺牲层和所述半导体层的晶格常数。
在本申请的示例性实施例中，形成所述多个存储单元还可以包括：在得到所述堆叠结构之后，
对所述堆叠结构中的半导体层进行图案化工艺，使所述半导体层形成所述晶体管的半导体柱，以及在所述半导体柱的至少部分侧壁上形成栅电极，所述半导体柱和所述栅电极构成所述晶体管。
在本申请的示例性实施例中，所述半导体器件的制造方法还可以包括：形成与所述晶体管连接的电容器，所述晶体管和与其连接的所述电容器构成所述存储单元。
下面通过本实施例半导体器件的制造过程进一步说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制备工艺。本实施例中所说的“光刻工艺”包括涂覆膜层、掩模曝光和显影，是相关技术中成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做具体的限定。
图3A为本申请示例性实施例提供的一种半导体器件在形成第一弛豫缓冲层后的纵截面示意图；图3B为图3A所示的半导体器件的俯视图；图4为本申请示例性实施例提供的一种半导体器件在对第一弛豫缓冲层表面进行CMP后的纵截面示意图；图5A为本申请示例性实施例提供的一种半导体器件在形成第二弛豫缓冲层后的纵截面示意图；图5B为图5A所示的半导体器件的俯视图；图6A为本申请示例性实施例提供的一种半导体器件在形成堆叠结构后的纵截面示意图；图6B为图6A所示的半导体器件的俯视图；图7A为本申请示例性实施例提供的一种半导体器件在形成半导体柱后的纵截面示意图；图7B为图7A所示的半导体器件的俯视图；图8A为本申请示例性实施例提供的一种半导体器件在形成位线后的纵截面示意图；图8B为图8A所示的半导体器件的俯视图；图9A为本申请示例性实施例提供的一种半导体器件在去除牺牲层后的纵截面示意图；图9B为图9A所示的半导体器件的俯视图；图10A为本申请示例性实施例提供的一种半导体器件在形成字线后的纵截面示意图；图10B为图10A所示的半导体器件的俯视图。
如图3A至图10B以及和图1A和图1B所示，在本申请的一个示例性实施例中，所述半导体器件的制造方法可以包括以下工艺过程。
S10：提供衬底10，在衬底10上外延生长第一弛豫缓冲层21。
示例性地，步骤S10可以包括：
S11：提供衬底10，对衬底10进行表面处理，包括但不限于：低温烘烤衬底10表面的水汽，然后升至高温并在H2氛围中去除衬底10表面的C和O等杂质元素，使衬底10表面呈现干净且新鲜的Si原子层；
S12：在经过表面处理的衬底10表面外延生长第一弛豫缓冲层21，包括：先在一定的温度T1(例如，T1<600℃)条件下，利用聚碳酸酯活性二氧化硅(DCS)和锗烷(GeH4)作为前驱体生长一定厚度t1(例如，t1>10nm)的Si1-yGey，然后升高温度到T2(例如，T1≤T2≤850℃)再生长一定厚度t2(例如，t2>100nm)的Si1-yGey，然后保持T2的温度进行退火，使得Si1-yGey远离衬底一侧的表面及附近表面的Si1-yGey薄膜的晶格常数基本接近或者达到晶体Si1-yGey晶格常数，即Si1-yGey表面的Si1-yGey薄膜为应变完全弛豫的膜层，得到第一弛豫缓冲层21，如图3A和图3B所示；其中，沿着远离衬底10的方向，第一弛豫缓冲层21的晶格常数是变化的，直至远离衬底一侧的表面及附近表面的Si1-yGey薄膜的晶格常数基本接近或者达到晶体Si1-yGey晶格常数。
由于应变弛豫会引起薄膜表面的粗糙度增加，如图3A所示，形成的第一弛豫缓冲层21表面具有较多凸起，在本实施例中，凸起可高达几十个纳米甚至更高，另外通过切片的截面TEM图像在Si/Si1-yGey界面可以观测到大量的位错(图中未示)出现，在薄膜生长过程中逐渐被抑制，第一弛豫缓冲层21表面的穿透位错密度约为1×106个/cm2至5×107个/cm2。
S20：对第一弛豫缓冲层21表面进行平坦化处理。
示例性地，步骤S20可以包括：
S21：采用化学机械抛光(Chemical Mechanical Polishing,CMP)工艺对第一弛豫缓冲层21表面进行磨抛，磨抛后第一弛豫缓冲层21表面的凸起高度可以降至几个纳米以内，例如，第一弛豫缓冲层21表面的表面粗糙度(RMS)＜2nm；
S22：利用有机试剂和无机试剂对磨抛后的第一弛豫缓冲层21表面进行反复清洗，清洗后的第一弛豫缓冲层21如图4所示。
S30：在第一弛豫缓冲层21远离衬底10的一侧外延生长第二弛豫缓冲层22。
示例性地，步骤S30可以包括：以一定的温度T3(T3≤T2)外延生长一定厚度t3(例如，t3≥10nm)的Si1-yGey层，并使该Si1-yGey层完全按照第一弛豫缓冲层21表面的弛豫的Si1-yGey晶格进行生长(即无应变的Si1-yGey层)，得到第二弛豫缓冲层22，如图5A和图5B所示；其中，第二弛豫缓冲层22中的位错密度明显小于第一弛豫缓冲层21中的位错密度。
S40：在第二弛豫缓冲层22远离衬底10的一侧外延生长第一绝缘层31，以及在第一绝缘层31远离衬底10的一侧交错外延生长半导体层40和牺牲层50，得到由交错堆叠的半导体层40和牺牲层50构成的堆叠结构。
示例性地，步骤S40可以包括：
S41：第一绝缘层31的外延生长，包括：在T3温度下，以DCS作为前驱体在第二弛豫缓冲层22远离衬底10的一侧进行Si外延生长，得到Si外延层形成的第一绝缘层31，第一绝缘层31的厚度为t4(例如，5nm≤t4≤100nm)；第一绝缘层31的作用是作为第二弛豫缓冲层22与堆叠结构之间的隔离层进行绝缘；
S42：堆叠结构的外延生长，包括：继续保持温度为T3，以DCS和GeH4作为前驱体在第一绝缘层31远离衬底10的一侧交错外延生长Si1-xGex(y≤x)和Si的超晶格结构，得到Si/Si1-xGex堆叠结构；其中Si外延层作为半导体层40，用于后续形成晶体管的源/漏电极和沟道；Si1-xGex外延层为应变层，作为牺牲层50，如图6A和图6B所示。
由于堆叠结构是在弛豫的Si1-yGey层上进行共格外延形成，堆叠结构相对弛豫的Si1-yGey层的晶格失配度要小于堆叠结构相对于Si衬底的失配度，故堆叠结构中的应变积累将大大减小，也就意味着可实现共格生长的堆叠结构的临界厚度增加，从而本申请实施例的方案可以进一步增大Si/SiGe堆叠结构的堆叠层数，进而提高3D半导体器件的存储密度。
S50：对所述堆叠结构进行图案化刻蚀，在所述堆叠结构中形成贯穿各半导体层40的第一沟槽61和第二沟槽62，得到图案化的堆叠结构；在第一沟槽61和第二沟槽62中填充第二绝缘层32。
示例性地，步骤S50可以包括：
S51：采用光刻法在所述堆叠结构的远离衬底10的顶面上定义出待形成的第一沟槽61和第二沟槽62的图案，沿着朝向衬底10的方向对所述堆叠结构进行刻蚀，在所述堆叠结构中形成贯穿各半导体层40的多个第一沟槽61和多个第二沟槽62；其中，各第一沟槽61沿垂直于衬底10的方向延伸并且沿平行于衬底10的第一方向延伸，多个第一沟槽61沿平行于衬底10的第二方向间隔分布，多个第一沟槽61将各半导体层40间隔为沿所述第一方向延伸并且沿所述第二方向间隔分布的多个半导体柱41；各第二沟槽62沿垂直于衬底10的方向延伸并且沿所述第二方向延伸，多个第二沟槽62沿所述第一方向间隔分布；
所述第一方向可以为如图7A和图7B所示的X方向，所述第二方向可以为如图7B所示的Y方向，垂直于衬底10的方向可以为如图7A所示的Z方向；第一沟槽61和第二沟槽62可以露出第一绝缘层31，例如，可以使第一沟槽61和第二沟槽62延伸至第一绝缘层31远离衬底10一侧的表面或内部；
S52：在第一沟槽61和第二沟槽62中填满第二绝缘层32，如图7A和图7B所示。第二绝缘层32用于将在沿所述第一方向上相邻的两列存储单元间隔开以及将位于不同层的存储单元间隔开。
示例性地，第二绝缘层32的材料可以为low-K介电质材料，即介电常数K<3.9的介电质材料，包括但不限于硅的氧化物，例如二氧化硅(SiO2)或其他含硅的膜层等，还包括空气(即形成air gap)。
S60：在半导体柱41中刻蚀形成位线孔，在所述位线孔中形成位线70。
示例性地，步骤S60可以包括：沿着朝向衬底10的方向对图案化的堆叠结构进行刻蚀，在图案化的堆叠结构中形成贯穿不同层的各半导体柱41的位线孔，在所述位线孔中形成位线70，并使位线70与各半导体柱41连接，如图8A和图8B所示。
示例性地，相邻两个第二沟槽62之间在所述第一方向上可以具有一个所述位线孔；所述位线孔可以沿垂直于衬底10的方向延伸，并且露出第一绝缘层31，例如，可以使所述位线孔延伸至第一绝缘层31远离衬底10一侧的表面或内部，形成的位线70也沿垂直于衬底10的方向延伸。
示例性地，所述位线的材料可以选自钨、钼、钴等具有相似性质的其他金属材料中的任意一种或多种。所述位线可以为单层或多层结构，例如，可以为由钛(Ti)、氮化钛(TiN) 和钨(W)形成的多层结构。
S70：刻蚀去除牺牲层50。
示例性地，步骤S70可以包括：采用光刻法定义光刻图案，刻蚀去除第一沟槽61中的第二绝缘层32，第一沟槽61的侧壁露出图案化的堆叠结构中的牺牲层50；采用选择性刻蚀工艺去除牺牲层50；在刻蚀去除牺牲层50后腾出的空间和第一沟槽61内填满第二绝缘层32，如图9A和图9B所示。
S80：形成字线和晶体管的栅电极。
相邻两个第二沟槽62之间的一个半导体柱41后续用于形成与同一条位线70连接的两个晶体管90。如图10A所示，沿着远离位线70的方向，半导体柱41依次包括第一电极区42、沟道区43、第二电极区44和第三电极区45，第一电极区42和第二电极区412中的一个用作所述晶体管的源电极，另一个用作所述晶体管的漏电极，第三电极区45用作与该晶体管连接的电容器的内电极。晶体管通过第一电极区42与位线70连接，晶体管通过第二电极区44与电容器的第三电极区连接。
示例性地，步骤S80可以包括：
S81：采用光刻法定义光刻图案，刻蚀去除第一沟槽61中部分区域的第二绝缘层32，使半导体柱41的沟道区43的至少部分侧壁露出；
S82：在沟道区43露出的侧壁上依次沉积栅极绝缘层81和栅电极82，形成环绕沟道区43至少部分侧壁的栅极绝缘层81和栅电极82，半导体柱41和栅电极82构成一个晶体管90；
S83：将位于同一层且沿所述第二方向间隔分布的多个晶体管的栅电极82连接在一起形成一条沿所述第二方向延伸的字线80，晶体管的栅电极82作为该字线80的一部分，如图10A和图10B所示；或者，单独形成一条沿所述第二方向延伸的字线80，并将位于同一层且沿所述第二方向间隔分布的一列晶体管的栅电极82与同一条字线80相连接。
示例性地，步骤S81还可以包括：在露出半导体柱41的沟道区43的至少部分侧壁之后，进行步骤S82之前，
采用选择性刻蚀工艺去除位于不同层的半导体柱41之间的第二绝缘层32，露出半导体柱41的沟道区43的整个侧壁；
步骤S82可以包括：在半导体柱41的沟道区43的整个露出的侧壁表面依次沉积栅极绝缘层81和栅电极82，形成全环绕沟道区43的栅极绝缘层81和栅电极82。
步骤S80还可以包括：在步骤S83之后，
S84：采用第二绝缘层32填充相邻半导体柱41之间的空隙。
S90：形成电容器。
示例性地，步骤S90可以包括：
S91：采用光刻法定义光刻图案，刻蚀去除第一沟槽61中部分区域的第二绝缘层32，使半导体柱41的第三电极区45的至少部分侧壁露出；
S92：在第三电极区45的露出的侧壁上依次沉积介电质层101和第四电极层102，形成环绕第三电极区45的至少部分侧壁的介电质层101和第四电极层102，第三电极区45、介电质层101和第四电极层102构成电容器100，环绕第三电极区45的第四电极层102作为该电容器100的外电极，晶体管90和电容器100构成存储单元110，得到如图1A和 图1B所示的半导体器件。
示例性地，步骤S91还可以包括：在露出半导体柱41的第三电极区45的至少部分侧壁之后，进行步骤S92之前，
采用选择性刻蚀工艺去除位于不同层的半导体柱41之间的第二绝缘层32，露出半导体柱41的第三电极区45的整个侧壁；
步骤S92可以包括：在半导体柱41的第三电极区45的整个露出的侧壁表面依次沉积介电质层101和第四电极层102，形成全环绕第三电极区45的介电质层101和第四电极层102。
示例性地，步骤S90还可以包括：在步骤S92之后，
S93：采用第二绝缘层32填充相邻半导体柱41之间的空隙，位于不同层的相邻两个存储单元110和位于同一层且沿所述第二方向间隔分布的相邻两个存储单元110之间通过第二绝缘层32进行绝缘。
示例性地，第二绝缘层32的材料不限于一种，即各步骤中所采用的第二绝缘层32的材料可以相同或不同。
本申请实施例还提供一种电子设备，所述电子设备包括如上本申请实施例提供的所述半导体器件。
在本申请的示例性实施例中，所述电子设备可以为：存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源等。存储装置可以包括计算机中的内存等，此处不作限定。
虽然本申请所揭露的实施方式如上，但所述的内容仅为便于理解本申请而采用的实施方式，并非用以限定本申请。任何本申请所属领域内的技术人员，在不脱离本申请所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (13)

  1. 一种半导体器件，包括：
    多个存储单元，分布于不同层、沿着垂直于衬底的方向堆叠且周期性分布；每一层包括多列存储单元；
    弛豫缓冲层，位于所述衬底与所述存储单元之间。
  2. 根据权利要求1所述的半导体器件，其中，所述弛豫缓冲层在弛豫状态下的晶格常数不同于所述衬底的晶格常数。
  3. 根据权利要求1所述的半导体器件，其中，所述弛豫缓冲层包括第一弛豫缓冲层和第二弛豫缓冲层，所述第一弛豫缓冲层位于所述衬底与所述第二弛豫缓冲层之间，所述第二弛豫缓冲层位于所述第一弛豫缓冲层与所述存储单元之间；
    沿着远离所述衬底的方向，所述第一弛豫缓冲层的晶格常数是变化的，所述第二弛豫缓冲层的晶格常数是不变的；
    所述第一弛豫缓冲层和所述第二弛豫缓冲层中均具有位错，并且所述第一弛豫缓冲层中的位错密度大于所述第二弛豫缓冲层中的位错密度。
  4. 根据权利要求3所述的半导体器件，其中，所述第一弛豫缓冲层至少在远离所述衬底的一侧的区域为应变完全弛豫的膜层。
  5. 根据权利要求1至4中任一项所述的半导体器件，其中，所述衬底的材料选自硅、锗、硅锗、碳化硅、砷化镓、砷化铟和磷化铟中的任意一种或多种；和/或，
    所述弛豫缓冲层的材料选自硅、锗、硅锗、碳化硅、砷化镓、铝镓砷、铟镓砷、砷化铟和磷化铟中的任意一种或多种；和/或，
    所述存储单元包括晶体管，所述晶体管包括半导体柱；所述半导体柱的主体材料选自硅、锗、硅锗、碳化硅、砷化镓、铟镓砷、砷化铟和磷化铟中的任意一种或多种。
  6. 根据权利要求5所述的半导体器件，其中，所述衬底的材料和所述半导体柱的主体材料均为硅，所述弛豫缓冲层的材料为硅锗；或者，
    所述衬底的材料为硅，所述弛豫缓冲层的材料选自砷化镓、铝镓砷和铟镓砷中的任意一种或多种，所述半导体柱的主体材料为砷化镓或铟镓砷。
  7. 根据权利要求5所述的半导体器件，其中，所述半导体器件还包括隔离层，所述隔离层位于所述弛豫缓冲层与所述存储单元之间，配置为对所述弛豫缓冲层与所述存储单元进行隔离；和/或，
    所述晶体管还包括栅电极，所述栅电极环绕所述半导体柱的至少部分侧壁；和/或，
    所述半导体柱沿平行于所述衬底的第一方向延伸；和/或，
    所述存储单元还包括电容器，所述电容器与同一个所述存储单元中的所述晶体管连接；和/或，
    所述半导体器件还包括：沿垂直于所述衬底的方向延伸的多条位线；和/或，
    位于不同层且沿所述第一方向相邻的两列所述存储单元的所述晶体管与同一条位线连接；
    所述半导体器件还包括：沿平行于所述衬底的第二方向延伸的多条字线；和/或，
    位于同一层且沿所述第二方向排列的一列所述存储单元的所述晶体管与同一条字线连接。
  8. 一种半导体器件的制造方法，所述半导体器件包括多个存储单元和弛豫缓冲层；所述多个存储单元分布于不同层、沿着垂直于衬底的方向堆叠且周期性分布，所述存储单元包括晶体管；
    所述半导体器件的制造方法包括：
    在所述衬底上形成所述弛豫缓冲层，并使所述弛豫缓冲层为弛豫的膜层；
    在所述弛豫缓冲层远离所述衬底的一侧形成所述多个存储单元。
  9. 根据权利要求8所述的制造方法，其中，在所述衬底上形成所述弛豫缓冲层，并使所述弛豫缓冲层为弛豫的膜层包括：
    采用外延工艺在所述衬底一侧生长第一弛豫缓冲层；其中，沿着远离所述衬底的方向，所述第一弛豫缓冲层的晶格常数是变化的，所述第一弛豫缓冲层中具有位错，所述第一弛豫缓冲层的远离所述衬底的一侧的区域为应变完全弛豫的膜层；
    采用外延工艺在所述第一弛豫缓冲层的远离所述衬底的一侧生长第二弛豫缓冲层，所述第二弛豫缓冲层的晶格结构与所述第一弛豫缓冲层远离所述衬底的一侧的晶格结构一致；所述第一弛豫缓冲层和所述第二弛豫缓冲层构成所述弛豫缓冲层。
  10. 根据权利要求9所述的制造方法，其中，在所述弛豫缓冲层远离所述衬底的一侧形成所述多个存储单元包括：
    采用外延工艺在所述弛豫缓冲层远离所述衬底的一侧形成隔离层；
    采用外延工艺在所述隔离层远离所述衬底的一侧交替生长半导体层和牺牲层，得到由交替的半导体层和牺牲层构成的堆叠结构。
  11. 根据权利要求10所述的制造方法，其中，所述弛豫缓冲层在弛豫状态下的晶格常数不同于所述衬底的晶格常数，所述弛豫缓冲层在弛豫状态下的晶格常数介于所述牺牲层和所述半导体层的晶格常数之间。
  12. 根据权利要求10所述的制造方法，其中，形成所述多个存储单元还包括：在得到所述堆叠结构之后，
    对所述堆叠结构中的半导体层进行图案化工艺，使所述半导体层形成所述晶体管的半导体柱，以及在所述半导体柱的至少部分侧壁上形成栅电极，所述半导体柱和所述栅电极构成所述晶体管；和/或
    所述半导体器件的制造方法还包括：形成与所述晶体管连接的电容器，所述晶体管和与其连接的所述电容器构成所述存储单元。
  13. 一种电子设备，包括根据权利要求1至7中任一所述的半导体器件。
PCT/CN2024/075856 2023-09-07 2024-02-04 半导体器件及其制造方法、电子设备 Pending WO2025050596A1 (zh)

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CN115223949A (zh) * 2021-04-19 2022-10-21 三星电子株式会社 半导体器件制造方法
CN115954361A (zh) * 2021-10-07 2023-04-11 三星电子株式会社 半导体器件
CN116583109A (zh) * 2023-06-27 2023-08-11 北京超弦存储器研究院 3d存储器及其制备方法、电子设备

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115223949A (zh) * 2021-04-19 2022-10-21 三星电子株式会社 半导体器件制造方法
CN115954361A (zh) * 2021-10-07 2023-04-11 三星电子株式会社 半导体器件
CN116583109A (zh) * 2023-06-27 2023-08-11 北京超弦存储器研究院 3d存储器及其制备方法、电子设备

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