WO2025035305A1 - 移位寄存器单元、驱动控制电路、显示装置及驱动方法 - Google Patents

移位寄存器单元、驱动控制电路、显示装置及驱动方法 Download PDF

Info

Publication number
WO2025035305A1
WO2025035305A1 PCT/CN2023/112706 CN2023112706W WO2025035305A1 WO 2025035305 A1 WO2025035305 A1 WO 2025035305A1 CN 2023112706 W CN2023112706 W CN 2023112706W WO 2025035305 A1 WO2025035305 A1 WO 2025035305A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
transistor
coupled
signal terminal
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/112706
Other languages
English (en)
French (fr)
Inventor
黄耀
都蒙蒙
董向丹
胡明
邱海军
杨栋芳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2023/112706 priority Critical patent/WO2025035305A1/zh
Priority to GB2512156.7A priority patent/GB2641664A/en
Priority to US18/711,696 priority patent/US20260171027A1/en
Priority to CN202380010096.7A priority patent/CN120112971A/zh
Publication of WO2025035305A1 publication Critical patent/WO2025035305A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register unit, a drive control circuit, a display device and a drive method.
  • the array substrate row drive (Gate Driver on Array, GOA) technology integrates the thin film transistor (Thin Film Transistor, TFT) drive control circuit on the array substrate of the display device to form a drive for the display device.
  • the drive control circuit is usually composed of multiple cascaded shift register units.
  • the output of the shift register unit is unstable, which will cause display abnormality.
  • the present disclosure provides a shift register unit, a drive control circuit, a display device and a drive method, and the specific scheme is as follows:
  • the present disclosure provides a shift register unit, which includes:
  • an input circuit coupled to the first node and configured to provide a signal at an input signal terminal to the first node in response to a signal at a first clock signal terminal;
  • control circuit coupled to the first node, the second node, the control signal terminal and the first reference signal terminal, and configured to provide the signals of the first clock signal terminal and the first reference signal terminal to a third node and the second node respectively in response to the signal of the first node, wherein the first node is not controlled by the second node or the third node;
  • the output circuit is coupled to the first node and the second node, and is configured to provide the signal of the first reference signal terminal to the output signal terminal in response to the signal of the second node, and to provide the signal of the second reference signal terminal to the output signal terminal in response to the signal of the first node.
  • control circuit includes a first control module, a second control module control module and a third control module;
  • the first control module is coupled to the first node and the third node, and is configured to provide the signal of the first clock signal terminal to the third node in response to the signal of the first node, and to provide the signal of the control signal terminal to the third node in response to the signal of the first clock signal terminal;
  • the second control module is coupled to the second node and the third node, and is configured to provide the signal of the second clock signal terminal to the second node in response to the signal of the third node and the second clock signal terminal;
  • the third control module is coupled to the first node and the second node, and is configured to provide a signal at a first reference signal terminal to the second node in response to a signal at the first node.
  • a voltage stabilizing circuit is also included;
  • the voltage stabilization circuit is coupled to the third node and is configured to maintain the potential of the third node.
  • the voltage stabilizing circuit includes a first capacitor
  • a first electrode of the first capacitor is coupled to the third node, and a second electrode of the first capacitor is coupled to the second reference signal terminal.
  • a protection circuit is also included;
  • the third node is coupled to the second control module through the protection circuit, and the protection circuit is configured to control conduction and disconnection between the third node and the second control module.
  • control signal terminal and the first clock signal terminal are the same signal terminal.
  • control signal terminal and the second reference signal terminal are the same signal terminal.
  • the input circuit includes a first transistor
  • a gate of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to the input signal terminal.
  • the first control module includes a second transistor and a third transistor
  • the gate of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the first clock signal terminal, and the second electrode of the second transistor is coupled to the third node;
  • a gate of the third transistor is coupled to the first clock signal terminal, a first electrode of the third transistor is coupled to the third node, and a second electrode of the third transistor is coupled to the control signal terminal.
  • the second control module includes a fourth transistor and a fifth transistor
  • the gate of the fourth transistor is coupled to the third node, the first electrode of the fourth transistor is coupled to the fourth node, and the second electrode of the fourth transistor is coupled to the second clock signal terminal;
  • a gate of the fifth transistor is coupled to the second clock signal terminal, a first electrode of the fifth transistor is coupled to the second node, and a second electrode of the fifth transistor is coupled to the fourth node.
  • a reset circuit is also included;
  • the reset circuit is coupled to the first node and the fourth node, and is configured to provide the signal of the first reference signal terminal to the first node in response to a signal of the fourth node.
  • the third control module includes a sixth transistor
  • a gate of the sixth transistor is coupled to the first node, a first electrode of the sixth transistor is coupled to the first reference signal terminal, and a second electrode of the sixth transistor is coupled to the second node.
  • the output circuit includes a seventh transistor, a second capacitor, an eighth transistor and a third capacitor;
  • the gate of the seventh transistor is coupled to the second node, the first electrode of the seventh transistor is coupled to the output signal terminal, and the second electrode of the seventh transistor is coupled to the second reference signal terminal;
  • a first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the first reference signal terminal;
  • the gate of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the second reference signal terminal, and the second electrode of the eighth transistor is coupled to the output signal terminal. catch;
  • a first electrode of the third capacitor is coupled to the first node, and a second electrode of the third capacitor is coupled to the output signal terminal.
  • the protection circuit includes a ninth transistor
  • the gate of the ninth transistor is coupled to the second reference signal terminal, the first electrode of the ninth transistor is coupled to the gate of the fourth transistor, and the second electrode of the ninth transistor is coupled to the third node.
  • the reset circuit includes a tenth transistor
  • a gate of the tenth transistor is coupled to the fourth node, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the first reference signal terminal.
  • an embodiment of the present disclosure provides a shift register unit, which includes:
  • a first transistor wherein a first electrode of the first transistor is directly connected to the first node
  • a second transistor wherein a gate of the second transistor is directly connected to the first node, and a second electrode of the second transistor is coupled to a third node;
  • a sixth transistor wherein a gate of the sixth transistor is directly connected to the first node, and a second electrode of the sixth transistor is coupled to the second node;
  • an eighth transistor wherein a gate of the eighth transistor is directly connected to the first node, a first electrode of the eighth transistor is coupled to the second reference signal terminal, and a second electrode of the eighth transistor is coupled to the output signal terminal;
  • the first node is not controlled by the second node or the third node.
  • a first capacitor a first electrode of the first capacitor is coupled to the third node, and a second electrode of the first capacitor is coupled to the second reference signal terminal.
  • a ninth transistor is also included.
  • a gate of the ninth transistor is coupled to the second reference signal terminal, and a second electrode of the ninth transistor is coupled to the third node.
  • a tenth transistor is further included;
  • a gate of the tenth transistor is coupled to the fourth node, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the first reference signal terminal.
  • a third transistor a first electrode of the third transistor being coupled to the third node, and a second electrode of the third transistor being coupled to the control signal terminal;
  • a fourth transistor a gate of the fourth transistor being coupled to the third node, and a first electrode of the fourth transistor being coupled to the fourth node;
  • a fifth transistor wherein a first electrode of the fifth transistor is coupled to the second node, and a second electrode of the fifth transistor is coupled to the fourth node;
  • a seventh transistor a gate of the seventh transistor being coupled to the second node, and a first electrode of the seventh transistor being coupled to the output signal terminal;
  • a second capacitor wherein a first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the first reference signal terminal;
  • a third capacitor wherein a first electrode of the third capacitor is coupled to the first node, and a second electrode of the third capacitor is coupled to the output signal terminal.
  • the gate of the first transistor is coupled to the first clock signal terminal, and the second electrode of the first transistor is coupled to the input signal terminal;
  • a first electrode of the second transistor is coupled to the first clock signal terminal
  • the gate of the third transistor is coupled to the first clock signal terminal
  • the second electrode of the fourth transistor is coupled to the second clock signal terminal
  • the gate of the fifth transistor is coupled to the second clock signal terminal
  • the first electrode of the sixth transistor is coupled to the first reference signal terminal
  • the second electrode of the seventh transistor is coupled to the second reference signal terminal
  • the second electrode of the eighth transistor is coupled to the output signal terminal.
  • control signal terminal and the first clock signal terminal are the same signal terminal.
  • control signal terminal and the second reference signal terminal are the same signal terminal.
  • an embodiment of the present disclosure provides a drive control circuit, which includes:
  • the input signal terminal of the first-stage shift register unit is coupled to the frame trigger signal terminal;
  • the input signal terminal of the next shift register unit is coupled to the output signal terminal of the previous shift register unit.
  • an embodiment of the present disclosure provides a display device, comprising:
  • an embodiment of the present disclosure provides a driving method of a shift register unit as described in any one of the above items, comprising:
  • the input circuit responds to the signal of the first clock signal terminal and provides the signal of the input signal terminal to the first node;
  • the control circuit responds to the signal of the first node and provides the signal of the first clock signal terminal and the signal of the first reference signal terminal to the third node and the second node, and controls the potential of the second node to be opposite to the potential of the first node;
  • the output circuit responds to the signal of the first node and provides the signal of the second reference signal terminal to the output signal terminal.
  • FIG1 is a schematic diagram of the structure of a shift register unit in the related art
  • FIG2 is a schematic diagram of voltage simulation waveforms of various nodes of the shift register unit shown in FIG1 in a working state
  • FIG3 is a schematic diagram of some structures of a shift register unit provided by an embodiment of the present disclosure.
  • FIG4 is another schematic diagram of the structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG7 is a timing diagram of some signals provided by an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of some further structures of a shift register unit provided by an embodiment of the present disclosure.
  • FIG9 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG10 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG11 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG12 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG13 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG14 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG15 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG16 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG17 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure.
  • FIG18 is a schematic diagram of some structures of a drive control circuit provided in an embodiment of the present disclosure.
  • FIG. 19 is a flow chart of a method for driving a shift register unit provided in an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of the structure of a shift register unit in a light-emitting drive circuit, and the shift register unit includes transistors M1 to M10 and capacitors C01 to C03.
  • FIG. 2 is a schematic diagram of the voltage simulation waveforms of each node of the shift register unit shown in FIG. 1 in a working state.
  • the potential of point n2 is pulled up by ecb, so that the voltage of point n2 is as high as 35V, which will cause M2, M3, M4, and M9 to be biased too much.
  • the VDS of M2 is as high as 40V
  • the VGS of M4 is 19V.
  • an embodiment of the present disclosure provides a shift register unit, as shown in FIG3 , the shift register unit includes:
  • the input circuit 10 is coupled to the first node N1 and is configured to provide a signal from the input signal terminal IP to the first node N1 in response to a signal from the first clock signal terminal CK;
  • the control circuit 20 is coupled to the first node N1, the second node N2, the control signal terminal CT and the first reference signal terminal VGL, and is configured to provide the signals of the first clock signal terminal and the first reference signal terminal to the third node and the second node respectively in response to the signal of the first node N1, and the first node is not controlled by the second node or the third node;
  • the output circuit 30 is coupled to the first node N1 and the second node N2, and is configured to provide the signal of the first reference signal terminal VGL to the output signal terminal OT in response to the signal of the second node N2, and to provide the signal of the second reference signal terminal VGH to the output signal terminal OT in response to the signal of the first node N1.
  • the signal of the first node N1 is controlled by the input circuit 10; the signals of the second node N2 and the third node N3 are controlled by the control circuit 20, and the second node N2 or the third node N3
  • the signal of the third node N3 will not affect the signal of the first node N1; the signal of the output signal terminal OT is controlled by the output circuit 30.
  • the number of devices used in the entire shift register unit is small, and the circuit complexity is low, which not only has low production cost, simple circuit structure, small occupied area, and is conducive to narrow frame design, but also, through the mutual cooperation of the above devices, the stability of the signal output by the output signal terminal OT can be improved.
  • the control circuit 20 includes a first control module 21 , a second control module 22 and a third control module 23 ;
  • the first control module 21 is coupled to the first node N1 and the third node N3, and is configured to provide the signal of the first clock signal terminal CK to the third node N3 in response to the signal of the first node N1, and to provide the signal of the control signal terminal CT to the third node N3 in response to the signal of the first clock signal terminal CK;
  • the second control module 22 is coupled to the second node N2 and the third node N3, and is configured to provide the signal of the second clock signal terminal CB to the second node N2 in response to the signal of the third node N3 and the second clock signal terminal CB;
  • the third control module 23 is coupled to the first node N1 and the second node N2 , and is configured to provide a signal of the first reference signal terminal VGL to the second node N2 in response to a signal of the first node N1 .
  • control signal terminal CT and the first clock signal terminal CK are the same signal terminal.
  • control signal terminal CT and the first clock signal terminal CK can be coupled together, which can reduce the number of signal lines and reduce the difficulty of wiring.
  • the input circuit 10 includes a first transistor T1;
  • a gate of the first transistor T1 is coupled to the first clock signal terminal CK, a first electrode of the first transistor T1 is coupled to the first node N1, and a second electrode of the first transistor T1 is coupled to the input signal terminal IP.
  • the first transistor T1 can be turned on under the control of the effective level of the first clock signal transmitted by the first clock signal terminal CK, and can be turned off under the control of the ineffective level of the first clock signal.
  • the first transistor T1 is set as an N-type transistor, then the effective level of the first clock signal is a high level, and the ineffective level of the first clock signal is a low level.
  • the input signal terminal IP and the first node N1 can be connected; when the first transistor T1 is in the off state, the input signal terminal IP and the first node N1 can be disconnected.
  • the first control module 21 includes a second transistor T2 and a third transistor T3;
  • the gate of the second transistor T2 is coupled to the first node N1, the first electrode of the second transistor T2 is coupled to the first clock signal terminal CK, and the second electrode of the second transistor T2 is coupled to the third node N3;
  • a gate of the third transistor T3 is coupled to the first clock signal terminal CK, a first electrode of the third transistor T3 is coupled to the third node N3, and a second electrode of the third transistor T3 is coupled to the control signal terminal CT.
  • the gate of the second transistor T2 is coupled to the first node N1, so that the second transistor T2 can be turned on under the control of the effective level of the signal transmitted by the first node N1, and turned off under the control of the invalid level of the signal transmitted by the first node N1.
  • the second transistor T2 is set as an N-type transistor, the effective level of the signal transmitted by the first node N1 is a high level, and the invalid level of the signal transmitted by the first node N1 is a low level.
  • the first clock signal terminal CK can be turned on with the third node N3; when the second transistor T2 is in the off state, the first clock signal terminal CK can be disconnected with the third node N3.
  • the gate of the third transistor T3 is coupled to the first clock signal terminal CK, so that the third transistor T3 can be turned on under the control of the effective level of the first clock signal transmitted by the first clock signal terminal CK, and can be turned off under the control of the invalid level of the first clock signal.
  • the third transistor T3 is set as an N-type transistor, then the effective level of the first clock signal is a high level, and the invalid level of the first clock signal is a low level.
  • the second control module 22 includes a fourth transistor T4 and a fifth transistor T5;
  • the gate of the fourth transistor T4 is coupled to the third node N3, the first electrode of the fourth transistor T4 is coupled to the fourth node N4, and the second electrode of the fourth transistor T4 is coupled to the second clock signal terminal CB;
  • a gate of the fifth transistor T5 is coupled to the second clock signal terminal CB, a first electrode of the fifth transistor T5 is coupled to the second node N2, and a second electrode of the fifth transistor T5 is coupled to the fourth node N4.
  • the fourth transistor T4 is turned on under the control of the effective level of the signal transmitted by the third node N3, and is turned off under the control of the invalid level of the signal transmitted by the third node N3.
  • the fourth transistor T4 is set as an N-type transistor, then the effective level of the signal transmitted by the third node N3 is a high level, and the invalid level of the signal transmitted by the third node N3 is a low level.
  • the second clock signal terminal CB can be connected to the fourth node N4; when the fourth transistor T4 is in the off state, the second clock signal terminal CB can be disconnected from the fourth node N4.
  • the fifth transistor T5 is turned on under the control of the effective level of the second clock signal provided by the second clock signal terminal CB, and is turned off under the control of the invalid level of the signal provided by the second clock signal.
  • the fifth transistor T5 is set as an N-type transistor, then the effective level of the second clock signal is a high level, and the invalid level of the second clock signal is a low level.
  • the third control module 23 includes a sixth transistor T6;
  • a gate of the sixth transistor T6 is coupled to the first node N1 , a first electrode of the sixth transistor T6 is coupled to the first reference signal terminal VGL, and a second electrode of the sixth transistor T6 is coupled to the second node N2 .
  • the sixth transistor T6 is turned on under the control of the effective level of the signal transmitted by the first node N1, and is turned off under the control of the invalid level of the signal transmitted by the first node N1.
  • the sixth transistor T6 is set as an N-type transistor, then the effective level of the signal transmitted by the first node N1 is a high level, and the invalid level of the signal transmitted by the first node N1 is a low level.
  • the sixth transistor T6 is in the on state, the first reference signal terminal VGL can be connected to the second node N2; when the sixth transistor T6 is in the off state, the first reference signal terminal VGL can be disconnected from the second node N2.
  • the output circuit 30 includes a seventh transistor T7, A second capacitor C2, an eighth transistor T8 and a third capacitor C3;
  • the gate of the seventh transistor T7 is coupled to the second node N2, the first electrode of the seventh transistor T7 is coupled to the output signal terminal OT, and the second electrode of the seventh transistor T7 is coupled to the second reference signal terminal VGH;
  • a first electrode of the second capacitor C2 is coupled to the second node N2, and a second electrode of the second capacitor C2 is coupled to the first reference signal terminal VGL;
  • the gate of the eighth transistor T8 is coupled to the first node N1, the first electrode of the eighth transistor T8 is coupled to the second reference signal terminal VGH, and the second electrode of the eighth transistor T8 is coupled to the output signal terminal OT;
  • a first electrode of the third capacitor C3 is coupled to the first node N1 , and a second electrode of the third capacitor C3 is coupled to the output signal terminal OT.
  • the seventh transistor T7 is turned on under the control of the effective level of the signal transmitted by the second node N2, and is turned off under the control of the invalid level of the signal transmitted by the second node N2.
  • the seventh transistor T7 is set as an N-type transistor, then the effective level of the signal transmitted by the second node N2 is a high level, and the invalid level of the signal transmitted by the second node N2 is a low level.
  • the eighth transistor T8 is turned on under the control of the effective level of the signal transmitted by the first node N1, and is turned off under the control of the invalid level of the signal transmitted by the first node N1.
  • the eighth transistor T8 is set as an N-type transistor, then the effective level of the signal transmitted by the first node N1 is a high level, and the invalid level of the signal transmitted by the first node N1 is a low level.
  • the first electrode of the above-mentioned transistor can be used as its source, and the second electrode can be used as its drain; or, the first electrode can be used as its drain, and the second electrode can be used as its source, without making a specific distinction here.
  • the transistor mentioned in the embodiments of the present disclosure can be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), and no limitation is made here.
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the active layer of each transistor in the above transistors may be made of metal oxide semiconductor material, and accordingly, each transistor may be made of metal oxide semiconductor material as an active layer.
  • the first reference signal terminal VGL can be configured to load a constant first reference voltage, and the first reference voltage is generally a negative value, such as -9V.
  • the second reference signal terminal VGH can load a constant second reference voltage, and the second reference voltage can generally be a positive value, such as 7V.
  • the specific values of the above voltages can be designed and determined according to the actual application environment, and are not limited here.
  • the above transistors can all be set as P-type transistors, which are not limited here.
  • the present disclosure also provides another structural diagram of a shift register unit, as shown in Figure 6, which is a modification of the embodiment in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the shift register unit further includes a voltage stabilizing circuit 40 ; the voltage stabilizing circuit 40 is coupled to the third node N3 and is configured to maintain the potential of the third node N3 .
  • the voltage stabilizing circuit 40 includes a first capacitor C1;
  • a first electrode of the first capacitor C1 is coupled to the third node N3 , and a second electrode of the first capacitor C1 is coupled to the second reference signal terminal VGH.
  • the first capacitor C1 can maintain the potential of the third node N3, thereby improving the stability of the voltage of the third node N3 and effectively avoiding the problem of excessive bias voltage of the third node N3.
  • control signal terminal CT and the first clock signal terminal CK are the same signal terminal.
  • control signal terminal CT and the first clock signal terminal CK may be coupled together, which may reduce the number of signal lines and reduce wiring difficulty.
  • the voltage value of the first reference signal vgl output by the first reference signal terminal VGL is a negative voltage
  • the voltage value of the second reference signal vgh output by the second reference signal terminal VGH is a positive voltage
  • all transistors are N-type transistors as an example for explanation, and the four stages of the first stage f1, the second stage f2, the third stage f3 and the fourth stage f4 in the signal timing diagram shown in FIG7 are selected.
  • the signal timing diagram shown in FIG7 is only the working process of a certain shift register unit in the current frame, and the working processes of the shift register unit in other frames are basically the same as the working process in the current frame, and will not be repeated here.
  • the input signal ip provides a high level
  • the first clock signal ck provides a high level
  • the second clock signal cb provides a low level
  • the first transistor T1 and the third transistor T3 are both turned on
  • the high level of the input signal ip is provided to the first node N1
  • the second transistor T2 the sixth transistor T6 and the eighth transistor T8 are all turned on
  • the high level of the first clock signal ck is provided to the third node N3
  • the fourth transistor T4 is turned on
  • the low level of the second clock signal cb is provided to the fourth node N4
  • the fifth transistor T5 is turned off
  • the low level of the first reference signal vgl is provided to the second node N2
  • the seventh transistor T7 is turned off
  • the high level of the second reference signal vgh is provided to the output signal terminal OT
  • the output signal terminal OT outputs a high level.
  • the input signal ip provides a low level
  • the first clock signal ck provides a low level
  • the second clock signal cb provides a high level
  • the first transistor T1 and the third transistor T3 are both turned off
  • the first node N1 maintains a high level
  • the second transistor T2 the sixth transistor T6 and the eighth transistor T8 are all turned on
  • the low level of the first clock signal ck is provided to the third node N3
  • the fourth transistor T4 is turned off
  • the fifth transistor T5 is turned on
  • the second node N2 maintains a low level
  • the seventh transistor T7 is turned off
  • the low level of the second node N2 is provided to the fourth node N4
  • the high level of the second reference signal vgh is provided to the output signal terminal OT
  • the output signal terminal OT outputs a high level.
  • the input signal ip provides a low level
  • the first clock signal ck provides a high level
  • the second clock signal cb provides a low level
  • the first transistor T1 and the third transistor T3 are both turned on
  • the input signal ip The low level of the second clock signal cb is provided to the first node N1, the second transistor T2, the sixth transistor T6 and the eighth transistor T8 are all turned off
  • the third node N3 is at a high level
  • the fourth transistor T4 is turned on
  • the low level of the second clock signal cb is provided to the fourth node N4
  • the fifth transistor T5 is turned off
  • the second node N2 maintains a low level
  • the seventh transistor T7 is turned off
  • the output signal terminal OT outputs a high level.
  • the input signal ip provides a low level
  • the first clock signal ck provides a low level
  • the second clock signal cb provides a high level
  • the first transistor T1 and the third transistor T3 are both turned off
  • the first node N1 maintains a low level
  • the second transistor T2 the sixth transistor T6 and the eighth transistor T8 are all turned off
  • the third node N3 maintains a high level
  • the fourth transistor T4 is turned on
  • the high level of the second clock signal cb is provided to the fourth node N4
  • the fifth transistor T5 is turned on
  • the second node N2 is a high level
  • the seventh transistor T7 is turned on
  • the low level of the first reference signal vgl is provided to the output signal terminal OT
  • the output signal terminal OT outputs a low level.
  • the potential of the third node N3 can be reduced from the original 35V to 17V, thereby greatly reducing the bias environment of the relevant transistors and improving the stability of the shift register unit.
  • the disclosed embodiment also provides another structural schematic diagram of the shift register unit, as shown in FIG8, which is modified for the embodiment mode in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the substantially similar parts are not repeated here.
  • the shift register unit further includes a voltage stabilizing circuit 40 ;
  • the voltage stabilizing circuit 40 is coupled to the third node N3 and is configured to maintain the potential of the third node N3.
  • the voltage stabilizing circuit 40 includes a first capacitor C1;
  • a first electrode of the first capacitor C1 is coupled to the third node N3 , and a second electrode of the first capacitor C1 is coupled to the second reference signal terminal VGH.
  • the first capacitor C1 can maintain the potential of the third node N3, thereby improving the stability of the voltage of the third node N3 and effectively avoiding the problem of excessive bias voltage of the third node N3.
  • control signal terminal CT and the second reference signal The signal terminal VGH is the same signal terminal.
  • control signal terminal CT and the second reference signal terminal VGH may be coupled together, which may reduce the number of signal lines and reduce wiring difficulty.
  • the disclosed embodiment also provides another structural diagram of a shift register unit, as shown in Figure 9, which is a modification of the embodiment in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • control signal terminal CT and the second reference signal terminal VGH are the same signal terminal.
  • control signal terminal CT and the second reference signal terminal VGH may be coupled together, which may reduce the number of signal lines and reduce wiring difficulty.
  • the disclosed embodiment also provides another structural diagram of a shift register unit, as shown in Figure 10, which is a modification of the embodiment in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the shift register unit further includes a protection circuit 50 ;
  • the third node N3 is coupled to the second control module 22 through the protection circuit 50 , and the protection circuit 50 is configured to control conduction and disconnection between the third node N3 and the second control module 22 .
  • control signal terminal CT and the second reference signal terminal VGH are the same signal terminal.
  • control signal terminal CT and the second reference signal terminal VGH may be coupled together, which may reduce the number of signal lines and reduce wiring difficulty.
  • the protection circuit 50 includes a ninth transistor T9;
  • a gate of the ninth transistor T9 is coupled to the second reference signal terminal VGH, a first electrode of the ninth transistor T9 is coupled to the gate of the fourth transistor T4, and a second electrode of the ninth transistor T9 is coupled to the third node N3.
  • the ninth transistor T9 is turned on under the control of the effective level of the second reference signal provided by the second reference signal terminal VGH, and is turned off under the control of the ineffective level of the second reference signal.
  • the ninth transistor T9 is set as an N-type transistor, the effective level of the second reference signal is a high level, and the invalid level of the second reference signal is a low level.
  • the gate of the fourth transistor T4 can be connected to the third node N3; when the ninth transistor T9 is in the off state, the gate of the fourth transistor T4 can be disconnected from the third node N3.
  • the present disclosure also provides another structural diagram of a shift register unit, as shown in Figure 11, which is a modification of the embodiment in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the shift register unit further includes a protection circuit 50;
  • the third node N3 is coupled to the second control module 22 through the protection circuit 50 , and the protection circuit 50 is configured to control conduction and disconnection between the third node N3 and the second control module 22 .
  • control signal terminal CT and the first clock signal terminal CK are the same signal terminal.
  • control signal terminal CT and the first clock signal terminal CK may be coupled together, which may reduce the number of signal lines and reduce wiring difficulty.
  • the protection circuit 50 includes a ninth transistor T9;
  • a gate of the ninth transistor T9 is coupled to the second reference signal terminal VGH, a first electrode of the ninth transistor T9 is coupled to the gate of the fourth transistor T4, and a second electrode of the ninth transistor T9 is coupled to the third node N3.
  • the ninth transistor T9 is turned on under the control of the effective level of the second reference signal provided by the second reference signal terminal VGH, and is turned off under the control of the invalid level of the second reference signal.
  • the ninth transistor T9 is set as an N-type transistor, then the effective level of the second reference signal is a high level, and the invalid level of the second reference signal is a low level.
  • the gate of the fourth transistor T4 can be turned on with the third node N3; when the ninth transistor T9 is in the off state, the gate of the fourth transistor T4 can be disconnected with the third node N3.
  • the present disclosure also provides another structural diagram of a shift register unit, as shown in FIG12 , which is a modification of the embodiment in the above embodiment.
  • FIG12 is a modification of the embodiment in the above embodiment. The differences between the above embodiments and their similarities are not described in detail here.
  • the shift register unit further includes a voltage stabilizing circuit 40 ;
  • the voltage stabilizing circuit 40 is coupled to the third node N3 and is configured to maintain the potential of the third node N3.
  • the voltage stabilizing circuit 40 includes a first capacitor C1;
  • a first electrode of the first capacitor C1 is coupled to the third node N3 , and a second electrode of the first capacitor C1 is coupled to the second reference signal terminal VGH.
  • the first capacitor C1 can maintain the potential of the third node N3, thereby improving the stability of the voltage of the third node N3 and effectively avoiding the problem of excessive bias voltage of the third node N3.
  • the shift register unit further includes a reset circuit 60 ;
  • the reset circuit 60 is coupled to the first node N1 and the fourth node N4 , and is configured to provide the signal of the first reference signal terminal VGL to the first node N1 in response to the signal of the fourth node N4 .
  • the reset circuit 60 includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is coupled to the fourth node N4 , a first electrode of the tenth transistor T10 is coupled to the first node N1 , and a second electrode of the tenth transistor T10 is coupled to the first reference signal terminal VGL.
  • the tenth transistor T10 is turned on under the control of the effective level of the signal transmitted by the fourth node N4, and is turned off under the control of the invalid level of the signal transmitted by the fourth node N4.
  • the tenth transistor T10 is set as an N-type transistor, then the effective level of the signal transmitted by the fourth node N4 is a high level, and the invalid level of the signal transmitted by the fourth node N4 is a low level.
  • the tenth transistor T10 is in the on state, the first node N1 and the fourth node N4 can be connected; when the tenth transistor T10 is in the off state, the first node N1 and the fourth node N4 can be disconnected.
  • a shift register unit comprising:
  • a first transistor T1 wherein a first electrode of the first transistor T1 is directly connected to a first node N1;
  • a second transistor T2 wherein a gate of the second transistor T2 is directly connected to the first node N1, and a second electrode of the second transistor T2 is coupled to a third node N3;
  • a sixth transistor T6 wherein a gate of the sixth transistor T6 is directly connected to the first node N1, and a second electrode of the sixth transistor T6 is coupled to the second node N2;
  • an eighth transistor T8 wherein a gate of the eighth transistor T8 is directly connected to the first node N1, a first electrode of the eighth transistor T8 is coupled to the second reference signal terminal VGH, and a second electrode of the eighth transistor T8 is coupled to the output signal terminal OT;
  • the first node N1 is not controlled by the second node N2 or the third node N3.
  • the shift register unit further includes:
  • the shift register unit further includes:
  • a third transistor T3 wherein a first electrode of the third transistor T3 is coupled to the third node N3, and a second electrode of the third transistor T3 is coupled to the control signal terminal CT;
  • a fourth transistor T4 wherein a gate of the fourth transistor T4 is coupled to the third node N3, and a first electrode of the fourth transistor T4 is coupled to the fourth node N4;
  • a fifth transistor T5 wherein a first electrode of the fifth transistor T5 is coupled to the second node N2, and a second electrode of the fifth transistor T5 is coupled to the fourth node N4;
  • a seventh transistor T7 wherein a gate of the seventh transistor T7 is coupled to the second node N2, and a first electrode of the seventh transistor T7 is coupled to the output signal terminal OT;
  • a second capacitor C2 wherein a first electrode of the second capacitor C2 is coupled to the second node N2, and a second electrode of the second capacitor C2 is coupled to the first reference signal terminal VGL;
  • the gate of the first transistor T1 is connected to The first clock signal terminal CK is coupled, and the second electrode of the first transistor T1 is coupled to the input signal terminal IP;
  • a first electrode of the second transistor T2 is coupled to the first clock signal terminal CK;
  • the gate of the third transistor T3 is coupled to the first clock signal terminal CK;
  • the second electrode of the fourth transistor T4 is coupled to the second clock signal terminal CB;
  • the gate of the fifth transistor T5 is coupled to the second clock signal terminal CB;
  • a first electrode of the sixth transistor T6 is coupled to the first reference signal terminal VGL;
  • the second electrode of the seventh transistor T7 is coupled to the second reference signal terminal VGH;
  • a second electrode of the eighth transistor T8 is coupled to the output signal terminal OT.
  • control signal terminal CT and the first clock signal terminal CK are the same signal terminal.
  • control signal terminal CT and the second reference signal terminal VGH are the same signal terminal.
  • the shift register unit further includes a ninth transistor T9;
  • a gate of the ninth transistor T9 is coupled to the second reference signal terminal VGH, and a second electrode of the ninth transistor T9 is coupled to the third node N3.
  • the shift register unit further includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is coupled to the fourth node N4 , a first electrode of the tenth transistor T10 is coupled to the first node N1 , and a second electrode of the tenth transistor T10 is coupled to the first reference signal terminal VGL.
  • the principle of solving the problem by the shift register unit is similar to that of the aforementioned shift register unit. Therefore, the implementation of the shift register unit can refer to the description of the aforementioned part, and the repeated parts will not be repeated.
  • the embodiment of the present disclosure also provides a drive control circuit, including a stage A plurality of shift register units are connected in series; the input signal end of the first shift register unit is coupled to the frame trigger signal end; in each two adjacent shift register units, the input signal end of the next shift register unit is coupled to the output signal end of the previous shift register unit.
  • the drive control circuit includes a plurality of cascaded shift register units SR1, SR2, SR3, ..., SRn-2, SRn-1, and SRn; wherein n is a natural number greater than 6.
  • the value of n depends on the actual design requirements.
  • the shift register unit can adopt the shift register unit illustrated in FIG6 above, and each shift register unit includes an input signal terminal, an output signal terminal, a first clock signal terminal, and a second clock signal terminal.
  • each endpoint is connected to the signal marked by the timing diagram shown in Figure 7: the input signal end of the shift register unit SR1 is coupled to the frame trigger signal end, stv represents the frame trigger signal provided by the frame trigger signal end, and in each of the remaining shift register units, the signal output end of the previous shift register unit is coupled to the input signal end of the next shift register unit, that is, the signal output by the output signal end of the shift register unit SR1 can be used as the signal of the input signal end of the shift register unit SR2, and the signal output by the output signal end of the shift register unit SR2 can be used as the signal of the input signal end of the shift register unit SR3...
  • the signal at the output signal end of the shift register unit SRn-1 can be used as the signal of the input signal end of the shift register unit SRn, until there is no next-level shift register unit.
  • the first clock signal end is connected to the first clock signal, and the second clock signal end is connected to the second clock signal.
  • the timing of other drive control circuits can be inferred based on the connection relationship of each shift register unit and the timing shown in Figure 7, which will not be repeated here.
  • the drive control circuit can be configured in a liquid crystal display panel or in an electroluminescent display panel, which is not limited here.
  • each shift register unit in the above-mentioned drive control circuit is the same as the above-mentioned shift register unit in the present disclosure in terms of function and structure, and the repeated parts are not repeated.
  • the drive control circuit can be configured in a liquid crystal display panel or in an electroluminescent display panel, which is not limited here.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned drive control circuit provided by the embodiment of the present disclosure.
  • the principle of solving the problem by the display device is similar to that of the above-mentioned drive control circuit, so the implementation of the display device can refer to the implementation of the above-mentioned drive control circuit.
  • the repeated parts will not be repeated here.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.
  • the display device may include multiple pixel units, multiple gate lines and data lines, and each pixel unit may include multiple sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels.
  • the above-mentioned display device provided in the embodiment of the present disclosure may be an organic light-emitting display device, or may also be a liquid crystal display device, which is not limited here.
  • the display device includes a plurality of scan lines; the plurality of scan lines are also provided with corresponding drive control circuits; one scan line is electrically connected to the signal output terminal of the first-stage shift register unit in the drive control circuit.
  • the TFT in the sub-pixel can be electrically connected to the scan line, and the above-mentioned drive control circuit can be used as a gate drive circuit, and the gate drive circuit is electrically connected to the scan line, and is used to provide a gate scan signal to the TFT in the sub-pixel.
  • the TFT in the sub-pixel can be an N-type transistor or a P-type transistor, which is not limited here.
  • the display device includes a plurality of light-emitting control signal lines and a plurality of scanning lines; a driving control circuit is provided corresponding to the plurality of light-emitting control signal lines; and one light-emitting control signal line is electrically connected to the signal output terminal of a first-level shift register unit in the driving control circuit. Also, a plurality of scanning lines are also provided corresponding to the driving control circuit; and one scanning line is electrically connected to the signal output terminal of a first-level shift register unit in the driving control circuit.
  • a plurality of organic light-emitting diodes and a pixel circuit connected to each organic light-emitting diode are generally provided.
  • a light-emitting control transistor for controlling the light emission of the organic light-emitting diode and a scanning control transistor for controlling the input of a data signal are provided in the pixel circuit.
  • the display device provided in the embodiment of the present disclosure is an organic light-emitting display device
  • the light-emitting control transistor can be electrically connected to the light-emitting control signal line
  • the scan control transistor can be electrically connected to the scan line.
  • the organic light-emitting display device may include an organic light-emitting display device provided in the embodiment of the present disclosure.
  • the driving control circuit can be used as a light-emitting driving circuit, and the light-emitting driving circuit is electrically connected to the light-emitting control transistor, and is used to provide a light-emitting control signal for the light-emitting control transistor; or, the driving control circuit can also be used as a gate driving circuit, and the gate driving circuit is electrically connected to the scan line, and is used to provide a gate scanning signal for the scan control transistor.
  • the organic light-emitting display device can also include two of the above-mentioned driving control circuits provided in the embodiments of the present disclosure, one of which can be used as a light-emitting driving circuit, electrically connected to the light-emitting control transistor, and is used to provide a light-emitting control signal for the light-emitting control transistor; and the other driving control circuit can be used as a gate driving circuit, electrically connected to the scan line, and is used to provide a gate scanning signal for the scan control transistor, which is not limited here.
  • the embodiment of the present disclosure further provides a driving method of the above-mentioned shift register unit, including:
  • the input circuit responds to the signal of the first clock signal terminal and provides the signal of the input signal terminal to the first node;
  • the control circuit responds to the signal of the first node and provides the signal of the first clock signal terminal and the signal of the first reference signal terminal to the third node and the second node, and controls the potential of the second node to be opposite to the potential of the first node;
  • the output circuit responds to the signal of the first node and provides the signal of the second reference signal terminal to the output signal terminal.
  • the driving method further includes:
  • control circuit provides the signal of the first clock signal terminal and the signal of the first reference signal terminal to the third node and the second node in response to the signal of the first node, and controls the potential of the second node to be opposite to the potential of the first node;
  • output circuit provides the signal of the second reference signal terminal to the output signal terminal in response to the signal of the first node;
  • the input circuit responds to the signal of the first clock signal terminal and provides the signal of the input signal terminal to the first node;
  • the control circuit responds to the signal of the first node and provides the signal of the first clock signal terminal and the signal of the first reference signal terminal to the first node.
  • supplying the third node and the second node controlling the potential of the second node to be opposite to the potential of the first node;
  • the output circuit responds to the signal of the first node, and supplies the signal of the second reference signal terminal to the output signal terminal;
  • control circuit responds to the signal of the first node to provide the signal of the first clock signal end and the signal of the first reference signal end to the third node and the second node, thereby controlling the potentials of the first node and the second node to be opposite; the output circuit responds to the signal of the second node to provide the signal of the first reference signal end to the output signal end.
  • the driving principle and specific implementation of the driving method are the same as those of the shift register unit in the above embodiment. Therefore, the driving method can be implemented with reference to the specific implementation of the shift register unit in the above embodiment, which will not be described in detail here.
  • the shift register unit, driving control circuit, display device and driving method provided by the embodiments of the present disclosure control the signal of the first node through the input circuit; control the signals of the second node and the third node through the control circuit, and the signal of the second node or the third node will not affect the signal of the first node; and control the signal of the output signal end through the output circuit.
  • the number of devices used in the entire shift register unit is small, and the circuit complexity is low. Not only is the production cost low, the circuit structure is simple, the occupied area is small, and it is conducive to the narrow frame design, but also, through the mutual cooperation of the above devices, the stability of the signal output by the output signal end can be improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种移位寄存器单元、驱动控制电路、显示装置及驱动方法，其中，移位寄存器单元包括：输入电路（10），与第一节点（N1）耦接，被配置为响应于第一时钟信号端（CK）的信号，将输入信号端（IP）的信号提供给第一节点（N1）；控制电路（20），与第一节点（N1）、第二节点（N2）、控制信号端（CT）以及第一参考信号端（VGL）耦接，被配置为响应于第一节点（N1）的信号，分别将第一时钟信号端（CK）与第一参考信号端（VGL）的信号提供给第三节点（N3）与第二节点（N2），第一节点（N1）不受第二节点（N2）或者第三节点（N3）的控制；输出电路（30），与第一节点（N1）和第二节点（N2）耦接，被配置为响应于第二节点（N2）的信号，将第一参考信号端（VGL）的信号提供给输出信号端（OT），以及响应于第一节点（N1）的信号，将第二参考信号端（VGH）的信号提供给输出信号端（OT）。

Description

移位寄存器单元、驱动控制电路、显示装置及驱动方法 技术领域
本公开涉及显示技术领域，特别涉及移位寄存器单元、驱动控制电路、显示装置及驱动方法。
背景技术
随着显示技术的飞速发展，显示装置越来越向着高集成度和低成本的方向发展。其中，阵列基板行驱动(Gate Driver on Array，GOA)技术将薄膜晶体管(Thin Film Transistor，TFT)驱动控制电路集成在显示装置的阵列基板上以形成对显示装置的驱动。其中，驱动控制电路通常由多个级联的移位寄存器单元构成。然而，移位寄存器单元输出不稳定，会导致显示异常。
发明内容
本公开提供了移位寄存器单元、驱动控制电路、显示装置及驱动方法，具体方案如下：
本公开实施例提供了一种移位寄存器单元，其中，包括：
输入电路，与第一节点耦接，被配置为响应于第一时钟信号端的信号，将输入信号端的信号提供给所述第一节点；
控制电路，与所述第一节点、第二节点、控制信号端以及第一参考信号端耦接，被配置为响应于所述第一节点的信号，分别将所述第一时钟信号端与所述第一参考信号端的信号提供给第三节点与所述第二节点，所述第一节点不受所述第二节点或者所述第三节点的控制；
输出电路，与所述第一节点和所述第二节点耦接，被配置为响应于所述第二节点的信号，将所述第一参考信号端的信号提供给输出信号端，以及响应于所述第一节点的信号，将第二参考信号端的信号提供给所述输出信号端。
可选地，在本公开实施例中，所述控制电路包括第一控制模块、第二控 制模块和第三控制模块；
所述第一控制模块，与所述第一节点和所述第三节点耦接，被配置为响应于所述第一节点的信号，将所述第一时钟信号端的信号提供给所述第三节点，以及响应于所述第一时钟信号端的信号，将所述控制信号端的信号提供给所述第三节点；
所述第二控制模块，与所述第二节点和所述第三节点耦接，被配置为响应于所述第三节点和第二时钟信号端的信号，将所述第二时钟信号端的信号提供给所述第二节点；
所述第三控制模块，与所述第一节点和所述第二节点耦接，被配置为响应于所述第一节点的信号，将第一参考信号端的信号提供给所述第二节点。
可选地，在本公开实施例中，还包括稳压电路；
所述稳压电路与所述第三节点耦接，被配置为保持所述第三节点的电位。
可选地，在本公开实施例中，所述稳压电路包括第一电容；
所述第一电容的第一极与所述第三节点耦接，所述第一电容的第二极与所述第二参考信号端耦接。
可选地，在本公开实施例中，还包括保护电路；
所述第三节点通过所述保护电路与所述第二控制模块耦接，所述保护电路被配置为控制所述第三节点与所述第二控制模块之间的导通与断开。
可选地，在本公开实施例中，所述控制信号端与所述第一时钟信号端为同一信号端。
可选地，在本公开实施例中，所述控制信号端与所述第二参考信号端为同一信号端。
可选地，在本公开实施例中，所述输入电路包括第一晶体管；
所述第一晶体管的栅极与所述第一时钟信号端耦接，所述第一晶体管的第一极与所述第一节点耦接，所述第一晶体管的第二极与所述输入信号端耦接。
可选地，在本公开实施例中，所述第一控制模块包括第二晶体管和第三 晶体管；
所述第二晶体管的栅极与所述第一节点耦接，所述第二晶体管的第一极与所述第一时钟信号端耦接，所述第二晶体管的第二极与所述第三节点耦接；
所述第三晶体管的栅极与所述第一时钟信号端耦接，所述第三晶体管的第一极与所述第三节点耦接，所述第三晶体管的第二极与所述控制信号端耦接。
可选地，在本公开实施例中，所述第二控制模块包括第四晶体管和第五晶体管；
所述第四晶体管的栅极与所述第三节点耦接，所述第四晶体管的第一极与第四节点耦接，所述第四晶体管的第二极与所述第二时钟信号端耦接；
所述第五晶体管的栅极与所述第二时钟信号端耦接，所述第五晶体管的第一极与所述第二节点耦接，所述第五晶体管的第二极与所述第四节点耦接。
可选地，在本公开实施例中，还包括复位电路；
所述复位电路与所述第一节点和第四节点耦接，被配置为响应于所述第四节点的信号，将所述第一参考信号端的信号提供给所述第一节点。
可选地，在本公开实施例中，所述第三控制模块包括第六晶体管；
所述第六晶体管的栅极与所述第一节点耦接，所述第六晶体管的第一极与所述第一参考信号端耦接，所述第六晶体管的第二极与所述第二节点耦接。
可选地，在本公开实施例中，所述输出电路包括第七晶体管、第二电容、第八晶体管和第三电容；
所述第七晶体管的栅极与所述第二节点耦接，所述第七晶体管的第一极与所述输出信号端耦接，所述第七晶体管的第二极与所述第二参考信号端耦接；
所述第二电容的第一极与所述第二节点耦接，所述第二电容的第二极与所述第一参考信号端耦接；
所述第八晶体管的栅极与所述第一节点耦接，所述第八晶体管的第一极与所述第二参考信号端耦接，所述第八晶体管的第二极与所述输出信号端耦 接；
所述第三电容的第一极与所述第一节点耦接，所述第三电容的第二极与所述输出信号端耦接。
可选地，在本公开实施例中，所述保护电路包括第九晶体管；
所述第九晶体管的栅极与所述第二参考信号端耦接，所述第九晶体管的第一极与第四晶体管的栅极耦接，所述第九晶体管的第二极与所述第三节点耦接。
可选地，在本公开实施例中，所述复位电路包括第十晶体管；
所述第十晶体管的栅极与所述第四节点耦接，所述第十晶体管的第一极与所述第一节点耦接，所述第十晶体管的第二极与所述第一参考信号端耦接。
相应地，本公开实施例提供了一种移位寄存器单元，其中，包括：
第一晶体管，所述第一晶体管的第一极与第一节点直接连接；
第二晶体管，所述第二晶体管的栅极与所述第一节点直接连接，所述第二晶体管的第二极与第三节点耦接；
第六晶体管，所述第六晶体管的栅极与所述第一节点直接连接，所述第六晶体管的第二极与第二节点耦接；
第八晶体管，所述第八晶体管的栅极与所述第一节点直接连接，所述第八晶体管的第一极与第二参考信号端耦接，所述第八晶体管的第二极与输出信号端耦接；
所述第一节点不受所述第二节点或者所述第三节点的控制。
可选地，在本公开实施例中，还包括：
第一电容；所述第一电容的第一极与所述第三节点耦接，所述第一电容的第二极与所述第二参考信号端耦接。
可选地，在本公开实施例中，还包括第九晶体管；
所述第九晶体管的栅极与所述第二参考信号端耦接，所述第九晶体管的第二极与所述第三节点耦接。
可选地，在本公开实施例中，还包括第十晶体管；
所述第十晶体管的栅极与第四节点耦接，所述第十晶体管的第一极与所述第一节点耦接，所述第十晶体管的第二极与所述第一参考信号端耦接。
可选地，在本公开实施例中，还包括：
第三晶体管，所述第三晶体管的第一极与所述第三节点耦接，所述第三晶体管的第二极与控制信号端耦接；
第四晶体管，所述第四晶体管的栅极与所述第三节点耦接，所述第四晶体管的第一极与所述第四节点耦接；
第五晶体管，所述第五晶体管的第一极与所述第二节点耦接，所述第五晶体管的第二极与所述第四节点耦接；
第七晶体管，所述第七晶体管的栅极与所述第二节点耦接，所述第七晶体管的第一极与所述输出信号端耦接；
第二电容，所述第二电容的第一极与所述第二节点耦接，所述第二电容的第二极与第一参考信号端耦接；
第三电容，所述第三电容的第一极与所述第一节点耦接，所述第三电容的第二极与所述输出信号端耦接。
可选地，在本公开实施例中，其中，
所述第一晶体管的栅极与所述第一时钟信号端耦接，所述第一晶体管的第二极与输入信号端耦接；
所述第二晶体管的第一极与所述第一时钟信号端耦接；
所述第三晶体管的栅极与所述第一时钟信号端耦接；
所述第四晶体管的第二极与所述第二时钟信号端耦接；
所述第五晶体管的栅极与所述第二时钟信号端耦接；
所述第六晶体管的第一极与所述第一参考信号端耦接；
所述第七晶体管的第二极与所述第二参考信号端耦接；
所述第八晶体管的第二极与所述输出信号端耦接。
可选地，在本公开实施例中，所述控制信号端与所述第一时钟信号端为同一信号端。
可选地，在本公开实施例中，所述控制信号端与所述第二参考信号端为同一信号端。
相应地，本公开实施例提供了一种驱动控制电路，其中，包括：
级联的多个如上面任一项所述的移位寄存器单元；
第一级移位寄存器单元的输入信号端与帧触发信号端耦接；
每相邻的两级移位寄存器单元中，下一级移位寄存器单元的输入信号端与上一级移位寄存器单元的输出信号端耦接。
相应地，本公开实施例提供了一种显示装置，其中，包括：
如上面所述的驱动控制电路。
相应地，本公开实施例提供了一种如上面任一项所述的移位寄存器单元的驱动方法，包括：
第一阶段，所述输入电路响应于所述第一时钟信号端的信号，将所述输入信号端的信号提供给所述第一节点；所述控制电路响应于所述第一节点的信号，将所述第一时钟信号端的信号与所述第一参考信号端的信号提供给所述第三节点与所述第二节点，控制所述第二节点的电位与所述第一节点的电位相反；所述输出电路响应于所述第一节点的信号，将所述第二参考信号端的信号提供给所述输出信号端。
附图说明
图1为相关技术中移位寄存器单元的结构示意图；
图2为图1所示的移位寄存器单元在工作状态下的各个节点电压仿真波形示意图；
图3为本公开实施例提供的一种移位寄存器单元的一些结构示意图；
图4为本公开实施例提供的一种移位寄存器单元的另一些结构示意图；
图5为本公开实施例提供的一种移位寄存器单元的又一些结构示意图；
图6为本公开实施例提供的一种移位寄存器单元的又一些结构示意图；
图7为本公开实施例提供的一些信号时序图；
图8为本公开实施例提供的一种移位寄存器单元的又一些结构示意图；
图9为本公开实施例提供的一种移位寄存器单元的又一些结构示意图；
图10为本公开实施例提供的一种移位寄存器单元的又一些结构示意图；
图11为本公开实施例提供的一种移位寄存器单元的又一些结构示意图；
图12为本公开实施例提供的一种移位寄存器单元的又一些结构示意图；
图13为本公开实施例提供的一种移位寄存器单元的又一些结构示意图；
图14为本公开实施例提供的一种移位寄存器单元的又一些结构示意图；
图15为本公开实施例提供的一种移位寄存器单元的又一些结构示意图；
图16为本公开实施例提供的一种移位寄存器单元的又一些结构示意图；
图17为本公开实施例提供的一种移位寄存器单元的又一些结构示意图；
图18为本公开实施例提供的驱动控制电路的一些结构示意图；
图19为本公开实施例提供的一种移位寄存器单元的驱动方法的方法流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者 机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
在相关技术中，结合图1和图2所示，其中，图1为发光驱动电路中移位寄存器单元的结构示意图，该移位寄存器单元包括晶体管M1～M10以及电容C01～C03。图2为图1所示的移位寄存器单元在工作状态下的各个节点电压仿真波形示意图。其中，在t04阶段，n2点电位被ecb拉高，使得n2点电压高达35V，会导致M2、M3、M4、M9偏压过大，比如，此时M2的VDS高达40V，M4的VGS为19V。一旦这些晶体管偏压过大容易造成器件特性偏移，从而影响发光驱动电路使用性能。
有鉴于此，本公开实施例提供了一种移位寄存器单元，如图3所示，该移位寄存器单元包括：
输入电路10，与第一节点N1耦接，被配置为响应于第一时钟信号端CK的信号，将输入信号端IP的信号提供给所述第一节点N1；
控制电路20，与所述第一节点N1、第二节点N2、控制信号端CT以及第一参考信号端VGL耦接，被配置为响应于所述第一节点N1的信号，分别将所述第一时钟信号端与所述第一参考信号端的信号提供给第三节点与所述第二节点，所述第一节点不受所述第二节点或者所述第三节点的控制；
输出电路30，与所述第一节点N1和所述第二节点N2耦接，被配置为响应于所述第二节点N2的信号，将所述第一参考信号端VGL的信号提供给输出信号端OT，以及响应于所述第一节点N1的信号，将第二参考信号端VGH的信号提供给所述输出信号端OT。
在本公开实施例中，通过输入电路10控制第一节点N1的信号；通过控制电路20控制第二节点N2和第三节点N3的信号，而且第二节点N2或者第 三节点N3的信号不会影响第一节点N1的信号；通过输出电路30控制输出信号端OT的信号。整个移位寄存器单元中所采用的器件数量少，电路复杂度低，不仅生产成本低，电路结构简单，占用面积小，利于窄边框设计，而且，通过上述器件的相互配合，可以使输出信号端OT输出的信号的稳定性提高。
在本公开实施例中，如图4所示，所述控制电路20包括第一控制模块21、第二控制模块22和第三控制模块23；
所述第一控制模块21，与所述第一节点N1和所述第三节点N3耦接，被配置为响应于所述第一节点N1的信号，将所述第一时钟信号端CK的信号提供给所述第三节点N3，以及响应于所述第一时钟信号端CK的信号，将所述控制信号端CT的信号提供给所述第三节点N3；
所述第二控制模块22，与所述第二节点N2和所述第三节点N3耦接，被配置为响应于所述第三节点N3和第二时钟信号端CB的信号，将所述第二时钟信号端CB的信号提供给所述第二节点N2；
所述第三控制模块23，与所述第一节点N1和所述第二节点N2耦接，被配置为响应于所述第一节点N1的信号，将第一参考信号端VGL的信号提供给所述第二节点N2。
在本公开实施例中，如图5所示，所述控制信号端CT与所述第一时钟信号端CK为同一信号端。示例性的，可以将控制信号端CT和第一时钟信号端CK耦接在一起，这样可以降低信号线的数量，降低布线难度。
在本公开实施例中，如图5所示，所述输入电路10包括第一晶体管T1；
所述第一晶体管T1的栅极与所述第一时钟信号端CK耦接，所述第一晶体管T1的第一极与所述第一节点N1耦接，所述第一晶体管T1的第二极与所述输入信号端IP耦接。
在具体实施过程中，第一晶体管T1可以在第一时钟信号端CK传输的第一时钟信号的有效电平的控制下导通，可以在第一时钟信号的无效电平的控制下截止。示例性的，第一晶体管T1设置为N型晶体管，则第一时钟信号的有效电平为高电平，第一时钟信号的无效电平为低电平。在第一晶体管T1处 于导通状态时，可以将输入信号端IP与第一节点N1导通；在第一晶体管T1处于截止状态时，可以将输入信号端IP与第一节点N1断开。
在本公开实施例中，如图5所示，所述第一控制模块21包括第二晶体管T2和第三晶体管T3；
所述第二晶体管T2的栅极与所述第一节点N1耦接，所述第二晶体管T2的第一极与所述第一时钟信号端CK耦接，所述第二晶体管T2的第二极与所述第三节点N3耦接；
所述第三晶体管T3的栅极与所述第一时钟信号端CK耦接，所述第三晶体管T3的第一极与所述第三节点N3耦接，所述第三晶体管T3的第二极与所述控制信号端CT耦接。
在具体实施过程中，第二晶体管T2的栅极与第一节点N1耦接，这样的话，第二晶体管T2可以在第一节点N1传输的信号的有效电平的控制下导通，在第一节点N1传输的信号的无效电平的控制下截止。示例性的，第二晶体管T2设置为N型晶体管，第一节点N1传输的信号的有效电平为高电平，第一节点N1传输的信号的无效电平为低电平。在第二晶体管T2处于导通状态时，可以将第一时钟信号端CK与第三节点N3导通；在第二晶体管T2处于截止状态时，可以将第一时钟信号端CK与第三节点N3断开。
在具体实施过程中，第三晶体管T3的栅极与第一时钟信号端CK耦接，这样的话，第三晶体管T3可以在第一时钟信号端CK传输的第一时钟信号的有效电平的控制下导通，可以在第一时钟信号的无效电平的控制下截止。示例性的，第三晶体管T3设置为N型晶体管，则第一时钟信号的有效电平为高电平，第一时钟信号的无效电平为低电平。
在本公开实施例中，如图5所示，所述第二控制模块22包括第四晶体管T4和第五晶体管T5；
所述第四晶体管T4的栅极与所述第三节点N3耦接，所述第四晶体管T4的第一极与第四节点N4耦接，所述第四晶体管T4的第二极与所述第二时钟信号端CB耦接；
所述第五晶体管T5的栅极与所述第二时钟信号端CB耦接，所述第五晶体管T5的第一极与所述第二节点N2耦接，所述第五晶体管T5的第二极与所述第四节点N4耦接。
在具体实施过程中，第四晶体管T4在第三节点N3传输的信号的有效电平的控制下导通，在第三节点N3传输的信号的无效电平的控制下截止。示例性的，第四晶体管T4设置为N型晶体管，则第三节点N3传输的信号的有效电平为高电平，第三节点N3传输的信号的无效电平为低电平。在第四晶体管T4处于导通状态时，可以将第二时钟信号端CB与第四节点N4导通；在第四晶体管T4处于截止状态时，可以将第二时钟信号端CB与第四节点N4断开。
在具体实施过程中，第五晶体管T5在第二时钟信号端CB提供的第二时钟信号的有效电平的控制下导通，在第二时钟信号提供的信号的无效电平的控制下截止。示例性的，第五晶体管T5设置为N型晶体管，则第二时钟信号的有效电平为高电平，第二时钟信号的无效电平为低电平。
在本公开实施例中，如图5所示，所述第三控制模块23包括第六晶体管T6；
所述第六晶体管T6的栅极与所述第一节点N1耦接，所述第六晶体管T6的第一极与所述第一参考信号端VGL耦接，所述第六晶体管T6的第二极与所述第二节点N2耦接。
在具体实施过程中，第六晶体管T6在第一节点N1传输的信号的有效电平的控制下导通，在第一节点N1传输的信号的无效电平的控制下截止。示例性的，第六晶体管T6设置为N型晶体管，则第一节点N1传输的信号的有效电平为高电平，第一节点N1传输的信号的无效电平为低电平。在第六晶体管T6处于导通状态时，可以将第一参考信号端VGL与第二节点N2导通；在第六晶体管T6处于截止状态时，可以将第一参考信号端VGL与第二节点N2断开。
在本公开实施例中，如图5所示，所述输出电路30包括第七晶体管T7、 第二电容C2、第八晶体管T8和第三电容C3；
所述第七晶体管T7的栅极与所述第二节点N2耦接，所述第七晶体管T7的第一极与所述输出信号端OT耦接，所述第七晶体管T7的第二极与所述第二参考信号端VGH耦接；
所述第二电容C2的第一极与所述第二节点N2耦接，所述第二电容C2的第二极与所述第一参考信号端VGL耦接；
所述第八晶体管T8的栅极与所述第一节点N1耦接，所述第八晶体管T8的第一极与所述第二参考信号端VGH耦接，所述第八晶体管T8的第二极与所述输出信号端OT耦接；
所述第三电容C3的第一极与所述第一节点N1耦接，所述第三电容C3的第二极与所述输出信号端OT耦接。
在具体实施过程中，第七晶体管T7在第二节点N2传输的信号的有效电平的控制下导通，在第二节点N2传输的信号的无效电平的控制下截止。示例性的，第七晶体管T7设置为N型晶体管，则第二节点N2传输的信号的有效电平为高电平，第二节点N2传输的信号的无效电平为低电平。
在具体实施过程中，第八晶体管T8在第一节点N1传输的信号的有效电平的控制下导通，在第一节点N1传输的信号的无效电平的控制下截止。示例性的，第八晶体管T8设置为N型晶体管，则第一节点N1传输的信号的有效电平为高电平，第一节点N1传输的信号的无效电平为低电平。
在具体实施过程中，根据信号的流通方向，上述晶体管的第一极可以作为其源极，第二极可以作为其漏极；或者，第一极作为其漏极，第二极作为其源极，在此不作具体区分。
需要说明的是，本公开实施例中提到的晶体管可以是薄膜晶体管(Thin Film Transistor，TFT)，也可以是金属氧化物半导体场效应管(Metal Oxide Semiconductor，MOS)，在此不做限定。
在本公开实施例中，上述晶体管中各个晶体管的有源层可以为金属氧化物半导体材料，相应地，各个晶体管可以为用金属氧化物半导体材料作为有 源层的N型晶体管；第一参考信号端VGL可以被配置为加载恒定的第一参考电压，并且第一参考电压一般为负值，比如，-9V。以及，第二参考信号端VGH可以加载恒定的第二参考电压，并且第二参考电压一般可以为正值，比如，7V。在实际应用中，上述电压具体数值可以根据实际应用环境来设计确定，在此不做限定。此外，上述晶体管可以均设置为P型晶体管，在此不做限定。
本公开实施例还提供了移位寄存器单元的另一种结构示意图，如图6所示，其针对上述实施例中的实施例方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不做赘述。
在本公开实施例中，如图6所示，移位寄存器单元还包括稳压电路40；所述稳压电路40与所述第三节点N3耦接，被配置为保持所述第三节点N3的电位。
在图6所示的示例性实施例中，所述稳压电路40包括第一电容C1；
所述第一电容C1的第一极与所述第三节点N3耦接，所述第一电容C1的第二极与所述第二参考信号端VGH耦接。
在具体实施过程中，第一电容C1可以保持第三节点N3的电位，从而提高第三节点N3的电压的稳定性，有效避免了第三节点N3偏压过大的问题。
在本公开实施例中，如图6所示，所述控制信号端CT与所述第一时钟信号端CK为同一信号端。
示例性的，可以将控制信号端CT与第一时钟信号端CK耦接在一起，这样可以降低信号线的数量，降低布线难度。
下面以图6所示的移位寄存器单元为例，结合图7所示的信号时序图，对本公开实施例提供的上述移位寄存器单元的工作过程作以描述。在下面描述中，以“1”表示高电平信号，以“0”表示低电平信号，ip表示输入信号端IP的输入信号，ck表示第一时钟信号端CK的第一时钟信号，cb表示第二时钟信号端CB的第二时钟信号，ot表示输出信号端OT的输出信号。需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作 过程，而不是在具体实施时施加在各晶体管的栅极上的电压。
具体地，以第一参考信号端VGL输出的第一参考信号vgl的电压值为负压，第二参考信号端VGH输出的第二参考信号vgh的电压值为正压，所有晶体管均为N型晶体管为例进行说明，选取图7所示的信号时序图中的第一阶段f1、第二阶段f2、第三阶段f3以及第四阶段f4这四个阶段。需要说明的是，图7所示的信号时序图仅是某个移位寄存器单元在当前帧中的工作过程，该移位寄存器单元在其它帧中的工作过程分别与该当前帧中的工作过程基本相同，在此不做赘述。
在第一阶段f1中，ip＝1，ck＝1，cb＝0；
由于输入信号ip提供高电平，第一时钟信号ck提供高电平，第二时钟信号cb提供低电平，则第一晶体管T1和第三晶体管T3均导通，输入信号ip的高电平提供给第一节点N1，第二晶体管T2、第六晶体管T6和第八晶体管T8均导通，第一时钟信号ck的高电平提供给第三节点N3，第四晶体管T4导通，第二时钟信号cb的低电平提供给第四节点N4，第五晶体管T5截止，第一参考信号vgl的低电平提供给第二节点N2，第七晶体管T7截止，第二参考信号vgh的高电平提供给输出信号端OT，则输出信号端OT输出高电平。
在第二阶段f2中，ip＝0，ck＝0，cb＝1；
由于输入信号ip提供低电平，第一时钟信号ck提供低电平，第二时钟信号cb提供高电平，则第一晶体管T1和第三晶体管T3均截止，第一节点N1维持高电平，第二晶体管T2、第六晶体管T6和第八晶体管T8均导通，第一时钟信号ck的低电平提供给第三节点N3，第四晶体管T4截止，第五晶体管T5导通，第二节点N2维持低电平，第七晶体管T7截止，第二节点N2的低电平提供给第四节点N4，第二参考信号vgh的高电平提供给输出信号端OT，则输出信号端OT输出高电平。
在第三阶段f3，ip＝0，ck＝1，cb＝0；
由于输入信号ip提供低电平，第一时钟信号ck提供高电平，第二时钟信号cb提供低电平，则第一晶体管T1和第三晶体管T3均导通，输入信号ip 的低电平提供给第一节点N1，第二晶体管T2、第六晶体管T6和第八晶体管T8均截止，第三节点N3为高电平，第四晶体管T4导通，第二时钟信号cb的低电平提供给第四节点N4，第五晶体管T5截止，第二节点N2维持低电平，第七晶体管T7截止，则输出信号端OT输出高电平。
在第四阶段f4，ip＝0，ck＝0，cb＝1；
由于输入信号ip提供低电平，第一时钟信号ck提供低电平，第二时钟信号cb提供高电平，则第一晶体管T1和第三晶体管T3均截止，第一节点N1维持低电平，第二晶体管T2、第六晶体管T6和第八晶体管T8均截止，第三节点N3维持高电平，第四晶体管T4导通，第二时钟信号cb的高电平提供给第四节点N4，第五晶体管T5导通，第二节点N2为高电平，第七晶体管T7导通，第一参考信号vgl的低电平提供给输出信号端OT，输出信号端OT输出低电平。
需要说明的是，在图6所示的示例性实施例中，第三节点N3的电位可以由原来的35V降低至17V，从而极大地减少了相关晶体管的偏压环境，提高了移位寄存器单元的稳定性能。本公开实施例还提供了移位寄存器单元的另一种结构示意图，如图8所示，其针对上述实施例中的实施例方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不做赘述。
在本公开实施例中，如图8所示，移位寄存器单元还包括稳压电路40；
所述稳压电路40与所述第三节点N3耦接，被配置为保持所述第三节点N3的电位。
在图8所示的示例性实施例中，所述稳压电路40包括第一电容C1；
所述第一电容C1的第一极与所述第三节点N3耦接，所述第一电容C1的第二极与所述第二参考信号端VGH耦接。
在具体实施过程中，第一电容C1可以保持第三节点N3的电位，从而提高第三节点N3的电压的稳定性，有效避免了第三节点N3偏压过大的问题。
在本公开实施例中，如图8所示，所述控制信号端CT与所述第二参考信 号端VGH为同一信号端。
示例性的，可以将控制信号端CT与第二参考信号端VGH耦接在一起，这样可以降低信号线的数量，降低布线难度。
本公开实施例还提供了移位寄存器单元的另一种结构示意图，如图9所示，其针对上述实施例中的实施例方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不做赘述。
在本公开实施例中，如图9所示，所述控制信号端CT与所述第二参考信号端VGH为同一信号端。
示例性的，可以将控制信号端CT与第二参考信号端VGH耦接在一起，这样可以降低信号线的数量，降低布线难度。
本公开实施例还提供了移位寄存器单元的另一种结构示意图，如图10所示，其针对上述实施例中的实施例方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不做赘述。
在本公开实施例中，如图10所示，移位寄存器单元还包括保护电路50；
所述第三节点N3通过所述保护电路50与所述第二控制模块22耦接，所述保护电路50被配置为控制所述第三节点N3与所述第二控制模块22之间的导通与断开。
在本公开实施例中，如图10所示，所述控制信号端CT与所述第二参考信号端VGH为同一信号端。
示例性的，可以将控制信号端CT与第二参考信号端VGH耦接在一起，这样可以降低信号线的数量，降低布线难度。
在本公开实施例中，如图10所示，所述保护电路50包括第九晶体管T9；
所述第九晶体管T9的栅极与所述第二参考信号端VGH耦接，所述第九晶体管T9的第一极与第四晶体管T4的栅极耦接，所述第九晶体管T9的第二极与所述第三节点N3耦接。
在具体实施过程中，第九晶体管T9在第二参考信号端VGH提供的第二参考信号的有效电平的控制下导通，在第二参考信号的无效电平的控制下截 止。示例性的，第九晶体管T9设置为N型晶体管，则第二参考信号的有效电平为高电平，第二参考信号的无效电平为低电平。在第九晶体管T9处于导通状态时，可以将第四晶体管T4的栅极与第三节点N3导通；在第九晶体管T9处于截止状态时，可以将第四晶体管T4的栅极与第三节点N3断开。
本公开实施例还提供了移位寄存器单元的另一种结构示意图，如图11所示，其针对上述实施例中的实施例方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不做赘述。
在本公开实施例中，如图11所示，移位寄存器单元还包括保护电路50；
所述第三节点N3通过所述保护电路50与所述第二控制模块22耦接，所述保护电路50被配置为控制所述第三节点N3与所述第二控制模块22之间的导通与断开。
在本公开实施例中，如图11所示，所述控制信号端CT与所述第一时钟信号端CK为同一信号端。
示例性的，可以将控制信号端CT与第一时钟信号端CK耦接在一起，这样可以降低信号线的数量，降低布线难度。
在本公开实施例中，如图11所示，所述保护电路50包括第九晶体管T9；
所述第九晶体管T9的栅极与所述第二参考信号端VGH耦接，所述第九晶体管T9的第一极与第四晶体管T4的栅极耦接，所述第九晶体管T9的第二极与所述第三节点N3耦接。
在具体实施过程中，第九晶体管T9在第二参考信号端VGH提供的第二参考信号的有效电平的控制下导通，在第二参考信号的无效电平的控制下截止。示例性的，第九晶体管T9设置为N型晶体管，则第二参考信号的有效电平为高电平，第二参考信号的无效电平为低电平。在第九晶体管T9处于导通状态时，可以将第四晶体管T4的栅极与第三节点N3导通；在第九晶体管T9处于截止状态时，可以将第四晶体管T4的栅极与第三节点N3断开。
本公开实施例还提供了移位寄存器单元的另一种结构示意图，如图12所示，其针对上述实施例中的实施例方式进行了变形。下面仅说明本实施例与 上述实施例的区别之处，其大致相同之处在此不做赘述。
在本公开实施例中，如图12所示，移位寄存器单元还包括稳压电路40；
所述稳压电路40与所述第三节点N3耦接，被配置为保持所述第三节点N3的电位。
在本公开实施例中，如图12所示，所述稳压电路40包括第一电容C1；
所述第一电容C1的第一极与所述第三节点N3耦接，所述第一电容C1的第二极与所述第二参考信号端VGH耦接。
在具体实施过程中，第一电容C1可以保持第三节点N3的电位，从而提高第三节点N3的电压的稳定性，有效避免了第三节点N3偏压过大的问题。
在本公开实施例中，如图12所示，移位寄存器单元还包括复位电路60；
所述复位电路60与所述第一节点N1和第四节点N4耦接，被配置为响应于所述第四节点N4的信号，将所述第一参考信号端VGL的信号提供给所述第一节点N1。
在本公开实施例中，如图12所示，所述复位电路60包括第十晶体管T10；
所述第十晶体管T10的栅极与所述第四节点N4耦接，所述第十晶体管T10的第一极与所述第一节点N1耦接，所述第十晶体管T10的第二极与所述第一参考信号端VGL耦接。
在具体实施过程中，第十晶体管T10在第四节点N4传输的信号的有效电平的控制下导通，在第四节点N4传输的信号的无效电平的控制下截止。示例性的，第十晶体管T10设置为N型晶体管，则第四节点N4传输的信号的有效电平为高电平，第四节点N4传输的信号的无效电平为低电平。在第十晶体管T10处于导通状态时，可以将第一节点N1与第四节点N4导通；在第十晶体管T10处于截止状态时，可以将第一节点N1与第四节点N4断开。
以上仅是举例说明本公开实施例提供的移位寄存器单元的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
基于同一公开构思，如图13至图17所示，本公开实施例还提供了一种 移位寄存器单元，包括：
第一晶体管T1，所述第一晶体管T1的第一极与第一节点N1直接连接；
第二晶体管T2，所述第二晶体管T2的栅极与所述第一节点N1直接连接，所述第二晶体管T2的第二极与第三节点N3耦接；
第六晶体管T6，所述第六晶体管T6的栅极与所述第一节点N1直接连接，所述第六晶体管T6第二极与第二节点N2耦接；
第八晶体管T8，所述第八晶体管T8的栅极与所述第一节点N1直接连接，所述第八晶体管T8的第一极与第二参考信号端VGH耦接，所述第八晶体管T8的第二极与输出信号端OT耦接；
所述第一节点N1不受第二节点N2或者第三节点N3的控制。
在图14和图15所示的示例性实施例中，移位寄存器单元还包括：
第一电容C1；所述第一电容C1的第一极与所述第三节点N3耦接，所述第一电容C1的第二极与所述第二参考信号端VGH耦接。
在本公开实施例中，如图14和图15所示，移位寄存器单元还包括：
第三晶体管T3，所述第三晶体管T3的第一极与所述第三节点N3耦接，所述第三晶体管T3的第二极与控制信号端CT耦接；
第四晶体管T4，所述第四晶体管T4的栅极与所述第三节点N3耦接，所述第四晶体管T4的第一极与所述第四节点N4耦接；
第五晶体管T5，所述第五晶体管T5的第一极与所述第二节点N2耦接，所述第五晶体管T5的第二极与所述第四节点N4耦接；
第七晶体管T7，所述第七晶体管T7的栅极与所述第二节点N2耦接，所述第七晶体管T7的第一极与所述输出信号端OT耦接；
第二电容C2，所述第二电容C2的第一极与所述第二节点N2耦接，所述第二电容C2的第二极与第一参考信号端VGL耦接；
第三电容C3，所述第三电容C3的第一极与所述第一节点N1耦接，所述第三电容C3的第二极与所述输出信号端OT耦接。
在本公开实施例中，如图14和图15所示，所述第一晶体管T1的栅极与 所述第一时钟信号端CK耦接，所述第一晶体管T1的第二极与输入信号端IP耦接；
所述第二晶体管T2的第一极与所述第一时钟信号端CK耦接；
所述第三晶体管T3的栅极与所述第一时钟信号端CK耦接；
所述第四晶体管T4的第二极与所述第二时钟信号端CB耦接；
所述第五晶体管T5的栅极与所述第二时钟信号端CB耦接；
所述第六晶体管T6的第一极与所述第一参考信号端VGL耦接；
所述第七晶体管T7的第二极与所述第二参考信号端VGH耦接；
所述第八晶体管T8的第二极与所述输出信号端OT耦接。
在本公开实施例中，如图14所示，所述控制信号端CT与所述第一时钟信号端CK为同一信号端。
在本公开实施例中，如图15所示，所述控制信号端CT与所述第二参考信号端VGH为同一信号端。
在本公开实施例中，如图16所示，移位寄存器单元还包括第九晶体管T9；
所述第九晶体管T9的栅极与所述第二参考信号端VGH耦接，所述第九晶体管T9的第二极与所述第三节点N3耦接。
在本公开实施例中，如图17所示，移位寄存器单元还包括第十晶体管T10；
所述第十晶体管T10的栅极与第四节点N4耦接，所述第十晶体管T10的第一极与所述第一节点N1耦接，所述第十晶体管T10的第二极与所述第一参考信号端VGL耦接。
以上仅是举例说明本公开实施例提供的移位寄存器单元的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在具体实施过程中，该移位寄存器单元解决问题的原理与前述移位寄存器单元相似，因此，该移位寄存器单元的实施可以参见前述部分的描述，重复之处不再赘述。
基于同一公开构思，本公开实施例还提供了一种驱动控制电路，包括级 联的多个移位寄存器单元；第一级移位寄存器单元的输入信号端与帧触发信号端耦接；每相邻的两级移位寄存器单元中，下一级移位寄存器单元的输入信号端与上一级移位寄存器单元的输出信号端耦接。
示例性的，如图18所示，驱动控制电路包括多个级联的移位寄存器单元SR1、SR2、SR3……SRn-2、SRn-1和SRn；其中n为大于6的自然数。其中，n的取值取决于实际的设计需要。该移位寄存器单元可以采用前述图6示例的移位寄存器单元，每一移位寄存器单元包括输入信号端、输出信号端、第一时钟信号端和第二时钟信号端。其中，各端点接入如图7所示的时序图所标记的信号：移位寄存器单元SR1的输入信号端与帧触发信号端耦接，stv表示帧触发信号端提供的帧触发信号，其余的每一级移位寄存器单元中，上一级移位寄存器单元的信号输出端与下一级移位寄存器单元的输入信号端耦接，即，移位寄存器单元SR1输出信号端输出的信号可以作为移位寄存器单元SR2的输入信号端的信号，移位寄存器单元SR2的输出信号端输出的信号可以作为移位寄存器单元SR3的输入信号端的信号……移位寄存器单元SRn-1的输出信号端的信号可以作为移位寄存器单元SRn的输入信号端的信号，直到无下一级移位寄存器单元为止。第一时钟信号端接入第一时钟信号，第二时钟信号端接入第二时钟信号。其它驱动控制电路的时序可以根据各移位寄存器单元的连接关系及图7所示的时序进行推理得到，在此不再赘述。该驱动控制电路可以应被配置为液晶显示面板中，也可以应被配置为电致发光显示面板中，在此不做限定。
具体地，上述驱动控制电路中的每个移位寄存器单元的具体结构与本公开上述移位寄存器单元在功能和结构上均相同，重复之处不再赘述。该驱动控制电路可以应被配置为液晶显示面板中，也可以应被配置为电致发光显示面板中，在此不作限定。
基于同一公开构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述驱动控制电路。该显示装置解决问题的原理与前述驱动控制电路相似，因此该显示装置的实施可以参见前述驱动控制电路的实施，重 复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
在具体实施时，显示装置可以包括多个像素单元，多条栅线和数据线，每个像素单元可以包括多个子像素，例如红色子像素、绿色子像素以及蓝色子像素。本公开实施例提供的上述显示装置可以为有机发光显示装置，或者也可以为液晶显示装置，在此不作限定。
在本公开实施例中，显示装置包括多条扫描线；多条扫描线也对应设置有驱动控制电路；一条扫描线与驱动控制电路中的一级移位寄存器单元的信号输出端电连接。例如，在本公开实施例提供的上述显示装置为液晶显示装置时，子像素中的TFT可以与扫描线电连接，并且使上述驱动控制电路可以作为栅极驱动电路，且该栅极驱动电路与扫描线电连接，应用于给子像素中的TFT提供栅极扫描信号。需要说明的是，子像素中的TFT可以为N型晶体管或P型晶体管，在此不作限定。
在本公开实施例中，显示装置包括多条发光控制信号线和多条扫描线；多条发光控制信号线对应设置有驱动控制电路；一条发光控制信号线与驱动控制电路中的一级移位寄存器单元的信号输出端电连接。以及，多条扫描线也对应设置有驱动控制电路；一条扫描线与驱动控制电路中的一级移位寄存器单元的信号输出端电连接。例如，在有机发光显示装置中，一般设置有多个有机发光二极管以及与各有机发光二极管连接的像素电路。一般像素电路中设置有用于控制有机发光二极管发光的发光控制晶体管和用于控制数据信号输入的扫描控制晶体管。
在具体实施时，在本公开实施例提供的上述显示装置为有机发光显示装置时，发光控制晶体管可以与发光控制信号线电连接，扫描控制晶体管可以与扫描线电连接，该有机发光显示装置可以包括一个本公开实施例提供的上 述驱动控制电路，该驱动控制电路可以作为发光驱动电路，且该发光驱动电路与发光控制晶体管电连接，应用于提供发光控制晶体管的发光控制信号；或者，该驱动控制电路也可以作为栅极驱动电路，且该栅极驱动电路与扫描线电连接，应用于提供扫描控制晶体管的栅极扫描信号。当然，该有机发光显示装置也可以包括两个本公开实施例提供的上述驱动控制电路，其中一个驱动控制电路可以作为发光驱动电路，与发光控制晶体管电连接，应用于提供发光控制晶体管的发光控制信号；则另一个驱动控制电路作为栅极驱动电路，与扫描线电连接，应用于提供扫描控制晶体管的栅极扫描信号，在此不作限定。
基于同一公开构思，如图19所示，本公开实施例还提供了一种上述的移位寄存器单元的驱动方法，包括：
S101：第一阶段，所述输入电路响应于所述第一时钟信号端的信号，将所述输入信号端的信号提供给所述第一节点；所述控制电路响应于所述第一节点的信号，将所述第一时钟信号端的信号与所述第一参考信号端的信号提供给所述第三节点与所述第二节点，控制所述第二节点的电位与所述第一节点的电位相反；所述输出电路响应于所述第一节点的信号，将所述第二参考信号端的信号提供给所述输出信号端。
在本公开实施例中，仍结合图19所示，在所述第一阶段之后，所述驱动方法还包括：
S102：第二阶段，所述控制电路响应于所述第一节点的信号，将所述第一时钟信号端的信号与所述第一参考信号端的信号提供给所述第三节点与所述第二节点，控制所述第二节点的电位与所述第一节点的电位相反；所述输出电路响应于所述第一节点的信号，将所述第二参考信号端的信号提供给所述输出信号端；
S103：第三阶段，所述输入电路响应于所述第一时钟信号端的信号，将所述输入信号端的信号提供给所述第一节点；所述控制电路响应于所述第一节点的信号，将所述第一时钟信号端的信号与所述第一参考信号端的信号提 供给所述第三节点与所述第二节点，控制所述第二节点的电位与所述第一节点的电位相反；所述输出电路响应于所述第一节点的信号，将所述第二参考信号端的信号提供给所述输出信号端；
S104：第四阶段，所述控制电路响应于所述第一节点的信号，将所述第一时钟信号端的信号与所述第一参考信号端的信号提供给所述第三节点与所述第二节点，控制所述第一节点和所述第二节点的电位相反；所述输出电路响应于所述第二节点的信号，将所述第一参考信号端的信号提供给所述输出信号端。
其中，该驱动方法的驱动原理和具体实施方式与上述实施例移位寄存器单元的原理和实施方式相同，因此，该驱动方法可参见上述实施例中移位寄存器单元的具体实施方式进行实施，在此不再赘述。
本公开实施例提供的移位寄存器单元、驱动控制电路、显示装置及驱动方法，通过输入电路控制第一节点的信号；通过控制电路控制第二节点和第三节点的信号，而且第二节点或者第三节点的信号不会影响第一节点的信号；通过输出电路控制输出信号端的信号。整个移位寄存器单元中所采用的器件数量少，电路复杂度低，不仅生产成本低，电路结构简单，占用面积小，利于窄边框设计，而且，通过上述器件的相互配合，可以使输出信号端输出的信号的稳定性提高。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (26)

  1. 一种移位寄存器单元，其中，包括：
    输入电路，与第一节点耦接，被配置为响应于第一时钟信号端的信号，将输入信号端的信号提供给所述第一节点；
    控制电路，与所述第一节点、第二节点、控制信号端以及第一参考信号端耦接，被配置为响应于所述第一节点的信号，分别将所述第一时钟信号端与所述第一参考信号端的信号提供给第三节点与所述第二节点，所述第一节点不受所述第二节点或者所述第三节点的控制；
    输出电路，与所述第一节点和所述第二节点耦接，被配置为响应于所述第二节点的信号，将所述第一参考信号端的信号提供给输出信号端，以及响应于所述第一节点的信号，将第二参考信号端的信号提供给所述输出信号端。
  2. 如权利要求1所述的移位寄存器单元，其中，所述控制电路包括第一控制模块、第二控制模块和第三控制模块；
    所述第一控制模块，与所述第一节点和所述第三节点耦接，被配置为响应于所述第一节点的信号，将所述第一时钟信号端的信号提供给所述第三节点，以及响应于所述第一时钟信号端的信号，将所述控制信号端的信号提供给所述第三节点；
    所述第二控制模块，与所述第二节点和所述第三节点耦接，被配置为响应于所述第三节点和第二时钟信号端的信号，将所述第二时钟信号端的信号提供给所述第二节点；
    所述第三控制模块，与所述第一节点和所述第二节点耦接，被配置为响应于所述第一节点的信号，将第一参考信号端的信号提供给所述第二节点。
  3. 如权利要求1所述的移位寄存器单元，其中，还包括稳压电路；
    所述稳压电路与所述第三节点耦接，被配置为保持所述第三节点的电位。
  4. 如权利要求3所述的移位寄存器单元，其中，所述稳压电路包括第一电容；
    所述第一电容的第一极与所述第三节点耦接，所述第一电容的第二极与所述第二参考信号端耦接。
  5. 如权利要求2或4所述的移位寄存器单元，其中，还包括保护电路；
    所述第三节点通过所述保护电路与所述第二控制模块耦接，所述保护电路被配置为控制所述第三节点与所述第二控制模块之间的导通与断开。
  6. 如权利要求1所述的移位寄存器单元，其中，所述控制信号端与所述第一时钟信号端为同一信号端。
  7. 如权利要求1所述的移位寄存器单元，其中，所述控制信号端与所述第二参考信号端为同一信号端。
  8. 如权利要求1所述的移位寄存器单元，其中，所述输入电路包括第一晶体管；
    所述第一晶体管的栅极与所述第一时钟信号端耦接，所述第一晶体管的第一极与所述第一节点耦接，所述第一晶体管的第二极与所述输入信号端耦接。
  9. 如权利要求2所述的移位寄存器单元，其中，所述第一控制模块包括第二晶体管和第三晶体管；
    所述第二晶体管的栅极与所述第一节点耦接，所述第二晶体管的第一极与所述第一时钟信号端耦接，所述第二晶体管的第二极与所述第三节点耦接；
    所述第三晶体管的栅极与所述第一时钟信号端耦接，所述第三晶体管的第一极与所述第三节点耦接，所述第三晶体管的第二极与所述控制信号端耦接。
  10. 如权利要求2所述的移位寄存器单元，其中，所述第二控制模块包括第四晶体管和第五晶体管；
    所述第四晶体管的栅极与所述第三节点耦接，所述第四晶体管的第一极与第四节点耦接，所述第四晶体管的第二极与所述第二时钟信号端耦接；
    所述第五晶体管的栅极与所述第二时钟信号端耦接，所述第五晶体管的第一极与所述第二节点耦接，所述第五晶体管的第二极与所述第四节点耦接。
  11. 如权利要求1所述的移位寄存器单元，其中，还包括复位电路；
    所述复位电路与所述第一节点和第四节点耦接，被配置为响应于所述第四节点的信号，将所述第一参考信号端的信号提供给所述第一节点。
  12. 如权利要求2所述的移位寄存器单元，其中，所述第三控制模块包括第六晶体管；
    所述第六晶体管的栅极与所述第一节点耦接，所述第六晶体管的第一极与所述第一参考信号端耦接，所述第六晶体管的第二极与所述第二节点耦接。
  13. 如权利要求1所述的移位寄存器单元，其中，所述输出电路包括第七晶体管、第二电容、第八晶体管和第三电容；
    所述第七晶体管的栅极与所述第二节点耦接，所述第七晶体管的第一极与所述输出信号端耦接，所述第七晶体管的第二极与所述第二参考信号端耦接；
    所述第二电容的第一极与所述第二节点耦接，所述第二电容的第二极与所述第一参考信号端耦接；
    所述第八晶体管的栅极与所述第一节点耦接，所述第八晶体管的第一极与所述第二参考信号端耦接，所述第八晶体管的第二极与所述输出信号端耦接；
    所述第三电容的第一极与所述第一节点耦接，所述第三电容的第二极与所述输出信号端耦接。
  14. 如权利要求5所述的移位寄存器单元，其中，所述保护电路包括第九晶体管；
    所述第九晶体管的栅极与所述第二参考信号端耦接，所述第九晶体管的第一极与第四晶体管的栅极耦接，所述第九晶体管的第二极与所述第三节点耦接。
  15. 如权利要求11所述的移位寄存器单元，其中，所述复位电路包括第十晶体管；
    所述第十晶体管的栅极与所述第四节点耦接，所述第十晶体管的第一极 与所述第一节点耦接，所述第十晶体管的第二极与所述第一参考信号端耦接。
  16. 一种移位寄存器单元，其中，包括：
    第一晶体管，所述第一晶体管的第一极与第一节点直接连接；
    第二晶体管，所述第二晶体管的栅极与所述第一节点直接连接，所述第二晶体管的第二极与第三节点耦接；
    第六晶体管，所述第六晶体管的栅极与所述第一节点直接连接，所述第六晶体管的第二极与第二节点耦接；
    第八晶体管，所述第八晶体管的栅极与所述第一节点直接连接，所述第八晶体管的第一极与第二参考信号端耦接，所述第八晶体管的第二极与输出信号端耦接；
    所述第一节点不受所述第二节点或者所述第三节点的控制。
  17. 如权利要求16所述的移位寄存器单元，其中，还包括：
    第一电容；所述第一电容的第一极与所述第三节点耦接，所述第一电容的第二极与所述第二参考信号端耦接。
  18. 如权利要求16或17所述的移位寄存器单元，其中，还包括第九晶体管；
    所述第九晶体管的栅极与所述第二参考信号端耦接，所述第九晶体管的第二极与所述第三节点耦接。
  19. 如权利要求18所述的移位寄存器单元，其中，还包括第十晶体管；
    所述第十晶体管的栅极与第四节点耦接，所述第十晶体管的第一极与所述第一节点耦接，所述第十晶体管的第二极与所述第一参考信号端耦接。
  20. 如权利要求16所述的移位寄存器单元，其中，还包括：
    第三晶体管，所述第三晶体管的第一极与所述第三节点耦接，所述第三晶体管的第二极与控制信号端耦接；
    第四晶体管，所述第四晶体管的栅极与所述第三节点耦接，所述第四晶体管的第一极与所述第四节点耦接；
    第五晶体管，所述第五晶体管的第一极与所述第二节点耦接，所述第五 晶体管的第二极与所述第四节点耦接；
    第七晶体管，所述第七晶体管的栅极与所述第二节点耦接，所述第七晶体管的第一极与所述输出信号端耦接；
    第二电容，所述第二电容的第一极与所述第二节点耦接，所述第二电容的第二极与第一参考信号端耦接；
    第三电容，所述第三电容的第一极与所述第一节点耦接，所述第三电容的第二极与所述输出信号端耦接。
  21. 如权利要求20所述的移位寄存器单元，其中，
    所述第一晶体管的栅极与所述第一时钟信号端耦接，所述第一晶体管的第二极与输入信号端耦接；
    所述第二晶体管的第一极与所述第一时钟信号端耦接；
    所述第三晶体管的栅极与所述第一时钟信号端耦接；
    所述第四晶体管的第二极与所述第二时钟信号端耦接；
    所述第五晶体管的栅极与所述第二时钟信号端耦接；
    所述第六晶体管的第一极与所述第一参考信号端耦接；
    所述第七晶体管的第二极与所述第二参考信号端耦接；
    所述第八晶体管的第二极与所述输出信号端耦接。
  22. 如权利要求21所述的移位寄存器单元，其中，所述控制信号端与所述第一时钟信号端为同一信号端。
  23. 如权利要求21所述的移位寄存器单元，其中，所述控制信号端与所述第二参考信号端为同一信号端。
  24. 一种驱动控制电路，其中，包括：
    级联的多个如权利要求1-15、16-23任一项所述的移位寄存器单元；
    第一级移位寄存器单元的输入信号端与帧触发信号端耦接；
    每相邻的两级移位寄存器单元中，下一级移位寄存器单元的输入信号端与上一级移位寄存器单元的输出信号端耦接。
  25. 一种显示装置，其中，包括：
    如权利要求24所述的驱动控制电路。
  26. 一种如权利要求1-15、16-23任一项所述的移位寄存器单元的驱动方法，其中，包括：
    第一阶段，所述输入电路响应于所述第一时钟信号端的信号，将所述输入信号端的信号提供给所述第一节点；所述控制电路响应于所述第一节点的信号，将所述第一时钟信号端的信号与所述第一参考信号端的信号提供给所述第三节点与所述第二节点，控制所述第二节点的电位与所述第一节点的电位相反；所述输出电路响应于所述第一节点的信号，将所述第二参考信号端的信号提供给所述输出信号端。
PCT/CN2023/112706 2023-08-11 2023-08-11 移位寄存器单元、驱动控制电路、显示装置及驱动方法 Ceased WO2025035305A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/CN2023/112706 WO2025035305A1 (zh) 2023-08-11 2023-08-11 移位寄存器单元、驱动控制电路、显示装置及驱动方法
GB2512156.7A GB2641664A (en) 2023-08-11 2023-08-11 Shift register unit, driving control circuit, display device, and driving method
US18/711,696 US20260171027A1 (en) 2023-08-11 2023-08-11 Shift register unit, drive control circuit, display apparatus , and drive method
CN202380010096.7A CN120112971A (zh) 2023-08-11 2023-08-11 移位寄存器单元、驱动控制电路、显示装置及驱动方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2023/112706 WO2025035305A1 (zh) 2023-08-11 2023-08-11 移位寄存器单元、驱动控制电路、显示装置及驱动方法

Publications (1)

Publication Number Publication Date
WO2025035305A1 true WO2025035305A1 (zh) 2025-02-20

Family

ID=94632046

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/112706 Ceased WO2025035305A1 (zh) 2023-08-11 2023-08-11 移位寄存器单元、驱动控制电路、显示装置及驱动方法

Country Status (4)

Country Link
US (1) US20260171027A1 (zh)
CN (1) CN120112971A (zh)
GB (1) GB2641664A (zh)
WO (1) WO2025035305A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN120977227A (zh) * 2025-08-25 2025-11-18 广州华星光电半导体显示技术有限公司 移位寄存器、栅极驱动电路及显示面板

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107424649A (zh) * 2017-05-25 2017-12-01 上海天马有机发光显示技术有限公司 一种移位寄存器、其驱动方法、发光控制电路及显示装置
KR20190030962A (ko) * 2017-09-15 2019-03-25 엘지디스플레이 주식회사 스캔 구동부 및 이를 이용한 표시장치
CN110415637A (zh) * 2019-08-29 2019-11-05 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN110634528A (zh) * 2019-09-18 2019-12-31 上海天马有机发光显示技术有限公司 移位寄存器、其驱动方法、驱动控制电路及显示装置
CN113053293A (zh) * 2021-04-07 2021-06-29 北京京东方技术开发有限公司 移位寄存器单元、栅极驱动电路、显示面板
CN113889022A (zh) * 2021-10-27 2022-01-04 合肥维信诺科技有限公司 移位寄存器、显示面板和显示装置
CN114937471A (zh) * 2022-05-27 2022-08-23 京东方科技集团股份有限公司 移位寄存器及其驱动电路、方法、显示面板、装置
CN115294916A (zh) * 2022-09-14 2022-11-04 北京京东方技术开发有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示面板
CN115394233A (zh) * 2022-09-30 2022-11-25 武汉天马微电子有限公司 一种移位寄存电路、移位寄存器、显示面板及显示装置
CN115641818A (zh) * 2022-10-26 2023-01-24 厦门天马显示科技有限公司 移位寄存单元、扫描驱动电路、显示面板及显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022120576A1 (zh) * 2020-12-08 2022-06-16 京东方科技集团股份有限公司 显示基板及显示面板
CN114842901A (zh) * 2021-02-01 2022-08-02 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、显示基板和显示装置

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107424649A (zh) * 2017-05-25 2017-12-01 上海天马有机发光显示技术有限公司 一种移位寄存器、其驱动方法、发光控制电路及显示装置
KR20190030962A (ko) * 2017-09-15 2019-03-25 엘지디스플레이 주식회사 스캔 구동부 및 이를 이용한 표시장치
CN110415637A (zh) * 2019-08-29 2019-11-05 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN110634528A (zh) * 2019-09-18 2019-12-31 上海天马有机发光显示技术有限公司 移位寄存器、其驱动方法、驱动控制电路及显示装置
CN113053293A (zh) * 2021-04-07 2021-06-29 北京京东方技术开发有限公司 移位寄存器单元、栅极驱动电路、显示面板
CN113889022A (zh) * 2021-10-27 2022-01-04 合肥维信诺科技有限公司 移位寄存器、显示面板和显示装置
CN114937471A (zh) * 2022-05-27 2022-08-23 京东方科技集团股份有限公司 移位寄存器及其驱动电路、方法、显示面板、装置
CN115294916A (zh) * 2022-09-14 2022-11-04 北京京东方技术开发有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示面板
CN115394233A (zh) * 2022-09-30 2022-11-25 武汉天马微电子有限公司 一种移位寄存电路、移位寄存器、显示面板及显示装置
CN115641818A (zh) * 2022-10-26 2023-01-24 厦门天马显示科技有限公司 移位寄存单元、扫描驱动电路、显示面板及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN120977227A (zh) * 2025-08-25 2025-11-18 广州华星光电半导体显示技术有限公司 移位寄存器、栅极驱动电路及显示面板

Also Published As

Publication number Publication date
CN120112971A (zh) 2025-06-06
GB2641664A (en) 2025-12-10
US20260171027A1 (en) 2026-06-18

Similar Documents

Publication Publication Date Title
CN113724770B (zh) 一种移位寄存器及其驱动方法
CN108597454B (zh) 一种移位寄存器及其驱动方法、扫描驱动电路和显示装置
CN111739471B (zh) 一种显示面板、驱动方法及显示装置
CN109147635B (zh) 一种移位寄存器、其驱动方法及显示装置
CN111445866B (zh) 移位寄存器、驱动方法、驱动控制电路及显示装置
CN113299223B (zh) 一种显示面板和显示装置
CN117012125B (zh) 移位寄存器、栅极驱动电路、显示面板及电子设备
US20220343855A1 (en) Gate driving circuit, display substrate, display device and gate driving method
CN107424649B (zh) 一种移位寄存器、其驱动方法、发光控制电路及显示装置
CN112419960B (zh) 移位寄存器、显示面板及显示装置
CN108538244B (zh) 一种移位寄存器及其驱动方法、发射驱动电路和显示装置
CN108831385A (zh) 扫描驱动电路、显示装置和驱动方法
CN108510938B (zh) 一种移位寄存器及其驱动方法、发射驱动电路和显示装置
CN106782285A (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN109389926B (zh) 移位寄存器、栅极驱动电路、阵列基板
CN105575329B (zh) 移位寄存器及驱动方法、驱动电路、阵列基板及显示装置
CN113077832B (zh) 移位寄存器单元及其驱动方法、扫描驱动电路、显示装置
CN117037664A (zh) 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN109584780B (zh) 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2023173259A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
WO2024145735A1 (zh) 像素驱动电路、像素驱动方法和显示装置
US12205540B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display panel
CN114333705A (zh) 驱动电路、显示面板、显示装置和稳压控制方法
US10937380B2 (en) Shift register and driving method therefor, gate driving circuit and display apparatus
CN114999557A (zh) 移位寄存器及其驱动方法、栅极驱动电路

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202380010096.7

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 18711696

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23948740

Country of ref document: EP

Kind code of ref document: A1

WWP Wipo information: published in national office

Ref document number: 202380010096.7

Country of ref document: CN

ENP Entry into the national phase

Ref document number: 202512156

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20230811

WWE Wipo information: entry into national phase

Ref document number: 2512156.7

Country of ref document: GB

WWP Wipo information: published in national office

Ref document number: 2512156.7

Country of ref document: GB

WWP Wipo information: published in national office

Ref document number: 18711696

Country of ref document: US

122 Ep: pct application non-entry in european phase

Ref document number: 23948740

Country of ref document: EP

Kind code of ref document: A1