WO2025033086A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2025033086A1
WO2025033086A1 PCT/JP2024/024954 JP2024024954W WO2025033086A1 WO 2025033086 A1 WO2025033086 A1 WO 2025033086A1 JP 2024024954 W JP2024024954 W JP 2024024954W WO 2025033086 A1 WO2025033086 A1 WO 2025033086A1
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Prior art keywords
region
floating
mesa
semiconductor device
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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PCT/JP2024/024954
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English (en)
French (fr)
Japanese (ja)
Inventor
俊之 松井
達也 内藤
晴司 野口
拓弥 山田
暢昭 古川
竜太郎 浜崎
巧裕 伊倉
秀平 立道
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to DE112024000313.3T priority Critical patent/DE112024000313T5/de
Priority to JP2025539222A priority patent/JPWO2025033086A1/ja
Priority to CN202480008739.9A priority patent/CN120570084A/zh
Publication of WO2025033086A1 publication Critical patent/WO2025033086A1/ja
Priority to US19/277,332 priority patent/US20250351553A1/en
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/161—IGBT having built-in components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/417—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/418—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/422—PN diodes having the PN junctions in mesas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/035—Etching a recess in the emitter region 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/415—Insulated-gate bipolar transistors [IGBT] having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/129—Cathode regions of diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/232—Emitter electrodes for IGBTs

Definitions

  • the present invention relates to a semiconductor device.
  • the semiconductor device may include a semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type.
  • Any of the above semiconductor devices may include one or more transistor sections having a collector region of a second conductivity type provided on the lower surface of the semiconductor substrate.
  • Any of the above semiconductor devices may include one or more diode sections having a cathode region of a first conductivity type provided on the lower surface of the semiconductor substrate and arranged alternately with the transistor sections in a first direction.
  • each of the transistor sections may have a plurality of trench sections arranged side by side in the first direction, including one or more gate trench sections.
  • each of the transistor sections may have a plurality of mesa sections that are regions sandwiched between the trench sections in the first direction.
  • each of the transistor sections may have a floating region of a second conductivity type provided for at least one of the gate trench sections and provided below a lower end of the gate trench section.
  • the one or more gate trench portions may include a first gate trench portion provided closest to the diode portion.
  • the multiple mesa portions may include a first mesa portion that is in contact with the first gate trench portion and provided between the first gate trench portion and the diode portion.
  • a first floating region may be provided below the first gate trench portion.
  • the first mesa portion may have a non-covered region that does not overlap with the first floating region.
  • the multiple trench portions may include one or more dummy trench portions.
  • the first mesa portion may be sandwiched between the first gate trench portion and a first dummy trench portion.
  • the first floating region provided below the lower end of the first gate trench portion may not extend below the lower end of the first dummy trench portion.
  • the first floating region may not be in contact with the first dummy trench portion when viewed from above.
  • the multiple trench portions may include a second dummy trench portion disposed on the opposite side of the first gate trench portion from the first dummy trench portion.
  • the distance between the first floating region and the second dummy trench portion in the first direction may be smaller than the distance between the first floating region and the first dummy trench portion.
  • the first floating region may be in contact with the second dummy trench portion when viewed from above.
  • the first mesa portion may have an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the first mesa portion may have a base region of a second conductivity type provided between the emitter region and the drift region. In any of the above semiconductor devices, the first mesa portion may have a longitudinal length in a second direction. In any of the above semiconductor devices, the first mesa portion may have the uncovered region in an intermediate region between both ends of the emitter region in the second direction.
  • a plurality of the non-covered regions may be arranged discretely in the second direction.
  • the sum of the lengths of the non-covered regions in the second direction may be smaller than the sum of the lengths of the regions overlapping with the first floating region in the second direction.
  • the first mesa portion may be provided in contact with the upper surface of the semiconductor substrate and may have a contact region of a second conductivity type that is arranged alternately with the emitter regions in the second direction.
  • the first floating region may be arranged below at least one of the emitter regions, and at least a portion of the contact region may be the uncovered region.
  • the first floating region may overlap at least one of the entire emitter regions.
  • the non-covered region may be provided in each of the contact regions.
  • any of the above semiconductor devices may include a well region of a second conductivity type that is disposed outside the first mesa portion in the second direction and has a higher concentration than the base region.
  • Any of the above semiconductor devices may include a first extension region of a second conductivity type that extends in the second direction from the well region to a position overlapping with the emitter region.
  • the well region may also be disposed outside the emitter region in the first direction.
  • Any of the above semiconductor devices may include a second extension region of a second conductivity type that extends in the first direction from the well region to a position overlapping with the emitter region.
  • the diode section may have a plurality of dummy trench sections arranged in the first direction, and a mesa section sandwiched between the dummy trench sections in the first direction.
  • the floating region may also be provided below the lower end of at least one of the dummy trench sections of the diode section.
  • the period at which the floating regions are provided in the first direction may be the same as the period at which the floating regions are provided in the first direction in the transistor section.
  • the transistor portion of any of the above semiconductor devices may have a boundary region between the first gate trench portion and the diode portion, the boundary region having one or more of the trench portions and one or more of the mesa portions.
  • the floating region may also be provided below the lower end of at least one of the trench portions in the boundary region.
  • the period at which the floating regions are provided in the first direction in the boundary region of any of the above semiconductor devices may be the same as the period at which the floating regions are provided in the first direction in the transistor portion other than the boundary region.
  • the area of the uncovered region in the first mesa portion may be larger than the area of the region that does not overlap with the floating region in the mesa portion that contacts the gate trench portion other than the first gate trench portion.
  • FIG. 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention.
  • FIG. 2 is an enlarged view of an area D in FIG.
  • FIG. 3 is a diagram showing an example of a cross section taken along the line ee in FIG. 2.
  • 1 is a diagram showing an example of the arrangement of floating regions 202 in a top view.
  • FIG. 13 is a diagram showing another example of the arrangement of the floating region 202 in a top view.
  • FIG. FIG. 13 is a diagram showing another example of the ee cross section.
  • FIG. 13 is a diagram showing another example of the ee cross section.
  • 1 is a top view showing an example of a transition region 92.
  • FIG. FIG. 9 is a diagram showing an example of the ff cross section in FIG. 8.
  • FIG. 11 is an XZ cross section showing another example of the structure of the boundary region 90 and the diode portion 80.
  • FIG. 13 is a diagram showing collector voltage-collector current characteristics in an embodiment and a reference example.
  • FIG. 11 is a diagram showing the trade-off characteristics between turn-on loss and reverse recovery dV/dt in the reference example and the working example.
  • one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper” and the other side as “lower.”
  • the upper surface is referred to as the upper surface and the other surface is referred to as the lower surface.
  • the directions of "upper” and “lower” are not limited to the direction of gravity or the directions when the semiconductor device is mounted.
  • the orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction.
  • the Z-axis does not limit the height direction relative to the ground.
  • the +Z-axis direction and the -Z-axis direction are opposite directions.
  • the Z-axis direction is described without indicating positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.
  • the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis.
  • the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis.
  • the direction of the Z-axis may be referred to as the depth direction.
  • the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis may be referred to as the horizontal direction.
  • the region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top side.
  • the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom side.
  • the conductivity type of a doped region doped with impurities is described as P type or N type.
  • impurities may specifically mean either N type donors or P type acceptors, and may be described as dopants.
  • doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor that exhibits N type conductivity or a semiconductor that exhibits P type conductivity.
  • the doping concentration means the concentration of the donor or the concentration of the acceptor in a thermal equilibrium state.
  • the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge.
  • the donor concentration is N D and the acceptor concentration is N A
  • the net doping concentration at any position is N D -N A.
  • the net doping concentration may be simply referred to as the doping concentration.
  • P+ type or N+ type when P+ type or N+ type is mentioned, it means that the doping concentration is higher than P type or N type, and when P- type or N- type is mentioned, it means that the doping concentration is lower than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means that the doping concentration is higher than P+ type or N+ type.
  • the unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).
  • chemical concentration refers to the atomic density of an impurity measured regardless of the state of electrical activation.
  • the chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS).
  • the above-mentioned net doping concentration can be measured by a voltage-capacitance measurement method (CV method).
  • the carrier concentration measured by a spreading resistance measurement method (SR method) may be the net doping concentration.
  • the carrier concentration measured by the CV method or the SR method may be a value in a thermal equilibrium state.
  • the donor concentration is sufficiently larger than the acceptor concentration in an N-type region, the carrier concentration in that region may be the donor concentration.
  • the carrier concentration in that region may be the acceptor concentration.
  • the doping concentration in an N-type region may be referred to as the donor concentration
  • the doping concentration in a P-type region may be referred to as the acceptor concentration.
  • the peak value may be taken as the concentration of the donor, acceptor or net doping in the region.
  • the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping.
  • atoms/cm 3 or /cm 3 is used to express concentration per unit volume. This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The notation of atoms may be omitted.
  • the carrier concentration measured by the SR method may be lower than the donor or acceptor concentration.
  • the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.
  • the donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor.
  • the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor is about 99% of the chemical concentration.
  • the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.
  • FIG. 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention.
  • FIG. 1 the positions of each component projected onto the top surface of a semiconductor substrate 10 are shown.
  • FIG. 1 only some of the components of the semiconductor device 100 are shown, and some components are omitted.
  • the semiconductor device 100 includes a semiconductor substrate 10.
  • the semiconductor substrate 10 is a substrate formed of a semiconductor material.
  • the semiconductor substrate 10 is a silicon substrate.
  • the semiconductor substrate 10 has edges 162 when viewed from above. When simply referred to as a top view in this specification, it means that the semiconductor substrate 10 is viewed from the top side.
  • the semiconductor substrate 10 has two sets of edges 162 that face each other when viewed from above. In FIG. 1, the X-axis and Y-axis are parallel to one of the edges 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.
  • the semiconductor substrate 10 has an active portion 160.
  • the active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation.
  • An emitter electrode is provided above the active portion 160, but is omitted in FIG. 1.
  • the active portion 160 may refer to the region that overlaps with the emitter electrode when viewed from above.
  • the active portion 160 may also include the region sandwiched between the active portions 160 when viewed from above.
  • the active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor).
  • the active section 160 may further be provided with a diode section 80 including a diode element such as a free wheel diode (FWD).
  • the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10.
  • the semiconductor device 100 in this example is a reverse conducting IGBT (RC-IGBT).
  • the region in which the transistor section 70 is arranged is marked with the symbol "I”
  • the region in which the diode section 80 is arranged is marked with the symbol "F”.
  • the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1).
  • the transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction.
  • the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction.
  • the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction.
  • the extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.
  • the diode section 80 has an N+ type cathode region in a region that contacts the lower surface of the semiconductor substrate 10.
  • the region in which the cathode region is provided is referred to as the diode section 80.
  • the diode section 80 is a region that overlaps with the cathode region when viewed from above.
  • a P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region.
  • the diode section 80 may also include an extension region 81 that extends the diode section 80 in the Y-axis direction to the gate wiring described below.
  • a collector region is provided on the lower surface of the extension region 81.
  • the transistor section 70 has a P+ type collector region in a region that contacts the bottom surface of the semiconductor substrate 10.
  • the transistor section 70 has a gate structure that has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film periodically arranged on the top surface side of the semiconductor substrate 10.
  • the semiconductor device 100 may have one or more pads above the semiconductor substrate 10.
  • the semiconductor device 100 in this example has a gate pad 164.
  • the semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad.
  • Each pad is disposed near an edge 162.
  • the vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view.
  • each pad may be connected to an external circuit via wiring such as a wire.
  • a gate potential is applied to the gate pad 164.
  • the gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160.
  • the semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with diagonal lines.
  • the gate wiring in this example has a peripheral gate wiring 130 and an active side gate wiring 131.
  • the peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view.
  • the peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view.
  • the region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160.
  • a well region is formed below the gate wiring.
  • the well region is a P-type region with a higher concentration than the base region described below, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region.
  • the region surrounded by the well region in a top view may be the active portion 160.
  • the peripheral gate wiring 130 is connected to the gate pad 164.
  • the peripheral gate wiring 130 is disposed above the semiconductor substrate 10.
  • the peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.
  • the active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, the variation in wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.
  • the peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160.
  • the peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10.
  • the peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.
  • the active side gate wiring 131 may be connected to the peripheral gate wiring 130.
  • the active side gate wiring 131 is provided extending in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 sandwiching the active section 160, so as to cross the active section 160 at approximately the center in the Y-axis direction.
  • the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region.
  • the semiconductor device 100 may also include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that simulates the operation of a transistor section provided in the active section 160.
  • a temperature sensor not shown
  • a current detector not shown
  • the semiconductor device 100 of this example includes an edge termination structure 190 between the active section 160 and the edge 162 when viewed from above.
  • the edge termination structure 190 of this example is disposed between the peripheral gate wiring 130 and the edge 162.
  • the edge termination structure 190 reduces electric field concentration on the upper surface side of the semiconductor substrate 10.
  • the edge termination structure 190 may include at least one of a guard ring, a field plate, and a resurf that are arranged in a ring shape surrounding the active section 160.
  • Region D includes transistor section 70, diode section 80, and active side gate wiring 131.
  • the semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10.
  • the gate trench section 40 and the dummy trench section 30 are each an example of a trench section.
  • the semiconductor device 100 of this example also includes an emitter electrode 52 and an active side gate wiring 131 provided above the upper surface of the semiconductor substrate 10.
  • the emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.
  • An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is omitted in FIG. 2.
  • a contact portion 54 is provided in the interlayer insulating film so as to penetrate the interlayer insulating film.
  • the contact portion 54 may have a contact hole provided in the interlayer insulating film and a conductive member filled in the contact hole. In FIG. 2, each contact portion 54 is hatched with diagonal lines.
  • the emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15.
  • the emitter electrode 52 is connected to the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 via a contact portion 54.
  • the emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film.
  • the emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.
  • the active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film.
  • the active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction.
  • the active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.
  • the emitter electrode 52 is formed of a material containing metal.
  • FIG. 2 shows the range in which the emitter electrode 52 is provided.
  • the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu.
  • the emitter electrode 52 may have a barrier metal made of titanium or a titanium compound under the region made of aluminum or the like.
  • the emitter electrode 52 may have a plug formed by embedding tungsten or the like in the contact hole so as to contact the barrier metal and aluminum or the like.
  • the well region 11 is provided so as to overlap with the active side gate wiring 131.
  • the well region 11 is also provided so as to extend by a predetermined width into an area where it does not overlap with the active side gate wiring 131.
  • the well region 11 is provided away from the end of the contact portion 54 in the Y-axis direction toward the active side gate wiring 131.
  • the well region 11 is a region of a second conductivity type having a higher doping concentration than the base region 14.
  • the base region 14 is P- type
  • the well region 11 is P+ type.
  • the transistor section 70 and the diode section 80 each have multiple trench sections arranged in the arrangement direction.
  • one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction.
  • the diode section 80 of this example multiple dummy trench sections 30 are provided along the arrangement direction.
  • no gate trench section 40 is provided in the diode section 80 of this example.
  • the gate trench portion 40 in this example may have two straight portions 39 (portions of the trench that are straight along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two straight portions 39.
  • the extension direction in FIG. 2 is the Y-axis direction.
  • the tip 41 is curved when viewed from above.
  • the tip 41 connects the ends of the two straight portions 39 in the Y-axis direction, thereby reducing electric field concentration at the ends of the straight portions 39.
  • the dummy trench portion 30 is provided between each straight portion 39 of the gate trench portion 40.
  • One dummy trench portion 30 may be provided between each straight portion 39, or multiple dummy trench portions 30 may be provided.
  • the dummy trench portion 30 may have a straight line shape extending in the extension direction, and may have a straight line portion 29 and a tip portion 31, similar to the gate trench portion 40.
  • the diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30.
  • the ends in the Y-axis direction of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 when viewed from above. In other words, at the ends in the Y-axis direction of each trench portion, the bottoms in the depth direction of each trench portion are covered by the well region 11. This makes it possible to reduce electric field concentration at the bottoms of each trench portion.
  • the mesa portion refers to the region inside the semiconductor substrate 10 that is sandwiched between the trench portions.
  • the upper end of the mesa portion is the upper surface of the semiconductor substrate 10.
  • the depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion.
  • the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench.
  • the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61.
  • the transistor portion 70 in this example has a boundary region 90.
  • the boundary region 90 is an end of the transistor portion 70 in the X-axis direction and is in contact with the diode portion 80.
  • the boundary region 90 has a collector region 22 on the lower surface 23 of the semiconductor substrate 10.
  • the boundary region 90 may include one or more trench portions.
  • the boundary region 90 may be provided with a gate trench portion 40, a dummy trench portion 30, or both trench portions.
  • the boundary region 90 is provided with a mesa portion 62.
  • the mesa portion 62 may have the same structure as the mesa portion 61.
  • the boundary region 90 may be a region whose structure on the upper surface 21 side is similar to that of the diode section 80 and whose structure on the lower surface 23 side is similar to that of the transistor section 70.
  • the transistor section 70 does not have to have the boundary region 90.
  • the mesa section 60 of the transistor section 70 and the mesa section 61 of the diode section 80 are disposed adjacent to each other at the boundary between the transistor section 70 and the diode section 80.
  • a base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active gate wiring 131 is referred to as the base region 14-e. In FIG. 2, the base region 14-e is shown at one end in the extension direction of each mesa portion, but the base region 14-e is also provided at the other end of each mesa portion. In each mesa portion, at least one of the emitter region 12 of the first conductivity type and the contact region 15 of the second conductivity type may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type with a higher concentration than the base region 14. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.
  • the mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10.
  • the emitter region 12 is provided in contact with the gate trench portion 40.
  • the mesa portion 60 in contact with the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10.
  • the emitter region 12 in the mesa portion 60 is provided in contact with the gate trench portion 40.
  • the emitter region 12 may or may not be in contact with the dummy trench portion 30.
  • the emitter region 12 is also provided in a region that overlaps with the contact portion 54.
  • the contact region 15 in the mesa portion 60 is provided in a region that overlaps with the contact portion 54.
  • the contact region 15 may or may not be in contact with the gate trench portion 40.
  • the contact region 15 may or may not be in contact with the dummy trench portion 30.
  • the emitter region 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction.
  • the contact region 15 in the mesa portion 60 may also be provided from one trench portion to the other trench portion in the X-axis direction.
  • the contact region 15 does not have to be in contact with either of the two trench portions that sandwich the mesa portion 60.
  • a base region 14 may be provided between the contact region 15 and the trench portion.
  • the contact regions 15 and emitter regions 12 of the mesa portion 60 are alternately arranged along the extension direction (Y-axis direction) of the trench portion.
  • the contact regions 15 and emitter regions 12 of the mesa portion 60 may be arranged in stripes along the extension direction (Y-axis direction) of the trench portion.
  • the emitter regions 12 are provided in the region in contact with the trench portion, and the contact regions 15 are provided in the region sandwiched between the emitter regions 12.
  • the mesa portion 60 may also be provided with emitter regions 12 instead of contact regions 15.
  • the emitter regions 12 may be provided in the entire region sandwiched between the base regions 14-e in the Y-axis direction.
  • the mesa portion 61 of the diode portion 80 does not have an emitter region 12.
  • a base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61.
  • a contact region 15 may be provided in contact with each of the base regions 14-e.
  • a base region 14 may be provided in the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61.
  • the base region 14 may be disposed over the entire region sandwiched between the contact regions 15.
  • the mesa portion 62 in the boundary region 90 in this example has a structure similar to that of the mesa portion 61.
  • a contact portion 54 is provided above each mesa portion.
  • the contact portion 54 is located in a region sandwiched between the base regions 14-e. In this example, the contact portion 54 is provided above the contact region 15, the base region 14, and the emitter region 12. The contact portion 54 is not provided in the region corresponding to the base region 14-e and the well region 11.
  • the contact portion 54 may be located in the center of the arrangement direction (X-axis direction) of the mesa portions 60.
  • an N+ type cathode region 82 is provided in a region adjacent to the underside of the semiconductor substrate 10.
  • a P+ type collector region 22 may be provided in the region of the underside of the semiconductor substrate 10 where the cathode region 82 is not provided.
  • the cathode region 82 and the collector region 22 are provided between the underside 23 of the semiconductor substrate 10 and the buffer region 20.
  • the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.
  • the cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and the P-type region (well region 11) that has a relatively high doping concentration and is formed deep, improving the breakdown voltage.
  • the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact portion 54 in the Y-axis direction.
  • the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact portion 54.
  • FIG. 3 is a diagram showing an example of the e-e cross section in FIG. 2.
  • the e-e cross section is an XZ plane passing through the emitter region 12 and the cathode region 82.
  • the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.
  • the interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10.
  • the interlayer insulating film 38 is a film that includes at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films.
  • the interlayer insulating film 38 is provided with the contact portion 54 described in FIG. 2.
  • the contact portion 54 is provided through the interlayer insulating film 38.
  • the contact portion 54 may be formed of a metal different from that of the emitter electrode 52.
  • the contact portion 54 may contain tungsten.
  • a barrier metal layer including at least one of a titanium film and a titanium nitride film may be provided at the bottom of the contact portion 54.
  • the contact portion 54 may be provided up to the upper surface 21 of the semiconductor substrate 10, or may be provided up to the inside of the semiconductor substrate 10.
  • the contact portion 54 is a contact trench provided from the upper surface 21 of the semiconductor substrate 10 to the inside of each mesa portion. This allows the contact area between the contact portion 54 and the semiconductor substrate 10 to be increased.
  • the lower end of the contact portion 54 of the transistor portion 70 is in contact with the emitter region 12.
  • the lower end of the contact portion 54 of the diode portion 80 is in contact with the base region 14.
  • the emitter electrode 52 is provided above the interlayer insulating film 38.
  • the emitter electrode 52 is connected to the semiconductor substrate 10 via a contact portion 54.
  • the collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10.
  • the emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.
  • the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.
  • the semiconductor substrate 10 has an N-type or N-type drift region 18.
  • the drift region 18 is provided in each of the transistor portion 70 and the diode portion 80.
  • an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10.
  • a drift region 18 is provided below the base region 14.
  • An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.
  • the emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40.
  • the emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60.
  • the emitter region 12 has a higher doping concentration than the drift region 18.
  • the base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.
  • the accumulation region 16 is provided below the base region 14.
  • the accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. In other words, the accumulation region 16 has a higher donor concentration than the drift region 18.
  • the carrier injection enhancement effect IE effect
  • the accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.
  • the mesa portion 61 of the diode section 80 has a P-type base region 14 in contact with the upper surface 21 of the semiconductor substrate 10.
  • a drift region 18 is provided below the base region 14.
  • an accumulation region 16 may be provided below the base region 14.
  • a P-type base region 14 is provided in the mesa portion 62 of the boundary region 90 in contact with the upper surface 21 of the semiconductor substrate 10.
  • a drift region 18 is provided below the base region 14.
  • An accumulation region 16 may be provided below the base region 14 in the mesa portion 62.
  • the mesa portion 62 in this example has a structure similar to that of the mesa portion 61.
  • the center of the trench portion in the X-axis direction may be the end of the boundary region 90 in the X-axis direction.
  • an N+ type buffer region 20 may be provided below the drift region 18.
  • the doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18.
  • the buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18.
  • the doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak.
  • the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.
  • the buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10.
  • the concentration peak of the buffer region 20 may be located at the same depth as the chemical concentration peak of hydrogen (protons) or phosphorus, for example.
  • the buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.
  • a P+ type collector region 22 is provided below the buffer region 20.
  • the acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14.
  • the collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor.
  • the acceptor of the collector region 22 is, for example, boron.
  • an N+ type cathode region 82 is provided below the buffer region 20.
  • the donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18.
  • the donor of the cathode region 82 is, for example, hydrogen or phosphorus.
  • the elements that serve as the donor and acceptor of each region are not limited to the above-mentioned examples.
  • the collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24.
  • the collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10.
  • the emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.
  • each trench portion is provided from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these doped regions.
  • the trench portion penetrating the doped region is not limited to being manufactured in the order of forming the doped region and then the trench portion.
  • the trench portion penetrating the doped region also includes a trench portion formed after the trench portion is formed.
  • the transistor section 70 has a gate trench section 40 and a dummy trench section 30.
  • the diode section 80 has a dummy trench section 30, but does not have a gate trench section 40.
  • the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.
  • the boundary region 90 is provided with a dummy trench portion 30, and does not have a gate trench portion 40.
  • the trench portion at the end of the boundary region 90 on the transistor portion 70 side may be a gate trench portion 40.
  • the gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44.
  • the gate insulating film 42 is provided to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
  • the gate conductive portion 44 is provided inside the gate insulating film 42 inside the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10.
  • the gate conductive portion 44 is formed of a conductive material such as polysilicon.
  • the gate conductive portion 44 may be provided longer than the base region 14 in the depth direction.
  • the gate trench portion 40 in this cross section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10.
  • the gate conductive portion 44 is electrically connected to the gate wiring.
  • a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section.
  • the dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10.
  • the dummy conductive portion 34 is electrically connected to the emitter electrode 52.
  • the dummy insulating film 32 is provided to cover the inner wall of the dummy trench.
  • the dummy conductive portion 34 is provided inside the dummy trench and is provided on the inside of the dummy insulating film 32.
  • the dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.
  • the dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.
  • the dummy conductive portion 34 is formed of a conductive material such as polysilicon.
  • the dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.
  • the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10.
  • the bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).
  • the depth position of the lower end 43 of the gate trench portion 40 is designated as Zt.
  • the semiconductor device 100 of this example includes a P-type floating region 202 provided below the lower end 43 of the gate trench portion 40.
  • the lower end 43 of the gate trench portion 40 refers to the portion of the gate trench portion 40 that is closest to the lower surface 23 of the semiconductor substrate 10. In the example of FIG. 3, the lower end 43 of the gate trench portion 40 is disposed at the center of the gate trench portion 40 in the X-axis direction.
  • the lower end 33 of the dummy trench portion 30 refers to the portion of the dummy trench portion 30 that is closest to the lower surface 23 of the semiconductor substrate 10. In the example of FIG. 3, the lower end 33 of the dummy trench portion 30 is disposed at the center of the dummy trench portion 30 in the X-axis direction.
  • At least a portion of the floating region 202 is provided at a position overlapping the lower end 43 in a top view, and is disposed below the lower end 43 in the Z-axis direction.
  • the floating region 202 may include a portion that does not overlap the lower end 43 in a top view.
  • the floating region 202 may include a portion that is provided above the lower end 43.
  • the floating region 202 may be in contact with the lower end 43 or may be separated from the lower end 43. In the example of FIG. 3, the floating region 202 is in contact with the entire curved portion including the lower end 43 in the gate trench portion 40.
  • the floating region 202 may be formed by injecting a P-type dopant near the lower end of the trench structure after forming the groove structure of the gate trench portion 40 and before forming the gate conductive portion 44.
  • the floating region 202 is electrically floating with respect to an electrode such as a metal or polysilicon. At least one of an N-type region and an insulating film is disposed between the floating region 202 and the electrode. In other words, the floating region 202 and the electrode are not connected by a P-type region and a conductive material.
  • the doping concentration of the floating region 202 may be equal to or lower than the doping concentration of the base region 14, or may be higher than the doping concentration of the base region 14.
  • the doping concentration of the floating region 202 in this example is higher than the doping concentration of the base region 14.
  • the doping concentration may be 1 ⁇ 10 15 cm ⁇ 3 or higher and 1 ⁇ 10 17 cm ⁇ 3 or lower.
  • the floating region 202 is disposed away from the base region 14.
  • An N-type region (at least one of the accumulation region 16 and the drift region 18 in this example) is provided between the floating region 202 and the base region 14.
  • Each transistor portion 70 has one or more floating regions 202. Each transistor portion 70 may have multiple floating regions 202. In each transistor portion 70, a floating region 202 may be provided in at least one gate trench portion 40, a floating region 202 may be provided in 50% or more of the gate trench portions 40, a floating region 202 may be provided in 80% or more of the gate trench portions 40, or a floating region 202 may be provided in all of the gate trench portions 40.
  • a floating region 202 is provided in the gate trench portion 40 closest to the diode portion 80. In multiple transistor portions 70, a floating region 202 may be provided in the gate trench portion 40 closest to the diode portion 80. In all transistor portions 70, a floating region 202 may be provided in the gate trench portion 40 closest to the diode portion 80.
  • the one or more gate trench portions 40 of the transistor portion 70 that is closest to the diode portion 80 in the first direction is referred to as the first gate trench portion 40-1.
  • the one or more dummy trench portions 30 of the transistor portion 70 that are disposed next to the first gate trench portion 40-1 are referred to as the first dummy trench portion 30-1 and the second dummy trench portion 30-2.
  • the first dummy trench portion 30-1 is disposed outside the first gate trench portion 40-1. In other words, the first dummy trench portion 30-1 is disposed between the first gate trench portion 40-1 and the diode portion 80. In this example, the first dummy trench portion 30-1 is disposed at the end of the boundary region 90.
  • the second dummy trench portion 30-2 is disposed inside the first gate trench portion 40-1. In other words, the second dummy trench portion 30-2 is disposed on the opposite side of the first dummy trench portion 30-1 with respect to the first gate trench portion 40-1.
  • the first mesa portion 60-1 is the mesa portion 60 sandwiched between the first gate trench portion 40-1 and the first dummy trench portion 30-1.
  • the mesa portion 60 that is in contact with the first gate trench portion 40-1 and is disposed on the opposite side to the first mesa portion 60-1 is referred to as the second mesa portion 60-2.
  • the second mesa portion 60-2 is the mesa portion 60 that is sandwiched between the first gate trench portion 40-1 and the second dummy trench portion 30-2.
  • each floating region 202 may or may not extend below the lower end 33 of the trench portion (in this example, the dummy trench portion 30) disposed next to the corresponding gate trench portion 40. Each floating region 202 may or may not contact the trench portion adjacent to the gate trench portion 40. In this example, each floating region 202 does not extend in the X-axis direction beyond the trench portion adjacent to the gate trench portion 40. Each floating region 202 does not extend below the mesa portion 60 that is not in contact with the gate trench portion 40.
  • FIG. 3 shows the first gate trench portion 40-1, the first floating region 202-1, the first mesa portion 60-1, and the second mesa portion 60-2 provided at one end of the transistor portion 70 in the X-axis direction.
  • the transistor portion 70 When the transistor portion 70 is sandwiched between two diode portions 80, the transistor portion 70 has the first gate trench portion 40-1, the first floating region 202-1, the first mesa portion 60-1, and the second mesa portion 60-2 provided at each of both ends in the X-axis direction.
  • each dummy trench portion 30 may be in contact with an N-type region (drift region 18 in this example).
  • N-type region drift region 18 in this example.
  • no P-type region is provided below the lower end 33, but an N-type region (drift region 18 in this example) is provided.
  • the floating region 202 By providing the floating region 202, when the transistor section 70 is turned on, it is possible to prevent electrons from flowing to the lower end 43 of the first gate trench section 40-1, and to leave a depletion layer near the lower end 43. This makes it possible to reduce the reverse recovery dV/dt.
  • the reverse recovery dV/dt is the slope of the time waveform of the anode-cathode voltage during reverse recovery of the diode section 80.
  • the semiconductor device 100 when the semiconductor device 100 is used in a circuit such as a three-phase inverter, it is possible to reduce the tail of the voltage waveform of the IGBT provided in the opposing arm. This makes it possible to improve the trade-off characteristics of turn-on loss and reverse recovery dV/dt.
  • a non-covered region that does not overlap with the first floating region is provided for the first mesa portion 60-1 arranged near the diode portion 80. This allows electrons from the first mesa portion 60-1 to flow more easily, suppressing snapback. In other words, snapback can be suppressed while improving the trade-off characteristics described above.
  • FIG. 4 is a diagram showing an example of the arrangement of the floating region 202 when viewed from above.
  • FIG. 4 shows an enlarged view of the transistor section 70 in the vicinity of the boundary region 90.
  • FIG. 4 also shows the well region 11 that is arranged outside the emitter region 12 in the Y-axis direction. Above the well region 11, the peripheral gate wiring 130 described in FIG. 1 extends in the X-axis direction.
  • the first mesa portion 60-1 has an uncovered region 212 that does not overlap with the first floating region 202-1.
  • the first mesa portion 60-1 may be provided with an uncovered region 212, and in all transistor portions 70, the first mesa portion 60-1 may be provided with an uncovered region 212.
  • the uncovered region 212 is provided over the entire X-axis direction of the first mesa portion 60-1.
  • Each mesa portion 60 has a longitudinal direction in the Y-axis direction.
  • the extension direction of the longest straight line among the end sides of the mesa portion 60 when viewed from above may be the longitudinal direction of the mesa portion 60.
  • the intermediate region 210 is between both ends of the emitter region 12 in the Y-axis direction.
  • the emitter regions 12 are arranged discretely in the Y-axis direction.
  • the outer ends of the two emitter regions 12 arranged at both ends in the Y-axis direction are the two ends of the intermediate region 210.
  • the emitter regions 12 and the contact regions 15 may be arranged alternately in the Y-axis direction.
  • the uncovered region 212 may be provided in the intermediate region 210 of the first mesa portion 60-1.
  • the first floating regions 202-1 are arranged in a plurality of discrete locations along the Y axis in the intermediate region 210 of the first mesa portion 60-1.
  • the uncovered regions 212 are also arranged in a plurality of discrete locations along the Y axis in the intermediate region 210 of the first mesa portion 60-1. This allows electrons from the first mesa portion 60-1 to flow more easily, suppressing snapback.
  • the first floating region 202-1 may overlap the first dummy trench portion 30-1 in top view, or may be separated from it. If the first floating region 202-1 is separated from the first dummy trench portion 30-1, snapback can be further suppressed.
  • the sum of the lengths L2 in the Y-axis direction of the multiple uncovered regions 212 may be smaller than the sum of the lengths L1 in the Y-axis direction of the regions overlapping with the first floating region 202-1. This makes it easier to improve the trade-off characteristics of turn-on loss-reverse recovery dV/dt.
  • the sum of the lengths L2 may be 70% or less of the sum of the lengths L1, or may be 50% or less.
  • the sum of the lengths L2 may be 10% or more of the sum of the lengths L1, 30% or more, or 50% or more.
  • the sum of lengths L2 may be greater than the sum of lengths L1. This makes it easier to suppress snapback.
  • the sum of lengths L2 may be 1.3 times or more, 1.5 times or more, or even 2 times or more, the sum of lengths L1.
  • the sum of lengths L2 may be 10 times or less, 3 times or less, or even 2 times or less, the sum of lengths L1.
  • the uncovered region 212 may also be provided in the intermediate region 210 of the second mesa portion 60-2.
  • the arrangement of the first floating region 202-1 and the uncovered region 212 of the second mesa portion 60-2 in the Y-axis direction may be similar to that of the first mesa portion 60-1.
  • the first floating region 202-1 in the second mesa portion 60-2 may overlap with the second dummy trench portion 30-2 in a top view, or may be separated from it.
  • the first floating region 202-1 may overlap with the second dummy trench portion 30-2 and may be separated from the first dummy trench portion 30-1.
  • the first floating region 202-1 is disposed below at least one emitter region 12 of the first mesa portion 60-1.
  • the first floating region 202-1 may overlap the entirety of the corresponding emitter region 12.
  • the first floating region 202-1 may be disposed below a plurality of emitter regions 12.
  • the first floating region 202-1 may be disposed for all emitter regions 12 except for the emitter regions 12 disposed at both ends in the Y-axis direction.
  • the first floating region 202-1 may also be disposed for all emitter regions 12 including the emitter regions 12 disposed at both ends in the Y-axis direction.
  • At least a portion of the contact region 15 is an uncovered region 212.
  • Each contact region 15 may be provided with an uncovered region 212.
  • the portion that contacts the emitter region 12 may overlap with the first floating region 202-1.
  • Each contact region 15 does not have to overlap with the first floating region 202-1.
  • the first floating region 202-1 may be disposed below at least one contact region 15 of the first mesa portion 60-1.
  • the first floating region 202-1 may be disposed below a plurality of contact regions 15.
  • the first floating region 202-1 may be disposed for all contact regions 15 except for the contact regions 15 disposed at both ends in the Y-axis direction.
  • the first floating region 202-1 may also be disposed for all contact regions 15 including the contact regions 15 disposed at both ends in the Y-axis direction.
  • the emitter region 12 is the uncovered region 212.
  • the uncovered region 212 may be provided in each emitter region 12.
  • the portion that contacts the contact region 15 may overlap the first floating region 202-1.
  • Each emitter region 12 does not have to overlap the first floating region 202-1.
  • one floating region 202 may be provided for each mesa portion 60.
  • the length in the Y-axis direction of the floating region 202 of the mesa portion 60 is greater than the length L1 in the Y-axis direction of one first floating region 202-1.
  • the length of the floating region 202 in this example is equal to the sum of the lengths L1 and L2.
  • the positions of both ends of the floating region 202 in the Y-axis direction in this example are equal to the positions of the outer ends of the first floating regions 202-1 arranged at both ends in the Y-axis direction.
  • the length in the Y-axis direction of the floating region 202 may be 50% or more, 70% or more, or 90% or more of the length in the Y-axis direction of the straight portion 39 of the gate trench portion 40.
  • the area of the uncovered region 212 in the first mesa portion 60-1 in a top view may be larger than the area of the region that does not overlap with the floating region 202 in the mesa portion 60 that contacts the gate trench portion 40 other than the first gate trench portion 40-1 (referred to as the second area).
  • the first area is the value obtained by multiplying the width of the first mesa portion 60-1 in the X-axis direction by the sum of the lengths L2.
  • the second area is the value obtained by multiplying the width of the mesa portion 60 in the X-axis direction by the sum of the lengths of the regions that do not overlap with the floating region 202 in the Y-axis direction.
  • the second area may be 0.
  • a first extension region 204 may be provided, extending from the well region 11 to a position overlapping with the emitter region 12.
  • the first extension region 204 is a P-type region.
  • the first extension region 204 is connected to the well region 11.
  • the well region 11 is connected to the emitter electrode 52.
  • the first extension region 204 may be provided at the same depth position as the floating region 202.
  • the first extension region 204 may have the same doping concentration as the floating region 202.
  • the first extension region 204 is separated from the floating region 202.
  • the first extension region 204 in this example overlaps with the entire emitter region 12 closest to the well region 11.
  • the first extension region 204 does not need to overlap with the emitter region 12 second closest to the well region 11.
  • the region from the well region 11 to below the outermost emitter region 12 can be at emitter potential. This makes the electric field distribution in the region where the first extension region 204 is provided uniform, and suppresses a decrease in breakdown voltage.
  • the first extension region 204 may be provided over the entire X-axis direction of the transistor section 70.
  • the first extension region 204 may be provided over the entire X-axis direction of the diode section 80.
  • FIG. 5 is a diagram showing another example of the arrangement of the floating regions 202 in a top view.
  • the arrangement of the first floating region 202-1 is the same as the example in FIG. 4.
  • the floating regions 202 other than the first floating region 202-1 are also arranged discretely in the Y-axis direction, similar to the first floating region 202-1.
  • the length in the Y-axis direction of the floating regions 202 other than the first floating region 202-1 may be the same as the length L1 of the first floating region 202-1.
  • the spacing in the Y-axis direction of the floating regions 202 other than the first floating region 202-1 may be the same as the spacing L2 of the first floating region 202-1.
  • At least one of the floating areas 202 other than the first floating area 202-1 may be arranged discretely in the Y-axis direction.
  • the floating area 202 adjacent to the first floating area 202-1 may be arranged discretely in the Y-axis direction.
  • the other floating areas 202 may be arranged continuously in the Y-axis direction, as in the example of FIG. 4. As shown in FIG. 5, all of the floating areas 202 may be arranged discretely in the Y-axis direction.
  • FIG. 6 is a diagram showing another example of the e-e cross section.
  • the arrangement of the first floating region 202-1 differs from the example described in FIG. 3.
  • the other structures may be similar to any of the examples described in FIG. 3 to FIG. 5.
  • the first floating region 202-1 in this example does not extend in the X-axis direction below the lower end 33 of the first dummy trench portion 30-1.
  • the first floating region 202-1 does not contact the first dummy trench portion 30-1 when viewed from above.
  • An uncovered region 212 is provided between the first floating region 202-1 and the first dummy trench portion 30-1.
  • the first floating region 202-1 may or may not extend below the contact portion 54 of the first mesa portion 60-1.
  • the first floating region 202-1 may or may not extend to the center of the first mesa portion 60-1 in the X-axis direction.
  • the first floating 202-1 may be arranged discretely in the Y-axis direction, as in the examples of Figures 4 and 5.
  • the first floating region 202-1 may be provided in a single continuous manner in the Y-axis direction, as in the floating region 202 of Figures 4 and 5. Even in this case, the non-covered region 212 is provided between the first dummy trench portion 30-1 and the first floating region 202, so snapback can be suppressed.
  • the width of the first mesa portion 60-1 in the X-axis direction is X1.
  • the width of the uncovered region 212 in the X-axis direction may be 10% or more of the width X1, 20% or more, or 30% or more.
  • the width of the uncovered region 212 in the X-axis direction may be 90% or less of the width X1, 80% or less, or 70% or less.
  • the width of the uncovered region 212 in the X-axis direction may be 50% or less of the width X1.
  • the first floating region 202-1 may be in contact with the second dummy trench portion 30-2 when viewed from above.
  • the first floating region 202-1 is in contact with the second dummy trench portion 30-2 in the XZ cross section.
  • the width of the second mesa portion 60-2 in the X-axis direction is X2.
  • Width X2 may be smaller than width X1.
  • the first gate trench portion 40-1 is disposed between the first dummy trench portion 30-1 and the second dummy trench portion 30-2, offset toward the second dummy trench portion 30-2.
  • FIG. 7 is a diagram showing another example of the e-e cross section.
  • the arrangement of the first floating region 202-1 differs from the example described in FIG. 6.
  • the other structures may be similar to any of the examples described in FIG. 6.
  • the first floating region 202-1 is also disposed away from the second dummy trench portion 30-2 in a top view.
  • the distance in the X-axis direction between the first floating region 202-1 and the first dummy trench portion 30-1 is X3, and the distance between the first floating region 202-1 and the second dummy trench portion 30-2 is X4.
  • the distance X4 may be smaller than the distance X3.
  • the distance X4 may be 50% or less of the distance X3, or may be 30% or less.
  • the distance X4 may be 0 as in the example of FIG. 6. Snapback can also be suppressed by this example.
  • the floating areas 202 other than the first floating area 202-1 may be similar to the example in FIG. 6. In another example, all floating areas 202 may have a structure similar to the first floating area 202-1 in FIG. 7.
  • FIG. 8 is a top view showing an example of a transition region 92.
  • the structure of the transition region 92 described in FIG. 8 may be combined with any of the examples described in this specification.
  • the structure of the transition region 92 described in FIG. 8 may be combined with the structure of the floating region 202 of any of the examples described in this specification.
  • the floating region 202 in the semiconductor device 100 described in FIG. 8 may have a structure different from the examples in FIG. 1 to FIG. 7.
  • the semiconductor device 100 described in FIG. 8 may not have a floating region 202.
  • the semiconductor device 100 described in FIG. 8 may not have a diode section 80.
  • the well region 11 is also disposed outside the emitter region 12 in the X-axis direction.
  • a peripheral gate wiring 130 is disposed, extending in the Y-axis direction.
  • the transition region 92 is disposed between the emitter region 12 (or the transistor portion 70) and the well region 11 in the X-axis direction. In the transition region 92, one or more trench portions are arranged side by side in the X-axis direction.
  • the transition region 92 may have one or more dummy trench portions 30, may have one or more gate trench portions 40, or may have both a dummy trench portion 30 and a gate trench portion 40.
  • the transition region 92 in this example has trench portions arranged in the same pattern as the transistor portion 70. In the transistor portion 70 in this example, one gate trench portion 40 and two dummy trench portions 30 are arranged alternately.
  • the transition region 92 may also have one gate trench portion 40 and two dummy trench portions 30 arranged alternately.
  • One or more trench portions may also be arranged inside the well region 11.
  • two dummy trench portions 30 are arranged inside the well region 11.
  • the transition region 92 may have a collector region 22 at a position where it contacts the lower surface 23.
  • the transition region 92 may have a cathode region 82 at a position where it contacts the lower surface 23.
  • the transition region 92 has one or more mesas 63.
  • the drift region 18 may be exposed on the upper surface 21 of the mesa portion 63.
  • the upper surface 21 of the mesa portion 63 may have a base region 14 provided thereon.
  • the semiconductor device 100 of this example includes a second extension region 220 provided in the transition region 92.
  • the second extension region 220 is a P-type region that extends in the X-axis direction from the well region 11 to a position where it overlaps with the emitter region 12.
  • the second extension region 220 is connected to the well region 11.
  • the second extension region 220 may be provided at the same depth position as the floating region 202.
  • the second extension region 220 may have the same doping concentration as the floating region 202.
  • the second extension region 204 in this example overlaps with the entire emitter region 12 of the mesa portion 60 that is closest to the well region 11 in the X-axis direction.
  • the second extension region 204 may overlap with the entire emitter regions 12 of two or more mesa portions 60 that are closest to the well region 11. If a contact region 15 is provided in the mesa portion 60, the second extension region 204 also overlaps with the contact region 15.
  • the second extension region 204 is not connected to the floating region 202.
  • the transition region 92 can be set to emitter potential. This makes the electric field distribution in the transition region 92 uniform, and suppresses a decrease in breakdown voltage.
  • the second extension region 220 may be provided in a range wider than the floating region 202 in the Y-axis direction.
  • the second extension region 220 may be connected at its end in the Y-axis direction to the first extension region 204 described in FIG. 4 and the like.
  • FIG. 9 is a diagram showing an example of the f-f cross section in FIG. 8.
  • the f-f cross section is an XZ plane including the well region 11, the transition region 92, and the transistor section 70.
  • the peripheral gate wiring 130 is disposed above the well region 11.
  • the peripheral gate wiring 130 and the well region 11 are insulated by an insulating film 221 such as an oxide film.
  • the upper surface structure such as the emitter electrode 52 and the interlayer insulating film 38, and the lower surface structure such as the collector electrode 24 are omitted.
  • the second extension region 220 is provided below the lower ends of one or more trench portions provided in the transition region 92.
  • the second extension region 220 may be in contact with the lower ends of each trench portion.
  • the second extension region 220 extends in the X-axis direction beyond the transition region 92 to the transistor portion 70.
  • the second extension region 220 extends to below the emitter region 12.
  • the second extension region 220 may extend to below the lower end of at least one gate trench portion 40 of the transistor portion 70. No floating region 202 is provided below the gate trench portion 40.
  • FIG. 10 is an XZ cross section showing another example structure of the boundary region 90 and the diode section 80.
  • the upper surface structure such as the emitter electrode 52 and the interlayer insulating film 38, and the lower surface structure such as the collector electrode 24 are omitted.
  • the boundary region 90 and the diode section 80 do not have a floating region 202.
  • a floating region 202 is provided in at least one of the boundary region 90 and the diode section 80.
  • the structure described in Figure 10 can be applied to any of the examples described in Figures 1 to 9.
  • the floating region 202 in the boundary region 90 the electric field distribution in the transistor section 70 other than the boundary region 90 and the boundary region 90 can be made uniform.
  • the floating region 202 in the diode section 80 the electric field distribution in the transistor section 70 and the diode section 80 can be made uniform.
  • the arrangement pattern of the trench portions in the transistor portion 70 is different from the examples of FIG. 3 and the like.
  • one gate trench portion 40 and one dummy trench portion 30 are arranged alternately in the X-axis direction.
  • the arrangement pattern of the trench portions in the transistor portion 70 may be either the pattern in FIG. 3 or FIG. 10, or may be another pattern.
  • a floating region 202 is provided in each gate trench portion 40.
  • the floating region 202 in the example of FIG. 10 does not extend to a position where it overlaps with a trench portion (in this example, a dummy trench portion 30) arranged next to the corresponding gate trench portion 40.
  • the floating region 202 may extend to a position where it overlaps with at least one trench portion arranged next to the gate trench portion 40, as described in FIG. 3 to FIG. 9.
  • the boundary region 90 has multiple dummy trench portions 30, multiple mesa portions 62, and one or more floating regions 202.
  • the floating regions 202 are provided below the lower end of at least one trench portion of the boundary region 90.
  • the period F2 at which the floating regions 202 are provided in the X-axis direction may be the same as the period F1 at which the floating regions 202 are provided in the X-axis direction in the transistor portion 70 other than the boundary region 90.
  • the period at which the floating regions 202 are provided is the distance between the center positions of the respective floating regions 202 in the X-axis direction.
  • a floating region 202 is also provided below the lower end of at least one trench portion of the diode portion 80.
  • the period F3 at which the floating regions 202 are provided in the X-axis direction may be the same as the period F1 in the transistor portion 70.
  • the floating regions 202 in the boundary region 90 may be arranged in a discrete manner in the Y-axis direction, or may be provided in a single continuous region.
  • the floating regions 202 in the diode section 80 may be arranged in a discrete manner in the Y-axis direction, or may be provided in a single continuous region.
  • the periods F1, F2, and F3 of the floating region 202 do not have to be the same.
  • the period F1 may be larger or smaller than the period F2.
  • the period F1 may be larger or smaller than the period F3.
  • the period F3 may be larger or smaller than the period F2.
  • the spacing in the X-axis direction of all trench portions in the semiconductor device 100 may be the same. In other examples, the spacing in the X-axis direction of the trench portions may not be uniform.
  • FIG. 11 shows the collector voltage-collector current characteristics in the embodiment and the reference example.
  • the reference example is an example in which the uncovered region 212 is not provided in the first mesa portion 60-1.
  • the embodiment is an example in which the uncovered region 212 is provided in the first mesa portion 60-1.
  • the floating region 202 makes it difficult for the electron current of the first mesa portion 60-1 to flow to the collector region 22. For this reason, in the reference example, as shown in FIG. 11, snapback occurs in which almost no collector current flows until the collector voltage becomes greater than a predetermined voltage. In contrast, in the semiconductor device 100 of the embodiment, the electron current of the first mesa portion 60-1 easily flows to the collector region 22. For this reason, snapback does not occur.
  • FIG. 12 is a diagram showing the trade-off characteristics of turn-on loss and reverse recovery dV/dt in the reference example and the working example.
  • FIG. 12 shows the trade-off relationship in which the turn-on loss increases when the reverse recovery dV/dt is reduced.
  • the reference example in FIG. 12 is a semiconductor device that does not have a floating region 202.
  • the semiconductor device of the embodiment is the semiconductor device 100 described in FIG. 1 to FIG. 10.
  • the semiconductor device 100 of the embodiment has an improved trade-off characteristic by having a floating region 202. For example, when the reverse recovery dV/dt is the same, the turn-on loss of the embodiment is smaller than that of the reference example.
  • the semiconductor device 100 can improve the trade-off characteristics between turn-on loss and reverse recovery dV/dt. As described in FIG. 11, the semiconductor device 100 can suppress snapback.
  • contact portion 60, 61, 62, 63... mesa portion, 60-1... first mesa portion, 60-2... second mesa portion, 70... transistor portion, 80... diode portion, 81... extension region, 82... cathode region, 90... boundary region, 92... transition region, 100... semiconductor device, 130... peripheral gate wiring, 131... active side gate wiring, 160... active portion, 162... edge, 164... gate pad, 190... edge termination structure portion, 202... floating region, 202-1... first floating region, 204... first extension region, 212... non-covered region, 220... second extension region, 221... insulating film

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US19/277,332 US20250351553A1 (en) 2023-08-07 2025-07-22 Semiconductor device

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014170780A (ja) * 2013-03-01 2014-09-18 Toyota Central R&D Labs Inc 逆導通ｉｇｂｔ
JP2019021891A (ja) * 2017-07-14 2019-02-07 富士電機株式会社 半導体装置
WO2022239285A1 (ja) * 2021-05-11 2022-11-17 富士電機株式会社 半導体装置
WO2023063411A1 (ja) * 2021-10-15 2023-04-20 富士電機株式会社 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014170780A (ja) * 2013-03-01 2014-09-18 Toyota Central R&D Labs Inc 逆導通ｉｇｂｔ
JP2019021891A (ja) * 2017-07-14 2019-02-07 富士電機株式会社 半導体装置
WO2022239285A1 (ja) * 2021-05-11 2022-11-17 富士電機株式会社 半導体装置
WO2023063411A1 (ja) * 2021-10-15 2023-04-20 富士電機株式会社 半導体装置

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