WO2025033084A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2025033084A1
WO2025033084A1 PCT/JP2024/024939 JP2024024939W WO2025033084A1 WO 2025033084 A1 WO2025033084 A1 WO 2025033084A1 JP 2024024939 W JP2024024939 W JP 2024024939W WO 2025033084 A1 WO2025033084 A1 WO 2025033084A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
contact
semiconductor device
trench portion
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2024/024939
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
功 吉川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2025539221A priority Critical patent/JPWO2025033084A1/ja
Priority to CN202480008986.9A priority patent/CN120604637A/zh
Priority to DE112024000331.1T priority patent/DE112024000331T5/de
Publication of WO2025033084A1 publication Critical patent/WO2025033084A1/ja
Priority to US19/277,320 priority patent/US20250351552A1/en
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/422—PN diodes having the PN junctions in mesas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/161—IGBT having built-in components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/417—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/418—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/035—Etching a recess in the emitter region 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/128—Anode regions of diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/232—Emitter electrodes for IGBTs

Definitions

  • the present invention relates to a semiconductor device.
  • the semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and a first conductivity type drift region provided therein.
  • Any of the semiconductor devices may include a first gate trench portion provided on the upper surface of the semiconductor substrate.
  • Any of the semiconductor devices may include a first dummy trench portion provided on the upper surface of the semiconductor substrate and arranged side by side with the first gate trench portion on the upper surface.
  • Any of the semiconductor devices may include a first mesa portion sandwiched between the first gate trench portion and the first dummy trench portion inside the semiconductor substrate.
  • any of the semiconductor devices may include a second conductivity type floating region on the upper surface side of the semiconductor substrate, which is arranged below the lower end of the first gate trench portion and does not extend below the lower end of the first dummy trench portion.
  • the first mesa portion of any of the above semiconductor devices may be provided in contact with the first gate trench portion and may have an emitter region of a first conductivity type having a higher concentration than the drift region.
  • the first mesa portion of any of the above semiconductor devices may be provided between the emitter region and the drift region and may have a base region of a second conductivity type in contact with the first gate trench portion.
  • the lower end of the first dummy trench portion may be in contact with a region of the first conductivity type.
  • the floating region does not need to be in contact with the lower end of the gate trench portion.
  • the floating region may be in contact with the lower end of the gate trench portion.
  • the first mesa portion may further include an accumulation region of the first conductivity type that is provided between the base region and the drift region and has a higher concentration than the drift region.
  • the accumulation region may be in contact with the floating region.
  • the lower end of the accumulation region may be located below the lower end of the floating region.
  • the lower end of the accumulation region may be located above the lower end of the floating region.
  • the first mesa portion may be in contact with the upper surface of the semiconductor substrate and may have a contact region of the second conductivity type having a higher concentration than the base region.
  • the first mesa portion may have a contact portion that is provided from the upper surface of the semiconductor substrate to the inside of the first mesa portion and is filled with a conductive material.
  • the lower end of the contact portion may be in contact with the contact region.
  • the first dummy trench portion may be provided on both sides of the first gate trench portion.
  • the floating region may be in contact with a sidewall of the first dummy trench portion.
  • the first dummy trench portion may have a polysilicon electrode doped with an impurity of a first conductivity type.
  • any of the above semiconductor devices may include a lower end region of the first conductivity type that is provided in contact with the lower end of the first dummy trench portion and has a higher concentration than the drift region.
  • any of the above semiconductor devices may have two dummy trench portions provided on the upper surface of the semiconductor substrate and arranged side by side on the upper surface.
  • the spacing between the first gate trench portion and the first dummy trench portion may be the same as the spacing between the two dummy trench portions.
  • any of the above semiconductor devices may include diode sections arranged alternately with the IGBTs in the first direction.
  • the IGBTs arranged between the diode sections may have a plurality of trench sections arranged side by side in the first direction, including the first gate trench section and the first dummy trench section.
  • the spacing between each of the plurality of trench sections may be the same.
  • FIG. 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention.
  • FIG. 2 is an enlarged view of an area D in FIG.
  • FIG. 3 is a diagram showing an example of a cross section taken along the line ee in FIG. 2.
  • FIG. 3 is a diagram showing an example of the ff cross section in FIG. 2.
  • FIG. 13 is a diagram showing collector voltage-collector current characteristics in an embodiment and a reference example.
  • FIG. 13 is a diagram showing collector voltage-collector current characteristics in an embodiment and a reference example.
  • 11A and 11B are diagrams illustrating an example of measuring the voltage and current of a semiconductor device according to an embodiment of the 13A and 13B are diagrams showing other measurement examples of voltage and current of the semiconductor device of the reference example.
  • FIG. 13A and 13B are diagrams showing another example of measurement of voltage and current of the semiconductor device of the example.
  • FIG. 11 is a diagram showing the trade-off characteristics between turn-on loss and reverse recovery dV/dt in the reference example and the working example.
  • FIG. 13 is a diagram showing another example of the ff cross section.
  • FIG. 13 is a diagram showing another example of the ff cross section.
  • FIG. 13 is a diagram showing another example of the ff cross section.
  • FIG. 13 is a diagram showing another example of the ff cross section.
  • FIG. 13 is a diagram showing another example of the ff cross section.
  • FIG. 13 is a diagram showing another example of the ff cross section.
  • FIG. 13 is a diagram showing another example of the ee cross section.
  • one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper” and the other side as “lower.”
  • the upper surface is referred to as the upper surface and the other surface is referred to as the lower surface.
  • the directions of "upper” and “lower” are not limited to the direction of gravity or the directions when the semiconductor device is mounted.
  • the orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction.
  • the Z-axis does not limit the height direction relative to the ground.
  • the +Z-axis direction and the -Z-axis direction are opposite directions.
  • the Z-axis direction is described without indicating positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.
  • the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis.
  • the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis.
  • the direction of the Z-axis may be referred to as the depth direction.
  • the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis may be referred to as the horizontal direction.
  • the region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top side.
  • the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom side.
  • the conductivity type of a doped region doped with impurities is described as P type or N type.
  • impurities may specifically mean either N type donors or P type acceptors, and may be described as dopants.
  • doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor that exhibits N type conductivity or a semiconductor that exhibits P type conductivity.
  • the doping concentration means the concentration of the donor or the concentration of the acceptor in a thermal equilibrium state.
  • the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge.
  • the donor concentration is N D and the acceptor concentration is N A
  • the net doping concentration at any position is N D -N A.
  • the net doping concentration may be simply referred to as the doping concentration.
  • P+ type or N+ type when P+ type or N+ type is mentioned, it means that the doping concentration is higher than P type or N type, and when P- type or N- type is mentioned, it means that the doping concentration is lower than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means that the doping concentration is higher than P+ type or N+ type.
  • the unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).
  • chemical concentration refers to the atomic density of an impurity measured regardless of the state of electrical activation.
  • the chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS).
  • the above-mentioned net doping concentration can be measured by a voltage-capacitance measurement method (CV method).
  • the carrier concentration measured by a spreading resistance measurement method (SR method) may be the net doping concentration.
  • the carrier concentration measured by the CV method or the SR method may be a value in a thermal equilibrium state.
  • the donor concentration is sufficiently larger than the acceptor concentration in an N-type region, the carrier concentration in that region may be the donor concentration.
  • the carrier concentration in that region may be the acceptor concentration.
  • the doping concentration in an N-type region may be referred to as the donor concentration
  • the doping concentration in a P-type region may be referred to as the acceptor concentration.
  • the peak value may be taken as the concentration of the donor, acceptor or net doping in the region.
  • the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping.
  • atoms/cm 3 or /cm 3 is used to express concentration per unit volume. This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The notation of atoms may be omitted.
  • the carrier concentration measured by the SR method may be lower than the donor or acceptor concentration.
  • the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.
  • the donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor.
  • the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor is about 99% of the chemical concentration.
  • the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.
  • FIG. 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention.
  • FIG. 1 the positions of each component projected onto the top surface of a semiconductor substrate 10 are shown.
  • FIG. 1 only some of the components of the semiconductor device 100 are shown, and some components are omitted.
  • the semiconductor device 100 includes a semiconductor substrate 10.
  • the semiconductor substrate 10 is a substrate formed of a semiconductor material.
  • the semiconductor substrate 10 is a silicon substrate.
  • the semiconductor substrate 10 has edges 162 when viewed from above. When simply referred to as a top view in this specification, it means that the semiconductor substrate 10 is viewed from the top side.
  • the semiconductor substrate 10 has two sets of edges 162 that face each other when viewed from above. In FIG. 1, the X-axis and Y-axis are parallel to one of the edges 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.
  • the semiconductor substrate 10 has an active portion 160.
  • the active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation.
  • An emitter electrode is provided above the active portion 160, but is omitted in FIG. 1.
  • the active portion 160 may refer to the region that overlaps with the emitter electrode when viewed from above.
  • the active portion 160 may also include the region sandwiched between the active portions 160 when viewed from above.
  • the active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor).
  • the active section 160 may further be provided with a diode section 80 including a diode element such as a free wheel diode (FWD).
  • the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10.
  • the semiconductor device 100 in this example is a reverse conducting IGBT (RC-IGBT).
  • the region in which the transistor section 70 is arranged is marked with the symbol "I”
  • the region in which the diode section 80 is arranged is marked with the symbol "F”.
  • the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1).
  • the transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction.
  • the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction.
  • the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction.
  • the extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.
  • the diode section 80 has an N+ type cathode region in a region that contacts the lower surface of the semiconductor substrate 10.
  • the region in which the cathode region is provided is referred to as the diode section 80.
  • the diode section 80 is a region that overlaps with the cathode region when viewed from above.
  • a P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region.
  • the diode section 80 may also include an extension region 81 that extends the diode section 80 in the Y-axis direction to the gate wiring described below.
  • a collector region is provided on the lower surface of the extension region 81.
  • the transistor section 70 has a P+ type collector region in a region that contacts the bottom surface of the semiconductor substrate 10.
  • the transistor section 70 has a gate structure that has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film periodically arranged on the top surface side of the semiconductor substrate 10.
  • the semiconductor device 100 may have one or more pads above the semiconductor substrate 10.
  • the semiconductor device 100 in this example has a gate pad 164.
  • the semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad.
  • Each pad is disposed near an edge 162.
  • the vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view.
  • each pad may be connected to an external circuit via wiring such as a wire.
  • a gate potential is applied to the gate pad 164.
  • the gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160.
  • the semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with diagonal lines.
  • the gate wiring in this example has a peripheral gate wiring 130 and an active side gate wiring 131.
  • the peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view.
  • the peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view.
  • the region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160.
  • a well region is formed below the gate wiring.
  • the well region is a P-type region with a higher concentration than the base region described below, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region.
  • the region surrounded by the well region in a top view may be the active portion 160.
  • the peripheral gate wiring 130 is connected to the gate pad 164.
  • the peripheral gate wiring 130 is disposed above the semiconductor substrate 10.
  • the peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.
  • the active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, the variation in wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.
  • the peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160.
  • the peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10.
  • the peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.
  • the active side gate wiring 131 may be connected to the peripheral gate wiring 130.
  • the active side gate wiring 131 is provided extending in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 sandwiching the active section 160, so as to cross the active section 160 at approximately the center in the Y-axis direction.
  • the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region.
  • the semiconductor device 100 may also include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that simulates the operation of a transistor section provided in the active section 160.
  • a temperature sensor not shown
  • a current detector not shown
  • the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the edge 162 when viewed from above.
  • the edge termination structure 90 in this example is disposed between the peripheral gate wiring 130 and the edge 162.
  • the edge termination structure 90 reduces electric field concentration on the upper surface side of the semiconductor substrate 10.
  • the edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf that are arranged in a ring shape surrounding the active portion 160.
  • Region D includes transistor section 70, diode section 80, and active side gate wiring 131.
  • the semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10.
  • the gate trench section 40 and the dummy trench section 30 are each an example of a trench section.
  • the semiconductor device 100 of this example also includes an emitter electrode 52 and an active side gate wiring 131 provided above the upper surface of the semiconductor substrate 10.
  • the emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.
  • An interlayer insulating film is provided between the emitter electrode 52 and the active gate wiring 131 and the upper surface of the semiconductor substrate 10, but is omitted in FIG. 2.
  • a contact portion 54 is provided in the interlayer insulating film so as to penetrate the interlayer insulating film.
  • the contact portion 54 may have a contact hole provided in the interlayer insulating film and a conductive member filled in the contact hole. In FIG. 2, each contact portion 54 is hatched with diagonal lines.
  • the emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15.
  • the emitter electrode 52 is connected to the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 via a contact portion 54.
  • the emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film.
  • the emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.
  • the active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film.
  • the active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction.
  • the active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.
  • the emitter electrode 52 is formed of a material containing metal.
  • FIG. 2 shows the range in which the emitter electrode 52 is provided.
  • the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu.
  • the emitter electrode 52 may have a barrier metal made of titanium or a titanium compound under the region made of aluminum or the like.
  • the emitter electrode 52 may have a plug formed by embedding tungsten or the like in the contact hole so as to contact the barrier metal and aluminum or the like.
  • the well region 11 is provided so as to overlap with the active side gate wiring 131.
  • the well region 11 is also provided so as to extend by a predetermined width into an area where it does not overlap with the active side gate wiring 131.
  • the well region 11 is provided away from the end of the contact portion 54 in the Y-axis direction toward the active side gate wiring 131.
  • the well region 11 is a region of a second conductivity type having a higher doping concentration than the base region 14.
  • the base region 14 is P- type
  • the well region 11 is P+ type.
  • the transistor section 70 and the diode section 80 each have multiple trench sections arranged in the arrangement direction.
  • one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction.
  • the diode section 80 of this example multiple dummy trench sections 30 are provided along the arrangement direction.
  • no gate trench section 40 is provided in the diode section 80 of this example.
  • the gate trench portion 40 in this example may have two straight portions 39 (portions of the trench that are straight along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two straight portions 39.
  • the extension direction in FIG. 2 is the Y-axis direction.
  • the tip 41 is curved when viewed from above.
  • the tip 41 connects the ends of the two straight portions 39 in the Y-axis direction, thereby reducing electric field concentration at the ends of the straight portions 39.
  • the dummy trench portion 30 is provided between each straight portion 39 of the gate trench portion 40.
  • One dummy trench portion 30 may be provided between each straight portion 39, or multiple dummy trench portions 30 may be provided.
  • the dummy trench portion 30 may have a straight line shape extending in the extension direction, and may have a straight line portion 29 and a tip portion 31, similar to the gate trench portion 40.
  • the diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30.
  • the ends in the Y-axis direction of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 when viewed from above. In other words, at the ends in the Y-axis direction of each trench portion, the bottoms in the depth direction of each trench portion are covered by the well region 11. This makes it possible to reduce electric field concentration at the bottoms of each trench portion.
  • the mesa portion refers to the region inside the semiconductor substrate 10 that is sandwiched between the trench portions.
  • the upper end of the mesa portion is the upper surface of the semiconductor substrate 10.
  • the depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion.
  • the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench.
  • the transistor portion 70 is provided with a mesa portion 60
  • the diode portion 80 is provided with a mesa portion 61.
  • the term "mesa portion” refers to both the mesa portion 60 and the mesa portion 61.
  • a base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active gate wiring 131 is referred to as the base region 14-e. In FIG. 2, the base region 14-e is shown at one end in the extension direction of each mesa portion, but the base region 14-e is also provided at the other end of each mesa portion. In each mesa portion, at least one of the emitter region 12 of the first conductivity type and the contact region 15 of the second conductivity type may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type with a higher concentration than the base region 14. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.
  • the mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10.
  • the emitter region 12 is provided in contact with the gate trench portion 40.
  • the mesa portion 60 in contact with the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10.
  • the emitter region 12 in the mesa portion 60 is provided in contact with the gate trench portion 40.
  • the emitter region 12 may or may not be in contact with the dummy trench portion 30.
  • the emitter region 12 is also provided in a region that overlaps with the contact portion 54.
  • the contact region 15 in the mesa portion 60 is provided in a region that overlaps with the contact portion 54.
  • the contact region 15 may or may not be in contact with the gate trench portion 40.
  • the contact region 15 may or may not be in contact with the dummy trench portion 30.
  • the emitter region 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction.
  • the contact region 15 in the mesa portion 60 may also be provided from one trench portion to the other trench portion in the X-axis direction.
  • the contact region 15 does not have to be in contact with either of the two trench portions that sandwich the mesa portion 60.
  • a base region 14 may be provided between the contact region 15 and the trench portion.
  • the contact regions 15 and emitter regions 12 of the mesa portion 60 are alternately arranged along the extension direction (Y-axis direction) of the trench portion.
  • the contact regions 15 and emitter regions 12 of the mesa portion 60 may be arranged in stripes along the extension direction (Y-axis direction) of the trench portion.
  • the emitter regions 12 are provided in the region in contact with the trench portion, and the contact regions 15 are provided in the region sandwiched between the emitter regions 12.
  • the mesa portion 60 may also be provided with emitter regions 12 instead of contact regions 15.
  • the emitter regions 12 may be provided in the entire region sandwiched between the base regions 14-e in the Y-axis direction.
  • the mesa portion 61 of the diode section 80 does not have an emitter region 12.
  • a base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61.
  • a contact region 15 may be provided in contact with each of the base regions 14-e.
  • a base region 14 may be provided in the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61.
  • the base region 14 may be disposed in the entire region sandwiched between the contact regions 15.
  • a contact portion 54 is provided above each mesa portion.
  • the contact portion 54 is located in a region sandwiched between the base regions 14-e. In this example, the contact portion 54 is provided above the contact region 15, the base region 14, and the emitter region 12. The contact portion 54 is not provided in the region corresponding to the base region 14-e and the well region 11.
  • the contact portion 54 may be located in the center of the arrangement direction (X-axis direction) of the mesa portions 60.
  • an N+ type cathode region 82 is provided in a region adjacent to the underside of the semiconductor substrate 10.
  • a P+ type collector region 22 may be provided in the region of the underside of the semiconductor substrate 10 where the cathode region 82 is not provided.
  • the cathode region 82 and the collector region 22 are provided between the underside 23 of the semiconductor substrate 10 and the buffer region 20.
  • the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.
  • the cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and the P-type region (well region 11) that has a relatively high doping concentration and is formed deep, improving the breakdown voltage.
  • the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact portion 54 in the Y-axis direction.
  • the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact portion 54.
  • FIG. 3 is a diagram showing an example of the e-e cross section in FIG. 2.
  • the e-e cross section is an XZ plane passing through the emitter region 12 and the cathode region 82.
  • the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.
  • the interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10.
  • the interlayer insulating film 38 is a film that includes at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films.
  • the interlayer insulating film 38 is provided with the contact portion 54 described in FIG. 2.
  • the contact portion 54 is provided through the interlayer insulating film 38.
  • the contact portion 54 may be formed of a metal different from that of the emitter electrode 52.
  • the contact portion 54 may contain tungsten.
  • a barrier metal layer including at least one of a titanium film and a titanium nitride film may be provided at the bottom of the contact portion 54.
  • the contact portion 54 may be provided up to the upper surface 21 of the semiconductor substrate 10, or may be provided up to the inside of the semiconductor substrate 10.
  • the contact portion 54 is a contact trench provided from the upper surface 21 of the semiconductor substrate 10 to the inside of each mesa portion. This allows the contact area between the contact portion 54 and the semiconductor substrate 10 to be increased.
  • the lower end of the contact portion 54 of the transistor portion 70 is in contact with the emitter region 12.
  • the lower end of the contact portion 54 of the diode portion 80 is in contact with the base region 14.
  • the emitter electrode 52 is provided above the interlayer insulating film 38.
  • the emitter electrode 52 is connected to the semiconductor substrate 10 via a contact portion 54.
  • the collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10.
  • the emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.
  • the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.
  • the semiconductor substrate 10 has an N-type or N-type drift region 18.
  • the drift region 18 is provided in each of the transistor portion 70 and the diode portion 80.
  • an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10.
  • a drift region 18 is provided below the base region 14.
  • An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.
  • the emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40.
  • the emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60.
  • the emitter region 12 has a higher doping concentration than the drift region 18.
  • the base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.
  • the accumulation region 16 is provided below the base region 14.
  • the accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. In other words, the accumulation region 16 has a higher donor concentration than the drift region 18.
  • the carrier injection enhancement effect IE effect
  • the accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.
  • the mesa portion 61 of the diode section 80 has a P-type base region 14 in contact with the upper surface 21 of the semiconductor substrate 10.
  • a drift region 18 is provided below the base region 14.
  • an accumulation region 16 may be provided below the base region 14.
  • an N+ type buffer region 20 may be provided below the drift region 18.
  • the doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18.
  • the buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18.
  • the doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak.
  • the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.
  • the buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10.
  • the concentration peak of the buffer region 20 may be located at the same depth as the chemical concentration peak of hydrogen (protons) or phosphorus, for example.
  • the buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.
  • a P+ type collector region 22 is provided below the buffer region 20.
  • the acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14.
  • the collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor.
  • the acceptor of the collector region 22 is, for example, boron.
  • an N+ type cathode region 82 is provided below the buffer region 20.
  • the donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18.
  • the donor of the cathode region 82 is, for example, hydrogen or phosphorus.
  • the elements that serve as the donor and acceptor of each region are not limited to the above-mentioned examples.
  • the collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24.
  • the collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10.
  • the emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.
  • each trench portion is provided from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these doped regions.
  • the trench portion penetrating the doped region is not limited to being manufactured in the order of forming the doped region and then the trench portion.
  • the trench portion penetrating the doped region also includes a trench portion formed after the trench portion is formed.
  • the transistor section 70 has a gate trench section 40 and a dummy trench section 30.
  • the diode section 80 has a dummy trench section 30, but does not have a gate trench section 40.
  • the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.
  • the gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44.
  • the gate insulating film 42 is provided to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
  • the gate conductive portion 44 is provided inside the gate insulating film 42 inside the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10.
  • the gate conductive portion 44 is formed of a conductive material such as polysilicon.
  • the gate conductive portion 44 may be provided longer than the base region 14 in the depth direction.
  • the gate trench portion 40 in this cross section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10.
  • the gate conductive portion 44 is electrically connected to the gate wiring.
  • a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section.
  • the dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10.
  • the dummy conductive portion 34 is electrically connected to the emitter electrode 52.
  • the dummy insulating film 32 is provided to cover the inner wall of the dummy trench.
  • the dummy conductive portion 34 is provided inside the dummy trench and is provided on the inside of the dummy insulating film 32.
  • the dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.
  • the dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.
  • the dummy conductive portion 34 is formed of a conductive material such as polysilicon.
  • the dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.
  • the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10.
  • the bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).
  • the depth position of the lower end 43 of the gate trench portion 40 is designated as Zt.
  • the semiconductor device 100 of this example includes a P-type floating region 202 provided below the lower end 43 of the gate trench portion 40.
  • the lower end 43 of the gate trench portion 40 refers to the portion of the gate trench portion 40 that is closest to the lower surface 23 of the semiconductor substrate 10. In the example of FIG. 3, the lower end 43 of the gate trench portion 40 is disposed at the center of the gate trench portion 40 in the X-axis direction.
  • the lower end 33 of the dummy trench portion 30 refers to the portion of the dummy trench portion 30 that is closest to the lower surface 23 of the semiconductor substrate 10. In the example of FIG. 3, the lower end 33 of the dummy trench portion 30 is disposed at the center of the dummy trench portion 30 in the X-axis direction.
  • At least a portion of the floating region 202 is provided at a position overlapping the lower end 43 in a top view, and is disposed below the lower end 43 in the Z-axis direction.
  • the floating region 202 may include a portion that does not overlap the lower end 43 in a top view.
  • the floating region 202 may include a portion that is provided above the lower end 43.
  • the floating region 202 may be in contact with the lower end 43 or may be separated from the lower end 43. In the example of FIG. 3, the floating region 202 is in contact with the entire curved portion including the lower end 43 in the gate trench portion 40.
  • the floating region 202 may be formed by injecting a P-type dopant near the lower end of the trench structure after forming the groove structure of the gate trench portion 40 and before forming the gate conductive portion 44.
  • the floating region 202 is electrically floating with respect to an electrode such as a metal or polysilicon. At least one of an N-type region and an insulating film is disposed between the floating region 202 and the electrode. In other words, the floating region 202 and the electrode are not connected by a P-type region and a conductive material.
  • the doping concentration of the floating region 202 may be equal to or lower than the doping concentration of the base region 14, or may be higher than the doping concentration of the base region 14.
  • the doping concentration of the floating region 202 in this example is higher than the doping concentration of the base region 14.
  • the doping concentration may be 1 ⁇ 10 15 cm ⁇ 3 or higher and 1 ⁇ 10 17 cm ⁇ 3 or lower.
  • the floating region 202 is disposed away from the base region 14.
  • An N-type region (at least one of the accumulation region 16 and the drift region 18 in this example) is provided between the floating region 202 and the base region 14.
  • the gate trench portion 40 below which the floating region 202 is disposed is referred to as the first gate trench portion 40-1.
  • the dummy trench portion 30 that is disposed on the upper surface 21 next to the first gate trench portion 40-1 in the X-axis direction is referred to as the first dummy trench portion 30-1.
  • the first gate trench portion 40-1 and the first dummy trench portion 30-1 are two trench portions adjacent to each other in the X-axis direction.
  • the first dummy trench portion 30-1 is disposed on both sides of the first gate trench portion 40-1 in the X-axis direction.
  • the mesa portion 60 sandwiched between the first gate trench portion 40-1 and the first dummy trench portion 30-1 is referred to as the first mesa portion 60-1.
  • the mesa portions 60 the one sandwiched between the two dummy trench portions 30 is referred to as the second mesa portion 60-2.
  • the second mesa portion 60-2 may have the same structure as the first mesa portion 60-1.
  • Each transistor portion 70 has one or more first gate trench portions 40-1. Each transistor portion 70 may have multiple first gate trench portions 40-1. In each transistor portion 70, 50% or more of the gate trench portions 40 may be first gate trench portions 40-1, 80% or more of the gate trench portions 40 may be first gate trench portions 40-1, or all of the gate trench portions 40 may be first gate trench portions 40-1.
  • the floating region 202 is disposed below the lower end 43 of the first gate trench portion 40-1, and does not extend below the lower end 33 of the adjacent first dummy trench portion 30-1.
  • the lower end 33 is in contact with an N-type region (drift region 18 in this example). Also, on the upper surface 21 side of the semiconductor substrate 10, no P-type region is provided below the lower end 33, but an N-type region (drift region 18 in this example) is provided.
  • the floating region 202 By providing the floating region 202, when the transistor section 70 is turned on, it is possible to prevent electrons from flowing to the lower end 43 of the first gate trench section 40-1, and to leave a depletion layer near the lower end 43. This makes it possible to reduce the reverse recovery dV/dt.
  • the reverse recovery dV/dt is the slope of the time waveform of the anode-cathode voltage during reverse recovery of the diode section 80.
  • the semiconductor device 100 when the semiconductor device 100 is used in a circuit such as a three-phase inverter, it is possible to reduce the tail of the voltage waveform of the IGBT provided in the opposing arm. This makes it possible to improve the trade-off characteristics of turn-on loss and reverse recovery dV/dt.
  • the floating region 202 extends below the lower end 33 of the first dummy trench portion 30-1, when a channel is formed in the base region 14 of the first mesa portion 60-1 and an electronic current flows, the electronic current is less likely to flow to the collector region 22. This may cause snapback when the transistor portion 70 is turned on. Also, the turn-on time of the transistor portion 70 may be longer. In the semiconductor device 100 of this example, the floating region 202 does not extend below the lower end 33 of the first dummy trench portion 30-1. This makes it easier for the electronic current to flow to the collector region 22 when a channel is formed in the base region 14 of the first mesa portion 60-1 and an electronic current flows. This makes it possible to suppress the occurrence of snapback and reduce the turn-on delay.
  • the floating region 202 in this example is arranged so as not to overlap with the first dummy trench portion 30-1 in top view.
  • the floating region 202 may be arranged so as not to contact the first dummy trench portion 30-1.
  • An N-type region is arranged between the floating region 202 in this example and the first dummy trench portion 30-1.
  • the floating region 202 may be arranged so as to overlap with the first mesa portion 60-1 in top view.
  • the first mesa portion 60-1 may have a region that does not overlap with the floating region 202 in top view. In the first mesa portion 60-1 in this example, the region that contacts the first dummy trench portion 30-1 does not overlap with the floating region 202.
  • the floating region 202 may extend to a position where it overlaps with the contact portion 54 of the first mesa portion 60-1, or may be arranged so as not to overlap.
  • the floating region 202 extends in the Y-axis direction when viewed from above.
  • the length of the floating region 202 in the Y-axis direction may be 50% or more, 70% or more, or 90% or more of the length of the straight portion 39 of the first gate trench portion 40-1 in the Y-axis direction.
  • the end of the floating region 202 in the Y-axis direction is located below the base region 14-e.
  • the distance in the X-axis direction between the first gate trench portion 40-1 and the first dummy trench portion 30-1 is set to X1.
  • the distance between the trench portions is the distance between the centers of the trench portions in the X-axis direction.
  • the distance in the X-axis direction between the two dummy trench portions 30 in the transistor portion 70 is set to X2.
  • the distance between the two first dummy trench portions 30-1 is X2.
  • the distance X1 and the distance X2 may be the same.
  • the distance in the X-axis direction between the two dummy trench portions 30 in the diode portion 80 is set to X3.
  • the distance X1, the distance X2, and the distance X3 may be the same.
  • the spacing between all trench portions in at least one transistor portion 70 that is sandwiched between two diode portions 80 in the X-axis direction may be the same. Also, the spacing between all trench portions in the semiconductor device 100 may be the same.
  • FIG. 4 is a diagram showing an example of the f-f cross section in FIG. 2.
  • the f-f cross section is an XZ plane passing through the contact region 15 and the cathode region 82.
  • the semiconductor device 100 in the f-f cross section has a contact region 15 instead of the emitter region 12 of the mesa portion 60 in the structure of the semiconductor device 100 in the e-e cross section.
  • a contact region 15 is also provided in the mesa portion 61.
  • the rest of the structure is similar to that of the semiconductor device 100 in the e-e cross section.
  • the contact region 15 is exposed on the upper surface 21 of the semiconductor substrate 10.
  • the contact region 15 is provided between the upper surface 21 and the base region 14.
  • the contact region 15 does not contact the trench portions on either side of each mesa portion.
  • the base region 14 is provided between the contact region 15 and each trench portion.
  • the contact region 15 in this example is connected to the emitter electrode 52 via the contact portion 54.
  • the contact region 15 may be provided with a groove portion into which the contact portion 54 is inserted. In this cross section, the lower ends of the contact portions 54 of the transistor portion 70 and the diode portion 80 contact the contact region 15.
  • FIG. 5 is a diagram showing the collector voltage-collector current characteristics in the embodiment and the reference example.
  • the reference example is an example in which the floating region 202 is extended to below the lower end 33 of the first dummy trench portion 30-1.
  • the embodiment is the semiconductor device 100 described in FIGS. 1 to 4.
  • the floating region 202 makes it difficult for the electron current of the first mesa portion 60-1 to flow to the collector region 22. For this reason, in the reference example, as shown in FIG. 5, snapback occurs in which almost no collector current flows until the collector voltage becomes greater than a predetermined voltage. In contrast, in the semiconductor device 100 of the embodiment, the electron current of the first mesa portion 60-1 easily flows to the collector region 22. For this reason, snapback does not occur.
  • FIG. 6 is a diagram showing an example of measuring the voltage and current of a reference example semiconductor device.
  • the reference example semiconductor device of FIG. 6 has a structure similar to that of the reference example semiconductor device of FIG. 5.
  • FIG. 6 shows the time waveforms of the collector voltage Vce, collector current Ic, and gate voltage Vge of the semiconductor device.
  • Vbus is the voltage of the bus wiring connected to the collector of the semiconductor device
  • Ic is the steady-state value of the collector current
  • Rg is the gate resistance
  • Tj is the temperature of the measurement environment.
  • the timing when a predetermined on-voltage is applied to the gate of the semiconductor device is set as reference time 0.
  • the time until the collector voltage Vce drops to 10% of the voltage value (600 V) in the off state is set as the turn-on time of the semiconductor device.
  • the gate voltage Vge increases.
  • the gate voltage Vge reaches about 440 V
  • a channel is formed in the base region 14.
  • the electron current in the first mesa portion 60-1 does not easily flow to the collector region 22, so the rise of the collector current Ic is delayed and the fall of the collector voltage Vce is also delayed.
  • the turn-on time becomes relatively long, and the loss at turn-on increases.
  • FIG. 7 is a diagram showing an example of measuring the voltage and current of a semiconductor device of the embodiment.
  • the semiconductor device of the embodiment of FIG. 7 is the semiconductor device 100 described in FIGS. 1 to 4.
  • the electron current of the first mesa portion 60-1 easily flows to the collector region 22. Therefore, there is a small delay in the rise of the collector current Ic and the fall of the collector voltage Vce. This makes the turn-on time relatively short, and the loss during turn-on can be reduced.
  • FIG. 8 is a diagram showing another example of measuring the voltage and current of the semiconductor device of the reference example.
  • the steady-state value of the collector current Ic 150 A
  • the steady-state value of the collector current Ic 15 A
  • the other conditions are the same as those of the reference example of FIG. 6.
  • the rise of the collector current Ic is delayed, and the fall of the collector voltage Vce is also delayed.
  • the turn-on time becomes relatively long, and the loss at turn-on increases.
  • FIG. 9 is a diagram showing another example of measuring the voltage and current of the semiconductor device of the embodiment.
  • the steady-state value of the collector current Ic (150 A) is different from the steady-state value of the collector current Ic (15 A) of the embodiment of FIG. 7.
  • the other conditions are the same as those of the embodiment of FIG. 7.
  • Figure 10 shows the trade-off characteristics between turn-on loss and reverse recovery dV/dt in the reference example and the working example.
  • Figure 10 shows the trade-off relationship in which the turn-on loss increases when the reverse recovery dV/dv is reduced.
  • the reference example in FIG. 10 is a semiconductor device that does not have a floating region 202.
  • the semiconductor device of the embodiment is the semiconductor device 100 described in FIG. 1 to FIG. 4.
  • the semiconductor device 100 of the embodiment has an improved trade-off characteristic by having a floating region 202. For example, when the reverse recovery dV/dt is the same, the turn-on loss of the embodiment is smaller than that of the reference example.
  • the semiconductor device 100 can improve the trade-off characteristics between turn-on loss and reverse recovery dV/dt. As described in FIG. 5, the semiconductor device 100 can suppress snapback. As described in FIG. 6 to FIG. 9, the semiconductor device 100 can reduce the turn-on delay in the transistor section 70.
  • FIG. 11 is a diagram showing another example of the f-f cross section.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 in FIGS. 3 and 4 in the structure of the accumulation region 16.
  • the other structures are similar to the semiconductor device 100 of any of the aspects described in this specification.
  • the accumulation region 16 in this example is in contact with the floating region 202.
  • the accumulation region 16 may or may not be in contact with the base region 14.
  • the lower end of the accumulation region 16 may be provided at the same depth position.
  • the lower end of the accumulation region 16 may be located closer to the upper surface 21 than the lower end 43 of the first gate trench portion 40-1, may be located closer to the lower surface 23 than the lower end 43, or may be located at the same depth as the lower end 43.
  • the lower end of the accumulation region 16 in this example is located above the lower end of the floating region 202.
  • a high-concentration accumulation region 16 is disposed near the floating region 202, it is possible to prevent the P-type dopant in the floating region 202 from diffusing too much, and it is possible to prevent the entire first mesa portion 60-1 from being covered by the floating region 202.
  • an N-type region is more likely to remain near the first dummy trench portion 30-1. This makes it easier to further prevent the occurrence of snapback, etc.
  • FIG. 12 is a diagram showing another example of the f-f cross section.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 in FIG. 11 in the structure of the accumulation region 16.
  • the other structures are similar to the semiconductor device 100 of any of the aspects described in this specification.
  • the lower end of the accumulation region 16 in this example is located below the lower end of the floating region 202.
  • the floating region 202 in this example is surrounded by the accumulation region 16 except for the portion that contacts the trench portion.
  • the lower end of the accumulation region 16 may be located on the upper surface 21 side of the semiconductor substrate 10.
  • the distance in the Z-axis direction between the lower end of the floating region 202 and the lower end of the accumulation region 16 may be 10 ⁇ m or less, 5 ⁇ m or less, or 3 ⁇ m or less.
  • the floating region 202 is surrounded by the accumulation region 16. This prevents the P-type dopant in the floating region 202 from diffusing too much, which would result in the entire first mesa portion 60-1 being covered by the floating region 202. For example, an N-type region is more likely to remain in the vicinity of the first dummy trench portion 30-1. This makes it easier to further prevent the occurrence of snapback, etc.
  • FIG. 13 is a diagram showing another example of the f-f cross section.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 of the other examples in the arrangement of the floating region 202.
  • the other structures are similar to the semiconductor device 100 of any of the aspects described in this specification.
  • the floating region 202 in this example is not in contact with the first gate trench portion 40-1.
  • the floating region 202 is disposed below the lower end 43 of the first gate trench portion 40-1 and away from the lower end 43.
  • the floating region 202 is disposed on the upper surface 21 side of the semiconductor substrate 10.
  • the distance in the Z-axis direction between the floating region 202 and the lower end 43 may be 10 ⁇ m or less, 5 ⁇ m or less, or 3 ⁇ m or less. According to this example, it is easier to ensure a path for electron current to flow from the first mesa portion 60-1 to the collector region 22. This makes it possible to further suppress the occurrence of snapback, etc.
  • FIG. 14 is a diagram showing another example of the f-f cross section.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 of the other examples in the arrangement of the floating region 202.
  • the other structures are similar to the semiconductor device 100 of any of the aspects described in this specification.
  • the floating region 202 in this example is in contact with the first dummy trench portion 30-1.
  • the floating region 202 may be in contact with both of the first dummy trench portions 30-1.
  • the floating region 202 does not extend below the lower end 33 of the first dummy trench portion 30-1.
  • the floating region 202 may be in contact with the sidewall of the first dummy trench portion 30-1.
  • the sidewall is the portion of the outer wall of the first dummy trench portion 30-1 other than the lower end 33.
  • the sidewall of the first dummy trench portion 30-1 may be a flat portion of the outer wall of the first dummy trench portion 30-1.
  • the dummy conductive portion 34 of the first dummy trench portion 30-1 in this example may be an electrode of polysilicon doped with N-type impurities. If the dummy conductive portion 34 is P-type polysilicon, the sidewall of the first dummy trench portion 30-1 and the floating region 202 will be at the same potential. In this case, the path through which the electron current flows from the channel is divided by the equipotential region, making it difficult for the electron current to flow. By making the dummy conductive portion 34 N-type, the sidewall of the first dummy trench portion 30-1 and the floating region 202 will be at different potentials. In this case, a path through which the electron current flows remains near the sidewall of the first dummy trench portion 30-1. This makes it possible to improve the trade-off characteristics of the semiconductor device 100 while suppressing the occurrence of snapback, etc.
  • the conductive portions of the trench portions other than the first dummy trench portion 30-1 may also be N-type polysilicon.
  • the doping concentration of the N-type impurity of the dummy conductive portion 34 of the first dummy trench portion 30-1 may be higher than the doping concentration of the N-type impurity of the gate conductive portion 44 of the first gate trench portion 40-1. This makes it easier to ensure a path for electronic current to flow near the sidewall of the first dummy trench portion 30-1.
  • the conductive portions of at least some of the trench portions other than the first dummy trench portion 30-1 may be P-type polysilicon.
  • the conductive portion of the first gate trench portion 40-1 may be P-type polysilicon.
  • FIG. 15 is a diagram showing another example of the f-f cross section.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 of the other examples in the arrangement pattern of the trench portions in the X-axis direction of the transistor portion 70.
  • the structure other than the arrangement pattern of the trench portions is the same as that of any of the semiconductor device 100 aspects described in this specification.
  • the transistor section 70 in this example has two first gate trench sections 40-1 arranged adjacent to each other in the X-axis direction.
  • the transistor section 70 has two first gate trench sections 40-1 and two first dummy trench sections 30-1 arranged alternately in the X-axis direction.
  • a floating region 202 is disposed below the lower end 43 of each first gate trench portion 40-1.
  • the floating regions 202 below two first gate trench portions 40-1 adjacent to each other in the X-axis direction may be separated from each other as shown in FIG. 15, or may be connected.
  • the mesa portion 60 sandwiched between the two first gate trench portions 40-1 is the third mesa portion 60-3.
  • the third mesa portion 60-3 may have the same structure as the first mesa portion 60-1.
  • the third mesa portion 60-3 may have a structure different from that of the first mesa portion 60-1.
  • the third mesa portion 60-3 may be sandwiched between the first mesa portions 60-1 in the X-axis direction.
  • three or more first gate trench portions 40-1 are not arranged consecutively in the X-axis direction.
  • FIG. 16 is a diagram showing another example of the f-f cross section.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 of the other examples in that it includes a bottom end region 204.
  • the structure other than the bottom end region 204 is the same as any of the semiconductor device 100 aspects described in this specification.
  • the lower end region 204 is an N-type region provided below the lower end 33 of the first dummy trench portion 30-1.
  • the doping concentration of the lower end region 204 is higher than the doping concentration of the drift region 18.
  • the doping concentration of the lower end region 204 may be at least twice, at least five times, or at least ten times the doping concentration of the drift region 18.
  • the doping concentration of the lower end region 204 may be higher or lower than the doping concentration of the floating region 202.
  • the bottom end region 204 may be in contact with the bottom end 33 of the first dummy trench portion 30-1, or may be separated from it.
  • the bottom end of the bottom end region 204 may be located above or below the bottom end of the floating region 202.
  • the bottom end region 204 may be in contact with the accumulation region 16, or may be separated from it.
  • FIG. 17 is a diagram showing another example of the e-e cross section.
  • the semiconductor device 100 of this example further includes a contact region 19 compared to the example shown in FIG. 3. Also, the arrangement of the contact portion 54 is different. The rest of the structure is the same as the example in FIG. 3.
  • the contact region 19 is provided in contact with the lower end of the contact portion 54, and is a P+ type region with a higher doping concentration than the base region 14.
  • the doping concentration of the contact region 19 may be the same as that of the contact region 15.
  • At least a part of the contact region 19 may be provided inside the base region 14.
  • the contact portion 54 in the transistor portion 70 may or may not be provided penetrating the emitter region 12. In this example, the contact region 19 in the transistor portion 70 is provided below the emitter region 12.
  • the entire contact region 19 in the diode portion 80 is provided inside the base region 14.
  • the contact region 19 may be provided at the same depth as in the e-e cross section. Furthermore, if an emitter region 12 is provided instead of the contact region 15, the f-f cross section will have the same structure as in FIG. 17.

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/JP2024/024939 2023-08-07 2024-07-10 半導体装置 Pending WO2025033084A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2025539221A JPWO2025033084A1 (https=) 2023-08-07 2024-07-10
CN202480008986.9A CN120604637A (zh) 2023-08-07 2024-07-10 半导体装置
DE112024000331.1T DE112024000331T5 (de) 2023-08-07 2024-07-10 Halbleitervorrichtung
US19/277,320 US20250351552A1 (en) 2023-08-07 2025-07-22 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2023128876 2023-08-07
JP2023-128876 2023-08-07

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US19/277,320 Continuation US20250351552A1 (en) 2023-08-07 2025-07-22 Semiconductor device

Publications (1)

Publication Number Publication Date
WO2025033084A1 true WO2025033084A1 (ja) 2025-02-13

Family

ID=94534034

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2024/024939 Pending WO2025033084A1 (ja) 2023-08-07 2024-07-10 半導体装置

Country Status (5)

Country Link
US (1) US20250351552A1 (https=)
JP (1) JPWO2025033084A1 (https=)
CN (1) CN120604637A (https=)
DE (1) DE112024000331T5 (https=)
WO (1) WO2025033084A1 (https=)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005142243A (ja) * 2003-11-05 2005-06-02 Toyota Motor Corp 絶縁ゲート型半導体装置およびその製造方法
JP2016162855A (ja) * 2015-02-27 2016-09-05 株式会社日立製作所 半導体装置およびそれを用いた電力変換装置
US20170243746A1 (en) * 2015-10-20 2017-08-24 Maxpower Semiconductor, Inc. Vertical power transistor with dual buffer regions
JP2019012762A (ja) * 2017-06-30 2019-01-24 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2019040954A (ja) * 2017-08-23 2019-03-14 トヨタ自動車株式会社 半導体装置
US20190157384A1 (en) * 2010-10-31 2019-05-23 Alpha And Omega Semiconductor Incorporated New dual-gate trench igbt with buried floating p-type shield
JP2019106529A (ja) * 2017-12-14 2019-06-27 富士電機株式会社 半導体装置
US20230135315A1 (en) * 2020-05-18 2023-05-04 China Resources Microelectronics (Chongqing) Co., Ltd. Semiconductor device and preparation method therefor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005142243A (ja) * 2003-11-05 2005-06-02 Toyota Motor Corp 絶縁ゲート型半導体装置およびその製造方法
US20190157384A1 (en) * 2010-10-31 2019-05-23 Alpha And Omega Semiconductor Incorporated New dual-gate trench igbt with buried floating p-type shield
JP2016162855A (ja) * 2015-02-27 2016-09-05 株式会社日立製作所 半導体装置およびそれを用いた電力変換装置
US20170243746A1 (en) * 2015-10-20 2017-08-24 Maxpower Semiconductor, Inc. Vertical power transistor with dual buffer regions
JP2019012762A (ja) * 2017-06-30 2019-01-24 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2019040954A (ja) * 2017-08-23 2019-03-14 トヨタ自動車株式会社 半導体装置
JP2019106529A (ja) * 2017-12-14 2019-06-27 富士電機株式会社 半導体装置
US20230135315A1 (en) * 2020-05-18 2023-05-04 China Resources Microelectronics (Chongqing) Co., Ltd. Semiconductor device and preparation method therefor

Also Published As

Publication number Publication date
US20250351552A1 (en) 2025-11-13
CN120604637A (zh) 2025-09-05
JPWO2025033084A1 (https=) 2025-02-13
DE112024000331T5 (de) 2025-11-06

Similar Documents

Publication Publication Date Title
JP7456520B2 (ja) 半導体装置
JP7497744B2 (ja) 半導体装置
CN111834440B (zh) 半导体装置
JP7468786B2 (ja) 半導体装置および製造方法
JP7658452B2 (ja) 半導体装置
JP7456113B2 (ja) 半導体装置
JP7613570B2 (ja) 半導体装置
US12471303B2 (en) Semiconductor device having an injection suppression region
JP7459976B2 (ja) 半導体装置
JP7593511B2 (ja) 半導体装置
US20230268342A1 (en) Semiconductor device
JP7670158B2 (ja) 半導体装置および半導体装置の製造方法
JP7666089B2 (ja) 半導体装置
CN115377098A (zh) 半导体装置
JP7704225B2 (ja) 半導体装置
JP7231064B2 (ja) 半導体装置
JP7683822B2 (ja) 半導体装置
JP7726385B2 (ja) 半導体装置および製造方法
WO2025033084A1 (ja) 半導体装置
WO2025033086A1 (ja) 半導体装置
JP7613576B2 (ja) 半導体装置
JP2024118696A (ja) 半導体装置および半導体装置の製造方法
JP2026023262A (ja) 半導体装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202480008986.9

Country of ref document: CN

ENP Entry into the national phase

Ref document number: 2025539221

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2025539221

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 112024000331

Country of ref document: DE

WWP Wipo information: published in national office

Ref document number: 202480008986.9

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 112024000331

Country of ref document: DE