WO2025013673A1 - Ｆｅｔ、電気機械器具、及び、ｆｅｔの製造方法 - Google Patents

Ｆｅｔ、電気機械器具、及び、ｆｅｔの製造方法 Download PDF

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WO2025013673A1
WO2025013673A1 PCT/JP2024/023734 JP2024023734W WO2025013673A1 WO 2025013673 A1 WO2025013673 A1 WO 2025013673A1 JP 2024023734 W JP2024023734 W JP 2024023734W WO 2025013673 A1 WO2025013673 A1 WO 2025013673A1
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semiconductor layer
gate
electrode
drain
source
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French (fr)
Japanese (ja)
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卓宏 山口
仁 梅沢
宏幸 川島
彰悟 伊藤
尚久 星川
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Ookuma Diamond Device Inc
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Ookuma Diamond Device Inc
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  • the present invention is based on the priority claim of Japanese Patent Application: Patent Application No. 2023-112565 (filed on July 7, 2023), the entire contents of which are incorporated herein by reference.
  • the present invention relates to a FET, an electrical device, and a method for manufacturing a FET.
  • One method for manufacturing diamond FETs is the self-alignment method described below (see, for example, Non-Patent Documents 1 to 3).
  • a diamond semiconductor layer e.g., a hydrogen-terminated diamond layer
  • an Au (gold) film is evaporated on the surface of the diamond semiconductor layer
  • a first resist is formed in the element region on the Au film, and using the first resist as a mask, the Au film is wet-etched until the diamond semiconductor layer is exposed, and the first resist is removed.
  • a second resist having an opening for forming a gate electrode and a source electrode/drain electrode is formed, and the Au film exposed from the opening of the second resist is wet-etched to form source electrode/drain electrode made of an Au film separated widely from the opening.
  • a gate electrode is formed by evaporation of metal on the diamond semiconductor layer exposed from the opening of the second resist, and then the second resist and the metal layer thereon are lifted off. This completes a MESFET (Metal Semiconductor Field Effect Transistor) type diamond FET.
  • MESFET Metal Semiconductor Field Effect Transistor
  • the self-aligned method allows the gate electrode to be positioned accurately relative to the source/drain electrodes, so even if the channel length or gate length is miniaturized to improve high-frequency characteristics, there is no alignment error, and diamond FETs can be manufactured stably, which is advantageous in maintaining a high yield.
  • the gate electrode is formed in the center between the source electrode and the drain electrode, so that the source-gate distance cannot be made smaller than the gate-drain distance in order to improve the high-frequency characteristics of the diamond FET.
  • the wet etching of the Au film when forming the source electrode/drain electrode proceeds symmetrically, and the gate electrode is formed in the center between the source electrode and the drain electrode when the gate electrode is subsequently formed.
  • the gate-drain distance is also reduced at the same time, and the source-gate resistance and the gate-drain resistance are reduced, limiting the high-voltage operating performance of the FET and making it impossible to achieve both high-frequency characteristics and high-voltage operation.
  • a diamond FET operating in the millimeter wave band is designed with a source-drain distance of 200 nm and a gate length of 100 nm, and is manufactured using the above-mentioned self-alignment method, the gate electrode will be formed in the center between the source and drain electrodes, and the source-gate distance and gate-drain distance will each be 50 nm.
  • the dielectric breakdown of the diamond semiconductor layer is designed to be 2 MV/cm, only 10 V can be applied to the 50 nm range. This makes operation under high voltages difficult, and ultimately limits the applicability as a power device. The same can be said for FETs other than diamond FETs.
  • the main objective of the present invention is to provide a FET, an electrical device, and a method for manufacturing a FET that can contribute to achieving both high-frequency characteristics and high-voltage operation while maintaining a high yield.
  • the FET according to the first aspect comprises a semiconductor layer, a source electrode and a drain electrode spaced apart on the semiconductor layer, and a gate electrode spaced apart from the source electrode and the drain electrode on the semiconductor layer between the source electrode and the drain electrode, the source-gate distance between the source electrode and the gate electrode on the upper surface of the semiconductor layer being different from the gate-drain distance between the gate electrode and the drain electrode on the upper surface of the semiconductor layer, and the gate electrode being configured to grow obliquely with respect to the upper surface of the semiconductor layer.
  • the electrical device according to the second aspect is equipped with the FET according to the first aspect.
  • the method for manufacturing a FET according to the third aspect includes the steps of forming a metal layer on a semiconductor layer, forming a resist having an opening on a portion of the metal layer, and wet-etching the metal layer exposed from the opening using the resist as a mask to form a source electrode and a drain electrode, and forming a gate electrode by depositing metal on the semiconductor layer through the opening, which is incident on the upper surface of the semiconductor layer from an oblique direction, using the resist as a mask.
  • the first to third aspects mentioned above can contribute to achieving both high frequency characteristics and high voltage operation while maintaining high yield.
  • FIG. 2 is a partial cross-sectional view showing a schematic example of the configuration of a diamond FET according to embodiment 1.
  • 1 is a partial cross-sectional view showing a schematic diagram of a first modified example of the configuration of a diamond FET according to embodiment 1.
  • FIG. 13 is a partial cross-sectional view showing a schematic diagram of a second modified example of the configuration of the diamond FET according to the first embodiment.
  • FIG. 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing a diamond FET according to the first embodiment.
  • 5A to 5C are cross-sectional process views following FIG. 4, which are schematic diagrams illustrating an example of a method for manufacturing a diamond FET according to the first embodiment.
  • FIG. 4 are schematic diagrams illustrating an example of a method for manufacturing a diamond FET according to the first embodiment.
  • FIG. 2 is a partial cross-sectional view showing a schematic state of the diamond FET according to embodiment 1 during the formation of a gate electrode.
  • 1 is a graph showing a relationship between the metal incidence angle to the upper surface of the diamond semiconductor layer of the diamond FET according to the first embodiment and the ratio of the source-gate distance/gate-drain distance.
  • 1 is a graph showing a relationship between the metal incidence angle with respect to the upper surface of the diamond semiconductor layer of the diamond FET according to the first embodiment and the maximum potential difference between the source and drain.
  • FIG. 11 is a partial cross-sectional view illustrating an example of the configuration of a FET according to a second embodiment.
  • FIG. 1 is a partial cross-sectional view showing an example of the configuration of the diamond FET according to the first embodiment.
  • FIG. 2 is a partial cross-sectional view showing a first modified example of the configuration of the diamond FET according to the first embodiment.
  • FIG. 3 is a partial cross-sectional view showing a second modified example of the configuration of the diamond FET according to the first embodiment. Note that the first embodiment will be described with the diamond FET as an example.
  • the diamond FET1 is a FET (field effect transistor) having a source electrode 12a, a drain electrode 12b, and a gate electrode 14a in the element region 2 on the diamond semiconductor layer 11 (hydrogen termination 11a in FIG. 1) (see FIG. 1).
  • the source-gate distance L SG between the source electrode 12a and the gate electrode 14a is configured to be smaller than the gate-drain distance L GD between the gate electrode 14a and the drain electrode 12b.
  • the diamond FET1 can be incorporated into electrical machinery and equipment such as semiconductor devices, power electronics devices, high-frequency devices, communication devices, sensing devices, automobiles, power transmission and distribution equipment, harsh environment devices, high-temperature environment devices, radiation environment devices, space equipment, and nuclear reactor equipment. Note that the diamond FET1 is an example, and the form 1 may be applied to a FET that does not use diamond.
  • a diamond semiconductor layer 11 is formed on a diamond substrate 10, with the upper surface ((001) surface) being a hydrogen termination 11a.
  • the hydrogen termination 11a is configured to be present in the element region 2 and not present outside the element region 2.
  • a source electrode 12a and a drain electrode 12b are disposed at intervals from each other and in ohmic contact with the hydrogen termination 11a.
  • a gate electrode 14a is disposed at intervals from each of the source electrode 12a and the drain electrode 12b and in Schottky contact with the hydrogen termination 11a.
  • the source-gate distance L SG between the source electrode 12a and the gate electrode 14a is smaller than the gate-drain distance L GD between the gate electrode 14a and the drain electrode 12b. That is, the gate electrode 14a is disposed at a position shifted from the center between the source electrode 12a and the drain electrode 12b toward the source electrode 12a.
  • the diamond FET 1 can be applied to a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a gate insulating film 13a between the gate electrode 14a and the hydrogen termination portion 11a as shown in FIG. 2, other than the MESFET as shown in FIG. 1, and can also be applied to a MIMSFET (Metal Insulator Metal Semiconductor Field Effect Transistor; not shown).
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • the diamond substrate 10 is a substrate made of a single crystal diamond (see FIG. 1).
  • a high-temperature, high-pressure synthetic single crystal diamond substrate can be used as the diamond substrate 10. It is preferable to use a diamond substrate 10 having a surface roughness (in accordance with ISO 4287) of 10 nm or less. If the surface roughness of the diamond substrate 10 exceeds 10 nm, it is preferable to polish the diamond substrate 10 so that the surface roughness is 10 nm or less. This has the advantage of reducing the surface roughness of the diamond semiconductor layer 11 synthesized on the diamond substrate 10 and improving the contact between the diamond semiconductor layer 11 and metals and insulating films.
  • the diamond semiconductor layer 11 is a layer (semiconductor layer) that includes diamond and has a portion that functions as a semiconductor (see FIG. 1).
  • the thickness of the diamond semiconductor layer 11 can be, for example, several ⁇ m or several tens of ⁇ m, but is not limited to this.
  • the diamond semiconductor layer 11 can be formed by chemical vapor deposition of diamond crystals (epitaxial diamond crystals) on the diamond substrate 10 using hydrogen and methane gas as raw materials, for example, using a microwave plasma CVD (Chemical Vapor Deposition) device.
  • the diamond semiconductor layer 11 formed in this manner has a hydrogen termination portion 11a on the (001) plane (upper surface).
  • the hydrogen termination portion 11a has a hole channel formed therein and exhibits p-type conduction.
  • the diamond semiconductor layer 11 is not limited to having a hydrogen termination portion 11a, but may have a portion containing (doped or implanted with) impurities (e.g., boron, phosphorus, etc.) in diamond.
  • a free-standing diamond film may be obtained by chemically vapor-depositing diamond crystals on a seed substrate using hydrogen and methane gas as raw materials using a microwave plasma CVD device, and then removing the seed substrate.
  • the source electrode 12a and the drain electrode 12b are electrodes made of a predetermined metal (see FIG. 1). For example, Au can be used for the source electrode 12a and the drain electrode 12b.
  • the source electrode 12a and the drain electrode 12b are formed on the diamond semiconductor layer 11. In order to ensure adhesion with the diamond semiconductor layer 11, it is preferable that the source electrode 12a and the drain electrode 12b are formed on the diamond semiconductor layer 11 in a state that has not been exposed to an etching agent, a resist stripper, or oxygen plasma for resist ashing.
  • the source electrode 12a and the drain electrode 12b are arranged so as to be in direct contact (ohmic contact) with the hydrogen termination portion 11a of the diamond semiconductor layer 11.
  • the source electrode 12a and the drain electrode 12b can be formed, for example, by forming a metal layer (for example, by vapor deposition or sputtering) on the diamond semiconductor layer 11, forming a resist for forming the source electrode/drain electrode on the metal layer, performing wet etching using the resist as a mask, and removing the resist.
  • the source-drain distance L SD which is the distance between the source electrode 12a and the drain electrode 12b, can be less than 200 nm, and is preferably less than 100 nm when operating in a high frequency band (for example, a cutoff frequency of 50 to 100 GHz).
  • the lower limit of the source-drain distance L SD is the limit distance at which the FET functions.
  • the source-drain distance L SD can be changed depending on the wet etching time.
  • the thickness of the source electrode 12a and the drain electrode 12b is preferably less than 100 nm when operating in a high frequency band, is preferably less than 50 nm when obtaining desired RF (Radio Frequency) characteristics, and is preferably less than 25 nm when operating in a higher frequency band (for example, a cutoff frequency of more than 100 GHz).
  • the lower limit of the thickness of the source electrode 12a and the drain electrode 12b is the critical film thickness (the same applies to other thicknesses for which no lower limit is specified).
  • the source electrode 12a and the drain electrode 12b may be directly in contact with the hydrogen termination 11a of the diamond semiconductor layer 11 as shown in FIG.
  • contact layers 15a and 15b may be disposed on the hydrogen termination 11a via contact layers 15a and 15b as shown in FIG. 3.
  • contact layers 15a and 15b for example, P+ diamond doped with B (boron) can be used.
  • the contact layers 15a and 15b can be formed on the diamond semiconductor layer 11 by, for example, hot filament CVD or microwave plasma CVD.
  • the B concentration can be, for example, 5 ⁇ 10 19 to 1 ⁇ 10 22 /cm 3.
  • the thickness of the contact layers 15a and 15b can be, for example, 20 to 300 nm.
  • reducing the distance of the LSD and thinning the source electrode 12a and the drain electrode 12b for that purpose are also effective methods.
  • the metal layer 12 is actually side-etched, and the LSD becomes large.
  • this effect naturally becomes larger as the thickness of the metal layer 12 becomes larger.
  • a fine structure with an LSD of less than 100 nm is required.
  • the thickness of the metal layer 12 less than 100 nm, it becomes easier to obtain the desired characteristics (e.g., RF characteristics).
  • the desired characteristics e.g., RF characteristics
  • making the LSD less than 50 nm is effective in fabricating elements for further high frequency regions.
  • the cutoff frequency fT which is an important index of high frequency characteristics, is generally proportional to the transconductance ( gm ).
  • the actually observed gm is inversely proportional to the L G.
  • the influence of R S gradually becomes impossible to ignore and eventually reaches a plateau due to the relationship (Equation 1 below) between the source-gate resistance R S when the intrinsic transconductance is g m0 .
  • the gate electrode 14a can be made of a metal film having a single layer structure of any of Al, Au, Ti, Mo, Cr, Ru, Cu, Pb, Zn, and Pt, or a laminated structure of any combination.
  • the gate electrode 14a is arranged so that the source-gate distance L SG is smaller than the gate-drain distance L GD .
  • Such a gate electrode 14a can be formed, for example, by forming a resist for forming a gate electrode on the diamond semiconductor layer 11, and using the resist as a mask, forming (depositing) a film of the metal for the gate electrode 14a, which is incident from an oblique direction (corresponding to the metal incidence angle ⁇ in FIG.
  • the resist for forming the gate electrode also serves as a resist for forming the source electrode/drain electrode, and after forming the source electrode 12a and the drain electrode 12b using the resist, the gate electrode 14a can be formed by a self-alignment method using the resist as it is.
  • the gate electrode 14a can be formed by forming a metal film for the gate electrode 14a on the diamond semiconductor layer 11, which is obliquely incident on the upper surface 11b of the diamond semiconductor layer 11 (for example, by deposition, sputtering, CVD, etc.), and then lifting off the resist and the metal film thereon.
  • the thickness of the gate electrode 14a can be 10 nm to 500 nm, and is preferably less than 100 nm in consideration of the size of the gate length L G.
  • the gate insulating film 13a can be, for example, an insulating film made of a single layer structure of any one of Al 2 O 3 , SiO 2 , HfO 2 , AlN, BN, Si 3 N 4 , SiON, Ta 2 O 5 , TiO 2 , WO 3 , CaF 2 , LaF 3 , and MgF 2 or a laminated structure of any combination.
  • the gate insulating film 13a can be formed, for example, in the above-mentioned method for forming the gate electrode 14a, by forming an insulating film for the gate insulating film 13a by a CVD method using a predetermined source gas before forming a metal film for the gate electrode 14a, and lifting off the insulating film between the resist and the metal film during lift-off.
  • the thickness of the gate insulating film 13a can be, for example, 5 nm to 100 nm.
  • a space for example, an air layer, a vacuum layer, an air gap, etc. may be used instead of the gate insulating film 13a.
  • the gate length L G which is the width of the gate electrode 14a, is preferably less than 100 nm in order to improve frequency characteristics (shorten the travel time of carriers traveling through the channel). In consideration of operating at a higher frequency band (for example, cutoff frequency over 100 GHz), it is preferably less than 60 nm, and in consideration of obtaining desired RF (Radio Frequency) characteristics, it is preferably less than 50 nm.
  • the lower limit of the gate length L G is the limit length that functions as a FET. In addition, the more the gate length L G is miniaturized, the lower the contact between the gate electrode 14a and the diamond semiconductor layer 11 becomes, and resistance components are generated or the element is easily broken and destroyed.
  • the passivation film can be made of an insulating material similar to that of the gate insulating film 13a , for example, an insulating film having a single layer structure of any of Al2O3, SiO2, HfO2, AlN, BN, Si3N4, SiON, Ta2O5 , TiO2 , WO3 , CaF2 , LaF3 , and MgF2 , or a laminate structure of any combination thereof, and in consideration of improving carrier mobility and processability, an insulating layer containing F (fluorine), for example, an insulating layer having a single layer structure of any of CaF2 , LaF3 , and MgF2, or a laminate structure of any combination thereof, can be used.
  • F fluorine
  • the thickness of the passivation film is preferably 100 nm or more, in consideration of ensuring the contact between the gate electrode 14a and the diamond semiconductor layer 11, and the contact between the source electrode 12a and the drain electrode 12b and the diamond semiconductor layer 11, and is preferably 300 nm or more, in consideration of the flatness or flat processability of the upper surface of the passivation film 15.
  • the ratio (L SG /L GD ) of the source-gate distance L SG to the gate-drain distance L GD on the upper surface 11b of the diamond semiconductor layer 11 can be less than 1 (less than 100% in percentage), and considering that it operates in a high frequency range, it is preferably 0.25 to 0.9.
  • the details of the ratio (L SG /L GD ) will be described later (see FIG. 7).
  • the gate electrode 14a is formed by depositing a metal film through an opening (corresponding to 21a in FIG. 5(D)) of a resist for forming a gate electrode (corresponding to 21 in FIG. 5(D)) from an oblique direction (corresponding to the metal incident direction 3 and metal incident angle ⁇ in FIG. 6) with respect to the upper surface 11b of the diamond semiconductor layer 11, so that the gate electrode 14a is configured to grow in an oblique direction with respect to the upper surface 11b of the diamond semiconductor layer 11.
  • the sidewall surface (the sidewall surface on the source electrode 12a side and the sidewall surface on the drain electrode 12b side) of the gate electrode 14a is configured to be displaced toward the drain electrode 12b as it moves away from the upper surface 11b of the diamond semiconductor layer 11 in the direction perpendicular thereto.
  • a gate electrode 14a can have a structure in which the metal extends obliquely along the metal incident direction 3 (at the metal incident angle ⁇ ), and in this case, the metal may have a structure in which multiple columns of fibrous metal extend obliquely.
  • the position and gate length of the gate electrode 14a between the source and drain on the top surface 11b of the diamond semiconductor layer 11 can be changed depending on the thickness of the resist for forming the gate electrode (corresponding to 21 in FIG. 5(D)), the width of the opening (corresponding to 21a in FIG. 5(D)), and the metal incidence direction (corresponding to 3 in FIG. 5(D) and the metal incidence angle ⁇ in FIG. 6) on the top surface 11b of the diamond semiconductor layer 11. Details of the metal incidence angle ⁇ will be described later (see FIG. 7 and FIG. 8).
  • Figures 4 and 5 are cross-sectional views showing the steps of a typical example of the manufacturing method of the diamond FET according to the first embodiment.
  • a diamond semiconductor layer 11 is formed on a diamond substrate 10 (see FIG. 4A).
  • the diamond semiconductor layer 11 can be formed by chemical vapor deposition of diamond crystals on the diamond substrate 10 using, for example, a microwave plasma CVD device with hydrogen and methane gases without added impurities as raw materials (volume ratio of methane to hydrogen is 0.5%).
  • the diamond semiconductor layer 11 formed in this way is hydrogen-terminated diamond having a hydrogen termination portion 11a on the (001) plane (upper surface).
  • the metal layer 12 is formed on the diamond semiconductor layer 11 (see FIG. 4(B)).
  • the metal layer 12 can be formed by depositing a predetermined metal (e.g., gold) on the diamond semiconductor layer 11, for example, by RF sputtering.
  • a resist 20 is formed to cover the element region 2 on the metal layer 12, and the metal layer 12 is etched using the resist 20 as a mask until the diamond semiconductor layer 11 is exposed (see FIG. 4(C)).
  • the resist 20 can be formed, for example, by a lithography method.
  • the metal layer 12 can be etched, for example, by using a wet etching agent.
  • the resist 20 is used as a mask to perform ozone treatment, selectively eliminating the hydrogen termination 11a in the diamond semiconductor layer 11 in the region other than the element region 2 (see FIG. 4(D)).
  • the region other than the element region 2 in the diamond semiconductor layer 11 (the region that has become the oxygen termination) becomes highly resistive, and the elements can be electrically insulated from each other.
  • the resist (20 in FIG. 4(D)) on the metal layer 12 is removed (see FIG. 5(A)).
  • the resist 20 can be removed, for example, with a resist remover or by ashing. After removing the resist 20, cleaning is performed.
  • a resist 21 having openings 21a for forming a gate electrode and a source electrode/drain electrode is formed on the diamond semiconductor layer 11 including the metal layer 12 (see FIG. 5B).
  • the resist 21 can be formed, for example, by a lithography method.
  • the metal layer (12 in FIG. 5B) exposed from the opening 21a is etched using the resist 21 as a mask, and the metal layer 12 is separated into the source electrode 12a and the drain electrode 12b by under-etching, and then the distance between the end faces of the source electrode 12a and the drain electrode 12b is made wider than the width of the opening 21a by side-etching (see FIG. 5C).
  • the metal layer 12 can be etched using, for example, a wet etching agent.
  • the metal for gate electrode 14a that is incident from the oblique direction (metal incident direction 3, corresponding to the metal incident angle ⁇ in FIG. 6) to the upper surface 11b of diamond semiconductor layer 11 is formed (deposited) on diamond semiconductor layer 11 through opening 21a (see FIG.
  • gate electrode 14a for example, the whole substrate is tilted so that the position of source electrode 12a is lower than the position of drain electrode 12b, and the metal for gate electrode 14a that is incident from the target directly above (metal incident direction 3) with respect to the horizontal plane is formed (deposited) on diamond semiconductor layer 11 through opening 21a by the self-alignment process that utilizes resist 21 as it is.At this time, the metal layer 14 that the metal for gate electrode 14a is formed (deposited) on resist 21 is also formed. As a result, a gate electrode 14a is formed in which the gate length is narrower than the width of the opening 21a and the source-gate distance (corresponding to LSG in FIG.
  • the substrate may be horizontally positioned and the target may be shifted from directly below the target in the horizontal direction to deposit the metal at an angle of incidence of less than 90°. Details of the metal incidence direction 3 will be described later (see FIG. 6).
  • the resist (21 in FIG. 5A) and the metal layer thereon (14 in FIG. 5A) are removed (see FIG. 1).
  • the resist 21 and the metal layer thereon 14 can be removed, for example, by lifting off using a resist remover. After removing the resist 21, cleaning is performed. Thereafter, depending on the size of the diamond FET 1, a passivation film (not shown) is formed, holes are drilled in the passivation film to form plugs or pads, and a multilayer wiring structure is formed as necessary.
  • FIG. 6 is a partial cross-sectional view showing a schematic state of the diamond FET according to form 1 during gate electrode formation.
  • FIG. 7 is a graph showing a schematic relationship between the metal incidence angle with respect to the top surface of the diamond semiconductor layer of the diamond FET according to form 1 and the fraction related to the source-gate distance/gate-drain distance.
  • FIG. 8 is a graph showing a schematic relationship between the metal incidence angle with respect to the top surface of the diamond semiconductor layer of the diamond FET according to form 1 and the maximum potential difference between the source and drain.
  • the metal incident direction 3 is the direction in which the metal is incident on the upper surface 11b of the diamond semiconductor layer 11, and corresponds to the metal incident angle ⁇ (see FIG. 6).
  • the metal incident angle ⁇ becomes smaller as it is tilted from the vertical direction (90°).
  • the metal incident angle ⁇ can be in the range of 80° or more and less than 90°, and the simulation of the fraction (L SG /L GD ) of the source-gate distance L SG to the gate-drain distance L GD on the upper surface 11b of the diamond semiconductor layer 11 in that range is less than 1 (less than 100% in percentage) as shown in FIG. 7.
  • the metal incident angle ⁇ By setting the metal incident angle ⁇ to less than 90°, there is an effect of reducing the source-gate distance L SG and expanding the gate-drain distance L GD .
  • the fraction (L SG /L GD ) and the shape of the gate electrode 14a change with the change in the metal incident angle ⁇ . It is preferable that the metal incident angle ⁇ is in the range of 82° or more and 88° or less.
  • the LSG is shorter than the LGD .
  • the method of the first embodiment can be applied to the case where the LSG is shorter than the LSG .
  • the specific value of the maximum potential difference between the gate and drain with respect to the metal incidence angle ⁇ varies depending on the value of each parameter.
  • the thickness of each of the source electrode 12a and the drain electrode 12b is 50 nm
  • the thickness of the resist 21 is 1000 nm
  • the gate length L G is 50 nm
  • the source-drain distance L SD is 200 nm
  • the maximum potential difference between the gate and drain with respect to the metal incidence angle ⁇ is simulated as shown in FIG. 8.
  • the metal incidence angle ⁇ is 90°
  • the maximum potential difference between the gate and drain is 15 V
  • the metal incidence angle ⁇ is reduced to 88°
  • the maximum potential difference between the gate and drain is 22.3 V.
  • the thickness of the resist 21 is the total thickness of the EB (Electron Beam) resist and the sacrificial layer (such as LOR (lift-off resist)). In many cases, the resist 21 is formed of multiple layers, and the horizontal size of each layer may also change.
  • the source-gate distance is L SG '
  • the gate length is L G '
  • the gate-drain distance is L GD '
  • ⁇ L SG
  • ⁇ L GD , then ⁇ L SG ⁇ ⁇ L GD , and therefore Lg ⁇ Lg', which is advantageous in improving element characteristics by shortening the gate length.
  • L SG /L GD is 0.4 to 0.8.
  • the gate electrode 14a is formed so as to grow obliquely with respect to the upper surface 11b of the diamond semiconductor layer 11 so that the source-gate distance LSG is different from the gate-drain distance LGD . Therefore, the gate electrode 14a can be formed close to the source electrode 12a by the self-alignment method, which contributes to achieving both high frequency characteristics and high voltage operation while maintaining a high yield.
  • FIG. 9 is a partial cross-sectional view showing a schematic example of the configuration of the FET according to the second embodiment.
  • the FET 30 includes a semiconductor layer 31, a source electrode 32a, a drain electrode 32b, and a gate electrode 33.
  • the source electrode 32a and the drain electrode 32b are disposed on the semiconductor layer 31 with a gap therebetween.
  • the gate electrode 33 is disposed between the source electrode 32a and the drain electrode 32b on the semiconductor layer 31 with a gap therebetween.
  • a source-gate distance L SG between the source electrode 32a and the gate electrode 33 on the upper surface 31b of the semiconductor layer 31 is different from a gate-drain distance L GD between the gate electrode 33 and the drain electrode 32b on the upper surface 31b of the semiconductor layer 31.
  • the gate electrode 33 is configured to grow in an oblique direction with respect to the upper surface 31b of the semiconductor layer 31.
  • the gate electrode 14a is formed so as to grow in a diagonal direction with respect to the upper surface 31b of the semiconductor layer 31 so that the source-gate distance LSG is different from the gate-drain distance LGD .
  • the gate electrode is configured to grow obliquely with respect to the upper surface of the semiconductor layer.
  • a sidewall surface of the gate electrode is configured to be displaced toward the drain electrode as it moves away from the upper surface of the semiconductor layer in a direction perpendicular to the upper surface; 2.
  • the FET of claim 1. [Appendix 3] the gate electrode has a structure in which a metal extends in the oblique direction relative to the upper surface of the semiconductor layer; 3. The FET of claim 1 or 2.
  • the oblique direction with respect to the upper surface of the semiconductor layer is a direction having an angle of 80° or more and less than 90° with respect to the upper surface of the semiconductor layer. 4.
  • a source-drain distance between the source electrode and the drain electrode is less than 200 nm.
  • the gate insulating film has a single layer structure of any one of Al2O3 , SiO2 , CaF2 , HfO2 , AlN, BN , Si3N4 , SiON , Ta2O5 , TiO2 , WO3 , LaF3 , and MgF2 , or a laminate structure of any combination thereof.
  • a method for manufacturing a FET comprising:
  • Diamond FET field-effect transistor
  • element region 3 metal incidence direction 10 diamond substrate 11 diamond semiconductor layer (semiconductor layer) 11a hydrogen termination portion 11b upper surface 12 metal layer 12a source electrode 12b drain electrode 13 insulating layer 13a gate insulating film 14 metal layer 14a gate electrode 15a, 15b contact layer 20, 21 resist 21a opening 30 FET 31 Semiconductor layer 31b Upper surface 32a Source electrode 32b Drain electrode 33 Gate electrode

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PCT/JP2024/023734 2023-07-07 2024-07-01 Ｆｅｔ、電気機械器具、及び、ｆｅｔの製造方法 Ceased WO2025013673A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07254618A (ja) * 1994-03-16 1995-10-03 Oki Electric Ind Co Ltd 半導体素子およびその製造方法
JPH09260398A (ja) * 1996-03-18 1997-10-03 Tokyo Gas Co Ltd 自己整合法による水素終端ダイヤモンドｆｅｔの製造方法
JP2009049143A (ja) * 2007-08-17 2009-03-05 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法、半導体装置及び電子機器
WO2014013728A1 (ja) * 2012-07-17 2014-01-23 出光興産株式会社 スパッタリングターゲット、酸化物半導体薄膜及びそれらの製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07254618A (ja) * 1994-03-16 1995-10-03 Oki Electric Ind Co Ltd 半導体素子およびその製造方法
JPH09260398A (ja) * 1996-03-18 1997-10-03 Tokyo Gas Co Ltd 自己整合法による水素終端ダイヤモンドｆｅｔの製造方法
JP2009049143A (ja) * 2007-08-17 2009-03-05 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法、半導体装置及び電子機器
WO2014013728A1 (ja) * 2012-07-17 2014-01-23 出光興産株式会社 スパッタリングターゲット、酸化物半導体薄膜及びそれらの製造方法

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