WO2025007410A1 - 晶体管的制备方法、晶体管阵列及电子设备 - Google Patents

晶体管的制备方法、晶体管阵列及电子设备 Download PDF

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WO2025007410A1
WO2025007410A1 PCT/CN2023/116816 CN2023116816W WO2025007410A1 WO 2025007410 A1 WO2025007410 A1 WO 2025007410A1 CN 2023116816 W CN2023116816 W CN 2023116816W WO 2025007410 A1 WO2025007410 A1 WO 2025007410A1
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film layer
silicon
silicon film
etching
transistor
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French (fr)
Inventor
董博闻
李辉辉
胡琪
李庚霏
王桂磊
赵超
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for manufacturing a transistor, a transistor array, and an electronic device.
  • the vertical gate-all-around (VGAA) transistor is a new type of semiconductor device. Compared with the planar GAA transistor, the vertical GAA transistor (VGAA) has a small projected area and is not limited in channel length.
  • the embodiments of the present application provide a method for manufacturing a transistor, a transistor array, and an electronic device, which can reduce the influence of capacitance between word lines.
  • the technical solution is as follows:
  • a method for preparing a transistor comprising:
  • first silicon film layer stacking a first silicon film layer, a germanium silicon film layer, and a second silicon film layer in sequence on a silicon substrate, wherein the first silicon film layer is adjacent to the silicon substrate;
  • a low dielectric material is deposited in the first etching groove, the second etching groove and on the second silicon film layer, and an air gap is formed by etching and depositing a silicon dielectric material on the top to isolate the gate material and obtain a vertical gate all-around transistor.
  • a low dielectric material is deposited in the first etched groove and the second etched groove and on the second silicon film layer, and an air gap is formed by etching and depositing a silicon dielectric material on the top to isolate the gate material and the second silicon film layer to obtain a vertical gate all-around transistor, comprising:
  • a silicon dielectric material is deposited on the second silicon film layer to obtain the vertical gate all-around transistor.
  • depositing a silicon dielectric material on the second silicon film layer to obtain the vertical gate all-around transistor includes:
  • the silicon dielectric material is deposited in the first etching groove and the second etching groove to obtain the vertical gate all-around transistor.
  • etching the silicon substrate, the first silicon film layer, the silicon germanium film layer and the second silicon film layer along the bit line direction to form a first etched groove includes:
  • Regions of the silicon substrate, the first silicon film layer, the silicon germanium film layer, and the second silicon film layer that are not covered by the first mask material are etched to form first etching grooves along the direction of the bit lines.
  • the step of filling the first etched groove with a metal material and annealing to generate a bit line includes:
  • the metal material is filled on the silicon dielectric material and annealed to generate a bit line, wherein adjacent bit lines are isolated by the silicon dielectric material.
  • etching the second silicon film layer and the silicon germanium film layer along the word line direction to form a second etched groove includes:
  • the regions of the second silicon film layer and the silicon germanium film layer that are not covered by the second mask material are etched to form second etching grooves along the direction of the word lines.
  • forming a plurality of columns of second mask material on the second silicon film layer along the word line direction includes:
  • the first etching groove is filled with an oxide material, and a plurality of columns of a second mask material are formed along the word line direction on the second silicon film layer filled with the oxide material.
  • the second mask material includes a mandrel material and a sidewall material distributed on both sides of the mandrel material;
  • the step of generating a channel based on the germanium silicon film layer comprises:
  • the silicon germanium film layer in the at least two silicon sub-pillars is removed and filled with oxide material to obtain the oxide material surrounding the epitaxial silicon material, and the epitaxial silicon material forms the channel of the transistor.
  • a transistor array is provided, wherein the transistor array includes a plurality of transistor units arranged in an array;
  • the transistor unit comprises a first source/drain, a channel, a second source/drain, and a normally closed contact which are vertically distributed in sequence, and the channel of the transistor unit is surrounded by a gate material;
  • the first sources/drains of the plurality of first transistor cells in the first queue are connected by coupling to a buried bit line;
  • the gate materials of the plurality of second transistor units in the second queue are connected, so that the word line is coupled to the plurality of second transistor units, wherein the first queue is a queue along the first array direction, and the second queue is a queue along the second array direction;
  • the surfaces of the transistor units between the plurality of the second queues are covered with a low dielectric material, the tops of the plurality of the second queues are covered with a silicon dielectric material, and air gaps are formed between the low dielectric materials.
  • an electronic device comprising a logic device, and the logic device comprises the transistor array as described in the above embodiment.
  • the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
  • a protective material is deposited between the ring gate and the top source/drain to prevent oxidation.
  • a high deposition rate and low step coverage dielectric is used to form an air gap between the word lines, thereby reducing the parasitic capacitance between the word lines, improving the device performance of the VGAA transistor, and reducing the preparation process. Complexity.
  • FIG1 is a schematic diagram of a vertical gate all-around transistor structure provided by one or more exemplary embodiments of the present application.
  • FIG2 is a flow chart of a method for manufacturing a VGAA transistor provided by an exemplary embodiment of the present application
  • FIG3 is a schematic diagram of a process preparation flow on a silicon substrate provided based on the embodiment shown in FIG2 ;
  • FIG4 is a schematic diagram of a process flow for forming a first mask material based on the embodiment shown in FIG2 ;
  • FIG6 is a schematic diagram of a process flow for preparing a bit line provided based on the embodiment shown in FIG2 ;
  • FIG8 is a schematic diagram of a process flow for forming a second mask material based on the embodiment shown in FIG2 ;
  • FIG9 is a flow chart of a method for manufacturing a VGAA transistor provided by another exemplary embodiment of the present application.
  • FIG11 is a schematic diagram of a process flow for selective epitaxy to generate epitaxial silicon material based on the embodiment shown in FIG9 ;
  • FIG12 is a schematic diagram of a process flow of mandrel etching provided based on the embodiment shown in FIG9 ;
  • FIG13 is a schematic diagram of a process flow for preparing oxide filling provided based on the embodiment shown in FIG9 ;
  • FIG14 is a schematic diagram of a process flow for preparing a word line based on the embodiment shown in FIG9 ;
  • FIG15 is a schematic diagram of a process flow for preparing a low dielectric material deposition provided based on the embodiment shown in FIG9 ;
  • FIG. 17 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application.
  • FIG. 18 is a schematic diagram of a process for forming a stacked structure according to one or more exemplary embodiments of the present application.
  • FIG. 20 is a schematic diagram of a process for forming a stacked structure according to another one or more exemplary embodiments of the present application.
  • FIG. 21 is a schematic diagram of a process of forming a stacked structure provided by one or more other exemplary embodiments of the present application.
  • a gate-all-around FET is a transistor structure in which the gate material wraps around the periphery of the channel. Compared with a planar GAA transistor, a vertical GAA transistor has a small projected area, an unlimited channel length, no contacted gate pitch (CGP) restrictions, good parasitic capacitance control, and is suitable for 3D integration.
  • CGP contacted gate pitch
  • a silicon film layer is provided as a source electrode, and a silicon nanocolumn perpendicular to the silicon film layer is formed on the silicon film layer.
  • a gate dielectric is deposited on the silicon nanocolumn and the silicon film layer, and a gate material is deposited on the surface of the gate dielectric.
  • the gate material is etched to cover the upper surface of the silicon nanocolumn, and the height of the silicon nanocolumn exceeds the coverage height of the gate material, and then an isolation layer is deposited to a height lower than the silicon nanocolumn.
  • a method for preparing a transistor is provided.
  • the method for preparing the transistor is mainly applied in a process for preparing a VGAA transistor.
  • a transistor array includes a plurality of transistor units arranged in an array; the transistor unit includes a first source/drain, a channel, a second source/drain, and a normally closed contact that are vertically distributed in sequence, and a gate material is wrapped around the channel of the transistor unit; the first source/drain of a plurality of first transistor units in a first queue is connected by coupling to a buried bit line; the gate materials of a plurality of second transistor units in a second queue are connected, so that a word line is coupled to a plurality of second transistor units, wherein the first queue is a queue along the first array direction, and the second queue is a queue along the second array direction; the surfaces of the transistor units between the plurality of second queues are covered with a low dielectric material, and the tops of the plurality of second queues are covered with a silicon dielectric material, and air gaps are formed between the low dielectric materials.
  • a transistor array 100 includes a plurality of transistor cells 110 .
  • Each transistor unit 110 is connected to a bit line (BL) 111 through a source/drain 113 and a word line (WL) 112 through a gate 114.
  • the gate 114 surrounds a channel 115, and a normally closed contact (NC) 116 contacts the source/drain 113.
  • the source/drain 113 is a heavily doped material, and the channel is a lightly doped material or an undoped material.
  • multiple transistor units 110 in the same column of the transistor array 100 are connected by coupling with the extended bit line 111; multiple transistor units 110 in the same row of the transistor array 100 are connected by coupling with the extended word line 112.
  • the word line WL112 is connected to the gate 114 as a gate line to turn on the transistor unit 110 ; the bit line BL111 is connected to the source/drain 113 as a data signal writing line.
  • the gate 114 surrounds the channel 115 .
  • the normally open contact or normally closed contact 116 refers to the natural state without any external effect (such as power on), at which time the normally open contact is disconnected and the normally closed contact 116 is connected.
  • the source/drain 113 of the transistor unit 110 is connected to the normally closed contact as an example for explanation. If the source is connected to the bit line 111, the drain is connected to the normally closed contact 116; if the drain is connected to the bit line 111, the source is connected to the normally closed contact 116.
  • the surfaces of the gate 114 and the source/drain 113 are covered with a low-dielectric (Low-K) material 40 to form an air layer for isolation.
  • Low-K low-dielectric
  • FIG2 is a flow chart of a method for preparing a VGAA transistor provided by an exemplary embodiment of the present application. As shown in FIG2 , the method includes the following steps.
  • Step 201 stacking a first silicon film layer, a germanium silicon film layer, and a second silicon film layer in sequence on a silicon substrate.
  • the first silicon film layer 11 is adjacent to the silicon substrate 00.
  • the silicon substrate may be properly doped to form a well.
  • the stacking sequence is to first deposit the first silicon film layer 11 on the silicon substrate 00 , deposit the silicon germanium film layer 12 on the first silicon film layer 11 , and then deposit the second silicon film layer 13 on the silicon germanium film layer 12 .
  • the first silicon film layer 11 and the second silicon film layer 13 are used as the source/drain in the transistor, and doping is performed during the in-situ growth process of the first silicon film layer 11 and the second silicon film layer 13.
  • the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 are deposited by in-situ growth, and the duration of the in-situ growth is controlled to control the thickness of the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13; and during the doping process, the ion implantation concentration of the first silicon film layer 11 and the second silicon film layer 13 is controlled.
  • a first silicon film layer 11 , a germanium silicon film layer 12 , and a second silicon film layer 13 are sequentially deposited on a silicon substrate 00 from bottom to top.
  • Step 202 etching along the bit line direction to form a first etched groove on the silicon substrate, the first silicon film layer, the germanium silicon film layer and the second silicon film layer, filling the first etched groove with metal material and annealing to generate a bit line.
  • multiple columns of first mask material 60 are formed on the second silicon film layer 13 along the bit line direction, and areas of the silicon substrate 00, the first silicon film layer 11, the germanium silicon film layer 12, and the second silicon film layer 13 that are not covered by the first mask material 60 are etched to form a first etching groove along the bit line direction.
  • photoresist is used as the first mask material 60, or other materials can be selected as the first mask material 60, and there is a certain etching selectivity ratio between the first mask material 60 and silicon and silicon germanium.
  • a self-aligned double patterning technology SADP
  • a self-aligned quadruple patterning technology SAQP
  • other self-aligned multiple patterning SAMP
  • SADP is used as an example for explanation in this embodiment.
  • SADP refers to the process of using non-photolithography process steps (thin film deposition, etching, etc.) to achieve spatial frequency doubling of the photolithography pattern after one photolithography is completed.
  • another photolithography and etching are used to remove the redundant pattern, thereby realizing the process of forming a patterned mask material.
  • a plurality of columns of first mask material 60 are formed on the second silicon film layer 13 along the bit line direction.
  • the etching rate of the silicon substrate 00, the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 is greater than the etching rate of the first mask material 60, so that the silicon substrate 00, the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 are etched while maintaining a small amount of sacrifice of the first mask material 60.
  • the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 are penetrated during the etching process, and the silicon substrate 00 with a partial thickness is etched by controlling the etching time, without penetrating the silicon substrate 00.
  • the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 are isolated by oxide.
  • the areas in the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 that are not covered by the first mask material 60 are etched to form candidate etching grooves along the bit line direction; oxide material 80 is deposited to cover the inner and outer surfaces of the candidate etching grooves with the oxide material 80, and the oxide material 80 is used to isolate the reaction between the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 and the metal material 20; on the basis of the candidate etching grooves, the areas in the silicon substrate 00 that are not covered by the first mask material 60 are etched to form a first etching groove along the bit line direction.
  • the areas in the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 that are not covered by the first mask material 60 are etched by controlling the etching time to obtain candidate etching grooves, and then an oxide material 80, such as silicon dioxide (SiO2), is deposited by atomic layer deposition (ALD).
  • the oxide material 80 covers the inner and outer surfaces of the candidate etching grooves, and the oxide and silicon substrate 00 are continuously etched.
  • the silicon substrate 00 with a preset thickness requirement is etched to obtain a first etching groove.
  • a metal material 20, such as tungsten (W) material is deposited at the bottom of the first etched groove, and the silicon substrate 00 is annealed to form a metal silicide as a bit line through annealing.
  • Annealing refers to the process of diffusing metal into the silicon substrate 00 through ohmic contact to form a metal silicide.
  • a silicon dielectric material 50 with a first height is firstly filled in the first etched groove.
  • the silicon dielectric material 50 can be implemented as a nitride material or an oxide material, which is not limited in this embodiment. Taking the nitride material as an example, the silicon dielectric material 50 can be implemented as silicon nitride (SiN), and the first height is less than the depth of the first etched groove in the silicon substrate 00.
  • the metal material 20 is filled on the silicon dielectric material 50 and annealed to generate a bit line, wherein adjacent bit lines are isolated by the silicon dielectric material 50.
  • atomic layer deposition ALD or chemical vapor deposition (Chemical Vapor Deposition) is used.
  • the silicon dielectric material 50 is deposited by CVD and polished, and then the silicon dielectric material 50 is etched to a first height by controlling the etching time.
  • the etching rate of the silicon dielectric material 50 is greater than the etching rate of the first mask material 60.
  • the silicon dielectric material 50 is filled in the first etched groove and ground flat, and then the silicon dielectric material 50 of a first height in the first etched groove is retained by etching, and the first height is less than the depth of the first etched groove of the silicon substrate 00, that is, the upper plane of the silicon dielectric material 50 after etching is below the upper plane of the silicon substrate 00.
  • the metal material 20 is deposited on the silicon dielectric material 50, a metal silicide is generated as a bit line by annealing.
  • excess metal material 20 is removed by wet etching.
  • Step 203 etching the second silicon film layer and the silicon germanium film layer along the word line direction to form a second etched groove, and after generating a channel based on the silicon germanium film layer, filling the second etched groove along the word line direction with a gate material to generate a word line.
  • a plurality of columns of second mask material 70 are formed on the second silicon film layer 13 along the word line direction, and the areas of the second silicon film layer 13 and the silicon germanium film layer 12 not covered by the second mask material 70 are etched to form second etching grooves along the word line direction.
  • the silicon dielectric material 50 can be filled after etching away the oxide, or the silicon dielectric material 50 can be directly filled without removing the oxide, which is not limited in this embodiment.
  • the silicon dielectric material 50 is used as an etching stop line when etching along the word line direction, that is, when the second silicon film layer 13 and the germanium silicon film layer 12 are etched along the word line direction, the etching time is controlled until the upper surface of the silicon dielectric material 50 is etched and the etching is stopped.
  • the oxide material 80 is continuously deposited on the silicon dielectric material 50 to a height exceeding the second silicon film layer 13 and then ground flat.
  • a plurality of columns of the second mask material 70 are formed on the oxide and the second silicon film layer 13, and the areas of the second silicon film layer 13, the silicon germanium film layer 12, and the oxide material 80 that are not covered by the second mask material 70 are etched to form a second etched groove along the word line direction.
  • the silicon dielectric material 50 is filled in the first etching groove to a level higher than the second silicon film layer 13 and then ground by ALD/CVD/furnace method, and the ground silicon dielectric material 50 is etched until the upper plane corresponding to the silicon dielectric material 50 is flush with the contact surface of the first silicon film layer 11 and the germanium silicon film layer 12.
  • the oxide material 80 is continuously deposited on the silicon dielectric material 50 to a level higher than the second silicon film layer 13 and then ground flat, and multiple rows of the second mask material 70 are formed on the oxide material 80 and the second silicon film layer 13 by SADP or SAQP.
  • the second silicon film layer 13, the silicon germanium film layer 12, and the area of the oxide material 80 not covered by the second mask material 70 are etched to form a second etched groove, wherein the etching rate of the second silicon film layer 13, the silicon germanium film layer 12, and the oxide material 80 is greater than the etching rate of the second mask material 70.
  • the second silicon film layer 13 , the germanium silicon film layer 12 , and the oxide material 80 are etched by dry etching or wet etching.
  • Step 204 depositing low dielectric material in the first etching groove, the second etching groove and on the first silicon film layer, and forming an air gap by etching and depositing silicon dielectric material on the top to isolate the gate material and obtain a vertical gate all-around transistor.
  • a low dielectric material is deposited to isolate the gate material to protect the word line and S/D.
  • the gate material includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, or includes conductive materials such as polysilicon, tantalum, aluminum, and tungsten.
  • an air gap with a dielectric constant of approximately 1 is used as the dielectric layer of the word line to reduce the parasitic capacitance between the word lines and improve the performance of the transistor in high-speed application scenarios.
  • R represents resistance
  • C represents capacitance
  • V represents voltage
  • f current frequency
  • a low dielectric material between the gate materials after depositing a low dielectric material between the gate materials, a portion of the low dielectric material is etched, and a silicon dielectric material is deposited on top, thereby forming an air gap between the gate materials, and the gate material is isolated by the low dielectric material and the air gap.
  • a low dielectric (Low-K) material is deposited on the surface of the ring gate and the upper source/drain to isolate the word line and reduce the K value between the word lines, that is, reduce the capacitance between the word lines, thereby improving the performance of the transistor.
  • Low-K low dielectric
  • a low dielectric material 40 is deposited in the first etching groove, the second etching groove and on the first silicon film layer 11; the low dielectric material 40 on the surface of the first silicon film layer 11 and the second silicon film layer 13 is etched, and part of the low dielectric material 40 between the gate material 30 is etched; and a silicon dielectric material 50 is deposited on the second silicon film layer 13 to obtain a vertical gate full-surround transistor.
  • the method provided in this embodiment after laying out the bit line, word line, source/drain and ring gate of the transistor, removes the high dielectric constant dielectric between the word lines, and deposits a layer of protective material between the ring gate and the top source/drain to avoid oxidation, and finally forms an air gap between the word lines through a high deposition rate and low step coverage dielectric, thereby reducing the parasitic capacitance between the word lines, improving the device performance of the VGAA transistor, and reducing the preparation complexity.
  • the method provided in this embodiment through the sequential stacking of a silicon substrate, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer, based on the first silicon film layer and the second silicon film layer as the source/drain, on the basis of forming a bit line on the silicon substrate through a first mask material, and forming a channel and a word line and a ring gate through a second mask material, thereby improving the alignment between the bit line, the channel, the source/drain, the word line and the ring gate, improving the preparation accuracy and success rate of the VGAA transistor, improving the device performance of the VGAA transistor, and reducing the preparation complexity.
  • the second mask material 70 includes a mandrel material 71 and spacer materials 72 distributed on both sides of the mandrel material 71, and a channel of the transistor is generated based on the mandrel material 71 and the spacer materials 72 distributed on both sides of the mandrel material 71.
  • FIG9 is a flow chart of a method for preparing a transistor provided by another exemplary embodiment of the present application. As shown in FIG9, the above steps 203 to 204 can also be implemented as the following steps 901 to 908.
  • Step 901 performing lateral etching of a first thickness on the surface of the silicon germanium film layer on the silicon pillars obtained by etching the first etching groove and the second etching groove.
  • the surface of the germanium silicon film layer 12 is laterally etched to a first thickness on the silicon pillar by lateral atomic layer etching (ALE) or lateral wet etching or lateral dry etching.
  • ALE lateral atomic layer etching
  • the germanium silicon film layer 12 is firstly etched separately by lateral ALE, wherein during the etching process, there is a certain selectivity between the etching of the second silicon film layer 13 and the germanium silicon film layer 12, so that the etching rate of the germanium silicon film layer 12 is greater than the etching rate of the second silicon film layer 13. Then, the second silicon film layer 13 and the germanium silicon film layer 12 are etched by silicon etching to achieve etching of the first thickness on the surface of the germanium silicon film layer 12.
  • the second thickness is smaller than the first thickness.
  • Epitaxial silicon material 90 is generated on the silicon pillar and silicon dielectric material 50 by epitaxy; the epitaxial silicon material 90 on the surface of the second silicon film layer 13 and the silicon dielectric material 50 is annealed to obtain epitaxial silicon material 90 of a second thickness generated on the surface of the silicon germanium film layer 12.
  • the process growth rate of the epitaxial silicon material is selective, that is, the epitaxial silicon rate on the silicon pillar and the surface of the silicon germanium material is faster, and the rate on the dielectric material is very low, so the main epitaxial silicon exists on the silicon pillar and the silicon germanium material.
  • intrinsic silicon i.e., epitaxial silicon material 90
  • epitaxial silicon material 90 is generated on the surface of the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 by selective epitaxy.
  • the selective epitaxy is to generate epitaxial silicon material 90 by reacting the precursor adsorbed on the silicon/silicon germanium material after depositing the precursor, while other materials will not adsorb the precursor, so epitaxial silicon material 90 will not be generated.
  • epitaxial silicon material 90 is generated on the surfaces of the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 by selective epitaxy, and after the epitaxial silicon material 90 on the surfaces of the first silicon film layer 11 and the second silicon film layer 13 is diffused by annealing, the epitaxial silicon material 90 on the surface of the silicon germanium film layer 12 is retained to obtain the epitaxial silicon material 90 of the second thickness on the surface of the silicon germanium film layer 12. As shown in FIG11, the second thickness is less than the first thickness.
  • Step 903 etching the portions of the second silicon film layer and the silicon germanium film layer covered by the mandrel material to split the silicon column into at least two sub-silicon columns.
  • the mandrel material 71 and the spacer material 72 correspond to a certain etching selectivity ratio, so that during the etching process of the mandrel material 71 , only a small amount of sacrificial etching occurs on the spacer material 72 .
  • the oxide material 80 is first filled between the silicon pillars, and the oxide material 80 not covered by the second mask material 70 is etched, and then the silicon dielectric material 50 is filled between the silicon pillars. It is worth noting that the silicon dielectric material 50 can be filled on the basis of etching the oxide material 80, or can be filled directly, or can be directly filled with the silicon dielectric material 50 without filling the oxide material 80, which is not limited in this embodiment.
  • the second silicon film layer 13 and the silicon germanium film layer 12 are etched, and the portions covered by the mandrel material 71 are etched, thereby exposing the second silicon film layer 13 and the silicon germanium film layer 12 on the etched side surfaces of the sub-silicon pillars.
  • Step 904 removing the silicon germanium film layer in at least two sub-silicon pillars, and filling with oxide material to obtain oxide material surrounding the epitaxial silicon material.
  • the germanium silicon film layer 12 on one side of the channel is exposed, and the other side of the channel is the oxide material 80. Therefore, the germanium silicon film layer 12 is etched and filled with the oxide material 80, so that the oxide material 80 can surround the epitaxial silicon material 90 and use the epitaxial silicon material 90 as a channel.
  • the germanium silicon film layer 12 in the sub-silicon pillars is removed by lateral etching, and the etched area between the sub-silicon pillars is filled with oxide material 80, and the oxide material 80 not covered by the side wall material 72 is etched, thereby obtaining the oxide material 80 surrounding the epitaxial silicon material 90.
  • Step 905 Fill the second etched groove with a silicon dielectric material.
  • the spacer material 72 after etching the spacer material 72 , the area between the sub-silicon pillars that is not filled with the silicon dielectric material 50 is filled with the silicon dielectric material 50 to a level higher than the second silicon film layer 13 and then ground flat.
  • the oxide material 80 retained in the structure is etched by wet etching, and the oxide is replaced by the gate material 30 by utilizing the selectivity between oxide and nitride.
  • the first height range corresponds to the height range of the second silicon film layer 13 , that is, the gate material 30 on the surface of the source/drain is removed by etching, and the gate material 30 on the surface of the channel is retained.
  • the silicon dielectric material 50 is filled between each sub-silicon pillar, and after etching the oxide material 80 on the sub-silicon pillar, the gate material 30 is generated along the word line direction, and the gate material 30 in the height range corresponding to the second silicon film layer 13 is etched, and the gate material 30 in the height range corresponding to the channel is retained.
  • silicon dielectric material 50 is filled between each silicon sub-pillar, so the silicon dielectric material 50 between each silicon sub-pillar is first etched, and then low dielectric material 40 is deposited on the surface of the silicon sub-pillar.
  • the metal material 20 is used as a normally closed contact, so the low dielectric material 40 on the upper surface is etched and removed to expose the upper surface of the source/drain, and the metal material 20 is deposited on the silicon pillar to contact the second silicon film layer 13, and the silicon dielectric material 50 is filled to form an air gap, and a vertical surrounding gate transistor is obtained.
  • the silicon dielectric material 50 between each sub-silicon pillar is first etched, and then the low dielectric material 40 is deposited on the surface of the sub-silicon pillar.
  • the upper layer of the low dielectric material 40 is etched to expose the upper layer of the source/drain.
  • the metal material 20 is deposited on the silicon pillar to contact the second silicon film layer 13. After filling the silicon dielectric material 50, a vertical surround gate transistor is obtained.
  • the method provided in this embodiment after laying out the bit line, word line, source/drain and ring gate of the transistor, removes the high dielectric constant dielectric between the word lines, and deposits a layer of protective material between the ring gate and the top source/drain to avoid oxidation, and finally forms an air gap between the word lines through a high deposition rate and low step coverage dielectric, thereby reducing the parasitic capacitance between the word lines, improving the device performance of the VGAA transistor, and reducing the preparation complexity.
  • the method provided in this embodiment through the sequential stacking of a silicon substrate, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer, based on the first silicon film layer and the second silicon film layer as the source/drain, on the basis of forming a bit line on the silicon substrate through a first mask material, and forming a channel and a word line and a ring gate through a second mask material, thereby improving the alignment between the bit line, the channel, the source/drain, the word line and the ring gate, improving the preparation accuracy and success rate of the VGAA transistor, improving the device performance of the VGAA transistor, and reducing the preparation complexity.
  • the method provided in this embodiment is based on the epitaxial VGAA transistor process flow, generates epitaxial silicon material as a channel and fills the gate material to surround it, thereby improving the alignment between the channel and the word line and the gate and improving the process accuracy.
  • the method provided in this embodiment utilizes oxide to perform a self-aligned replacement metal gate process, thereby improving the accuracy of generating gate materials.
  • step 201 when executing step 201 , well isolation is also formed in the stack structure.
  • part (A1) of FIG16 shows a stacked structure after forming well isolation.
  • Part (A2) of FIG16 shows a two-dimensional plan view of the stacked structure.
  • the silicon substrate 00 includes an upper silicon substrate 00-1 and a lower silicon substrate 00-2.
  • the lower silicon substrate 00-2 is doped to N type
  • the upper silicon substrate 00-1 is doped to P type
  • the first silicon film layer 11 is doped to P type.
  • the lower silicon substrate 00-2 is doped to P type
  • the upper silicon substrate 00-1 is doped to N type
  • the first silicon film layer 11 is doped to N type.
  • part (B1) of FIG. 16 shows the three-dimensional structure of the plurality of first silicon pillars 1601 obtained after considering the well isolation.
  • Part (B2) of FIG. 16 shows the plane view corresponding to the three-dimensional structure.
  • the etching depth of the longitudinal etching of the first silicon pillars 1601 only reaches the upper part of the silicon substrate 00-1, and the plurality of first silicon pillars 1601 (i.e., the bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 1601.
  • part (A1) of FIG. 17 shows a stacked structure after forming well isolation.
  • Part (A2) of FIG. 17 shows a two-dimensional plan view of the stacked structure.
  • the stacked structure after well isolation includes a silicon substrate 00, a first silicon film layer 11, a silicon germanium film layer 12, a second silicon film layer 13, and a third silicon film layer 14 located between the silicon substrate 00 and the first silicon film layer.
  • the silicon substrate 00 is doped to a P type
  • the first silicon film layer 11 and the third silicon film layer 14 are doped to a P type.
  • Doped to N type Doped to
  • part (B1) of FIG. 17 shows the three-dimensional structure of the plurality of first silicon pillars 1601 obtained after considering the well isolation.
  • Part (B2) of FIG. 17 shows the plane view corresponding to the three-dimensional structure.
  • the etching depth of the longitudinal etching of the first silicon pillars 1601 only reaches the third silicon film layer 14, and the plurality of first silicon pillars 1601 (i.e., the bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 1601.
  • step 201 Illustratively, the following four possible implementations are provided for the above step 201.
  • a first possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into N-type, and dope the upper part of the silicon substrate into P-type; sequentially stack a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the first silicon film layer into P-type.
  • an annealing operation is performed to restore the silicon substrate lattice.
  • FIG18 (A) shows a silicon substrate 00;
  • FIG18 (B) shows a lower silicon substrate 00-1 doped with N-type and an upper silicon substrate 00-2 doped with P-type.
  • FIG18 (C) shows a first silicon film layer 11, a germanium silicon film layer 12, and a second silicon film layer 13 stacked, wherein the first silicon film layer 11 is doped with P-type.
  • a second possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into P type, and dope the upper part of the silicon substrate into N type; sequentially stack a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the first silicon film layer into N type.
  • an annealing operation is performed to restore the silicon substrate lattice.
  • FIG. 19 (A) shows a silicon substrate 00;
  • FIG. 19 (B) shows a lower silicon substrate 00-1 doped with P type and an upper silicon substrate 00-2 doped with N type.
  • FIG. 19 (C) shows a first silicon film layer 11, a germanium silicon film layer 12, and a second silicon film layer 13 stacked, wherein the first silicon film layer 11 is doped with N type.
  • a third possible implementation method is to obtain a silicon substrate; dope the silicon substrate to N-type; sequentially stack a third silicon layer, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the third silicon layer and the first silicon film layer to P-type.
  • FIG20 (A) shows a silicon substrate 00
  • FIG20 (B) shows a silicon substrate 00 doped to N type
  • FIG20 (C) shows a third silicon film layer 14, a first silicon film layer 11, a germanium silicon film layer 12, and a second silicon film layer 13 stacked, wherein the third silicon film layer 14 is doped to P type, and the first silicon film layer 11 is doped to P type.
  • a fourth possible implementation method is to obtain a silicon substrate; dope the silicon substrate into P type; sequentially stack a third silicon film layer, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the third silicon film layer and the first silicon film layer into N type.
  • FIG21 (A) shows a silicon substrate 00
  • FIG21 (B) shows a silicon substrate 00 doped to P type
  • FIG21 (C) shows a third silicon film layer 14, a first silicon film layer 11, a germanium silicon film layer 12, and a second silicon film layer 13 stacked, wherein the third silicon film layer 14 is doped to N type, and the first silicon film layer 11 is doped to N type.
  • the embodiment of the present application provides an electronic device, which includes a logic device, and the logic device includes a transistor array as provided in the above embodiment.
  • the logic device can be applied to a logic operator and a memory, etc.
  • the transistor array is prepared by the process preparation method of the transistor provided in the above embodiment.
  • the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.
  • at least one refers to one or more
  • plural refers to two or more, unless otherwise expressly limited.
  • the term “and/or” in this application is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and/or B may represent: A exists alone, A and B exist at the same time, and B exists alone.
  • the character "/" in this article generally indicates that the previously associated objects are in an "or” relationship.

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Abstract

一种晶体管的制备方法，包括：在硅衬底（00）上依次堆叠第一硅膜层（11）、锗硅膜层（12）和第二硅膜层（13）；沿位线方向刻蚀硅衬底（00）、第一硅膜层（11）、锗硅膜层（12）和第二硅膜层（13）形成第一刻蚀槽，用金属材料（20）填充第一刻蚀槽并退火生成位线；沿字线方向刻蚀第二硅膜层（13）、锗硅膜层（12）形成第二刻蚀槽，并基于锗硅膜层（12）生成沟道后，用栅极材料（30）填充第二刻蚀槽形成字线；在第一刻蚀槽、第二刻蚀槽内和第二硅膜层（13）上沉积Low-K材料（40），并通过刻蚀Low-K材料（40）和在顶部沉积硅介质材料（50）形成空气间隙，对栅极材料（30）进行隔离，得到垂直栅极全环绕晶体管。还公开一种晶体管阵列、电子设备。

Description

晶体管的制备方法、晶体管阵列及电子设备
本申请要求于2023年07月06日提交的申请号为202310827613.1、发明名称为“晶体管的制备方法、晶体管阵列及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，特别涉及一种晶体管的制备方法、晶体管阵列及电子设备。
背景技术
垂直栅极全环绕(Vertical Gate-All-Around，VGAA)晶体管是一种新型半导体器件，相对平面GAA晶体管，垂直GAA晶体管(VGAA)投影面积小，且沟道长度不受限。
相关技术中，VGAA晶体管阵列中，字线和字线之间的隔离介质影响了字线之间的电容。通常绝缘介质的介电常数k值越高，则字线之间的寄生电容C越高，从而导致晶体管阵列电路的电阻电容延迟(RC delay)越大。
发明内容
本申请实施例提供了一种晶体管的制备方法、晶体管阵列及电子设备，能够降低字线之间产生电容影响的情况。所述技术方案如下：
一方面，提供了一种晶体管的制备方法，所述方法包括：
在硅衬底上依次堆叠第一硅膜层、锗硅膜层和第二硅膜层，其中，所述第一硅膜层与所述硅衬底相邻；
在所述硅衬底、所述第一硅膜层、所述锗硅膜层和所述第二硅膜层上沿位线方向刻蚀形成第一刻蚀槽，在所述第一刻蚀槽内填充金属材料并退火生成位线；
在所述第二硅膜层、所述锗硅膜层上沿字线方向刻蚀形成第二刻蚀槽，并基于所述锗硅膜层生成沟道后，在所述第二刻蚀槽内沿所述字线方向填充栅极材料生成字线；
在所述第一刻蚀槽、所述第二刻蚀槽内和所述第二硅膜层上沉积低介电材料，并通过刻蚀和在顶部沉积硅介质材料形成空气间隙，对所述栅极材料进行隔离，得到垂直栅极全环绕晶体管。
在一个可选的实施例中，所述在所述第一刻蚀槽和所述第二刻蚀槽内和所述第二硅膜层上沉积低介电材料，并通过刻蚀和在顶部沉积硅介质材料形成空气间隙，对所述栅极材料和所述第二硅膜层进行隔离，得到垂直栅极全环绕晶体管，包括：
在所述第一刻蚀槽和所述第二刻蚀槽内和所述第二硅膜层上沉积所述低介电材料；
刻蚀所述第一硅膜层和所述第二硅膜层表面的所述低介电材料，以及刻蚀所述栅极材料之间的部分低介电材料；
在所述第二硅膜层上沉积硅介质材料，得到所述垂直栅极全环绕晶体管。
在一个可选的实施例中，所述在所述第二硅膜层上沉积硅介质材料，得到所述垂直栅极全环绕晶体管，包括：
在所述第二硅膜层上沉积金属材料与所述第二硅膜层接触；
在所述第一刻蚀槽和所述第二刻蚀槽内沉积所述硅介质材料，得到所述垂直栅极全环绕晶体管。
在一个可选的实施例中，所述在所述硅衬底、所述第一硅膜层、所述锗硅膜层和所述第二硅膜层上沿位线方向刻蚀形成第一刻蚀槽，包括：
在所述第二硅膜层上沿所述位线方向形成多列第一掩膜材料；
刻蚀所述硅衬底、所述第一硅膜层、所述锗硅膜层和所述第二硅膜层中未被所述第一掩膜材料覆盖的区域，形成沿所述位线方向的第一刻蚀槽。
在一个可选的实施例中，所述在所述第一刻蚀槽内填充金属材料并退火生成位线，包括：
在所述第一刻蚀槽内填充得到第一高度的所述硅介质材料，其中，所述第一高度小于所述硅衬底中所述第一刻蚀槽的深度；
在所述硅介质材料上填充所述金属材料并退火生成位线，其中，相邻位线之间通过所述硅介质材料隔离。
在一个可选的实施例中，所述在所述第二硅膜层、所述锗硅膜层上沿字线方向刻蚀形成第二刻蚀槽，包括：
在所述第二硅膜层上沿字线方向形成多列第二掩膜材料；
刻蚀所述第二硅膜层、锗硅膜层中未被所述第二掩膜材料覆盖的区域，形成沿所述字线方向的第二刻蚀槽。
在一个可选的实施例中，所述在所述第二硅膜层上沿字线方向形成多列第二掩膜材料，包括：
在所述第一刻蚀槽内填充得到第二高度的所述硅介质材料，其中，所述第二高度的硅介质材料的上平面与所述第一硅膜层的上平面符合平面距离要求；
在所述第一刻蚀槽内填充氧化物材料，并在填充所述氧化物材料后的第二硅膜层上沿所述字线方向形成多列第二掩膜材料。
在一个可选的实施例中，所述第二掩膜材料包括心轴材料和分布在所述心轴材料两侧的侧墙材料；
所述基于所述锗硅膜层生成沟道，包括：
在所述第一刻蚀槽和所述第二刻蚀槽刻蚀得到的硅柱上，对所述锗硅膜层的表面进行第一厚度的侧向刻蚀；
在所述锗硅膜层被刻蚀的表面生成第二厚度的外延硅材料，所述第二厚度小于所述第一厚度；
在所述第二硅膜层和所述锗硅膜层对被所述心轴材料覆盖的部分进行刻蚀，将所述硅柱拆分为至少两个子硅柱；
对所述至少两个子硅柱中的锗硅膜层去除，并填充氧化物材料，得到围绕所述外延硅材料的氧化物材料，所述外延硅材料形成所述晶体管的沟道。
另一方面，提供了一种晶体管阵列，所述晶体管阵列中包括呈阵列排布的多个晶体管单元；
所述晶体管单元包括垂直依次分布的第一源/漏、沟道、第二源/漏、常闭触点，所述晶体管单元的沟道外环绕包覆栅极材料；
在第一队列中的多个第一晶体管单元的第一源/漏通过耦接埋入式位线连通；
在第二队列中的多个第二晶体管单元的栅极材料连通，得到字线与多个第二晶体管单元耦接，其中，第一队列是沿第一阵列方向的队列，第二队列是沿第二阵列方向的队列；
多个所述第二队列之间所述晶体管单元表面覆盖有低介电材料，多个所述第二队列顶部覆盖有硅介质材料，所述低介电材料之间形成有空气间隙。
另一方面，提供了一种电子设备，所述电子设备中包括逻辑器件，所述逻辑器件中包括如上述实施例中所述的晶体管阵列。
在一个可选的实施例中，所述电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或智能移动终端。
本申请实施例提供的技术方案带来的有益效果至少包括：
在铺设完成晶体管的位线、字线、源极/漏极和环栅后，通过在环栅和顶部源极/漏极之间沉积覆盖一层保护材料避免氧化，最后通过高沉积速率、低台阶覆盖性介质以形成字线之间的空气间隙，降低了字线之间的寄生电容，提高了VGAA晶体管的器件性能，并降低了制备 复杂度。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一个或多个示例性实施例提供的垂直栅极全环绕晶体管结构示意图；
图2是本申请一个示例性实施例提供的VGAA晶体管的制备方法的流程图；
图3是基于图2示出的实施例提供的硅衬底上的工艺制备流程的示意图；
图4是基于图2示出的实施例提供的第一掩膜材料形成的工艺制备流程的示意图；
图5是基于图2示出的实施例提供的第一刻蚀槽的工艺制备流程的示意图；
图6是基于图2示出的实施例提供的位线的工艺制备流程的示意图；
图7是基于图2示出的实施例提供的第二掩膜材料形成的工艺制备流程的示意图；
图8是基于图2示出的实施例提供的第二掩膜材料形成的工艺制备流程的示意图；
图9是本申请另一个示例性实施例提供的VGAA晶体管的制备方法的流程图；
图10是基于图9示出的实施例提供的对锗硅膜层进行侧向刻蚀的工艺制备流程的示意图；
图11是基于图9示出的实施例提供的选择性外延生成外延硅材料的工艺制备流程的示意图；
图12是基于图9示出的实施例提供的心轴刻蚀的工艺制备流程的示意图；
图13是基于图9示出的实施例提供的氧化物填充的工艺制备流程的示意图；
图14是基于图9示出的实施例提供的字线的工艺制备流程的示意图；
图15是基于图9示出的实施例提供的低介电材料沉积的工艺制备流程的示意图；
图16是本申请一个或多个示例性实施例提供的堆叠结构的示意图；
图17是本申请一个或多个示例性实施例提供的堆叠结构的示意图；
图18是本申请一个或多个示例性实施例提供的堆叠结构的形成过程的示意图；
图19是本申请另一个或多个示例性实施例提供的堆叠结构的形成过程的示意图；
图20是本申请另一个或多个示例性实施例提供的堆叠结构的形成过程的示意图；
图21是本申请另一个或多个示例性实施例提供的堆叠结构的形成过程的示意图。
硅衬底-00；
第一硅膜层-11，锗硅膜层-12，第二硅膜层-13；
金属材料-20，栅极材料-30，低介电材料-40；
硅介质材料-50，第一掩膜材料-60，第二掩膜材料-70；
氧化物材料-80，外延硅材料-90；
心轴材料-71，侧墙材料-72。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
全环绕栅极晶体管(Gate-All-Around FET)是指栅极材料在沟道外围环绕包裹的晶体管结构。相对平面GAA晶体管，垂直GAA晶体管的投影面积小，沟道长度不受限，没有接触栅极间距(Contacted Gate Pitch，CGP)限制，寄生电容控制好，适合3D集成。
相关技术中，在制作VGAA晶体管时，通常包括如下过程：
首先，提供硅膜层作为源极，并在硅膜层上形成垂直硅膜层的硅纳米柱，在硅膜层上沉积隔离层后，在硅纳米柱和硅膜层上沉积栅极介质，以及在栅极介质表面沉积栅极材料。刻 蚀栅极材料在硅纳米柱上表面的覆盖，并使硅纳米柱的高度超出栅极材料的覆盖高度，然后沉积隔离层至低于硅纳米柱的高度。在硅纳米柱上沉积硅作为漏极后，设置源极与下层的源极硅膜层接触，设置漏极与上层沉积的漏极硅接触，设置环栅材料沿着字线接触。
然而上述方式中，在设置位线、字线等材料时，无法确保位线、源漏区域、栅极区域、沟道等位置的准确对准。
本申请实施例中，提供了一种晶体管的制备方法，可选地，该晶体管的制备方法主要应用于VGAA晶体管的制备过程中。
首先对本申请实施例中，VGAA晶体管的结构进行介绍。
本申请实施例中，提供了一种晶体管阵列。晶体管阵列中包括呈阵列排布的多个晶体管单元；晶体管单元包括垂直依次分布的第一源/漏、沟道、第二源/漏、常闭触点，晶体管单元的沟道外环绕包覆栅极材料；在第一队列中的多个第一晶体管单元的第一源/漏通过耦接埋入式位线连通；在第二队列中的多个第二晶体管单元的栅极材料连通，得到字线与多个第二晶体管单元耦接，其中，第一队列是沿第一阵列方向的队列，第二队列是沿第二阵列方向的队列；多个第二队列之间晶体管单元表面覆盖有低介电材料，多个第二队列顶部覆盖有硅介质材料，在低介电材料之间形成有空气间隙。
如图1所示，在晶体管阵列100中包括多个晶体管单元110。
每个晶体管单元110通过源极/漏极113连接位线(Bit Line，BL)111、通过栅极114连接字线(Word Line，WL)112，栅极114环绕沟道115、常闭触点(Normal Contact，NC)116与源极/漏极113接触。其中，源极/漏极113为重掺杂材料，沟道为轻掺杂材料或者不掺杂材料。
其中，晶体管阵列100中在同一列的多个晶体管单元110通过与延伸的位线111耦接，对同一列的多个晶体管单元110进行连通；晶体管阵列100中在同一行的多个晶体管单元110通过与延伸的字线112耦接，对同一行的多个晶体管单元110进行连通。
其中，字线WL112连接栅极114，作为栅线开启晶体管单元110；位线BL111连接源极/漏极113，作为数据信号写入线。栅极114在沟道115外围环绕包裹。
常开触点或者常闭触点116是指在没有任何外部作用下的自然状态(比如通电)，这时候的常开触点就是断开的，常闭触点116就是接通的，本申请实施例中，以晶体管单元110的源极/漏极113连接常闭触点为例进行说明。其中，若与位线111连接的是源极，则与常闭触点116连接的是漏极；若与位线111连接的是漏极，则与常闭触点116连接的是源极。
本申请实施例中，栅极114和源极/漏极113表面覆盖有低介电(Low-K)材料40形成空气夹层进行隔离。
结合上述对VGAA晶体管的介绍，图2是本申请一个示例性实施例提供的VGAA晶体管的制备方法的流程图，如图2所示，该方法包括如下步骤。
步骤201，在硅衬底上依次堆叠第一硅膜层、锗硅膜层和第二硅膜层。
其中，第一硅膜层11与硅衬底00相邻。可选地，硅衬底可以适当掺杂以便形成阱。
也即，堆叠顺序为首先在硅衬底00上沉积第一硅膜层11，在第一硅膜层11上沉积锗硅膜层12，再在锗硅膜层12上沉积第二硅膜层13。
其中，第一硅膜层11和第二硅膜层13是用于作为晶体管中的源极/漏极，在第一硅膜层11和第二硅膜层13的原位生长过程中进行掺杂(doping)。其中，通过原位生长的方式沉积第一硅膜层11、锗硅膜层12和第二硅膜层13，控制原位生长的时长从而控制第一硅膜层11、锗硅膜层12和第二硅膜层13的厚度；以及在掺杂过程中，控制第一硅膜层11和第二硅膜层13的离子注入浓度。
示意性的，如图3所示，在硅衬底00上由下到上依次沉积有第一硅膜层11、锗硅膜层12和第二硅膜层13。
步骤202，在硅衬底、第一硅膜层、锗硅膜层和第二硅膜层上沿位线方向刻蚀形成第一刻蚀槽，在第一刻蚀槽内填充金属材料并退火生成位线。
在一些实施例中，在第二硅膜层13上沿位线方向形成多列第一掩膜材料60，并刻蚀硅衬底00、第一硅膜层11、锗硅膜层12和第二硅膜层13中未被第一掩膜材料60覆盖的区域，形成沿位线方向的第一刻蚀槽。
在一些实施例中，将光刻胶(Photoresist，PR)作为第一掩膜材料60，或者，也可以选择其他材料作为第一掩膜材料60，第一掩膜材料60与硅和锗硅之间存在一定的刻蚀选择比。可选地，采用自对准双重图案化技术(Self-aligned Double Patterning，SADP)或者自对准四重图案化技术(Self-aligned Quattuor Patterning，SAQP)或者其他自对准多重图案化(Self-aligned Multiple Patterning，SAMP)技术，在第一硅膜层11上形成多列第一掩膜材料60。
其中，本实施例中以SADP为例进行说明。SADP是指在一次光刻完成后，相继使用非光刻工艺步骤(薄膜沉积、刻蚀等)实现对光刻图形的空间倍频。最后，使用另外一次光刻和刻蚀把多余的图形去掉，从而所实现图案化掩膜材料形成的过程。在一些实施例中，SADP的过程包括：提供待刻蚀材料层；在待刻蚀材料层上形成牺牲光刻胶层；将牺牲光刻胶层中顶部和侧壁的光刻胶进行固化形成固化光刻胶外壳；对牺牲光刻胶层顶部的固化光刻胶外壳进行回刻，直到暴露出未固化的内部牺牲光刻胶层，位于内部牺牲光刻胶层侧壁的固化光刻胶外壳形成第一掩膜材料60的图形；去除未固化的内部牺牲光刻胶层，得到形成在第一硅膜层11上的多列第一掩膜材料60。
示意性的，如图4所示，在第二硅膜层13上沿位线方向形成多列第一掩膜材料60。
在一些实施例中，在刻蚀硅衬底00、第一硅膜层11、锗硅膜层12和第二硅膜层13中未被第一掩膜材料60覆盖的区域时，硅衬底00、第一硅膜层11、锗硅膜层12和第二硅膜层13的刻蚀速率大于第一掩膜材料60的刻蚀速率，从而在保持第一掩膜材料60少量牺牲的情况下，对硅衬底00、第一硅膜层11、锗硅膜层12和第二硅膜层13进行刻蚀。其中，第一硅膜层11、锗硅膜层12和第二硅膜层13在刻蚀的过程中被穿透，而通过控制刻蚀时长刻蚀部分厚度的硅衬底00，而不将硅衬底00穿透刻蚀。
在一些实施例中，为了避免第一硅膜层11、锗硅膜层12和第二硅膜层13在生成位线的过程中受到金属材料20的影响，通过氧化物对第一硅膜层11、锗硅膜层12和第二硅膜层13进行隔离。
可选地，首先刻蚀第一硅膜层11、锗硅膜层12和第二硅膜层13中未被第一掩膜材料60覆盖的区域，形成沿位线方向的候选刻蚀槽；沉积氧化物材料80，将氧化物材料80覆盖候选刻蚀槽的内表面和外表面，氧化物材料80用于隔离第一硅膜层11、锗硅膜层12和第二硅膜层13与金属材料20之间的反应；在候选刻蚀槽的基础上刻蚀硅衬底00中未被第一掩膜材料60覆盖的区域，形成沿位线方向的第一刻蚀槽。
示意性的，如图5所示，首先通过控制刻蚀时长对第一硅膜层11、锗硅膜层12和第二硅膜层13中未被第一掩膜材料60覆盖的区域进行刻蚀，得到候选刻蚀槽，然后通过原子层沉积(Atomic Layer Deposition，ALD)的方式沉积氧化物材料80，如：二氧化硅(SiO2)，该氧化物材料80覆盖候选刻蚀槽的内表面和外表面，继续对氧化物和硅衬底00进行刻蚀，通过控制刻蚀时长，对预设厚度要求的硅衬底00进行刻蚀，得到第一刻蚀槽。
在一些实施例中，在第一刻蚀槽底部沉积金属材料20，如：钨(W)材料，并通过退火处理，将硅衬底00退火为金属硅化物(silicide)作为位线。其中，退火是指通过欧姆接触将金属扩散到硅衬底00中形成金属硅化物的过程。
在一些实施例中，首先在第一刻蚀槽内填充第一高度的硅介质材料50，在一些实施例中，该硅介质材料50可以实现为氮化物材料或者氧化物材料，本实施例对此不加以限定。以氮化物材料为例进行说明，该硅介质材料50可以实现如：氮化硅(SiN)，第一高度小于硅衬底00中第一刻蚀槽的深度，在硅介质材料50上填充金属材料20并退火生成位线，其中，相邻位线之间通过硅介质材料50隔离。
可选地，在第一刻蚀槽内通过原子层沉积ALD或者化学气相沉积法(Chemical Vapor  Deposition，CVD)沉积硅介质材料50并磨平，再通过控制刻蚀时长将硅介质材料50刻蚀至第一高度。其中，硅介质材料50的刻蚀速率大于第一掩膜材料60的刻蚀速率。
示意性的，如图6所示，首先在第一刻蚀槽内填充硅介质材料50并磨平，再通过刻蚀保留第一刻蚀槽内第一高度的硅介质材料50，第一高度小于硅衬底00部分第一刻蚀槽的深度，也即，刻蚀后硅介质材料50的上平面在硅衬底00上平面以下。在硅介质材料50上沉积金属材料20后，通过退火生成金属硅化物作为位线。
可选地，多余的金属材料20通过湿法刻蚀进行去除。
步骤203，在第二硅膜层、锗硅膜层上沿字线方向刻蚀形成第二刻蚀槽，并基于锗硅膜层生成沟道后，在第二刻蚀槽内沿字线方向填充栅极材料生成字线。
在第二硅膜层13上沿字线方向形成多列第二掩膜材料70，并刻蚀第二硅膜层13、锗硅膜层12中未被第二掩膜材料70覆盖的区域，形成沿字线方向的第二刻蚀槽。
在一些实施例中，首先将第一掩膜材料60刻蚀清除后，在第二硅膜层13上形成第二掩膜材料70。
可选地，第二掩膜材料70用于控制字线生成方向，在沿字线方向形成第二掩膜材料70后，对第二硅膜层13和锗硅膜层12进行刻蚀，在一些实施例中，刻蚀时长控制在锗硅膜层12被刻蚀，而第一硅膜层11未被刻蚀或者刻蚀较少。
在一些实施例中，在第一刻蚀槽内填充得到第二高度的所述硅介质材料50，其中，第二高度的硅介质材料50的上平面与第一硅膜层11的上平面符合平面距离要求，如：硅介质材料50的上平面与第一硅膜层11的上平面在同一平面或者距离小于距离阈值。在第一刻蚀槽内填充氧化物材料80，并在填充氧化物材料80后的第一硅膜层11上沿字线方向形成多列第二掩膜材料70。
在一些实施例中，在第一刻蚀槽内填充得到第二高度的所述硅介质材料50时，首先填充超出第二硅膜层13高度的硅介质材料50，并做磨平处理，在通过控制刻蚀时长，将硅介质材料50刻蚀至第二高度。
在一些实施例中，由于在上述步骤202中在第一硅膜层11、锗硅膜层12和第二硅膜层13表面沉积有氧化物，可选地，可以在刻蚀清除氧化物后填充硅介质材料50，也可以在不清除氧化物的基础上直接填充硅介质材料50，本实施例对此不加以限定。
其中，硅介质材料50的是为了作为沿字线方向刻蚀时，刻蚀的停止线，也即，在沿字线方向对第二硅膜层13和锗硅膜层12进行刻蚀时，控制刻蚀时长直至刻蚀到硅介质材料50的上表面时，停止刻蚀。
在一些实施例中，在沉积第二高度的硅介质材料50后，在硅介质材料50上继续沉积氧化物材料80，至超出第二硅膜层13的高度并磨平。在氧化物和第二硅膜层13上形成多列第二掩膜材料70，并刻蚀第二硅膜层13、锗硅膜层12、氧化物材料80中未被第二掩膜材料70覆盖的区域，形成沿字线方向的第二刻蚀槽。
示意性的，如图7所示，在生成字线后，通过ALD/CVD/熔炉法(furnace)等方式在第一刻蚀槽内填充硅介质材料50至高于第二硅膜层13并磨平，对磨平后的硅介质材料50进行刻蚀，直至硅介质材料50对应的上平面与第一硅膜层11和锗硅膜层12接触面持平。
如图8所示，在硅介质材料50上继续沉积氧化物材料80至高于第二硅膜层13并磨平，并在氧化物材料80和第二硅膜层13上通过SADP或者SAQP形成多列第二掩膜材料70。在第二掩膜材料70的基础上对第二硅膜层13、锗硅膜层12、氧化物材料80中未被第二掩膜材料70覆盖的区域进行刻蚀，形成第二刻蚀槽，其中，第二硅膜层13、锗硅膜层12、氧化物材料80的刻蚀速率大于第二掩膜材料70的刻蚀速率。
在一些实施例中，通过干法刻蚀或者湿法刻蚀等方式对第二硅膜层13、锗硅膜层12、氧化物材料80进行刻蚀。
在一些实施例中，基于第二掩膜材料70在锗硅膜层12生成沟道后，在第二刻蚀槽内填充栅极材料30(Metal Gate)，得到环绕沟道的栅极以及生成字线，得到垂直全环绕栅极晶体 管。
步骤204，在第一刻蚀槽、第二刻蚀槽内和第一硅膜层上沉积低介电材料，并通过刻蚀和在顶部沉积硅介质材料形成空气间隙，对栅极材料进行隔离，得到垂直栅极全环绕晶体管。
在一些实施例中，去除字线周围的高K值介质后，沉积低介电材料对栅极材料进行隔离，保护字线和S/D。可选地，栅极材料包括氧化硅、氮化硅、氮氧化硅、氧化铝、氧化铪、氧化锆等介质材料，或者包括多晶硅，钽、铝、钨等导电材料。
为了降低高速读写情形下电路的阻容迟滞(RC delay，正比于R×C)和能量消耗(C×V×2f)，采用介电常数约为1的空气间隙(air gap)作为字线的介质层，降低字线之间的寄生电容，提高晶体管的高速应用场景下的性能。其中，R表示电阻，C表示电容，V表示电压，f表示电流频率。然而，由于金属与空气接触易发生氧化影响字线的性能，故，本申请实施例中，在栅极材料之间沉积低介电材料后，刻蚀部分低介电材料，并在顶部沉积硅介质材料，从而在栅极材料之间形成空气间隙，通过低介电材料和空气间隙对栅极材料进行隔离。
本申请实施例中，在设置位线、字线、环栅、源极/漏极后，在环栅和上层源极/漏极表面沉积低介电(Low-K)材料，对字线进行隔离，降低字线之间的K值，也即降低字线之间的电容量，从而提高了晶体管的性能表现。
可选地，在第一刻蚀槽、第二刻蚀槽内和第一硅膜层11上沉积低介电材料40；刻蚀第一硅膜层11和第二硅膜层13表面的低介电材料40，以及刻蚀栅极材料30之间的部分低介电材料40；在第二硅膜层13上沉积硅介质材料50，得到垂直栅极全环绕晶体管。
可选地，在第二硅膜层13上沉积金属材料20与第二硅膜层13接触；在第一刻蚀槽和第二刻蚀槽内沉积硅介质材料50，得到垂直栅极全环绕晶体管。
综上所述，本实施例提供的方法，在铺设完成晶体管的位线、字线、源极/漏极和环栅后，通过去除字线之间的高介电常数的介质，同时在环栅和顶部源极/漏极之间沉积覆盖一层保护材料避免氧化，最后通过高沉积速率、低台阶覆盖性介质以形成字线之间的空气间隙，降低了字线之间的寄生电容，提高了VGAA晶体管的器件性能，并降低了制备复杂度。
本实施例提供的方法，通过依次堆叠的硅衬底、第一硅膜层、锗硅膜层和第二硅膜层，基于第一硅膜层和第二硅膜层作为源极/漏极，通过第一掩膜材料在硅衬底上形成位线的基础上，通过第二掩膜材料形成沟道和字线以及环栅，提高了位线、沟道、源极/漏极以及字线和环栅之间的对准度，提高了VGAA晶体管的制备准确率和成功率，提高了VGAA晶体管的器件性能，并降低了制备复杂度。
在一些实施例中，第二掩膜材料70包括心轴材料71和分布在心轴材料71两侧的侧墙材料72，基于心轴材料71和分布在心轴材料71两侧的侧墙材料72生成晶体管的沟道。图9是本申请另一个示例性实施例提供的晶体管的制备方法的流程图，如图9所示，上述步骤203至步骤204还可以实现为如下步骤901至步骤908。
步骤901，在第一刻蚀槽和第二刻蚀槽刻蚀得到的硅柱上，对锗硅膜层的表面进行第一厚度的侧向刻蚀。
在一些实施例中，通过侧向(lateral)原子层刻蚀工艺(Atomic Layer Etching，ALE)或者侧向湿法刻蚀或者侧向干法刻蚀等方式，在硅柱上对锗硅膜层12表面进行第一厚度的侧向刻蚀。
在一些实施例中，首先通过lateral ALE单独对锗硅膜层12进行初步的刻蚀，其中，在该刻蚀过程中，第二硅膜层13和锗硅膜层12的刻蚀存在一定的选择比，从而锗硅膜层12的刻蚀速率大于第二硅膜层13的刻蚀速率。再通过硅刻蚀对第二硅膜层13和锗硅膜层12进行刻蚀，实现对锗硅膜层12表面进行第一厚度的刻蚀。
示意性的，如图10所示，通过侧向刻蚀，对硅柱中的锗硅膜层12的表面进行一个初步的刻蚀。在通过硅刻蚀对第二硅膜层13、锗硅膜层12进行刻蚀，实现对锗硅膜层12表面的第一厚度的刻蚀。
步骤902，在锗硅膜层被刻蚀的表面生成第二厚度的外延硅材料。
其中，第二厚度小于第一厚度。
在硅柱上和硅介质材料50上外延生成外延硅材料90；对第二硅膜层13和硅介质材料50表面的外延硅材料90进行退火，得到在锗硅膜层12表面生成的第二厚度的外延硅材料90。外延硅材料的过程生长速率存在选择性，即硅柱和锗硅材料表面外延硅速率较快，介质材料上速率非常低，因此主要的外延硅存在于硅柱和锗硅材料上。
在一些实施例中，通过选择性外延在第一硅膜层11、锗硅膜层12和第二硅膜层13表面生成本征硅，也即外延硅材料90。其中，选择性外延是通过沉积前驱物后，通过前驱物吸附在硅/锗硅材料上反应，生成外延硅材料90，而其他材料对该前驱物不会进行吸附，故也不会生成外延硅材料90。通过控制前驱物的吸附量或者外延生长的时长，在第一硅膜层11、锗硅膜层12和第二硅膜层13表面生成外延硅材料90，其中，锗硅膜层12表面生成第二厚度的外延硅材料90，通过退火处理将第一硅膜层11和第二硅膜层13表面的外延硅材料90扩散至硅材料中，与源极/漏极化为一体，保留在锗硅膜层12表面生成的外延硅材料90。
示意性的，如图11所示，通过选择性外延，在第一硅膜层11、锗硅膜层12和第二硅膜层13表面生成外延硅材料90，通过退火扩散第一硅膜层11和第二硅膜层13表面的外延硅材料90后，保留锗硅膜层12表面的外延硅材料90，得到在锗硅膜层12表面的第二厚度的外延硅材料90。如图11可知，第二厚度小于第一厚度。
其中，外延硅材料90形成晶体管的沟道。
步骤903，对第二硅膜层和锗硅膜层被心轴材料覆盖的部分进行刻蚀，将硅柱拆分为至少两个子硅柱。
在一些实施例中，心轴材料71和侧墙材料72对应一定的刻蚀选择比，从而在刻蚀心轴材料71的过程中，侧墙材料72仅存在少量的牺牲刻蚀。
可选地，首先在硅柱之间填充氧化物材料80，并刻蚀未被第二掩膜材料70覆盖的氧化物材料80，然后再硅柱之间填充硅介质材料50。值得注意的是，硅介质材料50可以在刻蚀氧化物材料80的基础上填充，也可以直接填充，还可以不填充氧化物材料80而直接填充硅介质材料50，本实施例对此不加以限定。
在填充硅介质材料50后，刻蚀第二硅膜层13和锗硅膜层12中被心轴材料71覆盖的部分，从而暴露出子硅柱被刻蚀侧表面的第二硅膜层13和锗硅膜层12。
示意性的，如图12所示，首先在硅柱之间填充氧化物材料80，并刻蚀未被第二掩膜材料70覆盖的氧化物材料80，再填充硅介质材料50，并刻蚀被心轴材料71覆盖的第二硅膜层13和锗硅膜层12。
步骤904，去除至少两个子硅柱中的锗硅膜层，并填充氧化物材料，得到围绕外延硅材料的氧化物材料。
由于心轴材料71被刻蚀后，存在沟道一侧的锗硅膜层12被暴露，而沟道另一侧为氧化物材料80，故，刻蚀锗硅膜层12并填充氧化物材料80，从而氧化物材料80能够包围外延硅材料90，将外延硅材料90作为沟道。
示意性的，如图13所示，在刻蚀被心轴材料71覆盖的第二硅膜层13和锗硅膜层12后，通过侧向刻蚀清除子硅柱中的锗硅膜层12，并在子硅柱之间被刻蚀的区域填充氧化物材料80，并刻蚀未被侧墙材料72覆盖的氧化物材料80，从而得到围绕外延硅材料90的氧化物材料80。
步骤905，在第二刻蚀槽内填充硅介质材料。
在一些实施例中，刻蚀侧墙材料72进行刻蚀后，在子硅柱之间未填充硅介质材料50的区域填充硅介质材料50至高于第二硅膜层13并磨平。
步骤906，刻蚀氧化物材料并沿第二刻蚀槽的方向填充栅极材料。
在一些实施例中，通过湿法刻蚀的方式对结构中保留的氧化物材料80进行刻蚀，并利用氧化物和氮化物之间的选择比，将氧化物替换为栅极材料30。
步骤907，刻蚀在第一高度范围内的栅极材料，保留在第二高度范围内的栅极材料。
其中，第一高度范围与第二硅膜层13的高度范围对应，也即，刻蚀清除在源极/漏极表面的栅极材料30，保留在沟道表面的栅极材料30。
示意性的，如图14所示，刻蚀侧墙材料72以及与侧墙材料72在同一高度范围的硅介质材料50后，在各个子硅柱之间填充硅介质材料50，刻蚀子硅柱上的氧化物材料80后，沿字线方向生成栅极材料30，并刻蚀与第二硅膜层13对应高度范围内的栅极材料30，保留与沟道对应高度范围内的栅极材料30。
步骤908，在第一刻蚀槽、第二刻蚀槽内和第二硅膜层上沉积低介电材料，刻蚀栅极材料之间的部分低介电材料，并在顶部沉积硅介质材料形成空气间隙对栅极材料进行隔离，得到垂直栅极全环绕晶体管。
在一些实施例中，各个子硅柱之间填充有硅介质材料50，故首先刻蚀各个子硅柱之间的硅介质材料50，然后在子硅柱表面沉积低介电材料40。可选地，在沉积低介电材料40后，由于上层源极/漏极还需要与金属材料20接触，将金属材料20作为常闭触点，故，将上表面的低介电材料40进行刻蚀去除，露出源极/漏极的上表面，并在硅柱上沉积金属材料20与第二硅膜层13接触，填充硅介质材料50形成空气间隙(air gap)后，得到垂直环绕栅极晶体管。
如图15所示，首先刻蚀各个子硅柱之间的硅介质材料50，然后在子硅柱表面沉积低介电材料40，将上层的低介电材料40刻蚀后露出上层的源极/漏极，然后在硅柱上沉积金属材料20与第二硅膜层13接触，填充硅介质材料50后，得到垂直环绕栅极晶体管。
综上所述，本实施例提供的方法，在铺设完成晶体管的位线、字线、源极/漏极和环栅后，通过去除字线之间的高介电常数的介质，同时在环栅和顶部源极/漏极之间沉积覆盖一层保护材料避免氧化，最后通过高沉积速率、低台阶覆盖性介质以形成字线之间的空气间隙，降低了字线之间的寄生电容，提高了VGAA晶体管的器件性能，并降低了制备复杂度。
本实施例提供的方法，通过依次堆叠的硅衬底、第一硅膜层、锗硅膜层和第二硅膜层，基于第一硅膜层和第二硅膜层作为源极/漏极，通过第一掩膜材料在硅衬底上形成位线的基础上，通过第二掩膜材料形成沟道和字线以及环栅，提高了位线、沟道、源极/漏极以及字线和环栅之间的对准度，提高了VGAA晶体管的制备准确率和成功率，提高了VGAA晶体管的器件性能，并降低了制备复杂度。
本实施例提供的方法，基于外延的VGAA晶体管工艺流程，生成外延硅材料作为沟道并填充栅极材料进行环绕，提高了沟道与字线和栅极之间的对准度，提高了工艺准确率。
本实施例提供的方法，利用氧化物进行自对准替代金属栅极工艺，提高了栅极材料的生成准确率。
基于图2所示的方法实施例，在执行步骤201时，还在堆叠结构中形成阱隔离。
在一个实施例中，结合参考图16，图16的(A1)部分示出了形成阱隔离之后的堆叠结构。图16的(A2)部分示出了堆叠结构的二维平面图。考虑阱隔离之后的堆叠结构包括硅衬底00、第一硅膜层11、锗硅膜层12和第二硅膜层13。进一步的，硅衬底00包括上部分硅衬底00-1和下部分硅衬底00-2。可选的，下部分硅衬底00-2被掺杂为N型，上部分硅衬底00-1被掺杂为P型，第一硅膜层11被掺杂为P型。可选的，下部分硅衬底00-2被掺杂为P型，上部分硅衬底00-1被掺杂为N型，第一硅膜层11被掺杂为N型。
可以注意到的是，图16的(B1)部分示出了考虑阱隔离之后得到的多个第一硅柱1601的立体结构。图16的(B2)部分示出了立体结构对应的平面图。此时，执行第一硅柱1601的纵向刻蚀的刻蚀深度仅达到上部分硅衬底00-1，多个第一硅柱1601(即位线)彼此之间通过PN结结构相互隔离，防止第一硅柱1601之间发生漏电。
在一个实施例中，结合参考图17，图17的(A1)部分示出了形成阱隔离之后的堆叠结构。图17的(A2)部分示出了堆叠结构的二维平面图。考虑阱隔离之后的堆叠结构包括硅衬底00、第一硅膜层11、锗硅膜层12、第二硅膜层13，以及位于硅衬底00和第一硅膜层中间的第三硅膜层14。可选的，硅衬底00被掺杂为P型，第一硅膜层11和第三硅膜层14被 掺杂为N型。
可以注意到的是，图17的(B1)部分示出了考虑阱隔离之后得到的多个第一硅柱1601的立体结构。图17的(B2)部分示出了立体结构对应的平面图。此时，执行第一硅柱1601的纵向刻蚀的刻蚀深度仅达到第三硅膜层14，多个第一硅柱1601(即位线)彼此之间通过PN结结构相互隔离，防止第一硅柱1601之间发生漏电。
示意性的，针对上述步骤201提供了如下四种可能的实现方式。
第一种可能的实现方式：获取硅衬底；将硅衬底中的下部分硅衬底掺杂为N型，将硅衬底中的上部分硅衬底掺杂为P型；在硅衬底上依次堆叠第一硅膜层、锗硅膜层和第二硅膜层；将第一硅膜层掺杂为P型。可选的，对硅衬底进行掺杂之后通过退火操作恢复硅衬底晶格。
结合参考图18，图18的(A)部分示出了硅衬底00；图18的(B)部分示出了掺杂为N型的下部分硅衬底00-1和掺杂为P型的上部分硅衬底00-2。图18的(C)部分示出了堆叠得到的第一硅膜层11、锗硅膜层12和第二硅膜层13，第一硅膜层11被掺杂为P型。
第二种可能的实现方式：获取硅衬底；将硅衬底中的下部分硅衬底掺杂为P型，将硅衬底中的上部分硅衬底掺杂为N型；在硅衬底上依次堆叠第一硅膜层、锗硅膜层和第二硅膜层；将第一硅膜层掺杂为N型。可选的，对硅衬底进行掺杂之后通过退火操作恢复硅衬底晶格。
结合参考图19，图19的(A)部分示出了硅衬底00；图19的(B)部分示出了掺杂为P型的下部分硅衬底00-1和掺杂为N型的上部分硅衬底00-2。图19的(C)部分示出了堆叠得到的第一硅膜层11、锗硅膜层12和第二硅膜层13，第一硅膜层11被掺杂为N型。
第三种可能的实现方式：获取硅衬底；将硅衬底掺杂为N型；在硅衬底上依次堆叠第三硅层、第一硅膜层、锗硅膜层和第二硅膜层；将第三硅层和第一硅膜层掺杂为P型。
结合参考图20，图20的(A)部分示出了硅衬底00；图20的(B)部分示出了掺杂为N型的硅衬底00。图20的(C)部分示出了堆叠得到的第三硅膜层14、第一硅膜层11、锗硅膜层12和第二硅膜层13，第三硅膜层14被掺杂为P型，第一硅膜层11被掺杂为P型。
第四种可能的实现方式：获取硅衬底；将硅衬底掺杂为P型；在硅衬底上依次堆叠第三硅膜层、第一硅膜层、锗硅膜层和第二硅膜层；将第三硅膜层和第一硅膜层掺杂为N型。
结合参考图21，图21的(A)部分示出了硅衬底00；图21的(B)部分示出了掺杂为P型的硅衬底00。图21的(C)部分示出了堆叠得到的第三硅膜层14、第一硅膜层11、锗硅膜层12和第二硅膜层13，第三硅膜层14被掺杂为N型，第一硅膜层11被掺杂为N型。
本申请实施例提供了一种电子设备，该电子设备中包括逻辑器件，逻辑器件中包括如上述实施例中所提供的晶体管阵列。该逻辑器件可以应用于逻辑运算器和存储器等。该晶体管阵列是通过如上实施例里中所提供的晶体管的工艺制备方法制备得到的。可选地，该电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或智能移动终端。
在本申请中，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“至少一个”是指一个或多个，术语“多个”指两个或两个以上，除非另有明确的限定。本申请中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
以上所述仅为本申请的示例性实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (11)

  1. 一种晶体管的制备方法，所述方法包括：
    在硅衬底(00)上依次堆叠第一硅膜层(11)、锗硅膜层(12)和第二硅膜层(13)，其中，所述第一硅膜层(11)与所述硅衬底(00)相邻；
    在所述硅衬底(00)、所述第一硅膜层(11)、所述锗硅膜层(12)和所述第二硅膜层(13)上沿位线方向刻蚀形成第一刻蚀槽，在所述第一刻蚀槽内填充金属材料(20)并退火生成位线；
    在所述第二硅膜层(13)、所述锗硅膜层(12)上沿字线方向刻蚀形成第二刻蚀槽，并基于所述锗硅膜层(12)生成沟道后，在所述第二刻蚀槽内沿所述字线方向填充栅极材料(30)形成字线；
    在所述第一刻蚀槽、所述第二刻蚀槽内和所述第二硅膜层(13)上沉积低介电材料(40)，并通过刻蚀和在顶部沉积硅介质材料(50)形成空气间隙，对所述栅极材料(30)进行隔离，得到垂直栅极全环绕晶体管。
  2. 根据权利要求1所述的方法，其中，所述在所述第一刻蚀槽和所述第二刻蚀槽内和所述第二硅膜层(13)上沉积低介电材料(40)，并通过刻蚀和在顶部沉积硅介质材料(50)形成空气间隙，对所述栅极材料(30)和所述第二硅膜层(13)进行隔离，得到垂直栅极全环绕晶体管，包括：
    在所述第一刻蚀槽和所述第二刻蚀槽内和所述第二硅膜层(13)上沉积所述低介电材料(40)；
    刻蚀所述第一硅膜层(11)和所述第二硅膜层(13)表面的所述低介电材料(40)，以及刻蚀所述栅极材料(30)之间的部分低介电材料(40)；
    在所述第二硅膜层(13)上沉积硅介质材料(50)，得到所述垂直栅极全环绕晶体管。
  3. 根据权利要求2所述的方法，其中，所述在所述第二硅膜层(13)上沉积硅介质材料(50)，得到所述垂直栅极全环绕晶体管，包括：
    在所述第二硅膜层(13)上沉积金属材料(20)与所述第二硅膜层(13)接触；
    在所述第一刻蚀槽和所述第二刻蚀槽内沉积所述硅介质材料(50)，得到所述垂直栅极全环绕晶体管。
  4. 根据权利要求1所述的方法，其中，所述在所述硅衬底(00)、所述第一硅膜层(11)、所述锗硅膜层(12)和所述第二硅膜层(13)上沿位线方向刻蚀形成第一刻蚀槽，包括：
    在所述第二硅膜层(13)上沿所述位线方向形成多列第一掩膜材料(60)；
    刻蚀所述硅衬底(00)、所述第一硅膜层(11)、所述锗硅膜层(12)和所述第二硅膜层(13)中未被所述第一掩膜材料(60)覆盖的区域，形成沿所述位线方向的第一刻蚀槽。
  5. 根据权利要求4所述的方法，其中，所述在所述第一刻蚀槽内填充金属材料(20)并退火生成位线，包括：
    在所述第一刻蚀槽内形成第一高度的所述硅介质材料(50)，其中，所述第一高度小于所述硅衬底(00)中所述第一刻蚀槽的深度；
    在所述硅介质材料(50)上填充所述金属材料(20)并退火生成位线，其中，相邻位线之间通过所述硅介质材料(50)隔离。
  6. 根据权利要求1所述的方法，其中，所述在所述第二硅膜层(13)、所述锗硅膜层(12) 上沿字线方向刻蚀形成第二刻蚀槽，包括：
    在所述第二硅膜层(13)上沿字线方向形成多列第二掩膜材料(70)；
    刻蚀所述第二硅膜层(13)、锗硅膜层(12)中未被所述第二掩膜材料(70)覆盖的区域，形成沿所述字线方向的第二刻蚀槽。
  7. 根据权利要求6所述的方法，其中，所述在所述第二硅膜层(13)上沿字线方向形成多列第二掩膜材料(70)，包括：
    在所述第一刻蚀槽内填充得到第二高度的所述硅介质材料(50)，其中，所述第二高度的硅介质材料(50)的上平面与所述第一硅膜层(11)的上平面符合平面距离要求；
    在所述第一刻蚀槽内填充氧化物材料(80)，并在填充所述氧化物材料(80)后的第二硅膜层(13)上沿所述字线方向形成多列第二掩膜材料(70)。
  8. 根据权利要求7所述的方法，其中，所述第二掩膜材料(70)包括心轴材料(71)和分布在所述心轴材料(71)两侧的侧墙材料(72)；
    所述基于所述锗硅膜层(12)生成沟道，包括：
    在所述第一刻蚀槽和所述第二刻蚀槽刻蚀得到的硅柱上，对所述锗硅膜层(12)的表面进行第一厚度的侧向刻蚀；
    在所述锗硅膜层(12)被刻蚀的表面生成第二厚度的外延硅材料(90)，所述第二厚度小于所述第一厚度；
    在所述第二硅膜层(13)和所述锗硅膜层(12)被所述心轴材料(71)覆盖的部分进行刻蚀，将所述硅柱拆分为至少两个子硅柱；
    对所述至少两个子硅柱中的锗硅膜层(12)去除，并填充氧化物材料(80)，得到围绕所述外延硅材料(90)的氧化物材料(80)，所述外延硅材料(90)形成所述晶体管的沟道。
  9. 一种晶体管阵列，所述晶体管阵列中包括呈阵列排布的多个晶体管单元；
    所述晶体管单元包括垂直依次分布的第一源/漏、沟道、第二源/漏、常闭触点，所述晶体管单元的沟道外环绕包覆栅极材料；
    在第一队列中的多个第一晶体管单元的第一源/漏通过耦接埋入式位线连通；
    在第二队列中的多个第二晶体管单元的栅极材料连通，得到字线与所述多个第二晶体管单元耦接，其中，第一队列是沿第一阵列方向的队列，第二队列是沿第二阵列方向的队列；
    多个所述第二队列之间所述晶体管单元表面覆盖有低介电材料，多个所述第二队列顶部覆盖有硅介质材料，在所述低介电材料之间形成有空气间隙。
  10. 一种电子设备，所述电子设备中包括逻辑器件，所述逻辑器件中包括如权利要求9所述的晶体管阵列。
  11. 根据权利要求10所述的电子设备，所述电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或智能移动终端。
PCT/CN2023/116816 2023-07-06 2023-09-04 晶体管的制备方法、晶体管阵列及电子设备 Ceased WO2025007410A1 (zh)

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