WO2025001039A1 - PCIe光互连链路建立方法、装置、设备、介质及系统 - Google Patents

PCIe光互连链路建立方法、装置、设备、介质及系统 Download PDF

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Publication number
WO2025001039A1
WO2025001039A1 PCT/CN2024/070455 CN2024070455W WO2025001039A1 WO 2025001039 A1 WO2025001039 A1 WO 2025001039A1 CN 2024070455 W CN2024070455 W CN 2024070455W WO 2025001039 A1 WO2025001039 A1 WO 2025001039A1
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WIPO (PCT)
Prior art keywords
electrical
pcie
sequence
electrical idle
optical
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Ceased
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PCT/CN2024/070455
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English (en)
French (fr)
Inventor
赵伟康
杨才坤
高显扬
慈潭龙
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Suzhou Metabrain Intelligent Technology Co Ltd
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Suzhou Metabrain Intelligent Technology Co Ltd
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Priority to US19/161,038 priority Critical patent/US20260121742A1/en
Publication of WO2025001039A1 publication Critical patent/WO2025001039A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/03—Arrangements for fault recovery
    • H04B10/038—Arrangements for fault recovery using bypasses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
    • H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
    • H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
    • H04B10/0795—Performance monitoring; Measurement of transmission parameters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/27—Arrangements for networking
    • H04B10/278—Bus-type networks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of signal transmission technology, and in particular to a method, device, equipment, non-volatile readable storage medium and system for establishing a PCIe optical interconnection link.
  • PCIe Peripheral Component Interconnect Express
  • PCB Printed Circuit Board
  • the loss problem caused by electrical interconnection has become increasingly prominent, and the signal transmission distance that can be achieved by electrical interconnection has gradually decreased.
  • low-loss optical interconnection is a preferred solution.
  • the corresponding standards of optical modules are not formulated for the PCIe protocol, some settings in the PCIe protocol are incompatible with the existing optical module standards.
  • the main problem is that it takes a while for the optical module receiving end to work stably after receiving a burst signal. During this period of time before stable operation, the back end cannot extract the clock signal from the data, that is, the link establishment process of the PCIe optical interconnection link will fail due to the electrical idle state. Therefore, how to achieve the establishment of the PCIe optical interconnection link is a problem that needs to be solved urgently.
  • the purpose of this application is to provide a PCIe optical interconnect link establishment method, device, equipment and non-volatile readable storage medium, which can establish a PCIe optical interconnect link and improve the success rate of establishing a PCIe optical interconnect link.
  • the specific scheme is as follows:
  • the present application discloses a PCIe optical interconnect link establishment method, which is applied to a pre-created bypass module, comprising:
  • the current link rate is recorded, and the electrical idle character sequence is counted to determine whether the electrical idle character sequence has been sent.
  • a target signal sequence of a corresponding rate is generated according to the link rate, and the target signal sequence is sent to the other end through the PCIe optical interconnect link so that the other end can maintain stable operation based on the target signal sequence.
  • record the current link rate including:
  • the link rate of the current PCIe optical interconnect link is determined and recorded.
  • the electrical idle character sequence is determined by counting the electrical idle character sequence. Whether the sending is completed, including:
  • the electrical idle character sequence is used to indicate that the transmitter will enter the electrical idle state
  • the method further includes:
  • the upstream data signal is directly transmitted through the PCIe optical interconnect link;
  • the upstream data signal is directly transmitted through the PCIe optical interconnect link.
  • generating a target signal sequence of a corresponding rate according to the link rate includes:
  • the target rate is determined based on the link rate according to a preset increase or decrease range, and a target signal sequence is generated according to the target rate.
  • sending the target signal sequence to the peer end through a PCIe optical interconnect link includes:
  • the target signal sequence is converted electro-optically by the local optical transmitting component and then sent to the optical receiving component at the other end through the PCIe optical interconnect link.
  • the peer maintains stable operation based on the target signal sequence, including:
  • the optical receiving component at the opposite end performs photoelectric conversion on the received optical signal to obtain a target signal sequence, and forwards the target signal sequence to the termination device in the bypass module at the opposite end so that the transimpedance amplifier in the optical module at the opposite end maintains stable operation.
  • the optical receiving component at the opposite end performs photoelectric conversion on the received optical signal to obtain an electrical signal
  • the step of forwarding the target signal sequence to the termination device in the bypass module at the opposite end is performed.
  • the method further includes:
  • the electrical signal is directly forwarded to the terminal device.
  • the method before detecting whether the target signal sequence exists in the electrical signal, the method further includes:
  • the step of detecting whether there is a target signal sequence in the electrical signal is performed.
  • the method further includes:
  • the current link rate is determined based on the electrical idle character sequence and recorded;
  • the target signal sequence is ready to be received.
  • the method further includes:
  • the electrical signal is directly forwarded to the terminal device.
  • bypass module is connected to the host and the optical module as an independent device.
  • bypass module is integrated in a PCIe signal repeater, and the PCIe signal repeater is connected to the host and the optical module respectively.
  • the bypass module includes a pattern generator, a data signal gate, a pattern detection controller and a termination device;
  • the pattern detection controller is configured to obtain an upstream data signal transmitted by the electrical path, detect whether there is an electrical idle character sequence in the upstream data signal, record the current link rate, determine whether the electrical idle character sequence is sent completely by counting the electrical idle character sequence, control the data transmission of the data signal selector, and control the pattern generator to generate a pattern;
  • the pattern generator is configured to generate a target signal sequence of a corresponding rate according to a link rate
  • the data signal selector is configured to obtain an upstream data signal transmitted by the electrical path and send a target signal sequence to a peer end through a PCIe optical interconnect link;
  • the termination device is configured to store the target signal sequence sent by the opposite end.
  • the code detection controller is further configured to receive an electrical signal sent by the opposite end after being photoelectrically converted by the optical receiving component, and control a signal transmission channel of the data signal selector;
  • the data signal selector is also configured to receive the electrical signal sent by the opposite end after photoelectric conversion by the optical receiving component, forward it to the termination device when the electrical signal is the target signal sequence, and forward it to the terminal device when the electrical signal is not the target signal sequence.
  • a PCIe optical interconnection link establishment device comprising:
  • a detection module is configured to obtain an upstream data signal transmitted by the electrical path and detect whether an electrical idle character sequence exists in the upstream data signal;
  • the recording module is configured to record the current link rate if an electrical idle character sequence exists, and determine whether the electrical idle character sequence has been sent by counting the electrical idle character sequence;
  • the sequence sending module is configured to generate a target signal sequence of a corresponding rate according to the link rate when the electrical idle character sequence is completed, and send the target signal sequence to the opposite end through the PCIe optical interconnection link so that the opposite end can maintain stable operation based on the target signal sequence.
  • an electronic device comprising:
  • a memory configured to store a computer program
  • the processor is configured to execute a computer program to implement the aforementioned PCIe optical interconnect link establishment method.
  • the present application discloses a computer non-volatile readable storage medium configured to store a computer program; wherein the computer program, when executed by a processor, implements the aforementioned PCIe optical interconnect link establishment method.
  • the data signal selector is respectively connected to the host, the optical transmitting component and the optical receiving component in the optical module, the pattern generator and the terminal device;
  • an upstream data signal transmitted by an electrical path is obtained, and it is detected whether an electrical idle character sequence exists in the upstream data signal; if an electrical idle character sequence exists, the current link rate is recorded, and it is determined whether the electrical idle character sequence has been sent by counting the electrical idle character sequence; when the electrical idle character sequence has been sent, a target signal sequence of a corresponding rate is generated according to the link rate, and the target signal sequence is sent to the opposite end through the PCIe optical interconnection link, so that the opposite end can maintain stable operation based on the target signal sequence.
  • FIG2 is a schematic diagram of an optional bypass module structure provided in the present application.
  • FIG3 is a flow chart of an optional PCIe optical interconnection method for a transmitting end provided by the present application
  • FIG7 is a schematic diagram of another optional PCIe optical interconnect system structure provided by the present application.
  • FIG8 is a schematic diagram of the structure of a PCIe optical interconnection link establishment device provided by the present application.
  • FIG. 9 is a structural diagram of an electronic device provided in this application.
  • the optical module receiving end needs a period of time to work stably after receiving a burst signal. During this period of time before stable operation, the back end cannot extract the clock signal from the data, that is, the optical module cannot cope with the sudden high-speed signal transmission after the electrical idle state, resulting in the failure of directly using the optical module to build the PCIe optical interconnection path.
  • the present application proposes a PCIe optical interconnection link establishment method, which can establish a PCIe optical interconnection link, improve the success rate of PCIe optical interconnection link establishment, and avoid the problem of link establishment failure due to the electrical idle state during the PCIe optical interconnection link establishment process.
  • the embodiment of the present application discloses a method for establishing a PCIe optical interconnection link, as shown in FIG1 , which is applied to a pre-created bypass module.
  • the method may include the following steps:
  • Step S11 acquiring an upstream data signal transmitted by the electrical path, and detecting whether an electrical idle character sequence exists in the upstream data signal.
  • the upstream data signal transmitted by the electrical path is first obtained, and after the acquisition, it is detected whether there is an electrical idle character sequence in the upstream data signal.
  • an electrical idle character sequence in the upstream data signal.
  • the transmitter (Tx) will send a corresponding character sequence (OrderedSets) to wake up the receiving end (Rx) when data needs to be transmitted to continue the link training process; optionally, before entering the EI state, the transmitter needs to send several electrical idle character sequences (ElectricalIdleOrderedSets, EIOS) defined by the PCIe protocol to the receiving end before entering the EI state; when the transmitter wants to exit the EI state, it needs to send several electrical idle exit character sequences (ElectricalIdleExitOrderedSets, EIEOS) defined by the PCIe protocol to the opposite device before exiting the EI state. Specifically, it can be determined whether there is an electrical idle character sequence in the upstream data signal according to the characteristics of the electrical idle character sequence defined by the PCIe protocol.
  • EIEOS Electrical idle exit character sequences
  • the method may further include: if it is determined that there is no electrical idle character sequence in the upstream data signal, directly transmitting the upstream data signal through the PCIe optical interconnection link. That is, if there is no electrical idle character sequence in the upstream data signal, it proves that the link is in a normal data transmission process, and at this time, the upstream data signal can be directly transmitted to the opposite end through the PCIe optical interconnection link.
  • Step S12 If there is an electrical idle character sequence, the current link rate is recorded, and the electrical idle character sequence is counted to determine whether the current electrical idle character sequence has been sent.
  • an electrical idle character sequence if an electrical idle character sequence is detected, it can indicate that the link is ready to enter The idle state records the current link rate at this time, and determines whether the electrical idle character sequence has been sent by counting the electrical idle character sequence. It can be understood that if the electrical idle character sequence is sent, it represents entering the idle state, otherwise it represents still in the preparation stage of entering the idle state.
  • recording the current link rate may include: determining and recording the link rate of the current PCIe optical interconnect link according to the sending rate of the electrical idle character sequence.
  • the link rate i.e., the link transmission rate, refers to the speed at which a host or a router sends data to a link. Therefore, the link rate of the current PCIe optical interconnect link may be determined and then recorded according to the sending rate of the electrical idle character sequence.
  • judging whether the current electrical idle character sequence has been sent by counting the electrical idle character sequence may include: counting the electrical idle character sequence; the electrical idle character sequence is used to indicate that the transmitting end will enter the electrical idle state; when the count value reaches the target value set by the PCIe protocol, judging that the current electrical idle character sequence has been sent, otherwise, judging that the current electrical idle character sequence has not been sent. That is, the total number of electrical idle character sequences sent each time the electrical idle state is entered is fixed, that is, the target value set by the above PCIe protocol, therefore, the electrical idle character sequence may be counted, and then judging that the current electrical idle character sequence has been sent according to the count value, and the count value reaches the target value, otherwise, it is not completed.
  • the method may further include: if it is judged that the electrical idle character sequence is not completely sent, directly transmitting the upstream data signal through the PCIe optical interconnection link. That is, if the electrical idle character sequence is not completely sent, it proves that the link is in the electrical idle character sequence transmission process, and at this time, the upstream data signal including the electrical idle character sequence can be directly transmitted to the opposite end through the PCIe optical interconnection link.
  • Step S13 When the electrical idle character sequence is sent, a target signal sequence of a corresponding rate is generated according to the link rate, and the target signal sequence is sent to the peer end through the PCIe optical interconnect link so that the peer end can maintain stable operation based on the target signal sequence.
  • a target signal sequence of a corresponding rate is generated according to the link rate, and the target signal sequence is sent to the opposite end through the PCIe optical interconnect link, so that the opposite end can maintain stable operation by continuously receiving the target signal sequence.
  • the link establishment fails due to the electrical idle state during the establishment of the PCIe optical interconnect link is that the link will store a sudden change in data rate when it changes from the electrical idle state to the normal data transmission state.
  • the trans-impedance amplifier (TIA) at the receiving end of the optical module needs a period of time to work stably after receiving the burst signal.
  • the target signal sequence is used to keep the trans-impedance amplifier in a normal working state, thereby avoiding the problem of link establishment failure caused by the electrical idle state.
  • generating a target signal sequence of a corresponding rate according to a link rate may include: determining a target rate according to a preset increase or decrease range based on the link rate, generating a target signal sequence according to the target rate, Target signal sequence. That is, the target rate can be obtained by appropriately reducing, increasing or keeping the link rate unchanged, as long as the difference between the target rate and the link rate is not so large that the transimpedance amplifier needs some time to adapt. In some cases, a minimum rate can be selected within the allowable range, which can avoid the problem of link establishment failure and save resources.
  • sending the target signal sequence to the opposite end through the PCIe optical interconnection link may include: performing electrical-optical conversion on the target signal sequence through a local optical transmitting component, and then sending the target signal sequence to the optical receiving component of the opposite end through the PCIe optical interconnection link. That is, the electrical signal of the target signal sequence is converted into an optical signal by using the optical transmitting component, and the optical signal is transmitted to the opposite end through the optical fiber.
  • the local and opposite ends in this embodiment are just descriptions from different perspectives, and the same is true for the transmitting end and the receiving end, but each terminal will correspond to a same bypass module for implementing the above steps.
  • a clock data recovery circuit which can send the local reference clock as input data to the phase adjustment module when facing a burst signal to ensure that the CDR (clock Data Recovery) module can recover the correct clock signal.
  • CDR clock Data Recovery
  • the optical link composed of the optical module and the optical fiber always maintains the active state of high-speed transmission before entering the electrical idle state when the link transmitting end and the receiving end enter the electrical idle state, avoiding the burst signal transmission mode of the receiving end entering the normal data transmission state from the electrical idle state, keeping the TIA of the receiving end of the optical module always in a stable working mode, completing the link training process and establishing a PCIe optical interconnection link between the transmitting end and the receiving end.
  • the opposite end maintains stable operation based on the target signal sequence, which may include: the optical receiving component of the opposite end performs photoelectric conversion on the received optical signal to obtain the target signal sequence, and forwards the target signal sequence to the terminal device in the bypass module of the opposite end, so that the transimpedance amplifier in the optical module of the opposite end maintains stable operation. That is, after the photoelectric conversion, the target signal sequence is extracted from the electrical signal, and the transimpedance amplifier of the opposite end can continue to work according to the target signal sequence.
  • the optical receiving component at the opposite end performs photoelectric conversion on the received optical signal to obtain a target signal sequence, including: the optical receiving component at the opposite end performs photoelectric conversion on the received optical signal to obtain an electrical signal; detects whether the target signal sequence exists in the electrical signal; if the target signal sequence exists, executes the step of forwarding the target signal sequence to the terminal device in the bypass module at the opposite end; if the target signal sequence does not exist, directly forwards the electrical signal to the terminal device. That is, first detect whether it is the target signal sequence, if it is not the target signal sequence, it may be normal data information or an electrical idle character sequence, and it can be directly sent to the terminal device.
  • the method before detecting whether there is a target signal sequence in the electrical signal, the method further includes: detecting whether there is an electrical idle character sequence in the electrical signal; if there is no electrical idle character sequence, executing the step of detecting whether there is a target signal sequence in the electrical signal; if there is an electrical idle character sequence, determining the current link rate according to the electrical idle character sequence and recording it; counting the electrical idle character sequence, and judging whether the electrical idle character sequence is sent according to the count value; if the electrical idle character sequence is sent, determining the current link rate according to the count value; and If the electrical idle character sequence is sent, the target signal sequence is ready to be received; if the electrical idle character sequence is not sent, the electrical signal is directly forwarded to the terminal device.
  • the other end can detect the electrical idle character sequence first and then the target signal sequence each time it receives the signal, thereby improving the detection efficiency.
  • the above method is applicable to the establishment of optical interconnection links under the CXL (Compute Express Link) protocol specification based on the PCIe5.0 protocol.
  • the upstream data signal transmitted by the electrical path is obtained, and it is detected whether there is an electrical idle character sequence in the upstream data signal; if there is an electrical idle character sequence, the current link rate is recorded, and it is determined whether the electrical idle character sequence is sent by counting the electrical idle character sequence; when the electrical idle character sequence is sent, a target signal sequence of the corresponding rate is generated according to the link rate, and the target signal sequence is sent to the opposite end through the PCIe optical interconnection link, so that the opposite end can maintain stable operation based on the target signal sequence.
  • the present application also provides an optional bypass module structure, the bypass module includes a code generator, a data signal selector, a code detection controller and a termination device; wherein the code detection controller is configured to obtain the upstream data signal transmitted by the electrical path, detect whether there is an electrical idle character sequence in the upstream data signal, record the current link rate, determine whether the electrical idle character sequence is sent by counting the electrical idle character sequence, control the data transmission of the data signal selector, and control the code generator to generate a code pattern; the code generator is configured to generate a target signal sequence of a corresponding rate according to the link rate; the data signal selector is configured to obtain the upstream data signal transmitted by the electrical path, and send the target signal sequence to the opposite end through the PCIe optical interconnect link; the termination device is configured to store the target signal sequence sent by the opposite end.
  • the code detection controller is configured to obtain the upstream data signal transmitted by the electrical path, detect whether there is an electrical idle character sequence in the upstream data signal, record the current link rate, determine whether the electrical idle character sequence is sent
  • 1 is a bypass module
  • 101 is a pattern generator
  • 102 is a data signal selector
  • 103 is an optical transmitter component
  • 104 is a pattern detection controller
  • 105 is an optical receiver component
  • 106 is a termination device
  • 201 is an electrical path connected to the bypass module
  • 301 is an optical fiber connected to the optical transmitter component and the optical receiver component.
  • the bypass module 1 receives the upstream signal through the receiving path (Rx) of the electrical path 201, and the received signal enters the data signal selector 102 and the pattern detection controller 104.
  • the pattern detection controller 104 controls the pattern generator 101 and the data signal selector 102, and then the signal output by the data signal selector 102 is converted into an optical signal by the optical transmitter component 103, and finally transmitted outward through the optical fiber 301.
  • the code detection controller is also configured to receive the electrical signal sent by the opposite end after the optical receiving component undergoes photoelectric conversion, and control the signal transmission channel of the data signal selector; the data signal selector is also configured to receive the electrical signal sent by the opposite end after the optical receiving component undergoes photoelectric conversion, and forward it to the termination device when the electrical signal is the target signal sequence, and forward it to the termination device when the electrical signal is not the target signal sequence. That is, when the device receives a signal through the optical fiber 301, the received signal is converted into photoelectric by the optical receiving component 105 and then input into the data signal selector 102 and the code detection controller 104.
  • the code detection controller 104 controls the data signal selector 102 to transmit the input signal into the terminal device 106 or through the electrical path 201.
  • the pattern detection controller supports identifying the pattern related to the electrical idle state during the PCIe link training process. That is, the pattern detection controller 104 needs to be able to identify the pattern related to EI during the PCIe link training process, including but not limited to ASIC (Application Specific Integrated Circuit) chips, ARM (Advanced RISC Machines) chips or FPGA (Field Programmable Gate Array) chips, etc., to achieve the function of pattern detection and control of data signal selector.
  • ASIC Application Specific Integrated Circuit
  • ARM Advanced RISC Machines
  • FPGA Field Programmable Gate Array
  • the signal rate supported by the data signal selector covers the signal rate specified by the PCIe protocol. That is, the data signal selector 102 is used to realize signal selection and the supported signal rate needs to cover the signal rate specified by the PCIe protocol, including but not limited to ASIC chips, ARM chips or FPGA chips, etc., to realize the signal selection function.
  • the code generator 101 can generate a code that complies with the PCIe protocol rate, including but not limited to an ASIC chip, an ARM chip or an FPGA chip, etc., to maintain the normal operation of the receiving end optical module.
  • the present application also provides an optional PCIe optical interconnection method at the transmitting end, as shown in FIG3 , including the following steps:
  • the upstream data signal is first transmitted to the data signal selector and pattern detection controller inside the bypass module;
  • the pattern detection controller detects whether there is an EIOS sequence in the upstream signal. If the pattern detection controller detects that there is an EIOS sequence in the upstream signal, it means that the transmitter is about to enter the electrical idle state. At this time, the pattern detection controller needs to determine the current link rate according to the EIOS sequence and count the EIOS sequence. If the pattern detection controller detects that there is no EIOS sequence in the upstream signal, it means that the transmitter has not entered the electrical idle state. The pattern detection controller controls the data signal selector to directly transmit the upstream data signal.
  • the EIOS sequence reaches the number set by the PCIe protocol, it means that the transmitter and receiver will enter the electrical idle state after completing the transmission and reception of this EIOS sequence; first, after the last EIOS sequence is directly transmitted through the data signal selector, the pattern detection controller controls the pattern generator to generate a signal with the same link rate as the current link rate. And control the data signal selector to transmit the signal generated by the pattern generator to ensure that the link still has high-speed signal transmission;
  • the peer device needs to wait for the sender to send several EIOS sequences before entering the electrical idle state.
  • the pattern detection controller controls the data signal selector to directly transmit the upstream data signal. At this time, the data signal is the EIOS sequence.
  • the optical receiving component converts the received optical signal into an electrical signal and transmits it to the data signal selector and the code detection controller;
  • the pattern detection controller detects an EIOS sequence in the signal, it means that the transmitter is about to enter the electrical idle state. At this time, the pattern detection controller needs to determine the current link rate based on the EIOS sequence and count the EIOS sequence;
  • the embodiment of the present application also discloses a PCIe optical interconnection link system, which includes: a host, an optical module and the aforementioned bypass module; the bypass module includes a pattern generator, a data signal selector, a pattern detection controller and a termination device;
  • the data signal selector is respectively connected to the host, the optical transmitting component and the optical receiving component in the optical module, the pattern generator and the terminal device;
  • the code detection controller is connected to the host, the data signal selector, the optical receiving component and the code generator respectively.
  • the bypass module can be integrated with the local optical transmitting component and the optical receiving component in the optical module.
  • FIG5 shows a schematic diagram of the structure of a PCIe optical interconnection system constructed by an optional PCIe optical interconnection link establishment device.
  • the bypass module 1 is integrated with the optical transmitting component 103 and the optical receiving component 105 in the optical module 2.
  • the chip directly connected to the server host and the bypass module 1 can be a CPU (Central Processing Unit), a PCIe Switch, a PCIe Retimer, a PCIe Redriver, etc.
  • the chip or device directly connected to the terminal device and the bypass module 1 can be a GPU (Graphics Processing Unit), an SSD (Solid State Drive), a DRAM (Dynamic Random Access Memory), a PCIe Switch, a PCIe Retimer, a PCIe Redriver, etc.
  • a GPU Graphics Processing Unit
  • SSD Solid State Drive
  • DRAM Dynamic Random Access Memory
  • PCIe Switch PCIe Retimer
  • PCIe Redriver a PCIe Redriver
  • the bypass module can also be connected to the host and the optical module as an independent device.
  • FIG. 6 shows a schematic diagram of the structure of a PCIe optical interconnection system constructed by an optional PCIe optical interconnection link establishment device, and the bypass module 1 is located between the host and the optical module 2 as an independent device.
  • the chip directly connected to the server host and the bypass module 1 can be a CPU, a PCIe Switch, a PCIe Retimer, a PCIe Redriver, etc.
  • the chip or device directly connected to the terminal device and the bypass module 1 can be a GPU, an SSD, a DRAM, a PCIe Switch, a PCIe Retimer, a PCIe Redriver, etc.
  • the bypass module can also be integrated into the PCIe signal repeater, and the PCIe signal repeater is connected to the host and the optical module respectively.
  • FIG7 shows a schematic diagram of the structure of a PCIe optical interconnection system constructed by an optional PCIe optical interconnection link establishment device, and the bypass module 1 is integrated into three types of PCIe signal relay devices 5: PCIe Switch, PCIe Retimer, and PCIe Redriver.
  • the core chip directly connected to the server host and the PCIe signal relay device 5 can be a CPU, etc.
  • the chip or device directly connected to the terminal device and the PCIe signal relay device 5 can be a GPU, SSD, DRAM, PCIe Switch, PCIe Retimer, PCIe Redriver, etc.
  • bypass module has a flexible integration form. It can be placed between the host and the optical module as a separate device, or it can be integrated into chips such as optical modules or PCIe signal repeaters.
  • the embodiment of the present application also discloses a PCIe optical interconnection link establishment device, as shown in FIG8 , the device includes:
  • the detection module 31 is configured to obtain an upstream data signal transmitted by the electrical path and detect whether an electrical idle character sequence exists in the upstream data signal;
  • the recording module 32 is configured to record the current link rate if there is an electrical idle character sequence, and determine whether the electrical idle character sequence has been sent by counting the electrical idle character sequence;
  • the sequence sending module 33 is configured to generate a target signal sequence of a corresponding rate according to the link rate when the electrical idle character sequence is completed, and send the target signal sequence to the opposite end through the PCIe optical interconnect link so that the opposite end can maintain stable operation based on the target signal sequence.
  • the upstream data signal transmitted by the electrical path is obtained, and it is detected whether there is an electrical idle character sequence in the upstream data signal; if there is an electrical idle character sequence, the current link rate is recorded, and it is determined whether the electrical idle character sequence is sent by counting the electrical idle character sequence; when the electrical idle character sequence is sent, a target signal sequence of the corresponding rate is generated according to the link rate, and the target signal sequence is sent to the opposite end through the PCIe optical interconnection link, so that the opposite end can maintain stable operation based on the target signal sequence.
  • the recording module 32 may specifically include:
  • the link rate determination unit is configured to determine and record the link rate of the current PCIe optical interconnect link according to the sending rate of the electrical idle character sequence.
  • the recording module 32 may specifically include:
  • a counting unit is configured to count an electrical idle character sequence; the electrical idle character sequence is used to indicate that the transmitting end is about to enter an electrical idle state;
  • the PCIe optical interconnection link establishment device may specifically include:
  • the first direct transmission unit is configured to, after detecting whether there is an electrical idle character sequence in the upstream data signal, directly transmit the upstream data signal through the PCIe optical interconnect link if it is determined that there is no electrical idle character sequence in the upstream data signal;
  • the second direct transmission unit is configured to directly transmit the upstream data signal through the PCIe optical interconnection link if it is determined that the electrical idle character sequence has not been sent completely.
  • the rate determination unit is configured to determine a target rate according to a preset increase or decrease range based on the link rate, and generate a target signal sequence according to the target rate.
  • sequence sending module 33 may specifically include:
  • the sequence sending unit is configured to perform electrical-optical conversion on the target signal sequence through the local optical transmitting component and then send it to the optical receiving component at the opposite end through the PCIe optical interconnection link.
  • the PCIe optical interconnection link establishment device may specifically include:
  • the target signal sequence acquisition unit may specifically include:
  • An electrical signal acquisition unit is configured to perform photoelectric conversion on a received optical signal by a light receiving component at the opposite end to obtain an electrical signal;
  • a target signal sequence detection unit configured to detect whether a target signal sequence exists in the electrical signal
  • the target signal sequence acquisition unit may specifically include:
  • an electrical idle character sequence detection unit configured to detect whether there is an electrical idle character sequence in the electrical signal before detecting whether there is a target signal sequence in the electrical signal
  • the execution unit is configured to execute the step of detecting whether there is a target signal sequence in the electrical signal if there is no electrical idle character sequence.
  • the target signal sequence acquisition unit may specifically include:
  • a recording unit configured to determine and record the current link rate according to the electrical idle character sequence if there is an electrical idle character sequence
  • a judging unit is configured to count the electrical idle character sequence and judge whether the electrical idle character sequence is sent completely according to the count value
  • the preparation unit is configured to prepare to receive the target signal sequence if the electrical idle character sequence is sent completely.
  • the forwarding unit is configured to directly forward the electrical signal to the terminal device if the electrical idle character sequence is not completely sent.
  • the bypass module may be integrated with the local optical transmitting component and the local optical receiving component in the optical module.
  • bypass module can be specifically connected to the host and the optical module as an independent device.
  • bypass module can be integrated in the PCIe signal repeater.
  • the signal repeater is connected to the host and the optical module respectively.
  • the bypass module may specifically include a pattern generator, a data signal gate, a pattern detection controller, and a termination device;
  • the pattern detection controller is configured to obtain an upstream data signal transmitted by the electrical path, detect whether there is an electrical idle character sequence in the upstream data signal, record the current link rate, determine whether the electrical idle character sequence is sent completely by counting the electrical idle character sequence, control the data transmission of the data signal selector, and control the pattern generator to generate a pattern;
  • the pattern generator is configured to generate a target signal sequence of a corresponding rate according to a link rate
  • the data signal selector is configured to obtain an upstream data signal transmitted by the electrical path and send a target signal sequence to a peer end through a PCIe optical interconnect link;
  • the termination device is configured to store a target signal sequence sent by the opposite end.
  • the code detection controller is further configured to receive the electrical signal sent by the opposite end after the optical receiving component performs photoelectric conversion, and control the signal transmission channel of the data signal selector;
  • the data signal selector is also configured to receive the electrical signal sent by the opposite end after photoelectric conversion by the optical receiving component, forward it to the termination device when the electrical signal is the target signal sequence, and forward it to the terminal device when the electrical signal is not the target signal sequence.
  • the pattern detection controller supports identifying patterns associated with electrical idle states during PCIe link training.
  • the signal rate supported by the data signal strobe covers the signal rate specified by the PCIe protocol.
  • the embodiment of the present application further discloses an electronic device, as shown in FIG9 .
  • the content in the figure cannot be regarded as any limitation on the scope of use of the present application.
  • FIG9 is a schematic diagram of the structure of an electronic device 40 provided in an embodiment of the present application.
  • the electronic device 40 may specifically include: at least one processor 41, at least one memory 42, a power supply 43, a communication interface 44, an input/output interface 45, and a communication bus 46.
  • the memory 42 is configured to store a computer program, which is loaded and executed by the processor 41 to implement the relevant steps in the PCIe optical interconnection link establishment method disclosed in any of the aforementioned embodiments.
  • the power supply 43 is configured to provide working voltage for each hardware device on the electronic device 40;
  • the communication interface 44 can create a data transmission channel between the electronic device 40 and external devices, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here;
  • the input and output interface 45 is configured to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.
  • the memory 42 as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc.
  • the resources stored thereon include an operating system 421, a computer program 422, and data 423 including upstream data signals, etc.
  • the storage method can be temporary storage or permanent storage.
  • the operating system 421 is configured to manage and control the hardware devices and computer programs 422 on the electronic device 40, so as to realize the operation and processing of the massive data 423 in the memory 42 by the processor 41.
  • the operating system 421 may be Windows Server (Windows server), Netware (a network operating system), or other operating system.
  • the computer program 422 can also include computer programs that can be configured to complete other specific tasks.
  • the embodiment of the present application also discloses a computer non-volatile readable storage medium, in which computer executable instructions are stored.
  • computer executable instructions When the computer executable instructions are loaded and executed by a processor, the steps of the PCIe optical interconnection link establishment method disclosed in any of the aforementioned embodiments are implemented.
  • each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments.
  • the same or similar parts between the embodiments can be referred to each other.
  • the description is relatively simple, and the relevant parts can be referred to the method part.
  • the steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two.
  • the software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM (Compact Disc Read-Only Memory), or any other form of non-volatile readable storage medium known in the art.

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Abstract

本申请公开了一种高速串行计算机扩展总线标准PCIe光互连链路建立方法、装置、设备、非易失性可读存储介质及系统，涉及信号传输技术领域。该方法包括：获取电通路传输的上游数据信号，并检测上游数据信号中是否存在电气空闲字符序列（S11）；若存在电气空闲字符序列，则记录当前的链路速率，并通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成（S12）；当本次电气空闲字符序列完成发送，根据链路速率生成相应速率的目标信号序列，并将目标信号序列通过PCIe光互连链路发送给对端，以便对端基于目标信号序列保持稳定工作（S13）。能够建立PCIe光互联链路，提高PCIe光互联链路建立的成功率，避免链路建立过程中因电气空闲状态导致链路建立失败的问题。

Description

PCIe光互连链路建立方法、装置、设备、介质及系统
相关申请的交叉引用
本申请要求于2023年06月28日提交中国专利局，申请号为202310771673.6，申请名称为“PCIe光互连链路建立方法、装置、设备、介质及系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及信号传输技术领域，特别涉及一种PCIe光互连链路建立方法、装置、设备、非易失性可读存储介质及系统。
背景技术
PCIe(Peripheral Component Interconnect Express)是一种高速串行计算机扩展总线标准，主要用于扩充计算机系统总线数据吞吐量以及提高设备通信速度。当前PCIe数据信号主要通过电互连方式构建传输路径，例如PCB(Printed Circuit Board，印制电路板)级铜线和铜缆。随着PCIe协议的不断更新，由电互连造成的损耗问题日益突出，电互连所能实现的信号传输距离也逐渐降低。此时，低损耗的光互连是一个优先的解决方案，但是，由于光模块相应标准并非针对PCIe协议制定，PCIe协议中有一些设定与现有光模块标准不兼容，主要问题在于光模块接收端在接收到突发信号时需要一段时间才能稳定工作，在稳定工作前的这段时间后端无法从数据中提取时钟信号，即PCIe光互连链路建立过程中会因电气空闲状态导致链路建立失败。因此，如何实现PCIe光互联链路的建立，是目前亟需解决的问题。
发明内容
有鉴于此，本申请的目的在于提供一种PCIe光互连链路建立方法、装置、设备及非易失性可读存储介质，能够建立PCIe光互联链路，提高PCIe光互联链路建立的成功率。其具体方案如下：
第一方面，本申请公开了一种PCIe光互连链路建立方法，应用于预先创建的旁路模块，包括：
获取电通路传输的上游数据信号，并检测上游数据信号中是否存在电气空闲字符序列；
若存在电气空闲字符序列，则记录当前的链路速率，并通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成；
当本次电气空闲字符序列完成发送，根据链路速率生成相应速率的目标信号序列，并将目标信号序列通过PCIe光互连链路发送给对端，以便对端基于目标信号序列保持稳定工作。
可选的，记录当前的链路速率，包括：
根据电气空闲字符序列的发送速率，确定当前PCIe光互连链路的链路速率并记录。
可选的，通过对电气空闲字符序列进行计数判断本次电气空闲字符序列 是否发送完成，包括：
通过对电气空闲字符序列进行计数；电气空闲字符序列用于表征发送端将进入电气空闲状态；
当计数值达到PCIe协议设定的目标值时判定本次电气空闲字符序列发送完成，否则，判定本次电气空闲字符序列没有发送完成。
可选的，检测上游数据信号中是否存在电气空闲字符序列之后，还包括：
若判定上游数据信号中不存在电气空闲字符序列，则直接通过PCIe光互连链路传输上游数据信号；
通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成之后，还包括：
若判定本次电气空闲字符序列没有发送完成，则直接通过PCIe光互连链路传输上游数据信号。
可选的，根据链路速率生成相应速率的目标信号序列，包括：
在链路速率的基础上根据预设增减范围确定出目标速率，根据目标速率生成目标信号序列。
可选的，将目标信号序列通过PCIe光互连链路发送给对端，包括：
将目标信号序列通过本地的光发射组件进行电光转换后，通过PCIe光互连链路发送给对端的光接收组件。
可选的，对端基于目标信号序列保持稳定工作，包括：
对端的光接收组件对接收到的光信号进行光电转换后，得到目标信号序列，并将目标信号序列转发给对端的旁路模块中的端接器件，以便对端的光模块内的跨阻抗放大器保持稳定工作。
可选的，对端的光接收组件对接收到的光信号进行光电转换后，得到目标信号序列，包括：
对端的光接收组件对接收到的光信号进行光电转换得到电信号；
检测电信号中是否存在目标信号序列；
若存在目标信号序列，则执行将目标信号序列转发给对端的旁路模块中的端接器件的步骤。
可选的，检测电信号中是否存在目标信号序列之后，还包括：
若不存在目标信号序列，则直接将电信号转发给终端设备。
可选的，检测电信号中是否存在目标信号序列之前，还包括：
检测电信号中是否存在电气空闲字符序列；
若不存在电气空闲字符序列，则执行检测电信号中是否存在目标信号序列的步骤。
可选的，检测电信号中是否存在电气空闲字符序列之后，还包括：
若存在电气空闲字符序列，则根据电气空闲字符序列确定当前的链路速率并记录；
对电气空闲字符序列进行计数，并根据计数值判断本次电气空闲字符序列是否发送完成；
若本次电气空闲字符序列发送完成，则准备接收目标信号序列。
可选的，根据计数值判断本次电气空闲字符序列是否发送完成之后，还包括：
若本次电气空闲字符序列没有发送完成，则直接将电信号转发给终端设备。
可选的，旁路模块与本地的光发射组件和光接收组件集成在光模块内。
可选的，旁路模块作为独立器件分别与主机和光模块相连。
可选的，旁路模块集成在PCIe信号中继器，PCIe信号中继器分别与主机和光模块相连。
可选的，旁路模块包括码型生成器、数据信号选通器、码型检测控制器和端接器件；
码型检测控制器被配置为获取电通路传输的上游数据信号，检测上游数据信号中是否存在电气空闲字符序列，记录当前的链路速率，通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成，控制数据信号选通器的数据传输，控制码型生成器生成码型；
码型生成器被配置为根据链路速率生成相应速率的目标信号序列；
数据信号选通器被配置为获取电通路传输的上游数据信号，将目标信号序列通过PCIe光互连链路发送给对端；
端接器件被配置为存储对端发送的目标信号序列。
可选的，码型检测控制器还被配置为接收对端发送的经过光接收组件进行光电转换后的电信号，控制数据信号选通器的信号传输通道；
数据信号选通器还被配置为接收对端发送的经过光接收组件进行光电转换后的电信号，在电信号为目标信号序列时转发给端接器件，在电信号不是目标信号序列时转发给终端设备。
可选的，码型检测控制器支持识别PCIe链路训练过程中与电气空闲状态相关的码型。
可选的，数据信号选通器支持的信号速率涵盖PCIe协议规定的信号速率。
第二方面，本申请公开了一种PCIe光互连链路建立装置，包括：
检测模块，被配置为获取电通路传输的上游数据信号，并检测上游数据信号中是否存在电气空闲字符序列；
记录模块，被配置为若存在电气空闲字符序列，则记录当前的链路速率，并通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成；
序列发送模块，被配置为当本次电气空闲字符序列完成发送，根据链路速率生成相应速率的目标信号序列，并将目标信号序列通过PCIe光互连链路发送给对端，以便对端基于目标信号序列保持稳定工作。
第三方面，本申请公开了一种电子设备，包括：
存储器，被配置为保存计算机程序；
处理器，被配置为执行计算机程序，以实现前述的PCIe光互连链路建立方法。
第四方面，本申请公开了一种计算机非易失性可读存储介质，被配置为存储计算机程序；其中计算机程序被处理器执行时实现前述的PCIe光互连链路建立方法。
第五方面，本申请公开了一种PCIe光互连链路系统，包括主机、光模块和前述的旁路模块；旁路模块包括码型生成器、数据信号选通器、码型检测控制器和端接器件；
数据信号选通器分别与主机、光模块中的光发射组件和光接收组件、码型生成器和端接器件相连；
码型检测控制器分别与主机、数据信号选通器、光接收组件和码型生成器相连。
本申请中，获取电通路传输的上游数据信号，并检测上游数据信号中是否存在电气空闲字符序列；若存在电气空闲字符序列，则记录当前的链路速率，并通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成；当本次电气空闲字符序列完成发送，根据链路速率生成相应速率的目标信号序列，并将目标信号序列通过PCIe光互连链路发送给对端，以便对端基于目标信号序列保持稳定工作。
可见，通过根据电气空闲字符序列判断链路是否将要进入电气空闲状态，并在进入电气空闲状态后，通过生成相应速率的目标信号序列维持本地和接收端的工作状态，能够避免突发信号对跨阻抗放大器产生的冲击，实现服务器等主机和外部设备之间通过光纤建立PCIe链路，避免PCIe光互连链路建立过程中因电气空闲状态导致链路建立失败的问题，即解决了链路退出电气空闲状态时互连链路会存在从无数据传输到高速数据信号传输的突发模式的问题。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本申请提供的一种PCIe光互连链路建立方法流程图；
图2为本申请提供的一种可选的旁路模块结构示意图；
图3为本申请提供的一种可选的发送端PCIe光互连方法流程图；
图4为本申请提供的一种可选的接收端PCIe光互连方法流程图；
图5为本申请提供的一种可选的PCIe光互连系统结构示意图；
图6为本申请提供的另一种可选的PCIe光互连系统结构示意图；
图7为本申请提供的另一种可选的PCIe光互连系统结构示意图；
图8为本申请提供的一种PCIe光互连链路建立装置结构示意图；
图9为本申请提供的一种电子设备结构图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
现有技术中，由于光模块相应标准并非针对PCIe协议制定，PCIe协议中有一些设定与现有光模块标准不兼容，主要问题在于光模块接收端在接收到突发信号时需要一段时间才能稳定工作，在稳定工作前的这段时间后端无法从数据中提取时钟信号，即光模块无法应对电气空闲状态后突然的高速信号传输，导致直接使用光模块构建PCIe光互连通路会构建失败。为克服上述技术问题，本申请提出一种PCIe光互连链路建立方法，能够建立PCIe光互联链路，提高PCIe光互联链路建立的成功率，避免PCIe光互连链路建立过程中因电气空闲状态导致链路建立失败的问题。
本申请实施例公开了一种PCIe光互连链路建立方法，参见图1所示，应用于预先创建的旁路模块，该方法可以包括以下步骤：
步骤S11：获取电通路传输的上游数据信号，并检测上游数据信号中是否存在电气空闲字符序列。
本实施例中，首先获取电通路传输的上游数据信号，获取后检测上游数据信号中是否存在电气空闲字符序列。可以理解的是，PCIe互连链路建立过程中存在链路训练过程，整个互连链路需要能在链路训练过程中正确传输信号才能使链路成功建立；链路训练过程中，链路会多次进入电气空闲(ElectricalIdle，EI)状态，进入EI状态后，互连链路中不会有数据信号传输。此后，发送端(Tx)在需要传输数据时会发送相应字符序列(OrderedSets)唤醒接收端(Rx)以继续链路训练过程；可选的，发送端在进入EI状态前，需要向接收端发送若干个由PCIe协议定义的电气空闲字符序列(ElectricalIdleOrderedSets，EIOS)，才能进入EI状态；当发送端要退出EI状态时，需要向对端设备发送若干个由PCIe协议定义的电气空闲退出字符序列(ElectricalIdleExitOrderedSets，EIEOS)，才能退出EI状态。具体可以根据PCIe协议定义的电气空闲字符序列的特征判断上游数据信号中是否存在电气空闲字符序列。
本实施例中，检测上游数据信号中是否存在电气空闲字符序列之后，还可以包括：若判定上游数据信号中不存在电气空闲字符序列，则直接通过PCIe光互连链路传输上游数据信号。即若上游数据信号中不存在电气空闲字符序列，则证明链路处于正常数据传输过程，此时直接通过PCIe光互连链路传输上游数据信号给对端即可。
步骤S12：若存在电气空闲字符序列，则记录当前的链路速率，并通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成。
本实施例中，若检测到电气空闲字符序列，则可以表征链路准备要进入 空闲状态了，此时记录当前的链路速率，并通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成，可以理解的是，若电气空闲字符序列发送完成则表征进入空闲状态，否则表征还处于进入空闲状态的准备阶段。
本实施例中，记录当前的链路速率，可以包括：根据电气空闲字符序列的发送速率，确定当前PCIe光互连链路的链路速率并记录。链路速率，即链路传输速率，是指主机或路由器向链路上发送数据的速度，因此可以根据电气空闲字符序列的发送速率，确定当前PCIe光互连链路的链路速率然后进行记录。
本实施例中，通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成，可以包括：通过对电气空闲字符序列进行计数；电气空闲字符序列用于表征发送端将进入电气空闲状态；当计数值达到PCIe协议设定的目标值时判定本次电气空闲字符序列发送完成，否则，判定本次电气空闲字符序列没有发送完成。即每次进入电气空闲状态发送的电气空闲字符序列的总数是固定的，即上述PCIe协议设定的目标值，因此，可以通过对电气空闲字符序列进行计数，然后根据计数值判断本次电气空闲字符序列发送完成，计数值达到目标值为完成，否则没有完成。
本实施例中，通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成之后，还可以包括：若判定本次电气空闲字符序列没有发送完成，则直接通过PCIe光互连链路传输上游数据信号。即若本次电气空闲字符序列没有发送完成，则证明链路处于电气空闲字符序列传输过程，此时直接通过PCIe光互连链路传输包括电气空闲字符序列在内的上游数据信号给对端即可。
步骤S13：当本次电气空闲字符序列完成发送，根据链路速率生成相应速率的目标信号序列，并将目标信号序列通过PCIe光互连链路发送给对端，以便对端基于目标信号序列保持稳定工作。
本实施例中，当判定本次电气空闲字符序列完成发送时，根据链路速率生成相应速率的目标信号序列，并将目标信号序列通过PCIe光互连链路发送给对端，以便对端通过不断接收目标信号序列保持稳定工作。可以理解的是，PCIe光互连链路建立过程中会因电气空闲状态导致链路建立失败的主要原因在于，从电气空闲状态到正常数据传输装状态时链路会存储数据速率的突变，然而，光模块接收端的跨阻抗放大器(Trans-Impendence Amplifier，TIA)在接收到突发信号时需要一段时间才能稳定工作，在稳定工作前的这段时间TIA无法准确将前端光电流信号转化为正确的电压信号，也就无法从数据中提取时钟信号，进而导致链路建立失败。本实施例中，利用目标信号序列保持跨阻抗放大器一直处于正常工作状态，从而避免因电气空闲状态导致链路建立失败的问题。
本实施例中，根据链路速率生成相应速率的目标信号序列，可以包括：在链路速率的基础上根据预设增减范围确定出目标速率，根据目标速率生成 目标信号序列。即可以在链路速率的基础上适当减或适当增或保持不变得到目标速率，该目标速率只要与链路速率的差异不会大到导致跨阻抗放大器需要一段时间去适应即可，在某些情况下，可以在允许范围内选择一个最低速率，这样既能避免链路建立失败的问题，也可以节约资源。
本实施例中，将目标信号序列通过PCIe光互连链路发送给对端，可以包括：将目标信号序列通过本地的光发射组件进行电光转换后，通过PCIe光互连链路发送给对端的光接收组件。即利用光发射组件将目标信号序列的电信号转换为光信号，通过光纤将光信号传输到对端。需要理解的是，本实施例中的本地和对端只是站在不同角度的描述，发送端和接收端同理，但是每个终端都会对应一个相同的旁路模块用于实现上述步骤。
相关技术中，还有采用时钟数据恢复电路的方式，其在面对突发信号时可以将本地参考时钟作为输入数据发送至相位调整模块，以保证CDR(clock Data Recovery，时钟数据恢复)模块可以恢复正确的时钟信号，虽然一定程度上解决数据信号紊乱时正确恢复时钟数据的工况，但是依然会面临突发模式下TIA无法迅速响应造成的稳定性问题，依然会导致链路训练过程中链路建立失败。而本实施例中，通过在发送端检测链路训练过程中标志进入电气空闲状态的EIOS序列，利用生成的相应速率的目标信号序列，保证链路发送端和接收端在进入电气空闲状态时光模块和光纤构成的光链路始终保持与进入电气空闲状态前的高速传输的活跃状态，避免接收端从电气空闲状态进入正常数据传输状态的突发信号传输模式，保持光模块接收端TIA始终处于稳定工作模式，完成链路训练过程并在发送端和接收端之间建立PCIe光互连链路。
本实施例中，对端基于目标信号序列保持稳定工作，可以包括：对端的光接收组件对接收到的光信号进行光电转换后，得到目标信号序列，并将目标信号序列转发给对端的旁路模块中的端接器件，以便对端的光模块内的跨阻抗放大器保持稳定工作。即光电转换后从电信号中提取得到目标信号序列，对端的跨阻抗放大器即可根据该目标信号序列继续工作。
本实施例中，对端的光接收组件对接收到的光信号进行光电转换后，得到目标信号序列，包括：对端的光接收组件对接收到的光信号进行光电转换得到电信号；检测电信号中是否存在目标信号序列；若存在目标信号序列，则执行将目标信号序列转发给对端的旁路模块中的端接器件的步骤；若不存在目标信号序列，则直接将电信号转发给终端设备。即先检测是否为目标信号序列，若不是目标信号序列则可能是正常数据信息或电气空闲字符序列，则直接发送给终端设备即可。
本实施例中，检测电信号中是否存在目标信号序列之前，还包括：检测电信号中是否存在电气空闲字符序列；若不存在电气空闲字符序列，则执行检测电信号中是否存在目标信号序列的步骤；若存在电气空闲字符序列，则根据电气空闲字符序列确定当前的链路速率并记录；对电气空闲字符序列进行计数，并根据计数值判断本次电气空闲字符序列是否发送完成；若本次电 气空闲字符序列发送完成，则准备接收目标信号序列；若本次电气空闲字符序列没有发送完成，则直接将电信号转发给终端设备。即由于电气空闲字符序列会在目标信号序列前传输，因此对端每次接收到信号后可以先检测电气空闲字符序列，再检测目标信号序列，提高检测效率。另外，上述方法适用用于基于PCIe5.0协议的CXL(Compute Express Link，计算快速链接)协议规范下的光互连链路建立。
由上可见，本实施例中获取电通路传输的上游数据信号，并检测上游数据信号中是否存在电气空闲字符序列；若存在电气空闲字符序列，则记录当前的链路速率，并通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成；当本次电气空闲字符序列完成发送，根据链路速率生成相应速率的目标信号序列，并将目标信号序列通过PCIe光互连链路发送给对端，以便对端基于目标信号序列保持稳定工作。
可见，通过根据电气空闲字符序列判断链路是否将要进入电气空闲状态，并在进入电气空闲状态后，通过生成相应速率的目标信号序列维持本地和接收端的工作状态，能够避免突发信号对跨阻抗放大器产生的冲击，实现服务器等主机和外部设备之间通过光纤建立PCIe链路，避免PCIe光互连链路建立过程中因电气空闲状态导致链路建立失败，即解决了链路退出电气空闲状态时互连链路会存在从无数据传输到高速数据信号传输的突发模式的问题。
在上述实施例的基础上，本申请还提供了一种可选的旁路模块结构，旁路模块包括码型生成器、数据信号选通器、码型检测控制器和端接器件；其中，码型检测控制器被配置为获取电通路传输的上游数据信号，检测上游数据信号中是否存在电气空闲字符序列，记录当前的链路速率，通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成，控制数据信号选通器的数据传输，控制码型生成器生成码型；码型生成器被配置为根据链路速率生成相应速率的目标信号序列；数据信号选通器被配置为获取电通路传输的上游数据信号，将目标信号序列通过PCIe光互连链路发送给对端；端接器件被配置为存储对端发送的目标信号序列。
例如图2所示，1为旁路模块，101为码型生成器，102为数据信号选通器，103为光发射组件，104为码型检测控制器，105为光接收组件，106为端接器件，201为与旁路模块连接的电通路，301为与光发射组件和光接收组件连接的光纤。当设备通过光纤301发送信号时，旁路模块1通过电通路201的接收通路(Rx)接收上游信号，接收的信号进入数据信号选通器102和码型检测控制器104，码型检测控制器104控制码型生成器101和数据信号选通器102，之后数据信号选通器102输出的信号经光发射组件103转化为光信号，最后通过光纤301向外传输。
本实施例中，码型检测控制器还被配置为接收对端发送的经过光接收组件进行光电转换后的电信号，控制数据信号选通器的信号传输通道；数据信号选通器还被配置为接收对端发送的经过光接收组件进行光电转换后的电信号，在电信号为目标信号序列时转发给端接器件，在电信号不是目标信号序 列时转发给终端设备。即当设备通过光纤301接收信号时，接收的信号经光接收组件105进行光电转换后输入数据信号选通器102和码型检测控制器104，码型检测控制器104控制数据信号选通器102以将输入的信号传入端节器件106或通过电通路201传输。
本实施例中，码型检测控制器支持识别PCIe链路训练过程中与电气空闲状态相关的码型。即码型检测控制器104需能识别PCIe链路训练过程中与EI相关的码型，包括但不限于ASIC(Application Specific Integrated Circuit)芯片、ARM(Advanced RISC Machines)芯片或FPGA(Field Programmable GateArray，现场可编程逻辑门阵列)芯片等，用以实现码型检测以及控制数据信号选通器的功能。
本实施例中，数据信号选通器支持的信号速率涵盖PCIe协议规定的信号速率。即数据信号选通器102用以实现信号选择通过，所支持信号速率需覆盖PCIe协议规定的信号速率，包括但不限于ASIC芯片、ARM芯片或FPGA芯片等，用以实现信号的选通功能。
本实施例中，码型生成器101可产生符合PCIe协议速率的码型，包括但不限于ASIC芯片、ARM芯片或FPGA芯片等，用以维持接收端光模块正常工作。
在上述实施例的基础上，本申请还提供了一种可选的发送端PCIe光互连方法，例如图3所示，包括以下步骤：
1、上游数据信号首先传入旁路模块内部的数据信号选通器和码型检测控制器；
2、码型检测控制器检测上游信号中是否有EIOS序列，若码型检测控制器检测上游信号中有EIOS序列则代表发送端将要进入电气空闲状态，此时码型检测控制器需根据EIOS序列判断当前链路速率，并对EIOS序列进行计数；若码型检测控制器检测上游信号中没有EIOS序列则代表发送端未进入电气空闲状态，码型检测控制器控制数据信号选通器直接传输上游数据信号；
3、若EIOS序列到达PCIe协议设定数目，代表发送端和接收端在完成本次EIOS序列的发送和接收后会进入电气空闲状态；首先通过数据信号选通器直接传输最后一个EIOS序列后，码型检测控制器控制码型生成器产生与当前链路速率相同的信号。并控制数据信号选通器传输码型生成器所生成的信号，以保证链路依然有高速信号传输；
4、若EIOS序列没有到达PCIe协议设定数目，此时对端设备还需等待发送端若干次EIOS序列才会进入电气空闲状态，码型检测控制器控制数据信号选通器直接传输上游数据信号，此时的数据信号为EIOS序列；
5、最终，经数据信号选通器传入的电信号通过光发送组件进行电光转换后经光纤传输到接收端。
在上述实施例的基础上，本申请还提供了一种可选的接收端PCIe光互连方法，例如图4所示，包括以下步骤：
1、首先，光接收组件将接收到的光信号转换为电信号后传入数据信号选通器和码型检测控制器；
2、码型检测控制器检测信号中是否有EIOS序列和码型生成器所产生的信号序列，若码型检测控制器检测信号中没有EIOS序列和码型生成器所产生的信号序列则表明发送端处于正常链路训练状态或正常数据传输状态，则码型检测控制器控制数据信号选通器直接传输电信号数据；
3、若码型检测控制器检测到信号中有EIOS序列，则代表发送端要进入电气空闲状态，此时码型检测控制器需根据EIOS序列判断当前链路速率，并对EIOS序列进行计数；
4、若EIOS序列达到PCIe协议设定数目，代表发送端已进入电气空闲状态，将不再发送训练序列或数据，此时码型检测控制器在传输完最后一个EIOS序列后，控制数据信号选通器将信号接入端接器件。
相应的，本申请实施例还公开了一种PCIe光互连链路系统，该系统包括：包括主机、光模块和前述的旁路模块；旁路模块包括码型生成器、数据信号选通器、码型检测控制器和端接器件；
数据信号选通器分别与主机、光模块中的光发射组件和光接收组件、码型生成器和端接器件相连；
码型检测控制器分别与主机、数据信号选通器、光接收组件和码型生成器相连。
本实施例中，旁路模块可以与本地的光发射组件和光接收组件集成在光模块内。例如图5所示为一种可选的PCIe光互连链路建立设备搭建的PCIe光互连系统结构示意图旁路模块1与光发射组件103和光接收组件105集成于光模块2中。服务器主机与旁路模块1直接相连的芯片可以为CPU(Central Processing Unit，中央处理器)、PCIe Switch(PCIe交换机)、PCIe Retimer(PCIe重定时器)、PCIe Redriver(PCIe重发器)等。终端设备与旁路模块1直接相连的芯片或器件可以为GPU(Graphics Processing Unit，图形处理器)、SSD(Solid State Drive，固态硬盘)、DRAM(Dynamic Random Access Memory，动态随机存取存储器)、PCIe Switch、PCIe Retimer、PCIe Redriver等。
本实施例中，旁路模块还可以作为独立器件分别与主机和光模块相连。例如图6示为一种可选的PCIe光互连链路建立设备搭建的PCIe光互连系统结构示意图，旁路模块1作为独立器件处于主机与光模块2之间。服务器主机与旁路模块1直接相连的芯片可以为CPU、PCIe Switch、PCIe Retimer、PCIe Redriver等。终端设备与旁路模块1直接相连的芯片或器件可以为GPU、SSD、DRAM、PCIe Switch、PCIe Retimer、PCIe Redriver等。
本实施例中，旁路模块还可以集成在PCIe信号中继器，PCIe信号中继器分别与主机和光模块相连。例如图7示为一种可选的PCIe光互连链路建立设备搭建的PCIe光互连系统结构示意图，旁路模块1被集成于PCIe Switch、PCIe Retimer、PCIe Redriver这三类PCIe信号中继器件5。服务器主机与PCIe信号中继器件5直接相连的核心芯片可以为CPU等。终端设备与PCIe信号中继器件5直接相连的芯片或器件可以为GPU、SSD、DRAM、PCIe Switch、 PCIe Retimer、PCIe Redriver等。
可见，旁路模块集成形式也较为灵活，可以作为单独的器件放置于主机和光模块之间，也可以集成与光模块或PCIe信号中继器等芯片中。
相应的，本申请实施例还公开了一种PCIe光互连链路建立装置，参见图8所示，该装置包括：
检测模块31，被配置为获取电通路传输的上游数据信号，并检测上游数据信号中是否存在电气空闲字符序列；
记录模块32，被配置为若存在电气空闲字符序列，则记录当前的链路速率，并通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成；
序列发送模块33，被配置为当本次电气空闲字符序列完成发送，根据链路速率生成相应速率的目标信号序列，并将目标信号序列通过PCIe光互连链路发送给对端，以便对端基于目标信号序列保持稳定工作。
由上可见，获取电通路传输的上游数据信号，并检测上游数据信号中是否存在电气空闲字符序列；若存在电气空闲字符序列，则记录当前的链路速率，并通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成；当本次电气空闲字符序列完成发送，根据链路速率生成相应速率的目标信号序列，并将目标信号序列通过PCIe光互连链路发送给对端，以便对端基于目标信号序列保持稳定工作。
可见，通过根据电气空闲字符序列判断链路是否将要进入电气空闲状态，并在进入电气空闲状态后，通过生成相应速率的目标信号序列维持本地和接收端的工作状态，能够避免突发信号对跨阻抗放大器产生的冲击，实现服务器等主机和外部设备之间通过光纤建立PCIe链路，避免PCIe光互连链路建立过程中因电气空闲状态导致链路建立失败，即解决了链路退出电气空闲状态时互连链路会存在从无数据传输到高速数据信号传输的突发模式的问题。
在一些可选实施例中，记录模块32具体可以包括：
链路速率确定单元，被配置为根据电气空闲字符序列的发送速率，确定当前PCIe光互连链路的链路速率并记录。
在一些可选实施例中，记录模块32具体可以包括：
计数单元，被配置为通过对电气空闲字符序列进行计数；电气空闲字符序列用于表征发送端将进入电气空闲状态；
判定单元，被配置为当计数值达到PCIe协议设定的目标值时判定本次电气空闲字符序列发送完成，否则，判定本次电气空闲字符序列没有发送完成。
在一些可选实施例中，PCIe光互连链路建立装置具体可以包括：
第一直传单元，被配置为在检测上游数据信号中是否存在电气空闲字符序列之后，若判定上游数据信号中不存在电气空闲字符序列，则直接通过PCIe光互连链路传输上游数据信号；
第二直传单元，被配置为若判定本次电气空闲字符序列没有发送完成，则直接通过PCIe光互连链路传输上游数据信号。
在一些可选实施例中，序列发送模块33具体可以包括：
速率确定单元，被配置为在链路速率的基础上根据预设增减范围确定出目标速率，根据目标速率生成目标信号序列。
在一些可选实施例中，序列发送模块33具体可以包括：
序列发送单元，被配置为将目标信号序列通过本地的光发射组件进行电光转换后，通过PCIe光互连链路发送给对端的光接收组件。
在一些可选实施例中，PCIe光互连链路建立装置具体可以包括：
目标信号序列获取单元，被配置为对端的光接收组件对接收到的光信号进行光电转换后，得到目标信号序列，并将目标信号序列转发给对端的旁路模块中的端接器件，以便对端的光模块内的跨阻抗放大器保持稳定工作。
在一些可选实施例中，目标信号序列获取单元具体可以包括：
电信号获取单元，被配置为对端的光接收组件对接收到的光信号进行光电转换得到电信号；
目标信号序列检测单元，被配置为检测电信号中是否存在目标信号序列；
执行单元，被配置为若存在目标信号序列，则执行将目标信号序列转发给对端的旁路模块中的端接器件的步骤。
在一些可选实施例中，目标信号序列获取单元具体可以包括：
转发单元，被配置为若不存在目标信号序列，则直接将电信号转发给终端设备。
在一些可选实施例中，目标信号序列获取单元具体可以包括：
气空闲字符序列检测单元，被配置为在检测电信号中是否存在目标信号序列之前，检测电信号中是否存在电气空闲字符序列；
执行单元，被配置为若不存在电气空闲字符序列，则执行检测电信号中是否存在目标信号序列的步骤。
在一些可选实施例中，目标信号序列获取单元具体可以包括：
记录单元，被配置为若存在电气空闲字符序列，则根据电气空闲字符序列确定当前的链路速率并记录；
判断单元，被配置为对电气空闲字符序列进行计数，并根据计数值判断本次电气空闲字符序列是否发送完成；
准备单元，被配置为若本次电气空闲字符序列发送完成，则准备接收目标信号序列。
在一些可选实施例中，目标信号序列获取单元具体可以包括：
转发单元，被配置为若本次电气空闲字符序列没有发送完成，则直接将电信号转发给终端设备。
在一些可选实施例中，旁路模块具体可以与本地的光发射组件和光接收组件集成在光模块内。
在一些可选实施例中，旁路模块具体可以作为独立器件分别与主机和光模块相连。
在一些可选实施例中，旁路模块具体可以集成在PCIe信号中继器，PCIe 信号中继器分别与主机和光模块相连。
在一些可选实施例中，旁路模块具体可以包括码型生成器、数据信号选通器、码型检测控制器和端接器件；
码型检测控制器被配置为获取电通路传输的上游数据信号，检测上游数据信号中是否存在电气空闲字符序列，记录当前的链路速率，通过对电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成，控制数据信号选通器的数据传输，控制码型生成器生成码型；
码型生成器被配置为根据链路速率生成相应速率的目标信号序列；
数据信号选通器被配置为获取电通路传输的上游数据信号，将目标信号序列通过PCIe光互连链路发送给对端；
端接器件被配置为存储对端发送的目标信号序列。
在一些可选实施例中，码型检测控制器还被配置为接收对端发送的经过光接收组件进行光电转换后的电信号，控制数据信号选通器的信号传输通道；
数据信号选通器还被配置为接收对端发送的经过光接收组件进行光电转换后的电信号，在电信号为目标信号序列时转发给端接器件，在电信号不是目标信号序列时转发给终端设备。
在一些可选实施例中，码型检测控制器支持识别PCIe链路训练过程中与电气空闲状态相关的码型。
在一些可选实施例中，数据信号选通器支持的信号速率涵盖PCIe协议规定的信号速率。
本申请实施例还公开了一种电子设备，参见图9所示，图中的内容不能被认为是对本申请的使用范围的任何限制。
图9为本申请实施例提供的一种电子设备40的结构示意图。该电子设备40，具体可以包括：至少一个处理器41、至少一个存储器42、电源43、通信接口44、输入输出接口45和通信总线46。其中，存储器42被配置为存储计算机程序，计算机程序由处理器41加载并执行，以实现前述任一实施例公开的PCIe光互连链路建立方法中的相关步骤。
本实施例中，电源43被配置为为电子设备40上的各硬件设备提供工作电压；通信接口44能够为电子设备40创建与外界设备之间的数据传输通道，其所遵循的通信协议是能够适用于本申请技术方案的任意通信协议，在此不对其进行具体限定；输入输出接口45，被配置为获取外界输入数据或向外界输出数据，其具体的接口类型可以根据具体应用需要进行选取，在此不进行具体限定。
另外，存储器42作为资源存储的载体，可以是只读存储器、随机存储器、磁盘或者光盘等，其上所存储的资源包括操作系统421、计算机程序422及包括上游数据信号在内的数据423等，存储方式可以是短暂存储或者永久存储。
其中，操作系统421被配置为管理与控制电子设备40上的各硬件设备以及计算机程序422，以实现处理器41对存储器42中海量数据423的运算与处理，其可以是WindowsServer(Windows服务器)、Netware(一种网络操作系 统)、Unix(一种操作系统)、Linux(一种操作系统内核)等。计算机程序422除了包括能够被配置为完成前述任一实施例公开的由电子设备40执行的PCIe光互连链路建立方法的计算机程序之外，还可以包括能够被配置为完成其他特定工作的计算机程序。
本申请实施例还公开了一种计算机非易失性可读存储介质，计算机非易失性可读存储介质中存储有计算机可执行指令，计算机可执行指令被处理器加载并执行时，实现前述任一实施例公开的PCIe光互连链路建立方法步骤。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
结合本文中所公开的实施例描述的方法或算法的步骤可以直接用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(Random Access Memory，RAM)、内存、只读存储器(Read-Only Memory，ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM(Compact Disc Read-Only Memory，紧凑型光盘只读存储器)、或技术领域内所公知的任意其它形式的非易失性可读存储介质中。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个......”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上对本申请所提供的一种PCIe光互连链路建立方法、装置、设备及非易失性可读存储介质进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (23)

  1. 一种高速串行计算机扩展总线标准PCIe光互连链路建立方法，其特征在于，应用于预先创建的旁路模块，包括：
    获取电通路传输的上游数据信号，并检测所述上游数据信号中是否存在电气空闲字符序列；
    若存在所述电气空闲字符序列，则记录当前的链路速率，并通过对所述电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成；
    当本次电气空闲字符序列完成发送，根据所述链路速率生成相应速率的目标信号序列，并将所述目标信号序列通过PCIe光互连链路发送给对端，以便对端基于所述目标信号序列保持稳定工作。
  2. 根据权利要求1所述的PCIe光互连链路建立方法，其特征在于，所述记录当前的链路速率，包括：
    根据所述电气空闲字符序列的发送速率，确定当前PCIe光互连链路的链路速率并记录。
  3. 根据权利要求1所述的PCIe光互连链路建立方法，其特征在于，所述通过对所述电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成，包括：
    通过对所述电气空闲字符序列进行计数；所述电气空闲字符序列用于表征发送端将进入电气空闲状态；
    当计数值达到PCIe协议设定的目标值时判定本次电气空闲字符序列发送完成，否则，判定本次电气空闲字符序列没有发送完成。
  4. 根据权利要求1所述的PCIe光互连链路建立方法，其特征在于，所述检测所述上游数据信号中是否存在电气空闲字符序列之后，还包括：
    若判定所述上游数据信号中不存在电气空闲字符序列，则直接通过所述PCIe光互连链路传输所述上游数据信号；
    所述通过对所述电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成之后，还包括：
    若判定本次电气空闲字符序列没有发送完成，则直接通过所述PCIe光互连链路传输所述上游数据信号。
  5. 根据权利要求1所述的PCIe光互连链路建立方法，其特征在于，所述根据所述链路速率生成相应速率的目标信号序列，包括：
    在所述链路速率的基础上根据预设增减范围确定出目标速率，根据所述目标速率生成目标信号序列。
  6. 根据权利要求1所述的PCIe光互连链路建立方法，其特征在于，所述将所述目标信号序列通过PCIe光互连链路发送给对端，包括：
    将所述目标信号序列通过本地的光发射组件进行电光转换后，通过所述PCIe光互连链路发送给对端的光接收组件。
  7. 根据权利要求1所述的PCIe光互连链路建立方法，其特征在于，所述对端基于所述目标信号序列保持稳定工作，包括：
    所述对端的光接收组件对接收到的光信号进行光电转换后，得到所述目标信号序列，并将所述目标信号序列转发给所述对端的旁路模块中的端接器件，以便所述对端的光模块内的跨阻抗放大器保持稳定工作。
  8. 根据权利要求7所述的PCIe光互连链路建立方法，其特征在于，所述对端的光接收组件对接收到的光信号进行光电转换后，得到所述目标信号序列，包括：
    所述对端的光接收组件对接收到的光信号进行光电转换得到电信号；
    检测所述电信号中是否存在所述目标信号序列；
    若存在所述目标信号序列，则执行所述将所述目标信号序列转发给所述对端的旁路模块中的端接器件的步骤。
  9. 根据权利要求8所述的PCIe光互连链路建立方法，其特征在于，所述检测所述电信号中是否存在所述目标信号序列之后，还包括：
    若不存在所述目标信号序列，则直接将所述电信号转发给终端设备。
  10. 根据权利要求8所述的PCIe光互连链路建立方法，其特征在于，所述检测所述电信号中是否存在所述目标信号序列之前，还包括：
    检测所述电信号中是否存在电气空闲字符序列；
    若不存在所述电气空闲字符序列，则执行所述检测所述电信号中是否存在所述目标信号序列的步骤。
  11. 根据权利要求10所述的PCIe光互连链路建立方法，其特征在于，所述检测所述电信号中是否存在电气空闲字符序列之后，还包括：
    若存在所述电气空闲字符序列，则根据所述电气空闲字符序列确定当前的链路速率并记录；
    对所述电气空闲字符序列进行计数，并根据计数值判断本次电气空闲字符序列是否发送完成；
    若本次电气空闲字符序列发送完成，则准备接收所述目标信号序列。
  12. 根据权利要求11所述的PCIe光互连链路建立方法，其特征在于，所述根据计数值判断本次电气空闲字符序列是否发送完成之后，还包括：
    若本次电气空闲字符序列没有发送完成，则直接将所述电信号转发给终端设备。
  13. 根据权利要求1所述的PCIe光互连链路建立方法，其特征在于，所述旁路模块与本地的光发射组件和光接收组件集成在光模块内。
  14. 根据权利要求1所述的PCIe光互连链路建立方法，其特征在于，所述旁路模块作为独立器件分别与主机和光模块相连。
  15. 根据权利要求1所述的PCIe光互连链路建立方法，其特征在于，所述旁路模块集成在PCIe信号中继器，所述PCIe信号中继器分别与主机和光模块相连。
  16. 根据权利要求1至15任一项所述的PCIe光互连链路建立方法，其特征在于，所述旁路模块包括码型生成器、数据信号选通器、码型检测控制器和端接器件；
    所述码型检测控制器被配置为获取电通路传输的上游数据信号，检测所 述上游数据信号中是否存在电气空闲字符序列，记录当前的链路速率，通过对所述电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成，控制所述数据信号选通器的数据传输，控制所述码型生成器生成码型；
    所述码型生成器被配置为根据所述链路速率生成相应速率的目标信号序列；
    所述数据信号选通器被配置为获取电通路传输的上游数据信号，将所述目标信号序列通过PCIe光互连链路发送给对端；
    所述端接器件被配置为存储对端发送的目标信号序列。
  17. 根据权利要求16所述的PCIe光互连链路建立方法，其特征在于，所述码型检测控制器还被配置为接收对端发送的经过光接收组件进行光电转换后的电信号，控制所述数据信号选通器的信号传输通道；
    所述数据信号选通器还被配置为接收对端发送的经过光接收组件进行光电转换后的电信号，在所述电信号为目标信号序列时转发给所述端接器件，在所述电信号不是目标信号序列时转发给终端设备。
  18. 根据权利要求16所述的PCIe光互连链路建立方法，其特征在于，所述码型检测控制器支持识别PCIe链路训练过程中与电气空闲状态相关的码型。
  19. 根据权利要求16所述的PCIe光互连链路建立方法，其特征在于，所述数据信号选通器支持的信号速率涵盖PCIe协议规定的信号速率。
  20. 一种PCIe光互连链路建立装置，其特征在于，包括：
    检测模块，被配置为获取电通路传输的上游数据信号，并检测所述上游数据信号中是否存在电气空闲字符序列；
    记录模块，被配置为若存在所述电气空闲字符序列，则记录当前的链路速率，并通过对所述电气空闲字符序列进行计数判断本次电气空闲字符序列是否发送完成；
    序列发送模块，被配置为当本次电气空闲字符序列完成发送，根据所述链路速率生成相应速率的目标信号序列，并将所述目标信号序列通过PCIe光互连链路发送给对端，以便对端基于所述目标信号序列保持稳定工作。
  21. 一种电子设备，其特征在于，包括：
    存储器，被配置为保存计算机程序；
    处理器，被配置为执行所述计算机程序，以实现如权利要求1至19任一项所述的PCIe光互连链路建立方法。
  22. 一种计算机非易失性可读存储介质，其特征在于，被配置为存储计算机程序；其中计算机程序被处理器执行时实现如权利要求1至19任一项所述的PCIe光互连链路建立方法。
  23. 一种PCIe光互连链路系统，其特征在于，包括主机、光模块和如权利要求1至19任一项所述的旁路模块；所述旁路模块包括码型生成器、数据信号选通器、码型检测控制器和端接器件；
    所述数据信号选通器分别与所述主机、所述光模块中的光发射组件和光接收组件、所述码型生成器和所述端接器件相连；
    所述码型检测控制器分别与所述主机、所述数据信号选通器、所述光接收组件和所述码型生成器相连。
PCT/CN2024/070455 2023-06-28 2024-01-03 PCIe光互连链路建立方法、装置、设备、介质及系统 Ceased WO2025001039A1 (zh)

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