WO2024255590A1 - 绝缘体上硅半导体元器件及工艺平台、制造方法 - Google Patents

绝缘体上硅半导体元器件及工艺平台、制造方法 Download PDF

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Publication number
WO2024255590A1
WO2024255590A1 PCT/CN2024/095982 CN2024095982W WO2024255590A1 WO 2024255590 A1 WO2024255590 A1 WO 2024255590A1 CN 2024095982 W CN2024095982 W CN 2024095982W WO 2024255590 A1 WO2024255590 A1 WO 2024255590A1
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electrode
region
silicon
drift region
insulator semiconductor
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French (fr)
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WO2024255590A9 (zh
Inventor
张龙
刘斯扬
何乃龙
盘成务
李浩宇
张森
肖魁
宋亮
孙伟锋
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Southeast University
CSMC Technologies Fab2 Co Ltd
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Southeast University
CSMC Technologies Fab2 Co Ltd
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Priority to US18/996,449 priority Critical patent/US20260040611A1/en
Priority to JP2025504156A priority patent/JP2025525640A/ja
Publication of WO2024255590A1 publication Critical patent/WO2024255590A1/zh
Publication of WO2024255590A9 publication Critical patent/WO2024255590A9/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/421—Insulated-gate bipolar transistors [IGBT] on insulating layers or insulating substrates, e.g. thin-film IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/657—Lateral DMOS [LDMOS] FETs having substrates comprising insulating layers, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/129—Cathode regions of diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular to a silicon-on-insulator semiconductor component, a silicon-on-insulator semiconductor process platform, and a method for manufacturing the silicon-on-insulator semiconductor component.
  • Integrated high-voltage devices such as LDMOS, LIGBT, and high-voltage diodes, etc.
  • SOI silicon on insulator
  • the thickness of the buried oxide layer is related to the breakdown voltage, a thick buried oxide layer will make the thermal conductivity of the device worse, and when the buried oxide layer is thick enough, it will not contribute to the breakdown voltage, and it will also lead to an increase in cost. Therefore, it is unrealistic to increase the breakdown voltage by continuing to increase the thickness of the buried oxide layer after the breakdown voltage reaches a certain value.
  • a silicon-on-insulator semiconductor component comprising: a substrate; a buried dielectric layer, arranged on the substrate; a first electrode; a second electrode; a drift region, arranged on the buried dielectric layer; a step structure is formed on the upper surface of the drift region, the step structure comprises a first side close to the first electrode, a second side close to the second electrode, and a transition region between the first side and the second side, the upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side; wherein the first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.
  • the component is a lateral double diffused metal-oxide-semiconductor field effect transistor
  • the first electrode is a source
  • the second electrode is a drain
  • the lateral double diffused metal-oxide-semiconductor field effect transistor further includes a gate.
  • the component is a lateral insulated gate bipolar transistor
  • the first electrode is an emitter
  • the second electrode is a collector
  • the lateral insulated gate bipolar transistor further includes a gate.
  • the component is a diode
  • the first electrode is an anode
  • the second electrode is a cathode
  • the step structure is a step structure, including a first table located on the first side, a second table located on the second side, and a step wall located in the transition area, and the height difference between the second table and the first table is 3 to 10 microns.
  • the inclination angle of the step wall is 20 degrees to 90 degrees.
  • the drift region has a first conductivity type
  • the component also includes a second conductivity type protective layer
  • the second conductivity type protective layer is located in the drift region and surrounds the corner formed by the first mesa and the step wall and the corner formed by the second mesa and the step wall, the first conductivity type and the second conductivity type are opposite conductivity types.
  • the component further includes a first electrode lead-out region and a second electrode lead-out region, and the first electrode lead-out region and the second electrode lead-out region are disposed on the buried dielectric layer.
  • the component further includes a field oxide layer, wherein the field oxide layer extends from the upper surface of the drift region close to the The second side of the second electrode extends to be close to the first side of the first electrode.
  • the component further includes an interlayer dielectric layer, and the interlayer dielectric layer at least covers the field oxide layer, the first electrode lead-out region, and the second electrode lead-out region.
  • a silicon-on-insulator semiconductor process platform comprising the silicon-on-insulator semiconductor component described in any of the foregoing embodiments, and further comprising at least one of a complementary metal-oxide-semiconductor field effect transistor and a well resistor.
  • a method for manufacturing a silicon-on-insulator semiconductor component comprising: obtaining a wafer, the wafer comprising a substrate, a buried dielectric layer on the substrate, and a drift region on the buried dielectric layer; forming a step structure on the upper surface of the drift region by photolithography and etching, the step structure comprising a first side, a second side, and a transition region between the first side and the second side, the upper surface of the second side being higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side; forming a first electrode and a second electrode; the first side being a side close to the first electrode, and the second side being a side close to the second electrode; wherein the first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied to the second electrode is greater than the voltage applied to the first electrode.
  • the step structure is a step structure, including a first table located on the first side, a second table located on the second side, and a step wall located in the transition region.
  • the method further includes: forming a protective layer in the drift region at the step structure by ion implantation, and the protective layer surrounds the corner formed by the first table and the step wall and the corner formed by the second table and the step wall.
  • the etching is a reactive ion etching process.
  • a silicon-on-insulator semiconductor component comprising: obtaining a wafer, the wafer comprising a substrate, a buried dielectric layer on the substrate, and a first epitaxial layer on the buried dielectric layer; forming a second epitaxial layer in a partial area on the first epitaxial layer, forming a step structure at the junction of the first epitaxial layer and the second epitaxial layer, the step structure comprising a first side on one side of the second epitaxial layer, a second side on one side of the first epitaxial layer, and a transition zone between the first side and the second side; forming a first electrode and a second electrode, the first side being a side close to the first electrode, and the second side being a side close to the second electrode; wherein the first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied to the second electrode is greater than the voltage applied to the first electrode.
  • FIG1 is a schematic diagram of a cross-sectional structure of a device in an embodiment in which a silicon-on-insulator semiconductor component is an LDMOS;
  • FIG2a is a schematic cross-sectional view of a SOI LDMOS having a whole protective layer formed thereon in one embodiment
  • FIG2b is a schematic cross-sectional view of a SOI LDMOS having protective layers respectively surrounding two corners formed thereon in one embodiment
  • FIG2c is a schematic cross-sectional view of a SOI LDMOS formed by a secondary epitaxial growth method in one embodiment
  • FIG3 is a schematic diagram of a cross-sectional structure of a device in an embodiment in which the silicon-on-insulator semiconductor component is a LIGBT;
  • FIG4 is a cross-sectional schematic diagram of a LIGBT formed by a secondary epitaxial growth method in one embodiment
  • FIG5 is a schematic cross-sectional structure diagram of a diode in an embodiment in which the silicon-on-insulator semiconductor component is a diode;
  • FIG6 is a cross-sectional schematic diagram of a diode formed by a secondary epitaxial growth method in one embodiment
  • FIG7 is a schematic cross-sectional structure diagram of a silicon-on-insulator semiconductor process platform in one embodiment of the present application.
  • FIG8 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor component in an embodiment of the present application.
  • FIG. 9 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor component in another embodiment of the present application.
  • FIG10 is a flow chart of steps between steps S420 and S430 in an embodiment in which the device to be manufactured is SOI LDMOS;
  • FIG. 11a to 11e are schematic cross-sectional views of devices during the process of manufacturing SOI LDMOS according to the method shown in FIG10;
  • FIG12 is a flow chart of steps between steps S420 and S430 in an embodiment in which the manufactured device is a SOI LIGBT;
  • FIG. 13a to 13e are schematic cross-sectional views of devices during the process of manufacturing SOI LIGBT according to the method shown in FIG12;
  • step 14 is a flow chart of steps between steps S420 and S430 in one embodiment in which the device to be manufactured is an SOI diode;
  • 15a to 15d are schematic cross-sectional views of devices during the process of manufacturing an SOI diode according to the method shown in FIG. 14 ;
  • 16 is a schematic cross-sectional view of a silicon-on-insulator semiconductor process platform in one embodiment of forming a drift region step structure by reactive ion etching;
  • FIG. 17 is a schematic diagram of the cross-sectional structure of a silicon-on-insulator semiconductor process platform in an embodiment of forming a drift region step structure using secondary epitaxy.
  • Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application.
  • variations from the shapes shown due to, for example, manufacturing techniques and/or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing.
  • an implanted region shown as a rectangle typically has rounded or curved features and/or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the present application.
  • the semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field.
  • P+ type represents P-type with heavy doping concentration
  • P-type represents P-type with medium doping concentration
  • P-type represents P-type with light doping concentration
  • N+ type represents N-type with heavy doping concentration
  • N-type represents N-type with medium doping concentration
  • N-type represents N-type with light doping concentration
  • integrated high-voltage devices can usually only reach a breakdown voltage of 600V and it is difficult to reach a breakdown voltage of more than 1200V. And the withstand voltage of integrated high-voltage devices cannot be increased to more than 1200V by thickening the top silicon, because simply increasing the thickness of the top silicon cannot solve the problem of longitudinal early breakdown.
  • the exemplary SOI semiconductor process platform adopts a structure of thick buried oxide layer and thin top silicon, which can make the integrated high-voltage device reach a breakdown voltage of 1200V. This is because the breakdown voltage of the device will increase with the increase of the thickness of the buried oxide layer within a certain range, and the thin top silicon limits the energy obtained by the carrier through the longitudinal electric field, making the device less likely to be broken down.
  • the present application proposes a silicon-on-insulator semiconductor component, comprising:
  • a buried dielectric layer is disposed on the substrate
  • a drift region is disposed on the buried dielectric layer; a step structure is formed on the upper surface of the drift region, the step structure includes a first side close to the first electrode, a second side close to the second electrode, and a transition region between the first side and the second side, the upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side;
  • the first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.
  • the above-mentioned silicon-on-insulator semiconductor component adopts a structure in which the thickness of the drift region at the low-voltage end of the device is smaller than the thickness of the drift region at the high-voltage end when a reverse bias is applied. In this way, the breakdown point of the device can be controlled below the high-voltage end, so that the drift region can be completely depleted, and the breakdown voltage of the device can still be improved without increasing the thickness of the buried oxide layer.
  • the silicon-on-insulator semiconductor device further includes a first electrode lead-out region and a second electrode lead-out region.
  • the first electrode lead-out region and the second electrode lead-out region are disposed on the buried dielectric layer and have P-type doping or N-type doping.
  • the first electrode is located on the first electrode lead-out region and is electrically connected to the first electrode lead-out region; the second electrode is located on the second electrode lead-out region and is electrically connected to the second electrode lead-out region.
  • the drift region has a first conductivity type
  • the component also includes a second conductivity type protective layer
  • the second conductivity type protective layer is located in the drift region and surrounds the corner formed by the first table and the step wall and the corner formed by the second table and the step wall, the first conductivity type and the second conductivity type are opposite conductivity types.
  • FIG. 1 is an embodiment of a silicon-on-insulator semiconductor device that is a lateral double-diffused Metal-Oxide-Semiconductor Field Effect Transistor (LDMOS for short).
  • LDMOS includes a substrate 110, a buried dielectric layer 120, a drift region 130, a first electrode 162, a second electrode 164 and a gate 166.
  • the first electrode 162 is a source electrode
  • the second electrode 164 is a drain electrode.
  • the upper surface of the drift region 130 is higher on the side close to the drain electrode (hereinafter referred to as the drift region high side) than on the side close to the source electrode (hereinafter referred to as the drift region low side), thereby forming a step structure 131.
  • the LDMOS further includes a first electrode lead-out region (i.e., source region) 142 located at the lower side of the drift region and a second electrode lead-out region (i.e., drain region) 144 located at the upper side of the drift region.
  • the first electrode 162 i.e., source
  • the second electrode 164 i.e., drain
  • the gate 166 extends from the lower side of the drift region to the edge of the first electrode lead-out region 142 and may overlap with the first electrode lead-out region 142 by a certain area.
  • the LDMOS further includes a field oxide layer 147 , which extends from the high side of the drift region to the low side of the drift region. A portion of the gate 166 extends onto the field oxide layer 147 .
  • the LDMOS is an N-type LDMOS
  • the drift region 130 is an N-type drift region
  • the LDMOS further includes a P-type body region 132 located at the low side of the drift region and an N-well 134 located at the high side of the drift region.
  • the first electrode lead-out region 142 is an N+ region located in the P-type body region 132.
  • the second electrode lead-out region 144 is an N+ region located in the N-well 134.
  • the LDMOS further includes a body lead region 146 located in the P-type body region 132 .
  • the body lead region 146 is a P+ region.
  • the first electrode 162 is electrically connected to the body lead region 146 .
  • the LDMOS further includes an interlayer dielectric (ILD) layer 150.
  • the interlayer dielectric layer 150 covers structures such as the gate 166, the field oxide layer 147, the first electrode lead-out region 142, the second electrode lead-out region 144, and the body lead-out region 146.
  • the buried dielectric layer 120 is a buried oxide layer, and its material may be silicon dioxide.
  • the step structure is a step structure, including a first table located on the first side, a second table located on the second side, and a step wall located in the transition region, the height difference between the second table and the first table (corresponding to H 1 in FIG. 1 ) is 3 to 10 microns, and a suitable height difference can ensure that the drift region is completely depleted.
  • the inclination angle of the step wall (corresponding to ⁇ 1 in FIG. 1 ) is 20 degrees to 90 degrees, and a suitable ⁇ 1 can ensure that the device is not broken down prematurely at the angle.
  • the LDMOS When the LDMOS is reverse biased, a positive voltage is applied to the drain, and the gate 166, the source and the substrate are grounded.
  • the PN junction formed by the P-type body region 132 and the N-type drift region 130 is reverse biased.
  • the depletion region in the drift region 130 can be extended to the upper surface of the buried oxide layer at most, and the electric field of the depletion region can be almost unaffected by the substrate 110.
  • the presence of the buried oxide layer improves the longitudinal withstand voltage of the device and avoids premature breakdown in the longitudinal direction when the depletion region expands toward the drain end.
  • the drift region width at the source end is smaller than the drift region thickness at the drain end, so that when the device works in the reverse withstand voltage state, the depletion region tends to expand toward the drain end, and can be more easily depleted from the source end to the drain end, so that the drift region 130 can be completely depleted before longitudinal breakdown, and the breakdown point is controlled at the junction of the drain end drift region and the buried oxide layer.
  • the breakdown voltage of the device can be increased without increasing the thickness of the buried oxide layer, so that the breakdown voltage of the device can reach more than 1200V.
  • the aforementioned drift region step structure of the silicon-on-insulator semiconductor device can be formed by a reactive ion etching (RIE) method, or by a secondary epitaxial method.
  • the secondary epitaxy can obtain a more "vertical" drift region step, see FIG2c.
  • FIG2c may be an LDMOS formed by a secondary epitaxy method, and its main difference from the structure shown in FIG1 is that the step structure is steeper, and its specific structure is not described in detail here; the structure shown in FIG1 may be formed by a reactive ion etching method.
  • the 1200V process platform proposed in this application is compatible with the 600V process platform and has good compatibility.
  • FIG3 is a schematic diagram of the cross-sectional structure of a device in an embodiment in which the silicon-on-insulator semiconductor component is a lateral insulated gate bipolar transistor (LIGBT).
  • the LIGBT includes a substrate 210, a buried dielectric layer 220, a drift region 230, a first electrode 262, a second electrode 264, and a gate 266.
  • the first electrode 262 is an emitter
  • the second electrode 264 is a collector.
  • the upper surface of the drift region 230 is higher on the side close to the collector (hereinafter referred to as the high side of the drift region) than on the side close to the emitter (hereinafter referred to as the low side of the drift region), thereby forming a step structure 231.
  • the LIGBT in the embodiment shown in FIG3 is an N-type LIGBT
  • the drift region 230 is an N-type drift region
  • the LIGBT further includes a P-type first body region 234 and a second body region 236, and an N-well 232.
  • the N-well 232 and the second body region 236 are located at the high side of the drift region, and the first body region 234 is located at the low side of the drift region.
  • the first body region 234 is provided with a first N+ region 242 and a first P+ region 246, and the emitter 262 is electrically connected to the first N+ region 242 and the first P+ region 246.
  • the N-well 232 is provided with a second P+ region 248, the second body region 236 is provided with a second N+ region 244, and the collector 264 is electrically connected to the second N+ region 244, the second P+ region 248 and the second body region 236.
  • the gate 266 extends from the low side of the drift region to the edge of the first N+ region 242, and may overlap with the first N+ region 242 by a certain area. When reverse bias is applied to LIGBT, the collector is connected to high voltage and the emitter is connected to low voltage or ground.
  • the LIGBT further includes a field oxide layer 247 , which extends from the high side of the drift region to the low side of the drift region. A portion of the gate 266 extends onto the field oxide layer 247 .
  • the LIGBT further includes an interlayer dielectric layer 250.
  • the interlayer dielectric layer 250 covers structures such as the gate 266, the field oxide layer 247, the first N+ region 242, the first P+ region 246, the second N+ region 244, the second P+ region 248, and the second body region 236.
  • the step structure of the drift region of the LIGBT can also be formed by reactive ion etching or secondary epitaxy. Among them, secondary epitaxy can obtain a more "vertical" drift region step, see Figure 4.
  • the main difference between Figure 4 and Figure 3 is that the step structure is steeper, and its specific structure is not repeated.
  • the structure shown in Figure 3 can be formed by reactive ion etching, and the height difference H2 between the second table and the first table is 3 to 10 microns, and the inclination angle ⁇ 2 of the step wall is 20 degrees to 90 degrees.
  • the LIGBT further includes a protective layer.
  • the protective layer is located in the drift region, has a conductivity type opposite to that of the drift region, and surrounds a corner formed by the first mesa and the step wall and a corner formed by the second mesa and the step wall.
  • the protective layer can be a whole structure or a structure that surrounds the two corners respectively.
  • the diode includes a substrate 310, a buried dielectric layer 320, a drift region 330, a first electrode 362, and a second electrode 364.
  • the first electrode 362 is an anode
  • the second electrode 364 is a cathode.
  • the upper surface of the drift region 330 is higher on the side close to the cathode (hereinafter referred to as the high side of the drift region) than on the side close to the anode (hereinafter referred to as the low side of the drift region), thereby forming a step structure 331.
  • the diode further includes a first electrode lead-out region (i.e., anode region) 342 located at the lower side of the drift region and a second electrode lead-out region (i.e., cathode region) 344 located at the higher side of the drift region.
  • the first electrode 362 i.e., anode
  • the second electrode 364 i.e., cathode
  • the cathode is connected to a high voltage
  • the anode is connected to a low voltage or grounded.
  • the drift region 330 is an N-type drift region, and the diode further includes an N-well 334 located at the high side of the drift region.
  • the second electrode lead region 344 is an N+ region located in the N-well 334.
  • the first electrode lead region 342 is a P+ region located at the low side of the drift region.
  • the diode further includes a field oxide layer 347 , which extends from the high side of the drift region to the low side of the drift region.
  • the diode further includes an interlayer dielectric layer 350.
  • the interlayer dielectric layer 350 covers structures such as the field oxide layer 347, the first electrode lead-out region 342, and the second electrode lead-out region 344.
  • the step structure of the drift region of the diode can also be formed by reactive ion etching or secondary epitaxy. A more "vertical" drift region step is obtained, see FIG6.
  • the main difference between FIG6 and FIG5 is that the step structure is steeper, and its specific structure is not repeated.
  • the structure shown in FIG5 can be formed by reactive ion etching, and the height difference H3 between the second table and the first table is 3 to 10 microns, and the inclination angle ⁇ 3 of the step wall is 20 degrees to 90 degrees.
  • the diode further includes a protective layer.
  • the protective layer is located in the drift region, has a conductivity type opposite to that of the drift region, and surrounds a corner formed by the first mesa and the step wall and a corner formed by the second mesa and the step wall.
  • the protective layer can be a whole structure or a structure that surrounds the two corners respectively.
  • the present application also provides a silicon-on-insulator semiconductor process platform, which includes the silicon-on-insulator semiconductor components as described in any of the above embodiments, and also includes low-voltage devices and/or passive devices.
  • the low-voltage device can be a complementary metal-oxide-semiconductor field effect transistor (Complementary Metal-Oxide-Semiconductor Field Effect Transistor, referred to as CMOS), and the passive device can be a well resistor.
  • CMOS complementary Metal-oxide-semiconductor field effect transistor
  • Figure 7 is a schematic diagram of the cross-sectional structure of the silicon-on-insulator semiconductor process platform in an embodiment of the present application.
  • the silicon-on-insulator semiconductor process platform includes LDMOS, LIGBT, diode, CMOS and well resistor.
  • LDMOS, LIGBT and diode have been introduced in the previous text and will not be repeated here. Different devices are isolated from each other by isolation structures.
  • the height of the upper surface of the drift region of the CMOS and well resistor structures is the same as the height of the high side of the drift region.
  • FIG8 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor component in an embodiment of the present application, in which the step structure of the drift region is formed by etching, and the manufacturing method comprises the following steps:
  • the wafer includes a substrate, a buried dielectric layer on the substrate and a drift region on the buried dielectric layer.
  • the drift region can be formed by epitaxy on the buried oxide layer.
  • the step structure includes a first side, a second side, and a transition area between the first side and the second side.
  • the upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side.
  • etching is specifically carried out by using a reactive ion etching process, which has good anisotropy and can obtain a relatively steep transition zone.
  • the reactive ion etching has a fast etching speed and can accurately control the etching depth.
  • the first side is a side close to the first electrode
  • the second side is a side close to the second electrode.
  • the formed components have a structure in which (when a reverse bias is applied) the thickness of the drift region at the low-voltage end of the device is less than the thickness of the drift region at the high-voltage end.
  • the breakdown point of the device can be controlled below the high-voltage end, so that the drift region can be completely depleted, and the breakdown voltage of the device can still be improved without increasing the thickness of the buried oxide layer.
  • a step of forming a protective layer in the drift region at the step structure by ion implantation may also be included.
  • the protective layer surrounds the corner formed by the first table and the step wall and the corner formed by the second table and the step wall.
  • the conductivity type of the protective layer is opposite to the conductivity type of the drift region.
  • the protective layer can be a whole structure or a structure that surrounds two corners respectively. In an embodiment in which the protective layer is a whole structure, the length of the injection window of the protective layer (the length direction is the length direction of the conductive channel) is 110% to 120% of the length of the transition region (the length direction is the length direction of the conductive channel).
  • Figure 16 is a schematic diagram of the cross-sectional structure of a silicon-on-insulator semiconductor process platform in an embodiment in which a step structure of the drift region is formed by reactive ion etching, in which the protective layer is a whole structure.
  • the protective layer is a structure that surrounds two corners respectively, the length of each injection window of the protective layer is 5% to 10% of the length of the transition region.
  • FIG. 9 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor device in another embodiment of the present application.
  • a step structure of a drift region is formed by a secondary epitaxial growth method, including the following steps:
  • the wafer comprises a substrate, a buried dielectric layer on the substrate and a first epitaxial layer on the buried dielectric layer.
  • a partial area of the surface of the first epitaxial layer can be exposed by photolithography, and then epitaxy is performed to form a second epitaxial layer in the exposed area.
  • a step structure is formed at the junction of the first epitaxial layer and the second epitaxial layer, and the step structure includes a first side on one side of the second epitaxial layer, a second side on one side of the first epitaxial layer, and a transition area between the first side and the second side.
  • the step structure is a step structure, including a first table located on the first side, a second table located on the second side, and a step wall located in the transition zone, the height difference between the second table and the first table is 3 to 10 microns, and the inclination angle of the step wall is 20 degrees to 90 degrees.
  • a step of forming a protective layer in the drift region at the step structure by ion implantation may also be included.
  • the protective layer surrounds the corner formed by the first table and the step wall and the corner formed by the second table and the step wall.
  • the conductivity type of the protective layer is opposite to the conductivity type of the drift region.
  • the protective layer can be a whole structure or a structure that surrounds two corners respectively. In an embodiment in which the protective layer is a whole structure, the length of the injection window of the protective layer (the length direction is the length direction of the conductive channel) is 110% to 120% of the length of the transition region (the length direction is the length direction of the conductive channel).
  • FIG. 17 is a schematic diagram of the cross-sectional structure of a silicon-on-insulator semiconductor process platform in an embodiment in which a step structure of a drift region is formed by secondary epitaxy, in which the protective layer is a structure that surrounds two corners.
  • the manufacturing method of SOI LDMOS further includes the following steps after step S420:
  • the P-type body region 132 and the N-well 134 may be formed by photolithography and ion implantation, as shown in Fig. 11b.
  • the P-type body region 132 is formed on a first side of the step structure, and the N-well 134 is formed on a second side of the step structure.
  • a field oxide layer 147 is formed on the surface of the drift region 130, between the P-type body region 132 and the N-well 134, as shown in Fig. 11c.
  • the field oxide layer 147 can be formed by deposition or thermal oxidation.
  • the gate 166 extends from the P-type body region 132 to the field oxide layer 147.
  • the gate 166 may be made of polysilicon and may be formed by deposition, photolithography, and etching.
  • an N+ source region i.e., a first electrode lead-out region 142
  • an N+ drain region i.e., a second electrode lead-out region 144
  • a P+ body lead-out region 146 is formed in a P-type body region 132 .
  • step S430 to form a first electrode 162 and a second electrode 164, and obtain the structure shown in FIG1 .
  • the first electrode 162 is electrically connected to the N+ source region
  • the second electrode 164 is electrically connected to the N+ drain region.
  • steps S421 to S425 are also applicable to the embodiment of forming a step structure of the drift region by secondary epitaxy, except that the step structure formed by secondary epitaxy is steeper.
  • the manufacturing method of SOI LIGBT further includes the following steps after step S420:
  • the first body region 234 and the N-well 232 may be formed by photolithography and ion implantation, as shown in Fig. 13b.
  • the first body region 234 is formed on a first side of the step structure, and the N-well 232 is formed on a second side of the step structure.
  • a field oxide layer 247 is formed on the surface of the drift region 130, between the first body region 234 and the N well 232, as shown in Fig. 13c.
  • the field oxide layer 247 can be formed by deposition or thermal oxidation.
  • the gate 266 extends from the first body region 234 to the field oxide layer 247.
  • the gate 266 may be made of polysilicon and may be formed by deposition, photolithography, and etching.
  • a first N+ region 242 and a first P+ region 246 are formed in the first body region 234.
  • a second P+ region 248 is formed in the N well 232, and a second N+ region 244 is formed in the second body region 236.
  • step S430 is performed to form a first electrode 262 and a second electrode 264, and the structure shown in FIG3 is obtained.
  • the first electrode 262 is electrically connected to the first N+ region 242 and the first P+ region 246, and the second electrode 264 is electrically connected to the second P+ region 248, the second N+ region 244 and the second body region 236.
  • steps S621 to S625 are also applicable to the embodiment of forming a step structure of the drift region by secondary epitaxy, except that the step structure formed by secondary epitaxy will be steeper.
  • the method for manufacturing SOI diode further includes the following steps after step S420:
  • the N-well 334 may be formed by photolithography and ion implantation, as shown in Fig. 15b.
  • the N-well 334 is formed on the second side of the step structure.
  • a field oxide layer 347 is formed on the surface of the drift region 330, as shown in Fig. 15c.
  • the field oxide layer 347 can be formed by deposition or thermal oxidation.
  • the N+ cathode region ie, the second electrode lead-out region 344
  • the P+ anode region ie, the first electrode lead-out region 342
  • step S430 to form a first electrode 362 and a second electrode 364, and obtain the structure shown in FIG5 .
  • the first electrode 362 is electrically connected to the P+ anode region
  • the second electrode 364 is electrically connected to the N+ cathode region.
  • steps S721 to S724 are also applicable to the embodiment of forming a step structure of the drift region by secondary epitaxy, except that the step structure formed by secondary epitaxy will be steeper.

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Abstract

本申请涉及一种绝缘体上硅半导体元器件，包括：衬底；掩埋介质层，设于所述衬底上；第一电极；第二电极；漂移区，设于所述掩埋介质层上；所述漂移区的上表面形成落差结构，所述落差结构包括靠近所述第一电极的第一侧、靠近所述第二电极的第二侧、以及所述第一侧与第二侧之间的过渡区，所述第二侧的上表面高于所述第一侧的下表面，从而使所述漂移区在所述第二侧的厚度大于在所述第一侧的厚度；其中，所述第一电极和第二电极被配置为：在所述元器件被施加反向偏压时，第二电极施加的电压大于第一电极施加的电压。

Description

绝缘体上硅半导体元器件及工艺平台、制造方法
相关申请
本申请要求2023年06月15日提交的，申请号为2023107131192，名称为“绝缘体上硅半导体元器件及工艺平台、制造方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及半导体制造领域，特别是涉及一种绝缘体上硅半导体元器件，还涉及一种绝缘体上硅半导体工艺平台，以及一种绝缘体上硅半导体元器件的制造方法。
背景技术
随着超大规模集成电路在各个领域内的广泛应用，系统对高压高功率半导体器件的发展要求越来越高。利用绝缘体上硅(Silicon On Insulator,简称SOI)技术的集成型高压器件(如LDMOS、LIGBT以及高压Diode等)兼具了SOI技术和器件本身的优点，工作速度快、寄生效应低、高击穿电压、工艺制备简单、方便集成，因而得到了广泛的研究与应用。但常规的绝缘体上硅集成型高压器件难以实现1200V及以上的击穿电压。尽管埋氧层的厚度与击穿电压有关，但是厚的埋氧层会使器件的导热性变差，并且当埋氧层足够厚的时候对击穿电压将没有贡献，还会导致成本的上升，因此在击穿电压高到一定值后通过继续增加埋氧层的厚度来提高击穿电压是不现实的。
发明内容
第一方面，提供了一种绝缘体上硅半导体元器件，包括：衬底；掩埋介质层，设于所述衬底上；第一电极；第二电极；漂移区，设于所述掩埋介质层上；所述漂移区的上表面形成落差结构，所述落差结构包括靠近所述第一电极的第一侧、靠近所述第二电极的第二侧、以及所述第一侧与第二侧之间的过渡区，所述第二侧的上表面高于所述第一侧的下表面，以使所述漂移区在所述第二侧的厚度大于在所述第一侧的厚度；其中，所述第一电极和第二电极被配置为：在所述元器件被施加反向偏压时，第二电极施加的电压大于第一电极施加的电压。
在其中一个实施例中，所述元器件是横向双扩散金属-氧化物-半导体场效应晶体管，所述第一电极是源极，所述第二电极是漏极，所述横向双扩散金属-氧化物-半导体场效应晶体管还包括栅极。
在其中一个实施例中，所述元器件是横向绝缘栅双极晶体管，所述第一电极是发射极，所述第二电极是集电极，所述横向绝缘栅双极晶体管还包括栅极。
在其中一个实施例中，所述元器件是二极管，所述第一电极是阳极，所述第二电极是阴极。
在其中一个实施例中，所述落差结构为台阶结构，包括位于所述第一侧的第一台面、位于所述第二侧的第二台面、以及位于所述过渡区的阶壁，所述第二台面与第一台面的高度落差为3至10微米。
在其中一个实施例中，所述阶壁的倾斜角度为20度至90度。
在其中一个实施例中，所述漂移区具有第一导电类型，所述元器件还包括第二导电类型保护层，所述第二导电类型保护层位于所述漂移区中，并包围所述第一台面和阶壁形成的拐角以及所述第二台面和阶壁形成的拐角，所述第一导电类型和第二导电类型为相反的导电类型。
在其中一个实施例中，所述元器件还包括第一电极引出区和第二电极引出区，所述第一电极引出区和所述第二电极引出区设于所述掩埋介质层上。
在其中一个实施例中，所述元器件还包括场氧化层，所述场氧化层从所述漂移区的上表面靠近所述 第二电极的第二侧延伸至靠近所述第一电极的第一侧。
在其中一个实施例中，所述元器件还包括层间介质层，所述层间介质层至少覆盖所述场氧化层、所述第一电极引出区和所述第二电极引出区。
第二方面，提供了一种绝缘体上硅半导体工艺平台，包括前述任一实施例所述的绝缘体上硅半导体元器件，还包括互补金属-氧化物-半导体场效应晶体管和阱电阻中的至少一种。
第三方面，提供了一种绝缘体上硅半导体元器件的制造方法，包括：获取晶圆，所述晶圆包括衬底、衬底上的掩埋介质层及掩埋介质层上的漂移区；通过光刻和刻蚀使所述漂移区的上表面形成落差结构，所述落差结构包括第一侧、第二侧、以及所述第一侧与第二侧之间的过渡区，所述第二侧的上表面高于所述第一侧的下表面，以使所述漂移区在所述第二侧的厚度大于在所述第一侧的厚度；形成第一电极和第二电极；所述第一侧为靠近所述第一电极的一侧，所述第二侧为靠近所述第二电极的一侧；其中，所述第一电极和第二电极被配置为：在所述元器件被施加反向偏压时，第二电极施加的电压大于第一电极施加的电压。
在其中一个实施例中，所述落差结构为台阶结构，包括位于所述第一侧的第一台面、位于所述第二侧的第二台面、以及位于所述过渡区的阶壁，在所述形成第一电极和第二电极之前，所述方法还包括：通过离子注入在所述台阶结构处的漂移区中形成保护层，所述保护层包围所述第一台面和阶壁形成的拐角以及所述第二台面和阶壁形成的拐角。
在其中一个实施例中，所述刻蚀为反应离子刻蚀工艺。
第四方面，提供了另一种绝缘体上硅半导体元器件的制造方法，包括：获取晶圆，所述晶圆包括衬底、衬底上的掩埋介质层及掩埋介质层上的第一外延层；在所述第一外延层上的部分区域形成第二外延层，所述第一外延层和第二外延层的交界处形成落差结构，所述落差结构包括第二外延层一侧的第一侧、第一外延层一侧的第二侧、以及所述第一侧与第二侧之间的过渡区；形成第一电极和第二电极，所述第一侧为靠近所述第一电极的一侧，所述第二侧为靠近所述第二电极的一侧；其中，所述第一电极和第二电极被配置为：在所述元器件被施加反向偏压时，第二电极施加的电压大于第一电极施加的电压。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些申请的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的申请、目前描述的实施例和/或示例以及目前理解的这些申请的最佳模式中的任何一者的范围的限制。
图1是绝缘体上硅半导体元器件为LDMOS的一实施例中，器件的剖面结构示意图；
图2a是一实施例中形成有一整块保护层的SOI LDMOS的剖面示意图，图2b是一实施例中形成有分别包围两个拐角处的保护层的SOI LDMOS的剖面示意图，图2c是一实施例中采用二次外延的方法形成的SOI LDMOS的剖面示意图；
图3是绝缘体上硅半导体元器件为LIGBT的一实施例中，器件的剖面结构示意图；
图4是一实施例中采用二次外延的方法形成的LIGBT的剖面示意图；
图5是绝缘体上硅半导体元器件为二极管的一实施例中，二极管的剖面结构示意图；
图6是一实施例中采用二次外延的方法形成的二极管的剖面示意图；
图7是本申请一实施例中绝缘体上硅半导体工艺平台的剖面结构示意图；
图8是本申请一实施例中绝缘体上硅半导体元器件的制造方法的流程图；
图9是本申请另一实施例中绝缘体上硅半导体元器件的制造方法的流程图；
图10是制造的器件为SOI LDMOS的一实施例中步骤S420与S430之间的步骤的流程图；
图11a至图11e是根据图10所示的方法制造SOI LDMOS的过程中器件的剖面示意图；
图12是制造的器件为SOI LIGBT的一实施例中步骤S420与S430之间的步骤的流程图；
图13a至图13e是根据图12所示的方法制造SOI LIGBT的过程中器件的剖面示意图；
图14是制造的器件为SOI二极管的一实施例中步骤S420与S430之间的步骤的流程图；
图15a至图15d是根据图14所示的方法制造SOI二极管的过程中器件的剖面示意图；
图16是采用反应离子刻蚀形成漂移区台阶结构的一实施例中绝缘体上硅半导体工艺平台的剖面结构示意图；
图17是采用二次外延形成漂移区台阶结构的一实施例中绝缘体上硅半导体工艺平台的剖面结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。本说明书中的“连接”，如果被连接的电路、模块、单元等相互之间具有电信号或数据的传递，则应理解为“电性连接”、“通信连接”等。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。可以理解，“至少一个”是指一个或多个，“多个”是指两个或两个以上。“元件的至少部分”是指元件的部分或全部。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述申请的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本申请的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
对于常规的SOI半导体工艺平台而言，集成型高压器件通常只能达到600V级别的击穿电压而很难达到1200V以上的击穿电压。并且通过加厚顶硅无法将集成型高压器件的耐压提升至1200V以上，因为单纯地增加顶硅的厚度无法解决纵向提前击穿的问题。示例性的SOI半导体工艺平台采用厚埋氧层和薄顶硅的结构，可以使集成型高压器件达到1200V击穿电压。这是因为器件的击穿电压在一定范围内会随着埋氧层厚度的增大而增大，同时薄顶层硅限制了载流子通过纵向电场所获得的能量，使得器件更不容易被击穿。但是这种方案存在明显的缺点，因为SOI结构的埋氧层阻隔了热量向衬底传导，这就导致器件的散热性较差，造成器件局部晶格温度升高，引发器件的电学参数发生退化，这些退化现象使得器件可靠性变差，对于具有厚埋氧层的器件来说这个问题就更为明显。
本申请提出一种绝缘体上硅半导体元器件，包括：
衬底；
掩埋介质层，设于所述衬底上；
第一电极；
第二电极；
漂移区，设于所述掩埋介质层上；所述漂移区的上表面形成落差结构，所述落差结构包括靠近所述第一电极的第一侧、靠近所述第二电极的第二侧、以及所述第一侧与第二侧之间的过渡区，所述第二侧的上表面高于所述第一侧的下表面，从而使所述漂移区在所述第二侧的厚度大于在所述第一侧的厚度；
其中，所述第一电极和第二电极被配置为：在所述元器件被施加反向偏压时，第二电极施加的电压大于第一电极施加的电压。
上述绝缘体上硅半导体元器件，采用施加反向偏压时器件低压端的漂移区厚度小于高压端的漂移区厚度的结构，这样可以将器件的击穿点控制在高压端的下方，使得漂移区能够完全耗尽，在不增加埋氧层厚度的前提下依然可以提高器件的击穿电压。
在本申请的一个实施例中，绝缘体上硅半导体元器件还包括第一电极引出区和第二电极引出区。第一电极引出区和第二电极引出区设于掩埋介质层上，具有P型掺杂或N型掺杂。第一电极位于所述第一电极引出区上，与所述第一电极引出区电性连接；第二电极位于所述第二电极引出区上，与所述第二电极引出区电性连接。
在本申请的一个实施例中，漂移区具有第一导电类型，所述元器件还包括第二导电类型保护层，所述第二导电类型保护层位于所述漂移区中，并包围所述第一台面和阶壁形成的拐角以及所述第二台面和阶壁形成的拐角，所述第一导电类型和第二导电类型为相反的导电类型。
图1是绝缘体上硅半导体元器件为横向双扩散金属-氧化物-半导体场效应晶体管(Lateral double-diffused Metal-Oxide-Semiconductor Field Effect Transistor,简称为LDMOS)的一实施例中，器件 的剖面结构示意图。LDMOS包括衬底110、掩埋介质层120、漂移区130、第一电极162、第二电极164及栅极166。其中第一电极162是源极，第二电极164是漏极。漂移区130的上表面在靠近漏极的一侧(以下可以称为漂移区高侧)高于靠近源极的一侧(以下可以称为漂移区低侧)，从而形成落差结构131。
该LDMOS还包括位于漂移区低侧的第一电极引出区(即源极区)142和位于漂移区高侧的第二电极引出区(即漏极区)144。第一电极162(即源极)位于第一电极引出区142上，与第一电极引出区142电性连接。第二电极164(即漏极)位于第二电极引出区144上，与第二电极引出区144电性连接。在图1所示的实施例中，栅极166从漂移区低侧延伸至第一电极引出区142的边缘，并可以与第一电极引出区142有一定面积的交叠。
在图1所示的实施例中，该LDMOS还包括场氧层147，场氧层147从漂移区高侧延伸至漂移区低侧。栅极166的一部分延伸至场氧层147上。
在图1所示的实施例中，该LDMOS为N型LDMOS，漂移区130为N型漂移区，LDMOS还包括位于漂移区低侧的P型体区132和位于漂移区高侧的N阱134。第一电极引出区142为N+区，位于P型体区132中。第二电极引出区144为N+区，位于N阱134中。
在图1所示的实施例中，该LDMOS还包括位于P型体区132中的体引出区146。体引出区146为P+区。第一电极162与体引出区146电性连接。
在本申请的一个实施例中，该LDMOS还包括层间介质(ILD)层150。层间介质层150覆盖栅极166、场氧层147、第一电极引出区142、第二电极引出区144、体引出区146等结构。
在本申请的一个实施例中，掩埋介质层120为埋氧层，其材质可以为二氧化硅。
在本申请的一个实施例中，落差结构为台阶结构，包括位于所述第一侧的第一台面、位于所述第二侧的第二台面、以及位于所述过渡区的阶壁，所述第二台面与第一台面的高度落差(对应图1中的H1)为3至10微米，合适的高度差可以保证漂移区完全耗尽。所述阶壁的倾斜角度(对应图1中的θ1)为20度至90度，合适的θ1可以保证器件在该角度的位置不被提前击穿。
LDMOS施加反向偏压时，漏极加正电压，栅极166、源极和衬底接地。P型体区132和N型的漂移区130所构成的PN结反偏，随着外加偏压的不断增大，低掺杂的漂移区130内空间电荷区向漏端扩展。漂移区130内的耗尽区最多能够扩展至埋氧层上表面，且该耗尽区的电场可以几乎不受衬底110的影响，埋氧层的存在提升了器件的纵向耐压，避免在耗尽区向漏端扩展时在纵向上提前击穿。同时，源端的漂移区度小于漏端的漂移区厚度，这样就使得当器件工作在反向耐压状态时耗尽区更趋向于向漏端扩展，能够更容易的由源端耗尽到漏端，使得漂移区130能够在纵向击穿前完全耗尽，将击穿点控制在漏端漂移区与埋氧层交界处。这样在不增加埋氧层厚度的前提下依然可以提高器件的击穿电压，使器件的击穿电压达到1200V以上。
参见图2a，在本申请的一个实施例中，LDMOS还包括保护层136。保护层136位于漂移区130中，具有与漂移区130相反的导电类型，并包围第一台面和阶壁形成的拐角以及第二台面和阶壁形成的拐角。保护层136可以为图2a所示的一整块结构，也可以为图2b所示的分别包围两个拐角处的结构。通过在阶梯拐角处形成导电类型与漂移区130相反的保护层，能够避免因阶梯拐角导致的电场线集中而导致的器件提前击穿。
在本申请的一些实施例中，绝缘体上硅半导体元器件的前述漂移区台阶结构可以采用反应离子刻蚀(Reactive Ion Etching，RIE)的方法形成，或者采用二次外延的方法形成。其中二次外延可以获得更为“垂直”的漂移区台阶，参见图2c。图2c可以是采用二次外延的方法形成的LDMOS，其与图1所示结构的主要区别在于台阶结构更陡峭，在此不对其具体结构进行赘述；图1所示结构可以是采用反应离子刻蚀的方法形成。若采用一次外延加反应离子刻蚀的方法或二次外延的方法来实现本申请所提出的 漂移区阶梯结构，则可以实现1200V绝缘体上硅半导体工艺平台；若采用常规的一次外延的方法，就可以实现600V绝缘体上硅半导体工艺平台。因此本申请所提出的1200V工艺平台兼容600V工艺平台，具有良好的兼容性。
图3是绝缘体上硅半导体元器件为横向绝缘栅双极晶体管(Lateral Insulated Gate Bipolar Transistor，简称LIGBT)的一实施例中，器件的剖面结构示意图。LIGBT包括衬底210、掩埋介质层220、漂移区230、第一电极262、第二电极264及栅极266。其中第一电极262是发射极，第二电极264是集电极。漂移区230的上表面在靠近集电极的一侧(以下可以称为漂移区高侧)高于靠近发射极的一侧(以下可以称为漂移区低侧)，从而形成落差结构231。
图3所示实施例中的LIGBT为N型LIGBT，漂移区230为N型漂移区，LIGBT还包括P型的第一体区234和第二体区236，以及N阱232。N阱232和第二体区236位于漂移区高侧，第一体区234位于漂移区低侧。第一体区234中设有第一N+区242和第一P+区246，发射极262电性连接第一N+区242和第一P+区246。N阱232中设有第二P+区248，第二体区236中设有第二N+区244，集电极264电性连接第二N+区244、第二P+区248及第二体区236。在图3所示的实施例中，栅极266从漂移区低侧延伸至第一N+区242的边缘，并可以与第一N+区242有一定面积的交叠。LIGBT施加反向偏压时，集电极接高压，发射极接低压或接地。
在图3所示的实施例中，该LIGBT还包括场氧层247，场氧层247从漂移区高侧延伸至漂移区低侧。栅极266的一部分延伸至场氧层247上。
在本申请的一个实施例中，该LIGBT还包括层间介质层250。层间介质层250覆盖栅极266、场氧层247、第一N+区242、第一P+区246、第二N+区244、第二P+区248、第二体区236等结构。
LIGBT的漂移区台阶结构同样可以采用反应离子刻蚀或者二次外延的方法形成。其中二次外延可以获得更为“垂直”的漂移区台阶，参见图4。图4与图3的主要区别在于台阶结构更陡峭，其具体结构不再赘述。图3所示结构可以是采用反应离子刻蚀的方法形成，第二台面与第一台面的高度落差H2为3至10微米，阶壁的倾斜角度θ2为20度至90度。
在本申请的一个实施例中，LIGBT还包括保护层。保护层位于漂移区中，具有与漂移区相反的导电类型，并包围第一台面和阶壁形成的拐角以及第二台面和阶壁形成的拐角。保护层可以为一整块结构，也可以为分别包围两个拐角处的结构。
图5是绝缘体上硅半导体元器件为二极管的一实施例中，二极管的剖面结构示意图。二极管包括衬底310、掩埋介质层320、漂移区330、第一电极362及第二电极364。其中第一电极362是阳极，第二电极364是阴极。漂移区330的上表面在靠近阴极的一侧(以下可以称为漂移区高侧)高于靠近阳极的一侧(以下可以称为漂移区低侧)，从而形成落差结构331。
该二极管还包括位于漂移区低侧的第一电极引出区(即阳极区)342和位于漂移区高侧的第二电极引出区(即阴极区)344。第一电极362(即阳极)位于第一电极引出区342上，与第一电极引出区342电性连接。第二电极364(即阴极)位于第二电极引出区344上，与第二电极引出区344电性连接。二极管施加反向偏压时，阴极接高压，阳极接低压或接地。
在图5所示的实施例中，漂移区330为N型漂移区，二极管还包括位于漂移区高侧的N阱334。第二电极引出区344为N+区，位于N阱334中。第一电极引出区342为P+区，位于漂移区低侧。
在图5所示的实施例中，该二极管还包括场氧层347，场氧层347从漂移区高侧延伸至漂移区低侧。
在本申请的一个实施例中，该二极管还包括层间介质层350。层间介质层350覆盖场氧层347、第一电极引出区342、第二电极引出区344等结构。
二极管的漂移区台阶结构同样可以采用反应离子刻蚀或者二次外延的方法形成。其中二次外延可以 获得更为“垂直”的漂移区台阶，参见图6。图6与图5的主要区别在于台阶结构更陡峭，其具体结构不再赘述。图5所示结构可以是采用反应离子刻蚀的方法形成，第二台面与第一台面的高度落差H3为3至10微米，阶壁的倾斜角度θ3为20度至90度。
在本申请的一个实施例中，二极管还包括保护层。保护层位于漂移区中，具有与漂移区相反的导电类型，并包围第一台面和阶壁形成的拐角以及第二台面和阶壁形成的拐角。保护层可以为一整块结构，也可以为分别包围两个拐角处的结构。
本申请还提供一种绝缘体上硅半导体工艺平台，其包括如前述任一实施例所述的绝缘体上硅半导体元器件，还包括低压器件和/或无源器件。在本申请的一个实施例中，低压器件可以是互补金属-氧化物-半导体场效应晶体管(Complementary Metal-Oxide-Semiconductor Field Effect Transistor,简称CMOS)，无源器件可以是阱电阻。图7是本申请一实施例中绝缘体上硅半导体工艺平台的剖面结构示意图，在图7所示的实施例中，绝缘体上硅半导体工艺平台包括LDMOS、LIGBT、二极管、CMOS及阱电阻。其中LDMOS、LIGBT及二极管的结构已在前文介绍，此处不赘述。不同的器件之间通过隔离结构相互隔离。CMOS及阱电阻结构的漂移区上表面的高度与漂移区高侧的高度相同。
本申请相应提供一种绝缘体上硅半导体元器件的制造方法，可以用于制造以上任一实施例所述的绝缘体上硅半导体元器件。图8是本申请一实施例中绝缘体上硅半导体元器件的制造方法的流程图，该实施例中漂移区台阶结构采用刻蚀的方式形成，所述制造方法包括如下步骤：
S410，获取晶圆。
晶圆包括衬底、衬底上的掩埋介质层及掩埋介质层上的漂移区。漂移区可以是在埋氧层上通过外延形成。
S420，通过光刻和刻蚀使漂移区的上表面形成落差结构。
在光刻胶露出的区域刻蚀掉一定厚度的漂移区(外延层)，从而使得被刻蚀区域的外延层厚度小于其他部分的外延层厚度。即落差结构包括第一侧、第二侧、以及第一侧与第二侧之间的过渡区。第二侧的上表面高于第一侧的下表面，从而使漂移区在第二侧的厚度大于在第一侧的厚度。
在本申请的一个实施例中，刻蚀具体是采用反应离子刻蚀工艺，其各向异性好，可以获得较为陡峭的过渡区。并且反应离子刻蚀的刻蚀速度快，能够精准控制刻蚀深度。
S430，形成第一电极和第二电极。
所述第一侧为靠近第一电极的一侧，第二侧为靠近第二电极的一侧。
上述绝缘体上硅半导体元器件的制造方法，形成的元器件具有(施加反向偏压时)器件低压端的漂移区厚度小于高压端的漂移区厚度的结构，这样可以将器件的击穿点控制在高压端的下方，使得漂移区能够完全耗尽，在不增加埋氧层厚度的前提下依然可以提高器件的击穿电压。
在本申请的一个实施例中，在步骤S420之后、步骤S430之前，还可以包括通过离子注入在所述台阶结构处的漂移区中形成保护层的步骤。保护层包围所述第一台面和阶壁形成的拐角以及所述第二台面和阶壁形成的拐角。保护层的导电类型与漂移区的导电类型相反。保护层可以为一整块结构，也可以为分别包围两个拐角处的结构。在保护层为一整块结构的实施例中，保护层的注入窗口的长度(长度方向为导电沟道的长度方向)为过渡区的长度(长度方向为导电沟道的长度方向)的110％～120％。图16是采用反应离子刻蚀形成漂移区台阶结构的一实施例中绝缘体上硅半导体工艺平台的剖面结构示意图，该实施例中保护层为一整块结构。在保护层为分别包围两个拐角处的结构的实施例中，保护层的每个注入窗口的长度为过渡区的长度的5％～10％。
图9是本申请另一实施例中绝缘体上硅半导体元器件的制造方法的流程图，该实施例中漂移区台阶结构采用二次外延的方法形成，包括如下步骤：
S510，获取晶圆。
晶圆包括衬底、衬底上的掩埋介质层及掩埋介质层上的第一外延层。
S520，在第一外延层上的部分区域形成第二外延层。
可以通过光刻使第一外延层表面的部分区域露出，然后再进行外延，在该露出区域形成第二外延层。这样就使得第一外延层和第二外延层的交界处形成落差结构，落差结构包括第二外延层一侧的第一侧、第一外延层一侧的第二侧、以及第一侧与第二侧之间的过渡区。
S530，形成第一电极和第二电极。
在本申请的一个实施例中，所述落差结构为台阶结构，包括位于所述第一侧的第一台面、位于所述第二侧的第二台面、以及位于所述过渡区的阶壁，所述第二台面与第一台面的高度落差为3至10微米，所述阶壁的倾斜角度为20度至90度。
在本申请的一个实施例中，在步骤S520之后、步骤S530之前，还可以包括通过离子注入在所述台阶结构处的漂移区中形成保护层的步骤。保护层包围所述第一台面和阶壁形成的拐角以及所述第二台面和阶壁形成的拐角。保护层的导电类型与漂移区的导电类型相反。保护层可以为一整块结构，也可以为分别包围两个拐角处的结构。在保护层为一整块结构的实施例中，保护层的注入窗口的长度(长度方向为导电沟道的长度方向)为过渡区的长度(长度方向为导电沟道的长度方向)的110％～120％。在保护层为分别包围两个拐角处的结构的实施例中，保护层的每个注入窗口的长度为过渡区的长度的5％～10％。图17是采用二次外延形成漂移区台阶结构的一实施例中绝缘体上硅半导体工艺平台的剖面结构示意图，该实施例中保护层为包围两个拐角处的结构。
以制造SOI LDMOS为例，步骤S420完成后的结构如图11a所示。参见图10，SOI LDMOS的制造方法在步骤S420之后还包括如下步骤：
S421，形成P型体区和N阱。
可以通过光刻和离子注入形成P型体区132和N阱134，参见图11b。P型体区132形成于落差结构的第一侧，N阱134形成于落差结构的第二侧。
S422，形成场氧层。
在漂移区130的表面、P型体区132和N阱134之间形成场氧层147，参见图11c。场氧层147可以通过淀积或热氧化的方式形成。
S423，形成栅极。
在图11d所示的实施例中，栅极166从P型体区132上延伸至场氧层147上。栅极166的材质可以为多晶硅。栅极166可以通过淀积、光刻及刻蚀的方式形成。
S424，形成源极区、漏极区及体引出区。
参见图11e，N+源极区(即第一电极引出区142)形成于P型体区132中，N+漏极区(即第二电极引出区144)形成于N阱134中，P+的体引出区146形成于P型体区132中。
S425，形成层间介质层及接触孔。
淀积层间介质层150，然后刻蚀层间介质层150形成接触孔。之后执行步骤S430形成第一电极162和第二电极164，即得到图1所示的结构。第一电极162与N+源极区电性连接，第二电极164与N+漏极区电性连接。上述步骤S421至S425除了适用于反应离子刻蚀形成漂移区台阶结构的实施例，也同样适用于二次外延形成漂移区台阶结构的实施例，只是二次外延形成的台阶结构更为陡峭。
以制造SOI LIGBT为例，步骤S420完成后的结构如图13a所示。参见图12，SOI LIGBT的制造方法在步骤S420之后还包括如下步骤：
S621，形成第一体区和N阱。
可以通过光刻和离子注入形成第一体区234和N阱232，参见图13b。第一体区234形成于落差结构的第一侧，N阱232形成于落差结构的第二侧。
S622，形成场氧层。
在漂移区130的表面、第一体区234和N阱232之间形成场氧层247，参见图13c。场氧层247可以通过淀积或热氧化的方式形成。
S623，形成栅极。
在图13d所示的实施例中，栅极266从第一体区234上延伸至场氧层247上。栅极266的材质可以为多晶硅。栅极266可以通过淀积、光刻及刻蚀的方式形成。
S624，形成第一N+区、第二N+区、第一P+区、第二P+区及第二体区。
参见图13e，第一N+区242和第一P+区246形成于第一体区234中。第二P+区248形成于N阱232中，第二N+区244形成于第二体区236中。
S625，形成层间介质层及接触孔。
淀积层间介质层250，然后刻蚀层间介质层250形成接触孔。之后执行步骤S430形成第一电极262和第二电极264，即得到图3所示的结构。第一电极262与第一N+区242、第一P+区246电性连接，第二电极264与第二P+区248、第二N+区244及第二体区236电性连接。上述步骤S621至S625除了适用于反应离子刻蚀形成漂移区台阶结构的实施例，也同样适用于二次外延形成漂移区台阶结构的实施例，只是二次外延形成的台阶结构会更为陡峭。
以制造SOI二极管为例，步骤S420完成后的结构如图15a所示。参见图14，SOI二极管的制造方法在步骤S420之后还包括如下步骤：
S721，形成N阱。
可以通过光刻和离子注入形成N阱334，参见图15b。N阱334形成于落差结构的第二侧。
S722，形成场氧层。
在漂移区330的表面形成场氧层347，参见图15c。场氧层347可以通过淀积或热氧化的方式形成。
S723，形成阳极区和阴极区。
参见图15d，N+阴极区(即第二电极引出区344)位于N阱334中，P+阳极区(即第一电极引出区342)形成于落差结构的第一侧。
S724，形成层间介质层及接触孔。
淀积层间介质层350，然后刻蚀层间介质层350形成接触孔。之后执行步骤S430形成第一电极362和第二电极364，即得到图5所示的结构。第一电极362与P+阳极区电性连接，第二电极364与N+阴极区电性连接。上述步骤S721至S724除了适用于反应离子刻蚀形成漂移区台阶结构的实施例，也同样适用于二次外延形成漂移区台阶结构的实施例，只是二次外延形成的台阶结构会更为陡峭。
应该理解的是，虽然本申请的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且本申请的流程图中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种绝缘体上硅半导体元器件，包括：
    衬底；
    掩埋介质层，设于所述衬底上；
    第一电极；
    第二电极；
    漂移区，设于所述掩埋介质层上；所述漂移区的上表面形成落差结构，所述落差结构包括靠近所述第一电极的第一侧、靠近所述第二电极的第二侧、以及所述第一侧与第二侧之间的过渡区，所述第二侧的上表面高于所述第一侧的下表面，以使所述漂移区在所述第二侧的厚度大于在所述第一侧的厚度；
    其中，所述第一电极和第二电极被配置为：在所述元器件被施加反向偏压时，第二电极施加的电压大于第一电极施加的电压。
  2. 根据权利要求1所述的绝缘体上硅半导体元器件，其中，所述元器件是横向双扩散金属-氧化物-半导体场效应晶体管，所述第一电极是源极，所述第二电极是漏极，所述横向双扩散金属-氧化物-半导体场效应晶体管还包括栅极。
  3. 根据权利要求1所述的绝缘体上硅半导体元器件，其中，所述元器件是横向绝缘栅双极晶体管，所述第一电极是发射极，所述第二电极是集电极，所述横向绝缘栅双极晶体管还包括栅极。
  4. 根据权利要求1所述的绝缘体上硅半导体元器件，其中，所述元器件是二极管，所述第一电极是阳极，所述第二电极是阴极。
  5. 根据权利要求1-4中任一项所述的绝缘体上硅半导体元器件，其中，所述落差结构为台阶结构，包括位于所述第一侧的第一台面、位于所述第二侧的第二台面、以及位于所述过渡区的阶壁，所述第二台面与第一台面的高度落差为3至10微米。
  6. 根据权利要求5所述的绝缘体上硅半导体元器件，其中所述阶壁的倾斜角度为20度至90度。
  7. 根据权利要求5所述的绝缘体上硅半导体元器件，其中，所述漂移区具有第一导电类型，所述元器件还包括第二导电类型保护层，所述第二导电类型保护层位于所述漂移区中，并包围所述第一台面和阶壁形成的拐角以及所述第二台面和阶壁形成的拐角，所述第一导电类型和第二导电类型为相反的导电类型。
  8. 根据权利要求5所述的绝缘体上硅半导体元器件，还包括第一电极引出区和第二电极引出区，所述第一电极引出区和所述第二电极引出区设于所述掩埋介质层上。
  9. 根据权利要求8所述的绝缘体上硅半导体元器件，还包括场氧化层，所述场氧化层从所述漂移区的上表面靠近所述第二电极的第二侧延伸至靠近所述第一电极的第一侧。
  10. 根据权利要求9所述的绝缘体上硅半导体元器件，还包括层间介质层，所述层间介质层至少覆盖所述场氧化层、所述第一电极引出区和所述第二电极引出区。
  11. 一种绝缘体上硅半导体工艺平台，其中，包括权利要求1-10中任一项所述的绝缘体上硅半导体元器件，还包括互补金属-氧化物-半导体场效应晶体管和阱电阻中的至少一种。
  12. 一种绝缘体上硅半导体元器件的制造方法，包括：
    获取晶圆，所述晶圆包括衬底、衬底上的掩埋介质层及掩埋介质层上的漂移区；
    通过光刻和刻蚀使所述漂移区的上表面形成落差结构，所述落差结构包括第一侧、第二侧、以及所述第一侧与第二侧之间的过渡区，所述第二侧的上表面高于所述第一侧的下表面，以使所述漂移区在所述第二侧的厚度大于在所述第一侧的厚度；
    形成第一电极和第二电极；所述第一侧为靠近所述第一电极的一侧，所述第二侧为靠近所述第二电极的一侧；
    其中，所述第一电极和第二电极被配置为：在所述元器件被施加反向偏压时，第二电极施加的电压大于第一电极施加的电压。
  13. 根据权利要求12所述的绝缘体上硅半导体元器件的制造方法，其中所述落差结构为台阶结构，包括位于所述第一侧的第一台面、位于所述第二侧的第二台面、以及位于所述过渡区的阶壁，在所述形成第一电极和第二电极之前，所述方法还包括：
    通过离子注入在所述台阶结构处的漂移区中形成保护层，所述保护层包围所述第一台面和阶壁形成的拐角以及所述第二台面和阶壁形成的拐角。
  14. 根据权利要求12所述的绝缘体上硅半导体元器件的制造方法，其中，所述刻蚀为反应离子刻蚀工艺。
  15. 一种绝缘体上硅半导体元器件的制造方法，包括：
    获取晶圆，所述晶圆包括衬底、衬底上的掩埋介质层及掩埋介质层上的第一外延层；
    在所述第一外延层上的部分区域形成第二外延层，所述第一外延层和第二外延层的交界处形成落差结构，所述落差结构包括第二外延层一侧的第一侧、第一外延层一侧的第二侧、以及所述第一侧与第二侧之间的过渡区；
    形成第一电极和第二电极，所述第一侧为靠近所述第一电极的一侧，所述第二侧为靠近所述第二电极的一侧；
    其中，所述第一电极和第二电极被配置为：在所述元器件被施加反向偏压时，第二电极施加的电压大于第一电极施加的电压。
PCT/CN2024/095982 2023-06-15 2024-05-29 绝缘体上硅半导体元器件及工艺平台、制造方法 Ceased WO2024255590A1 (zh)

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