WO2024255557A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2024255557A1
WO2024255557A1 PCT/CN2024/094893 CN2024094893W WO2024255557A1 WO 2024255557 A1 WO2024255557 A1 WO 2024255557A1 CN 2024094893 W CN2024094893 W CN 2024094893W WO 2024255557 A1 WO2024255557 A1 WO 2024255557A1
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WIPO (PCT)
Prior art keywords
metal layer
gate line
gate
display panel
layer
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2024/094893
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English (en)
French (fr)
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WO2024255557A9 (zh
Inventor
龙春平
徐健
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BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
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Application filed by BOE Technology Group Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP24822509.6A priority Critical patent/EP4730969A1/en
Publication of WO2024255557A1 publication Critical patent/WO2024255557A1/zh
Publication of WO2024255557A9 publication Critical patent/WO2024255557A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • Embodiments of the present invention relate to a display panel and a display device.
  • the display devices widely used in the display field include thin film transistor liquid crystal display devices (TFT-LCD) and active matrix organic light emitting diode (AMOLED) display devices, etc.
  • TFT-LCD thin film transistor liquid crystal display devices
  • AMOLED active matrix organic light emitting diode
  • AMOLED active matrix organic light emitting diode
  • Organic light-emitting diode display devices using active matrix organic light-emitting diodes as light-emitting elements are thinner and lighter than conventional liquid crystal display devices.
  • Organic light-emitting diode display devices also have the characteristics of fast response speed, wide viewing angle and low voltage drive. Therefore, organic light-emitting diode display devices can be widely used in cellular phones, portable information terminals, televisions and monitors.
  • the structure of an organic light-emitting diode display device mainly includes a cathode and an anode, and a light-emitting functional layer sandwiched between the cathode and the anode.
  • each sub-pixel has a switching transistor and a driving transistor. By adjusting the switching transistor and the driving transistor, the light-emitting layer in the organic light-emitting diode display device emits light.
  • At least one embodiment of the present invention provides a display panel and a display device, the display panel comprising: a pixel circuit arranged on a substrate, the pixel circuit comprising a sensing transistor, a driving transistor, a first gate line and a second gate line, wherein a first source-drain electrode of the sensing transistor and a first source-drain electrode of the driving transistor are electrically connected via a first connecting electrode; the first gate line and the second gate line extend in a first direction, and in a second direction intersecting the first direction, a spacer is arranged between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and the first connecting electrode, the first gate line, the second gate line and the spacer
  • a spacing portion is arranged between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and the first connecting electrode, the first gate line, the second gate line and the spacing portion are arranged on the same layer, so that the voltage change on the first
  • At least one embodiment of the present invention provides a display panel, comprising: a base substrate; a pixel circuit arranged on the base substrate, the pixel circuit comprising a sensing transistor, a driving transistor, a first gate line and a second gate line, wherein a first source-drain electrode of the sensing transistor and a first source-drain electrode of the driving transistor are electrically connected via a first connecting electrode; the first gate line and the second gate line extend in a first direction, and in a second direction intersecting the first direction, a spacer is arranged between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and the first connecting electrode, the first gate line, the second gate line and the spacer are arranged in the same layer.
  • the display panel provided by at least one embodiment of the present invention further includes a switching transistor and a storage capacitor arranged on the base substrate, wherein the first source and drain electrode of the switching transistor and the gate of the driving transistor are connected through a second connecting electrode, the first plate of the storage capacitor is connected to the second connecting electrode, and the second plate of the storage capacitor is connected to the first connecting electrode.
  • the display panel provided by at least one embodiment of the present invention further includes a first metal layer, an active layer, a second metal layer and a third metal layer stacked in sequence on the base substrate, wherein the first metal layer includes an initialization signal line extending in the second direction, a power supply voltage signal line at least partially extending in the second direction, the first electrode and a data line; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor and a channel region of the switching transistor; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor, a gate of the switching transistor and the second electrode; the third metal layer includes the first connecting electrode, the spacer, the second gate line extending in the first direction and the first gate line.
  • the first metal layer includes an initialization signal line extending in the second direction, a power supply voltage signal line at least partially extending in the second direction, the first electrode and a data line
  • the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor
  • the gate of the sensing transistor extends in the second direction to be electrically connected to the first gate line
  • the gate of the switching transistor extends in a direction opposite to the second direction to be electrically connected to the second gate line
  • the first gate line connected to the gate of the sensing transistor and the second gate line connected to the gate of the switching transistor are located on different sides of any one of the spacers in the second direction.
  • the third metal layer further includes A first connection structure, a second connection structure and a third connection structure extending in the second direction, wherein the orthographic projection of the first connection structure on the substrate is located within the orthographic projection of the initialization signal line on the substrate, the orthographic projection of the second connection structure on the substrate is located within the orthographic projection of the first electrode plate on the substrate, and the orthographic projection of the third connection structure on the substrate is located within the orthographic projection of the data line on the substrate.
  • the display panel provided by at least one embodiment of the present invention further includes a buffer layer arranged on the side of the first metal layer away from the base substrate, a gate insulation layer arranged between the active layer and the second metal layer, an interlayer insulation layer arranged between the second metal layer and the third metal layer, and a passivation layer and a planarization layer arranged on the side of the third metal layer away from the base substrate.
  • a first via structure and a third via structure are provided in the interlayer insulating layer, the third metal layer is electrically connected to the active layer through the first via structure, and the third metal layer is electrically connected to the second metal layer through the third via structure; a second via structure is passed through the interlayer insulating layer and the buffer layer, and the third metal layer is electrically connected to the first metal layer through the second via structure.
  • the first connection structure is electrically connected to the initialization signal line through the second via structure, and is electrically connected to the second source-drain electrode of the sensing transistor through the first via structure;
  • the second connection structure is electrically connected to the first source-drain electrode of the switching transistor through the first via structure, and is electrically connected to the second plate through the third via structure;
  • the third connection structure is electrically connected to the data line through the second via structure, and is electrically connected to the second source-drain electrode of the switching transistor through the first via structure.
  • At least a portion of the third metal layer has an overlapping area with the first metal layer and the second metal layer to form the storage capacitor between the first metal layer and the second metal layer, and to form a capacitor structure between the second metal layer and the third metal layer.
  • the orthographic projection of the first source-drain electrode of the sensing transistor on the base substrate overlaps with the orthographic projection of the power supply voltage signal line on the base substrate.
  • the power supply voltage signal line includes a first power supply voltage signal line extending in the second direction, wherein the first power supply voltage signal line It includes a first part, a second part and a third part extending in the second direction and connected in sequence, the first part and the third part have the same width in the first direction, the second part has a width in the first direction smaller than the first part, and one end of the second part in the second direction is connected to an edge of the first part close to the third part and away from the initialization signal line, and the other end of the second part in the second direction is connected to an edge of the third part close to the first part and away from the initialization signal line.
  • the orthographic projection of the first source-drain electrode of the sensing transistor on the base substrate is spaced apart from the orthographic projection of the second portion of the power supply voltage signal line on the base substrate.
  • the first electrode plate includes a first electrode plate sub-block and a second electrode plate sub-block connected to each other in the first direction
  • the second metal layer includes a first extension portion and a second extension portion extending from a portion of the second electrode plate corresponding to the second electrode plate sub-block in the second direction
  • two second connecting electrodes are respectively connected to the first extension portion and the second extension portion.
  • At least one embodiment of the present invention provides a display panel, further comprising an organic light emitting diode, wherein: Ast is the area of the storage capacitor, dgc is the minimum distance between the first gate line and the storage capacitor, Lc is the length of the side of the first plate sub-block adjacent to the first gate line, Wg is the width of the first gate line in the second direction, and THKILD is the thickness of the interlayer insulating layer corresponding to the storage capacitor.
  • V gON is a turn-on voltage of the second gate line
  • V gOFF is a turn-off voltage of the second gate line
  • Voled is a voltage across the organic light emitting diode
  • ⁇ is an optical constant.
  • the storage capacitor is a three-layer structure formed by the first metal layer, the second metal layer and the third metal layer.
  • THK BUF is the thickness of the buffer layer between the first metal layer and the second metal layer in the storage capacitor.
  • W DD is the length of the spacer between the first gate line and the first connecting electrode in the second direction
  • d gd is the minimum spacing between the first gate line and the spacer between the first gate line and the first connecting electrode
  • d sd is the minimum spacing between the first connecting electrode and the spacer between the first gate line and the first connecting electrode.
  • L c is the length of the side of the first plate sub-block adjacent to the first gate line
  • L p is the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction
  • R l is the ratio of the length of the side of the first plate sub-block adjacent to the first gate line to the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction.
  • Wc is the width of the storage capacitor in the first direction
  • Pitch is the width of a sub-pixel in the first direction
  • the display panel provided by at least one embodiment of the present invention further includes a first metal layer, an active layer, and a second metal layer stacked in sequence on the base substrate, wherein the first metal layer includes an initialization signal line extending in the second direction, a power supply voltage signal line at least partially extending in the second direction, the first electrode plate, and a data line; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, and a channel region of the switching transistor; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor, a gate of the switching transistor, the second electrode plate, the first connecting electrode, the spacer, the second gate line extending in the first direction, and the first gate line.
  • the first metal layer includes an initialization signal line extending in the second direction, a power supply voltage signal line at least partially extending in the second direction, the first electrode plate, and a data line
  • the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, and
  • the gate of the switching transistor is electrically connected to the second gate line
  • the gate of the sensing transistor is electrically connected to the first gate line
  • the second gate line connected to the gate of the switching transistor and the first gate line connected to the gate of the sensing transistor are located on different sides of the first electrode plate in the second direction, and in the second direction, the second connecting electrode is between the first connecting electrode and the second gate line connected to the gate of the switching transistor.
  • At least one embodiment of the present invention provides a display panel, further comprising a substrate disposed on the substrate A switching transistor on the drive transistor, wherein the first source-drain electrode of the switching transistor and the gate of the driving transistor are connected via a second connecting electrode.
  • the display panel provided by at least one embodiment of the present invention further includes a first metal layer, an active layer, a second metal layer and a third metal layer stacked in sequence on the base substrate, wherein the first metal layer includes an initialization signal line, a power supply voltage signal line and a data line extending in the second direction, and a light shielding portion; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor and a channel region of the switching transistor; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor and a gate of the switching transistor; the third metal layer includes the first connecting electrode, the spacer, the second gate line extending in the first direction and the first gate line.
  • the first metal layer includes an initialization signal line, a power supply voltage signal line and a data line extending in the second direction, and a light shielding portion
  • the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor and a channel region of the switching transistor
  • the third metal layer also includes a first connecting structure and a second connecting structure extending in the second direction, the orthographic projection of the first connecting structure on the base substrate is located within the orthographic projection of the initialization signal line on the base substrate, and the orthographic projection of the second connecting structure on the base substrate is located within the orthographic projection of the data line on the base substrate.
  • the display panel provided by at least one embodiment of the present invention further includes a buffer layer arranged on the side of the first metal layer away from the base substrate, a gate insulation layer arranged between the active layer and the second metal layer, an interlayer insulation layer arranged between the second metal layer and the third metal layer, and a passivation layer and a planarization layer arranged on the side of the third metal layer away from the base substrate.
  • a first via structure is provided in the interlayer insulating layer, and the third metal layer is electrically connected to the active layer through the first via structure;
  • a second via structure is passed through the interlayer insulating layer and the buffer layer, and the third metal layer is electrically connected to the power supply voltage signal line through the second via structure.
  • a storage capacitor is formed between the third metal layer and the second metal layer.
  • the display panel provided by at least one embodiment of the present invention further includes a switching transistor and a storage capacitor arranged on the base substrate, wherein the first source-drain electrode of the switching transistor and the first electrode plate of the storage capacitor are connected via a second connecting electrode.
  • At least one embodiment of the present invention provides a display panel, further comprising a first metal layer, an active layer, and a second metal layer sequentially stacked on the base substrate, wherein the first metal layer comprises an initialization signal line, a power supply voltage signal line and a data line extending in the second direction; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, a channel region of the switching transistor and the first electrode; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor and a gate of the switching transistor, the first connecting electrode, the spacer, a second electrode of the storage capacitor, the second gate line extending in the first direction and the first gate line.
  • the first metal layer comprises an initialization signal line, a power supply voltage signal line and a data line extending in the second direction
  • the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, a channel region of the switching transistor and the first electrode
  • the second metal layer includes a gate of the
  • the edge of the first electrode plate of the storage capacitor on the side close to the second gate line extends in the first direction to just above the power supply voltage signal line.
  • the second metal layer further includes a first connection structure extending in the second direction, and the orthographic projection of the first connection structure on the base substrate is located within the orthographic projection of the initialization signal line on the base substrate.
  • the display panel provided by at least one embodiment of the present invention further includes a buffer layer arranged on the side of the first metal layer away from the base substrate, a gate insulation layer and an interlayer insulation layer arranged between the active layer and the second metal layer, and a passivation layer and a planarization layer arranged on the side of the second metal layer away from the base substrate, wherein a first via structure is arranged in the interlayer insulation layer, and the second metal layer is electrically connected to the active layer through the first via structure; a second via structure passes through the interlayer insulation layer and the buffer layer, and the second metal layer is electrically connected to the power supply voltage signal line through the second via structure.
  • the display panel provided by at least one embodiment of the present invention further includes a cathode voltage line, wherein the cathode voltage line includes a first cathode voltage line extending in the first direction and a second cathode voltage line extending in the second direction, and the first cathode voltage line and the second cathode voltage line intersect;
  • the power supply voltage signal line also includes a second power supply voltage signal line extending in the first direction, and the first power supply voltage signal line and the second power supply voltage signal line intersect.
  • the second cathode voltage routing includes a three-layer stacked structure
  • the second cathode voltage routing includes a second cathode voltage routing first sublayer located in the first metal layer, a second cathode voltage routing second sublayer located in the second metal layer, and a second cathode voltage routing third sublayer located in the third metal layer
  • the second cathode voltage routing first sublayer and the second cathode voltage routing third sublayer are electrically connected through a fourth via structure
  • the second cathode voltage routing second sublayer and the second cathode voltage routing third sublayer are electrically connected through a fifth via structure.
  • the display panel provided by at least one embodiment of the present invention further includes an organic light emitting diode, wherein the organic light emitting diode includes an anode, and any one of the first sublayer of the second cathode voltage routing, the second sublayer of the second cathode voltage routing, and the third sublayer of the second cathode voltage routing is electrically connected to the anode through a sixth via structure.
  • the third sub-layer of the first cathode voltage wiring is electrically connected to the anode through the sixth via structure.
  • the display panel provided by at least one embodiment of the present invention further includes an encapsulation layer arranged on the organic light emitting diode, and a quantum dot layer arranged on the encapsulation layer, wherein the quantum dot layer is configured to process light emitted from the organic light emitting diode.
  • At least one embodiment of the present invention further provides a display device, which includes the display panel provided by any of the above embodiments.
  • FIG1 is a block diagram of a display panel provided by at least one embodiment of the present invention.
  • FIG2 shows a schematic diagram of a 3T1C pixel circuit for the display panel
  • FIG3 shows a signal timing diagram of the pixel circuit in FIG2 during a display process
  • FIG4 shows a signal timing diagram of the pixel circuit in FIG2 during the detection process
  • FIG5 shows another signal timing diagram of the pixel circuit in FIG2 during the detection process
  • FIG6 is a layout diagram of a multi-layer structure stacked in a display panel
  • FIG. 7 is a schematic diagram of a planar structure of a first metal layer included in a display panel provided by at least one embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a planar structure of a first metal layer and an active layer stack included in a display panel provided by at least one embodiment of the present invention
  • FIG. 9 is a schematic diagram of a planar structure of a stack of a first metal layer, an active layer, and a second metal layer included in a display panel provided by at least one embodiment of the present invention.
  • FIG10 is a schematic diagram of a planar structure of a via structure formed in the stacked structure shown in FIG9 ;
  • FIG11 is a schematic diagram of a planar structure of a third metal layer included in a display panel provided by at least one embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in a display panel provided by at least one embodiment of the present invention
  • FIG13 is a schematic diagram of a cross-sectional structure of a display panel provided by at least one embodiment of the present invention.
  • FIG. 14 is a schematic diagram of a planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in yet another display panel provided by at least one embodiment of the present invention
  • FIG15 is a schematic diagram of a planar structure of a first metal layer included in the display panel in FIG14 ;
  • FIG16 is a schematic diagram of a planar structure of a first metal layer and an active layer stack included in the display panel in FIG14;
  • FIG17 is a schematic plan view of a stacked structure of a first metal layer, an active layer, and a second metal layer included in the display panel of FIG14 ;
  • FIG18 is a schematic diagram of a planar structure of a via structure formed in the stacked structure shown in FIG14;
  • FIG19 is a schematic diagram of a planar structure of a third metal layer included in the display panel in FIG14;
  • FIG20 is a schematic diagram of a planar structure of a stack of a first metal layer, an active layer, and a second metal layer included in yet another display panel provided by at least one embodiment of the present invention
  • FIG21 is a schematic diagram of a planar structure of a first metal layer and an active layer stack included in the display panel in FIG20 ;
  • FIG22 is a schematic diagram of a planar structure of a second metal layer included in the display panel in FIG20 ;
  • FIG. 23 is a schematic diagram of a planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in yet another display panel provided by at least one embodiment of the present invention
  • FIG24 is a schematic diagram of a planar structure of a first metal layer included in the display panel in FIG23;
  • FIG25 is a schematic diagram of a planar structure of a first metal layer and an active layer stack included in the display panel in FIG23;
  • FIG26 is a schematic plan view of a stacked layer of a first metal layer, an active layer, and a second metal layer included in the display panel of FIG23 ;
  • FIG27 is a schematic diagram of a planar structure of a via structure formed in the stacked structure shown in FIG26;
  • FIG28 is a schematic diagram of a planar structure of a third metal layer included in the display panel in FIG23;
  • FIG29 is a schematic diagram of the cross-sectional structure of the display panel in FIG23;
  • FIG30 is a schematic plan view of a stacked structure of a first metal layer, an active layer, and a second metal layer included in yet another display panel provided by at least one embodiment of the present invention
  • FIG31 is a schematic diagram of a planar structure of a first metal layer and an active layer stack included in the display panel in FIG30 ;
  • FIG32 is a schematic diagram of the planar structure of the second metal layer in FIG30;
  • FIG33 is a schematic diagram of the cross-sectional structure of the display panel in FIG30;
  • 34 is a schematic diagram of a planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in yet another display panel provided by at least one embodiment of the present invention
  • FIG35 is a schematic diagram of a planar structure of a first metal layer and a third metal layer stacked together, included in the display panel in FIG34 ;
  • 36 is a schematic diagram of a planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in yet another display panel provided by at least one embodiment of the present invention
  • FIG37 is a schematic diagram of a cross-sectional structure of a second cathode voltage wiring of the display panel shown in FIG36 cut along a second direction;
  • FIG38 is a schematic cross-sectional view of the structure shown in FIG37 with a cathode and a pixel defining layer added;
  • FIG39 is a schematic diagram of a cross-sectional structure after an organic light emitting diode is added to the display panel shown in FIG36;
  • FIG40 is a schematic diagram of a planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in yet another display panel provided by at least one embodiment of the present invention
  • FIG41 is a schematic diagram of a cross-sectional structure of the display panel shown in FIG40.
  • FIG. 42 is a block diagram of a display device provided by at least one embodiment of the present invention.
  • the features such as “parallel”, “perpendicular” and “same” used in the embodiments of the present invention include the situations of “parallel”, “perpendicular”, “same” in a strict sense, as well as the situations of “approximately parallel”, “approximately perpendicular”, “approximately the same”, etc., which contain certain errors.
  • the above-mentioned “approximately” may mean that the difference of the compared objects is within 10% or 5% of the average value of the compared objects.
  • the component or element may be one or more, or may be understood as at least one.
  • At least one refers to one or more
  • multiple refers to at least two.
  • the “same-layer arrangement” in the embodiments of the present invention refers to the relationship between multiple film layers formed by the same material after the same step (for example, a one-step patterning process).
  • the “same layer” here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.
  • FIG. 1 is a block diagram of a display panel provided by at least one embodiment of the present invention.
  • the display panel 10 includes a plurality of sub-pixels 100 arranged in an array, for example, each sub-pixel 100 includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light.
  • the display panel is an organic light-emitting diode (OLED) display panel, and the light-emitting element is an organic light-emitting diode.
  • the display panel may also include a plurality of scan lines and a plurality of data lines for providing scan signals (control signals) and data signals to the plurality of sub-pixels, thereby driving the plurality of sub-pixels for display.
  • the display panel may further include power lines, detection lines, etc.
  • the pixel circuit includes a driving subcircuit for driving the light-emitting element to emit light and a detection subcircuit for detecting the electrical characteristics of the subpixel to achieve external compensation.
  • the embodiment of the present invention does not limit the specific structure of the pixel circuit.
  • Fig. 2 shows a schematic diagram of a 3T1C pixel circuit for the display panel.
  • the pixel circuit may further include a compensation circuit and a reset circuit, etc., which is not limited in the embodiments of the present invention.
  • the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor Cst.
  • the first electrode of the first transistor T1 is electrically connected to the first capacitor electrode of the storage capacitor Cst and the gate of the third transistor T3, the second electrode of the first transistor T1 is configured to receive the data signal GT, and the first transistor T1 is configured to write the data signal DT into the gate of the third transistor T3 and the storage capacitor Cst in response to the first control signal G1;
  • the first electrode of the third transistor T3 is electrically connected to the second capacitor electrode of the storage capacitor Cst, and is configured to be electrically connected to the first electrode of the light-emitting element, and the second electrode of the third transistor T3 is configured to receive the first power supply voltage V1 (for example, a high power supply voltage V1).
  • the first electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3 and the second capacitor electrode of the storage capacitor Cst, the second electrode of the second transistor T2 is configured to be connected to the detection line 230 to be connected to the external detection circuit 21, and the second transistor T2 is configured to detect the electrical characteristics of the sub-pixel to which it belongs in response to the second control signal G2 to achieve external compensation; the electrical characteristics include, for example, the threshold voltage and/or carrier mobility of the third transistor T3, or the threshold voltage and driving current of the light-emitting element.
  • the external detection circuit 21 is, for example, a conventional circuit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), and the embodiments of the present invention are not described in detail.
  • the transistors used in the embodiments of the present invention can all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the embodiments of the present invention are all described by taking thin film transistors as an example.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be indistinguishable in structure.
  • transistors can be divided into N-type and P-type transistors according to the characteristics of the transistor.
  • the turn-on voltage is a low level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high level voltage (for example, 5V, 10V or other suitable voltages);
  • the turn-on voltage is a high level voltage (for example, 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low level voltage (for example, 0V, -5V, -10V or other suitable voltages).
  • the transistor in Figure 2 is an N-type transistor as an example for description, but it is not a limitation of the present invention.
  • FIG3 shows a signal timing diagram of the pixel circuit in FIG2 during a display process
  • FIG4 shows a signal timing diagram of the pixel circuit in FIG2 during a detection process
  • FIG5 shows another signal timing diagram of the pixel circuit in FIG2 during a detection process.
  • the display process of each frame of image includes a data writing and resetting stage 1 and a light emitting stage 2.
  • FIG3 shows the timing waveforms of each signal in each stage.
  • a working process of the 3T1C pixel circuit includes: in the data writing and resetting stage 1, the first control signal G1 and the second control signal G2 are both on signals, the first transistor T1 and the second transistor T2 are turned on, the data signal DT is transmitted to the gate of the third transistor T3 through the first transistor T1, the first switch K1 is turned off, and the analog-to-digital converter is connected to the detection line 130 and the second transistor T2.
  • a reset signal is written to the first electrode of the light-emitting element (for example, the anode of an OLED), and the third transistor T3 is turned on and generates a driving current to charge the first electrode of the light-emitting element to an operating voltage; in light-emitting stage 2, the first control signal G1 and the second control signal G2 are both off signals. Due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the third transistor T3 operates in a saturated state with a constant current, and drives the light-emitting element to emit light.
  • FIG4 shows a signal timing diagram of the pixel circuit when detecting the threshold voltage.
  • a working process of the 3T1C pixel circuit includes: the first control signal G1 and the second control signal G2 are both turn-on signals, the first transistor T1 and the second transistor T2 are turned on, and the data signal DT is transmitted to the gate of the third transistor T3 through the first transistor T1; the first switch K1 is closed, the analog-to-digital converter writes a reset signal to the first electrode (node N3) of the light-emitting element through the detection line 230 and the second transistor T2, the third transistor T3 is turned on and charges the node N3 until the third transistor T3 is turned off, and the digital-to-analog converter samples the voltage on the detection line 230 to obtain the threshold voltage of the third transistor T3.
  • This process can be performed, for example, when the display device is turned off.
  • FIG5 shows a signal timing diagram of the pixel circuit when performing carrier mobility detection.
  • a working process of the 3T1C pixel circuit includes: in the first stage, the first control signal G1 and the second control signal G2 are both on signals, the first transistor T1 and the second transistor T2 are turned on, and the data signal DT is transmitted to the gate of the third transistor T3 through the first transistor T1; the first switch K1 is closed, and the analog-to-digital converter writes a reset signal to the first electrode (node N3) of the light-emitting element through the detection line 230 and the second transistor T2; in the second stage, the first control signal G1 is a closing signal, the second control signal G1 is an on signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the first switch K1 and the second switch K2 are disconnected to float the detection line 130; due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the third transistor T3 works in a saturated
  • the electrical characteristics of the third transistor T3 can be obtained and a corresponding compensation algorithm can be implemented.
  • the display panel 10 may further include a data driving circuit 23 and a scanning driving circuit 24.
  • the data driving circuit 23 is configured to send a data signal, such as the above-mentioned data signal DT, as required (e.g., an image signal input to the display device); the pixel circuit of each sub-pixel is also configured to receive the data signal and apply the data signal to the gate of the first transistor.
  • the scanning driving circuit 24 is configured to output various scanning signals, such as the above-mentioned first control signal G1 and the second control signal G2.
  • the signal G2 is, for example, an integrated circuit chip (IC) or a gate drive circuit (GOA) directly fabricated on a display substrate.
  • IC integrated circuit chip
  • GOA gate drive circuit
  • the display panel 10 further includes a control circuit 22.
  • the control circuit 22 is configured to control the data driving circuit 23 to apply a data signal, and to control the gate driving circuit to apply a scan signal.
  • An example of the control circuit 22 is a timing control circuit (T-con).
  • the control circuit 22 can be in various forms, for example, including a processor 121 and a memory 127, the memory 121 including an executable code, and the processor 121 runs the executable code to execute the above-mentioned detection method.
  • the processor 121 may be a central processing unit (CPU) or other forms of processing devices having data processing capabilities and/or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.
  • CPU central processing unit
  • PLC programmable logic controller
  • the memory 127 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • Volatile memory may include, for example, random access memory (RAM) and/or cache memory (cache), etc.
  • Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.
  • One or more computer program instructions may be stored on a computer-readable storage medium, and the processor 121 may run the desired functions of the program instructions.
  • Various applications and various data may also be stored in the computer-readable storage medium, such as electrical characteristic parameters obtained in the above-mentioned detection method, etc.
  • FIG6 is a layout of a multi-layer structure stacked in a display panel.
  • the first source-drain electrode T2a of the sensing transistor T2 and the first source-drain electrode T3a of the driving transistor T3 are electrically connected through the connection electrode corresponding to the N3 node.
  • the connection electrode corresponding to the N3 node and the sensing gate line 201 are adjacently arranged in the second direction Y.
  • the first source-drain electrode T1a of the switching transistor T1 and the second source-drain electrode T3b of the driving transistor T3 are electrically connected through the connection electrode corresponding to the N1 node.
  • the inventor of the present invention has noticed that since the sensing gate line 201 and the connection electrode corresponding to the N3 node are close in the second direction Y, when the sensing gate line 201 generates a voltage jump, a voltage jump will be caused at the N3 node, so that a large instantaneous current will be generated at the N3 node to impact the organic light emitting diode, thereby damaging the organic light emitting diode and reducing the life of the organic light emitting diode.
  • the voltage jump at the N3 node will also cause a voltage change at the N1 node.
  • the voltage change at the N3 node is larger than that at the N1 node, the voltage change at the N3 node causes greater damage to the organic light-emitting diode device than the damage caused by the voltage change at the N1 node. Therefore, it is possible to consider A spacing portion is provided between the corresponding connecting electrode and the sensing gate line to reduce the voltage change at the N3 node caused by the voltage jump of the sensing gate line.
  • At least one embodiment of the present invention provides a display panel, which includes: a base substrate; a pixel circuit arranged on the base substrate, the pixel circuit including a sensing transistor, a driving transistor, a first gate line and a second gate line, wherein a first source-drain electrode of the sensing transistor and a first source-drain electrode of the driving transistor are electrically connected via a first connecting electrode; the first gate line and the second gate line extend in a first direction, and in a second direction intersecting the first direction, a spacer is arranged between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and the first connecting electrode, the first gate line, the second gate line and the spacer are arranged in the same layer.
  • a voltage change caused to the first connecting electrode when a voltage jump occurs in the first gate line or the second gate line can be reduced, thereby reducing damage to a light-emitting diode and ensuring the service life of the light-emitting diode.
  • Figure 7 is a schematic diagram of the planar structure of a first metal layer included in a display panel provided by at least one embodiment of the present invention
  • Figure 8 is a schematic diagram of the planar structure of a first metal layer and an active layer stack included in a display panel provided by at least one embodiment of the present invention
  • Figure 9 is a schematic diagram of the planar structure of a first metal layer, an active layer and a second metal layer stack included in a display panel provided by at least one embodiment of the present invention
  • Figure 10 is a schematic diagram of the planar structure of a via structure formed in the stacked structure shown in Figure 9
  • Figure 11 is a schematic diagram of the planar structure of a third metal layer included in a display panel provided by at least one embodiment of the present invention
  • Figure 12 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in a display panel provided by at least one embodiment of the present invention.
  • the display panel 30 includes a base substrate 31, a pixel circuit 32 disposed on the base substrate 31, the pixel circuit 32 includes a sensing transistor T2, a driving transistor T3, a first gate line 321 and a second gate line 323, a first source-drain electrode T2a of the sensing transistor T2 and a first source-drain electrode T3a of the driving transistor T3 are electrically connected through a first connecting electrode M; the first gate line 321 and the second gate line 323 extend in a first direction X, and extend in a second direction Y intersecting the first direction X.
  • a spacer 322 is disposed between the first connection electrode M and the first gate line 321 and between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are disposed in the same layer, the spacer 322 is disposed between the first connection electrode M and the first gate line 321 and between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are disposed in the same layer.
  • the layer can reduce the voltage change on the first connection electrode M caused by the voltage jump of the first gate line 321 or the second gate line 323, thereby reducing the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, thereby ensuring the service life of the light-emitting diode.
  • the first gate line 321 is a sensing gate line
  • the second gate line 323 is a switching gate line
  • the embodiments of the present invention are not limited thereto, and the first gate line 321 and the second gate line 323 may also be other gate lines.
  • the embodiment of the present invention is described by taking the first direction X as the row direction and the second direction Y as the column direction.
  • the first direction X may be the column direction and the second direction Y may be the row direction, which is not limited in the embodiment of the present invention.
  • the display panel 30 also includes a switching transistor T1 and a storage capacitor Cst arranged on the base substrate 31, the first source-drain electrode T1a of the switching transistor T1 and the gate T3g of the driving transistor T3 are connected through the second connecting electrode K, the first plate Ca of the storage capacitor Cst is also connected to the second connecting electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connecting electrode M.
  • first connection electrode M and the second connection electrode K are both long strips disposed on the third metal layer.
  • first connection electrode M and the second connection electrode K are disposed at different positions, but are also long strips.
  • the display panel 30 includes a first metal layer 301, an active layer 302, a second metal layer 303, and a third metal layer 304 which are sequentially stacked on a base substrate 31.
  • the insulating layer is not directly shown in the plan views shown in FIGS. 7 to 12 , and only the via structure is used to represent the insulating layer, a layer structure having an insulating function is also provided between the adjacent layers, and a via structure is provided in the layer structure having an insulating function, and the layer structures to be connected are connected through the via structure.
  • the first metal layer 301 includes an initialization signal line 3011, a power supply voltage signal line 3012, a first electrode Ca, and a data line 3013 extending in the second direction Y.
  • the lengths of the initialization signal line 3011, the power supply voltage signal line 3012, and the data line 3013 in the second direction Y are equal or approximately equal, and the length of the first electrode Ca in the second direction Y is less than the lengths of the initialization signal line 3011, the power supply voltage signal line 3012, and the data line 3013 in the second direction Y.
  • the widths of the initialization signal line 3011 and the data line 3013 in the first direction X are equal or approximately equal, And they are all smaller than the width of the power supply voltage signal line 3012 in the first direction X, and the width of the power supply voltage signal line 3012 in the first direction X is smaller than the width of the first electrode Ca in the first direction X.
  • the minimum distance between the first electrode Ca and the adjacent power supply voltage signal line 3012 in the first direction X is smaller than the minimum distance between the initialization signal line 3011 and the power supply voltage signal line 3012 in the first direction X, and is smaller than the minimum distance between the first electrode Ca and the adjacent data line 3013 in the first direction X.
  • FIG. 7 and FIG. 12 only show that the power supply voltage signal line 3012 includes a portion extending in the second direction Y, in other embodiments, the power supply voltage signal line 3012 may also include a portion extending in the first direction X.
  • the first metal layer 301 and the active layer 302 are stacked, and the active layer 302 includes the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, and the channel region T1c of the switching transistor T1.
  • the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31, the orthographic projection of the initialization signal line 3011 on the substrate 31, and the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 overlap with each other.
  • the orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31, the orthographic projection of the power supply voltage signal line 3012 on the substrate 31, and the orthographic projection of the first electrode Ca on the substrate 31 overlap with each other.
  • the orthographic projection of the channel region T1c of the switching transistor T1 on the substrate 31, the orthographic projection of the first electrode Ca on the substrate 31, and the orthographic projection of the data line 3013 on the substrate 31 overlap with each other.
  • the first metal layer 301, the active layer 302 and the second metal layer 303 are stacked in sequence, and the second metal layer 303 includes the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, the gate T1g of the switch transistor T1 and the second electrode Cb.
  • the gate T2g of the sensing transistor T2 and the gate T1g of the switch transistor T1 are both in the shape of a long strip extending in a direction parallel to the second direction Y, and the gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, and the gate T1g of the switch transistor T1 extends from the channel region T1c of the switch transistor T1 in the second direction Y.
  • the gate T3g of the driving transistor T3 and the second electrode Cb form an integral structure. In combination with FIG9 and FIG12 , the orthographic projection of the second electrode Cb on the substrate substrate 31 is smaller than the orthographic projection of the first electrode Ca on the substrate substrate 31.
  • FIG. 10 shows that the via structure includes a first via structure 3071, a second via structure 3072, and a third via structure 3073.
  • the connection relationship between the first via structure 3071, the second via structure 3072, and the third via structure 3073 is described below.
  • FIG. 10 shows six first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e and 3071f), six second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e and 3072f) and three third via structures 3073 (3073a, 3073b and 3073c).
  • the six first via structures 3071 respectively correspond to positions at both ends of the channel region T2c of the sensing transistor T2, positions at both ends of the channel region T3c of the driving transistor T3, and positions at both ends of the channel region T1c of the switching transistor T1.
  • the first via structure 3071a and the first via structure 3071b respectively correspond to positions at both ends of the channel region T2c of the sensing transistor T2;
  • the first via structure 3071c and the first via structure 3071d respectively correspond to positions at both ends of the channel region T3c of the driving transistor T3;
  • the first via structure 3071e and the first via structure 3071f respectively correspond to positions at both ends of the channel region T1c of the switching transistor T1.
  • the orthographic projections of the second via structure 3072a and the second via structure 3072b on the substrate substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate substrate 31 in the second direction Y;
  • the orthographic projections of the second via structure 3072c and the second via structure 3072d on the substrate substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate substrate 31, and are located on both sides of the channel region T2c of the sensing transistor T2 in the second direction Y;
  • the orthographic projection of the second via structure 3072e on the substrate substrate 31 is located within the orthographic projection of the first electrode plate Ca on the substrate substrate 31, and is not located within the orthographic projection of the second electrode plate Cb on the substrate substrate 31;
  • the orthographic projection of the second via structure 3072f on the substrate substrate 31 is located within the orthographic projection of the data line 3013 on the substrate substrate
  • the orthographic projection of the third via structure 3073a on the substrate substrate 31 is located within the orthographic projection of the gate T2g of the sensing transistor T2 on the substrate substrate 31; the orthographic projection of the third via structure 3073b on the substrate substrate 31 is located within the orthographic projection of the first electrode plate Ca on the substrate substrate 31, and is located within the orthographic projection of the second electrode plate Cb on the substrate substrate 31; the orthographic projection of the third via structure 3073c on the substrate substrate 31 is located within the orthographic projection of the gate T1g of the switching transistor T1 on the substrate substrate 31.
  • the third metal layer 304 includes a first connection electrode M, a spacer 322, a second gate line 323 and a first gate line 321 extending in a first direction X, and a first connection structure 3041, a second connection structure 3042 and a third connection structure 3043 extending in a second direction Y.
  • the second gate line 323 and the first gate line 321 are both in the shape of long strips and extend in the first direction X.
  • the first connection electrode M is also in the shape of long strips and extends in the first direction X.
  • the first connection structure 3041, the second connection structure 3042 and the third connection structure 3043 are used to realize the connection between the third metal layer 304 and other layer structures.
  • the spacer 322 is connected to the first gate line 323 and the first gate line 321.
  • 322b is located between the first connection electrode M and the first gate line 321, so as to reduce the voltage change on the first connection electrode M caused by the voltage jump of the first gate line 321.
  • the spacer 322a is located between the first connection electrode M and the second gate line 323, so as to reduce the voltage change on the first connection electrode M caused by the voltage jump of the second gate line 323, thereby reducing the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode.
  • the channel region T2c of the sensing transistor T2 is electrically connected to the first connection structure 3041 through the first via structure 3071a, and is electrically connected to the first connection electrode M through the first via structure 3071b;
  • the channel region T3c of the driving transistor T3 is electrically connected to the spacer 322a through the first via structure 3071c, and is electrically connected to the main body 326 through the first via structure 3071d;
  • the channel region T1c of the switch transistor T1 is electrically connected to the second connection structure 3042 through the first via structure 3071e, and is electrically connected to the third connection structure 3043 through the first via structure 3071f.
  • the first connection structure 3041 is electrically connected to the initialization signal line 3011 located at the first metal layer 301 through the second via structure 3072a and the second via structure 3072b.
  • the spacer 322a is electrically connected to the power supply voltage signal line 3012 through the second via structure 3072c
  • the spacer 322b is electrically connected to the power supply voltage signal line 3012 through the second via structure 3072d.
  • the first connection electrode M is electrically connected to the first electrode plate Ca through the second via structure 3072e.
  • the third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f.
  • the gate T2g of the sensing transistor T2 extends in the second direction Y to be electrically connected to the first gate line 321, and the gate T2g of the sensing transistor T2 is electrically connected to the first gate line 321 through the third via structure 3073a.
  • the gate T1g of the switching transistor T1 extends in the direction opposite to the second direction Y to be electrically connected to the second gate line 323, and the first gate line 321 connected to the gate T2g of the sensing transistor T2 and the second gate line 323 connected to the gate T1g of the switching transistor T1 are located on different sides of the spacer 322 in the second direction Y.
  • the gate T1g of the switching transistor T1 is electrically connected to the second gate line 323 through the third via structure 3073c.
  • the gate T3g of the driving transistor T3 and the second electrode plate Cb are an integral structure, and the second electrode plate Cb is electrically connected to the second connection structure 3042 through the third via structure 3073b.
  • the second connection structure 3042 is reused as the second connection electrode K.
  • the orthographic projection of the first connection structure 3041 on the base substrate 31 is located within the orthographic projection of the initialization signal line 3011 on the base substrate 31
  • the second connection structure 3042 The orthographic projection on the base substrate 31 is located within the orthographic projection of the first electrode plate Ca on the base substrate 31, and the orthographic projection of the third connection structure 3043 on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31.
  • the orthographic projections of the spacers 322a and 322b on the base substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the base substrate 31.
  • a spacer 322a and a spacer 322b located in the third metal layer 304 are respectively provided between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on both sides thereof in the second direction Y.
  • the spacer 322b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321 connected thereto.
  • the first source-drain electrode T2a of the sensing transistor T2 is located in the third metal layer 304, the power supply voltage signal line 3012 is located in the first metal layer 301, the spacer 322b located in the third metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072d; the spacer 322a located in the third metal layer 304 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072c.
  • the switch transistor T1 can reduce the coupling between the second connection electrode K and the gate line (the first gate line 321 or the second gate line 323).
  • the storage capacitor Cst is a double-layer capacitor between the third metal layer 304 and the second metal layer 303 and between the first metal layer 301 and the second metal layer 303.
  • the voltage change of the first connection electrode M will cause the voltage change of the second connection electrode K.
  • the voltage rise of the first connection electrode M is normal.
  • the rise of the voltage of the second connection electrode K is caused by the coupling of the voltage rise of the first connection electrode M.
  • the gate of the driving transistor T3 and the power supply voltage signal line 3012 are equivalent to a capacitor, and the storage capacitor Cst is also a capacitor. In the coupling process, there will be a capacitor voltage division, so the voltage rise of the second connection electrode K is not as high as the voltage rise of the first connection electrode M.
  • the above design can make the spacer 322 set between the first connection electrode M and the first gate line 321, and the first connection electrode M is formed in the third metal layer 304, and is set in the same layer as the first gate line 321. Through the shielding effect of the spacer 322, the life of the organic light emitting diode display device can be extended.
  • the sensing transistor T2 and the first connection electrode M connected thereto have a spacer 322 on both sides of the second direction Y, respectively shielding the first gate line 321 and the second gate line 323 from the electrical conduction of the first connection electrode M.
  • the influence of the voltage change is eliminated, that is, due to the existence of the spacer 322, the parasitic capacitance between the first gate line 321 or the second gate line 323 and the first connection electrode 24 cannot be formed.
  • FIG13 is a schematic diagram of a cross-sectional structure of a display panel provided by at least one embodiment of the present invention.
  • the display panel 30 further includes a buffer layer 305 disposed on a side of the first metal layer 301 away from the base substrate 31.
  • the buffer layer 305 is formed in a whole layer on the base substrate 31.
  • a power supply voltage signal line 3012 is shown on the first metal layer 301.
  • a gate insulating layer 306 is disposed between the active layer 302 and the second metal layer 303, and an interlayer insulating layer 307 is disposed between the second metal layer 303 and the third metal layer 304.
  • a passivation layer 308 and a planarization layer 309 are sequentially disposed on a side of the third metal layer 304 away from the base substrate 31.
  • the interlayer insulating layer 307, the passivation layer 308 and the planarization layer 309 are also formed in a whole layer.
  • a first via structure 3071 is provided in the interlayer insulating layer 307, and the third metal layer 304 is electrically connected to the active layer 302 through the first via structure 3071.
  • a second via structure 3072 is passed through the interlayer insulating layer 307 and the buffer layer 305, and the third metal layer 304 is electrically connected to the first metal layer 301 through the second via structure 3072.
  • a third via structure 3073 is provided in the interlayer insulating layer 307, and the third metal layer 304 is electrically connected to the second metal layer 303 through the third via structure 3073.
  • a double-layer capacitor structure is shown on the left side of Figure 13, that is, a first capacitor structure is formed between the third metal layer 304 and the second metal layer 303, and a second capacitor structure is formed between the second metal layer 303 and the first metal layer 301, and the orthographic projections of the third metal layer 304, the second metal layer 303 and the first metal layer 301 on the substrate 31 all have overlapping parts.
  • the first connection structure 3041 is electrically connected to the second source-drain electrode T2b of the sensing transistor T2 through the first via structure 3071a.
  • the second connection structure 3042 is electrically connected to the first source-drain electrode T1a of the switching transistor T1 through the first via structure 3071e, and is electrically connected to the second electrode plate Cb through the third via structure 3073b;
  • the third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f, and is electrically connected to the second source-drain electrode T1b of the switching transistor T1 through the first via structure 3071f.
  • the third metal layer 304 has an overlapping area with the first metal layer 301 and the second metal layer 303, so as to form a storage capacitor Cst between the first metal layer 301 and the second metal layer 303, and a capacitor structure between the second metal layer 303 and the third metal layer 304, thereby forming a dual capacitor structure.
  • the first source-drain electrode T2a of the sensing transistor T2 is on the substrate 31
  • the orthographic projection on the substrate 31 overlaps with the orthographic projection of the power supply voltage signal line 3012 on the base substrate 31.
  • Figure 14 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided by at least one embodiment of the present invention
  • Figure 15 is a schematic diagram of the planar structure of the first metal layer included in the display panel in Figure 14
  • Figure 16 is a schematic diagram of the planar structure of the stack of the first metal layer and the active layer included in the display panel in Figure 14
  • Figure 17 is a schematic diagram of the planar structure of the stack of the first metal layer, the active layer and the second metal layer included in the display panel in Figure 14
  • Figure 18 is a schematic diagram of the planar structure of a via structure formed in the stacked structure shown in Figure 14
  • Figure 19 is a schematic diagram of the planar structure of the third metal layer included in the display panel in Figure 14.
  • the display panel 30 includes a base substrate 31, a pixel circuit 32 disposed on the base substrate 31, the pixel circuit 32 includes a sensing transistor T2, a driving transistor T3, a switching transistor T1, a first gate line 321, a second gate line 323 and a storage capacitor Cst, a first source-drain electrode T2a of the sensing transistor T2 and a first source-drain electrode T3a of the driving transistor T3 are electrically connected through a first connecting electrode M; the first gate line 321 and the second gate line 323 extend in a first direction X, and in a second direction Y intersecting the first direction X, between the first connecting electrode M and the first gate line 321, between the first connecting electrode M and the second gate line 323 A spacer 322 is arranged between the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322, and the first connection electrode M and the first gate line 321, and the spacer 322 are arranged
  • the first source-drain electrode T1a of the switching transistor T1 and the gate T3g of the driving transistor T3 are connected through the second connection electrode K, the first plate Ca of the storage capacitor Cst is connected to the second connection electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connection electrode M to form a whole pixel circuit.
  • a spacer 322a and a spacer 322b located in the third metal layer 304 are respectively provided between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on both sides thereof in the second direction Y.
  • the spacer 322b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321.
  • the electrode T2a is located in the third metal layer 304, the power supply voltage signal line 3012 is located in the first metal layer 301, and the spacer 322b located in the third metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072d; the spacer 322a located in the third metal layer 304 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072c.
  • the switching transistor T1 can reduce the coupling between the second connection electrode K and the gate line (the first gate line 321 or the second gate line 323).
  • the storage capacitor Cst is a double-layer capacitor, which is respectively between the third metal layer 304 and the second metal layer 303, and between the first metal layer 301 and the second metal layer 303.
  • a portion of the first metal layer 301 is removed below the first source-drain electrode T2a of the sensing transistor T2, which can reduce parasitic capacitance, that is, the power supply voltage signal line 3012 is narrowed at a position corresponding to the first source-drain electrode T2a of the sensing transistor T2 and the first connecting electrode M, which can reduce the overlapping area and parasitic capacitance of the power supply voltage signal line 3012 and the first source-drain electrode T2a of the sensing transistor T2.
  • the switch transistor T1 is two thin film transistors connected in parallel, one of which is arranged at a position close to the second gate line 323 on the upper side, and the other is arranged at a position close to the first gate line 321 on the lower side, that is, arranged on both sides of the first connection electrode M in the second direction, and at the same time, a portion of the first electrode Ca of the storage capacitor Cst is reduced in length in the second direction Y.
  • the above design can increase the channel width-to-length ratio and driving current of the switch transistor T1, which is beneficial to the driving of the high-resolution display panel and reduces the charging time.
  • the spacing between a portion of the third metal layer corresponding to a portion of the storage capacitor and the first gate line 321 or the second gate line 323 on both sides thereof in the second direction Y can also be increased to reduce the coupling between the first electrode Ca of the storage capacitor Cst connected to the first connection electrode M and the first gate line 321 or the second gate line 323, and reduce the length of the parasitic capacitance coupled between the first connection electrode M and the gate line.
  • a portion of the first metal layer 301 below the first source-drain electrode T2 a of the sensing transistor T2 is removed, thereby preventing the first connection electrode M and the bottom gate of the sensing transistor T2 from coupling to generate leakage current.
  • the display panel 30 includes The first metal layer 301, the active layer 302, the second metal layer 303 and the third metal layer 304 are stacked on the base substrate 31.
  • the insulating layer is not directly shown in the plan views shown in FIG. 14 to FIG. 19, and only the via structure is used to represent the insulating layer, a layer structure that plays an insulating role is also arranged between the adjacent layers, and a via structure is arranged in the layer structure that plays an insulating role, and the layer structures that need to be connected are connected through the via structure.
  • the pixel circuit corresponding to two sub-pixels arranged in the first direction X is used as an example for description.
  • the first metal layer 301 includes an initialization signal line 3011, a power supply voltage signal line 3012, a first electrode Ca and a data line 3013 extending in the second direction Y.
  • the initialization signal line 3011 and the data line 3013 are both straight lines extending in the second direction Y.
  • the power supply voltage signal line 3012 includes a first power supply voltage signal line 3012a extending in the second direction Y, and the first power supply voltage signal line 3012a includes a first part 3012b, a second part 3012c and a third part 3012d extending in the second direction Y and connected in sequence, the first part 3012b and the third part 3012d have the same width in the first direction X, the width of the second part 3012c in the first direction X is smaller than the width of the first part 3012b in the first direction X, and one end of the second part 3012c in the second direction Y is connected to an edge of the first part 3012b close to the third part 3012d and away from the initialization signal line 3011, and the other end of the second part 3012c in the second direction Y is connected to an edge of the third part 3012d close to the first part 3012b and away from the initialization signal line 3011.
  • the edge of the second portion 3012c farthest from the initialization signal line 3011, the edge of the first portion 3012b farthest from the initialization signal line 3011, and the edge of the third portion 3012d farthest from the initialization signal line 3011 are all aligned and on a straight line, so a notch is formed between the second portion 3012c and the initialization signal line 3011.
  • the first electrode Ca includes a first electrode sub-block Ca1 and a second electrode sub-block Ca2 connected to each other in a first direction X, the second electrode sub-block Ca2 is closer to the data line 3013 than the first electrode sub-block Ca1, and the length of the second electrode sub-block Ca2 in the second direction Y is less than the length of the first electrode sub-block Ca1 in the second direction Y, and in FIG. 15, the upper edge of the second electrode sub-block Ca2 is lower than the upper edge of the first electrode sub-block Ca1, and the lower edge of the second electrode sub-block Ca2 is higher than the lower edge of the first electrode sub-block Ca1.
  • the first metal layer 301 and the active layer 302 are stacked, and the active layer 302 includes the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, and the channel region T1c of the two switch transistors T1.
  • the positive projection of the channel region T2c of the sensing transistor T2 on the substrate 31 and the initialization signal line The orthographic projections of the channel region T3c of the driving transistor T3 on the substrate 31 overlap with the orthographic projections of the power supply voltage signal line 3012 on the substrate 31 and the orthographic projections of the first electrode plate Ca on the substrate 31.
  • the orthographic projections of the channel region T1c of the two switching transistors T1 on the substrate 31 overlap with the orthographic projections of the data line 3013 on the substrate 31.
  • the first metal layer 301, the active layer 302, and the second metal layer 303 are stacked in sequence, and the second metal layer 303 includes the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, the gate T1g of the switch transistor T1, and the second electrode plate Cb, and the gates of the two switch transistors T1 are an integrated structure.
  • the gate T2g of the sensing transistor T2 and the gate T1g of the switch transistor T1 are both in the shape of a long strip extending in a direction parallel to the second direction Y, and the gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, and the gate T1g of the switch transistor T1 extends from the channel region T1c of the switch transistor T1 located below in the second direction Y.
  • the gate T3g of the driving transistor T3 and the second electrode plate Cb form an integrated structure.
  • the second metal layer 303 includes a first extension portion 3031 and a second extension portion 3032 extending from a portion of the second electrode plate Cb corresponding to the second electrode plate sub-block Ca2 in the second direction Y, and two second connection structures 3042 are respectively connected to the first extension portion 3031 and the second extension portion 3032.
  • the orthographic projections of the first extension portion 3031 and the second extension portion 3032 on the base substrate 31 have no overlapping portion with the orthographic projection of the first electrode plate Ca on the base substrate 31.
  • first extension portion 3031 and the second extension portion 3032 are both in the shape of long strips.
  • the embodiments of the present invention are not limited thereto, and the first extension portion 3031 and the second extension portion 3032 may also be in other shapes such as blocks.
  • first via structure 3071 a first via structure 3071, a second via structure 3072, and a third via structure 3073 are shown in FIG18, and the connection relationship between the first via structure 3071, the second via structure 3072, and the third via structure 3073 is described below.
  • eight first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e1, 3071e2, 3071f1, and 3071f2), six second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, and 3072f), and four third via structures 3073 (3073a, 3073b, 3073c, and 3073d) are shown at the position corresponding to one sub-pixel in FIG18.
  • the eight first via structures 3071 correspond to the positions of both ends of the channel region T2c of the sensing transistor T2, the positions of both ends of the channel region T3c of the driving transistor T3, and the positions of both ends of the channel region T1c of the two switch transistors T1.
  • the first via structures 3071 are connected to the sensing transistor T2.
  • the first via structure 3071a and the first via structure 3071b respectively correspond to the positions of the two ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to the positions of the two ends of the channel region T3c of the driving transistor T3; the first via structure 3071e1 and the first via structure 3071f1 respectively correspond to the positions of the two ends of the channel region T1c of one of the switching transistors T1; the first via structure 3071e2 and the first via structure 3071f2 respectively correspond to the positions of the two ends of the channel region T1c of the other switching transistor T1.
  • the orthographic projections of the second via hole structure 3072a and the second via hole structure 3072b on the substrate substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate substrate 31 in the second direction Y; the orthographic projections of the second via hole structure 3072c and the second via hole structure 3072d on the substrate substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the second direction Y.
  • the orthographic projection of the second via structure 3072e on the substrate 31 is located within the orthographic projection of the first electrode plate Ca on the substrate 31, and is not located within the orthographic projection of the second electrode plate Cb on the substrate 31;
  • the orthographic projection of the second via structure 3072f on the substrate 31 is located within the orthographic projection of the data line 3013 on the substrate 31.
  • the orthographic projection of the third via structure 3073a on the base substrate 31 is located within the orthographic projection of the gate T2g of the sensing transistor T2 on the base substrate 31; the orthographic projections of the third via structure 3073b1 and the third via structure 3073b2 on the base substrate 31 are respectively located within the orthographic projections of the first extension portion 3031 and the second extension portion 3032 on the base substrate 31; the orthographic projection of the third via structure 3073c on the base substrate 31 is located within the orthographic projection of the gate T1g of the switching transistor T1 on the base substrate 31.
  • the third metal layer 304 includes a first connection electrode M, a spacer 322, a second gate line 323 and a first gate line 321 extending in a first direction X, a first connection structure 3041 and a third connection structure 3043 extending in a second direction Y, and two second connection structures 3042 extending in the first direction X.
  • the second gate line 323 and the first gate line 321 are both in the shape of long strips and extend in the first direction X.
  • the first connection electrode M is also in the shape of long strips and extends in the first direction X.
  • the first connection structure 3041, the second connection structure 3042 and the third connection structure 3043 are used to realize the connection between the third metal layer 304 and other layer structures.
  • the spacer 322b is located between the first connection electrode M and the first gate line 321, so as to reduce the voltage jump of the first gate line 321 to the first connection electrode M.
  • the spacer 322a is located between the first connection electrode M and the second gate line 323, thereby reducing the voltage change on the first connection electrode M caused by the voltage jump of the second gate line 323, and further reducing the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode.
  • the second connection electrode K is reused as the second connection structure 3042 .
  • the channel region T2c of the sensing transistor T2 is electrically connected to the first connection structure 3041 through the first via structure 3071a, and is electrically connected to the first connection electrode M through the first via structure 3071b;
  • the channel region T3c of the driving transistor T3 is electrically connected to the spacer 322a through the first via structure 3071c, and is electrically connected to the main body 326 through the first via structure 3071d;
  • the channel region T1c of the switch transistor T1 located on the upper side is electrically connected to the second connection structure 3042 located on the upper side through the first via structure 3071e1, and is electrically connected to the third connection structure 3043 through the first via structure 3071f1;
  • the channel region T1c of the switch transistor T1 located on the lower side is electrically connected to the second connection structure 3042 located on the lower side through the first via structure 3071e2, and is electrically connected to the third connection structure 3043 through the first via structure 3071f2.
  • the first connection structure 3041 is electrically connected to the initialization signal line 3011 located at the first metal layer 301 through the second via structure 3072a and the second via structure 3072b.
  • the spacer 322a is electrically connected to the first portion 3012b of the first power supply voltage signal line 3012a through the second via structure 3072c, and the spacer 322b is electrically connected to the third portion 3012d of the first power supply voltage signal line 3012a through the second via structure 3072d.
  • the first connection electrode M is electrically connected to the first electrode plate Ca through the second via structure 3072e.
  • the third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f.
  • the gate T2g of the sensing transistor T2 extends in the second direction Y to be electrically connected to the first gate line 321, and the gate T2g of the sensing transistor T2 is electrically connected to the first gate line 321 through a third via structure 3073a.
  • the gate T1g of the switching transistor T1 extends in a direction opposite to the second direction Y to be electrically connected to the second gate line 323, and the first gate line 321 connected to the gate T2g of the sensing transistor T2 and the second gate line 323 connected to the gate T1g of the switching transistor T1 are located on different sides of the spacer 322 in the second direction Y.
  • the gate T1g of the switching transistor T1 is electrically connected to the second gate line 323 through a third via structure 3073c.
  • the first extension portion 3031 is electrically connected to the second connection structure 3042 located on the upper side through a third via structure 3073b1, and the second extension portion 3032 is electrically connected to the second connection structure 3042 located on the lower side through a third via structure 3073b2.
  • Structure 3042 is electrically connected.
  • the orthographic projection of the first connection structure 3041 on the base substrate 31 is located within the orthographic projection of the initialization signal line 3011 on the base substrate 31, and the orthographic projection of the third connection structure 3043 on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31.
  • the orthographic projections of the spacers 322a and 322b on the base substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the base substrate 31.
  • a spacer 322a and a spacer 322b located in the third metal layer 304 are respectively provided between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on both sides thereof in the second direction Y.
  • the spacer 322b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321 connected thereto.
  • the first source-drain electrode T2a of the sensing transistor T2 is located in the third metal layer 304, the power supply voltage signal line 3012 is located in the first metal layer 301, the spacer 322b located in the third metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072d; the spacer 322a located in the third metal layer 304 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072c.
  • the switch transistor T1 can reduce the coupling between the second connection electrode K and the gate line (the first gate line 321 or the second gate line 323).
  • the storage capacitor Cst is a double-layer capacitor between the third metal layer 304 and the second metal layer 303 and between the first metal layer 301 and the second metal layer 303.
  • the voltage change of the first connection electrode M will cause the voltage change of the second connection electrode K.
  • the voltage rise of the first connection electrode M is normal.
  • the rise of the voltage of the second connection electrode K is caused by the coupling of the voltage rise of the first connection electrode M.
  • the second connection electrode K and the power supply voltage signal line 3012 are equivalent to a capacitor, and the storage capacitor Cst is also a capacitor.
  • the voltage rise of the second connection electrode K is not as high as the voltage rise of the first connection electrode M.
  • the voltage of the first connection electrode M is more stable, so the first connection electrode M is protected and shielded by the spacer 322 to reduce the jump voltage.
  • the above design can make the spacer 322 set between the first connection electrode M and the first gate line 321, and the first connection electrode M is formed in the third metal layer 304, and is set in the same layer as the first gate line 321.
  • the shielding effect of the spacer 322 can extend the life of the organic light emitting diode display device.
  • the sensing transistor T2 and its The connected first connection electrode M has a spacer 322 on both sides of the second direction Y, which respectively shields the influence of the first gate line 321 and the second gate line 323 on the voltage change of the first connection electrode M, that is, due to the existence of the spacer 322, a parasitic capacitance cannot be formed between the first gate line 321 or the second gate line 323 and the first connection electrode M.
  • the positive projection of the first source-drain electrode T2a of the sensing transistor T2 on the substrate substrate 31 is spaced from the positive projection of the power supply voltage signal line 3012 on the substrate substrate 31, that is, the first source-drain electrode T2a of the sensing transistor T2 is at the recess between the second portion 3012c and the initialization signal line 3011.
  • the data line 3013 is configured to provide a data signal (data voltage) to the pixel circuit
  • the second gate line 323 is configured to provide a first scanning signal to the pixel circuit
  • the first gate line 321 is configured to provide a second scanning signal to the pixel circuit
  • the initialization signal line 3011 is configured to provide an initialization signal to the pixel circuit
  • the power supply voltage signal line 3012 is configured to provide a first power supply voltage VDD to the pixel circuit.
  • cross-sectional structures corresponding to the embodiments shown in the plan views of FIG. 14 to FIG. 19 can refer to the above description about FIG. 13 , which will not be repeated here.
  • the driving current of the driving transistor T3 is Wherein, W is the width of the channel of the driving transistor T3 (the width in the second direction), L is the length of the channel of the driving transistor T3 (the length in the first direction), ⁇ n is the carrier mobility of the driving transistor T3, V TH is the threshold voltage of the driving transistor T3, C GI is the capacitance of the gate insulating layer, V GS is the voltage difference between the gate T3g and the first source-drain electrode T3a of the driving transistor T3, and V DS is the voltage difference between the first source-drain electrode T3a and the second source-drain electrode T3b of the driving transistor T3.
  • the display panel 30 further includes an organic light emitting diode, and the display panel 30 includes a storage capacitor Cst, And meet is greater than or equal to 0.013, ⁇ V dr is the jump voltage when the first connection electrode M is not shielded, ⁇ V g is the jump voltage of the first gate line 321, C gc is the parasitic capacitance between the first gate line 321 and the storage capacitor C st , C st is the size of the storage capacitor, Ast is the area of the storage capacitor C st , d gc is the minimum spacing between the first gate line 321 and the storage capacitor C st (the minimum spacing in the second direction Y), L c is the distance between the first plate sub-block closest to the first gate line 321, and L c is the distance between the first gate line 321 and the storage capacitor C st .
  • the length of a portion of a gate line 321 in the first direction i.e., the length of the side of the first electrode Ca closest to the first gate line 321)
  • Wg is the width of the first gate line 321
  • dst is the thickness of the insulating medium corresponding to the storage capacitor Cst , that is, the thickness THKILD of the interlayer insulating layer between the first electrode Ca and the second electrode Cb
  • ⁇ is the dielectric constant of the organic material forming the interlayer insulating layer
  • Agc is the area of the parasitic capacitance formed between the first gate line and the storage electrode.
  • V gON is the on voltage of the second gate line
  • V gOFF is the off voltage of the second gate line
  • V oled is the voltage across the organic light emitting diode
  • ⁇ is an optical constant
  • ⁇ V gray is the change of grayscale voltage
  • the storage capacitor is a three-layer structure formed by a first metal layer, a second metal layer and a third metal layer. And meet is greater than or equal to 0.006, ⁇ V dr is the jump voltage of the first connection electrode M, ⁇ V g is the jump voltage of the first gate line 321, C gc is the parasitic capacitance between the first gate line 321 and the storage capacitor C st , C st is the size of the storage capacitor, Ast is the area of the storage capacitor, d gc is the minimum spacing between the first gate line 321 and the storage capacitor (the minimum spacing in the second direction Y), d stu is the thickness of the insulating medium corresponding to the upper capacitor in the storage capacitor, that is, the thickness of the interlayer insulating layer between the first plate Ca and the second plate Cb THK ILD , d std is the thickness of the insulating medium between the lower capacitor in the storage capacitor, that is, the first metal layer and the second metal layer, that is,
  • V gON is the on voltage of the first gate line 321
  • V gOFF is the off voltage of the first gate line 321
  • V oled is the voltage across the organic light emitting diode
  • ⁇ is an optical constant
  • ⁇ V gray is the change of grayscale voltage.
  • W DD is the length of the spacer 322 b between the first gate line 321 and the first connection electrode M in the second direction Y
  • d gd is the minimum distance between the first gate line 321 and the spacer 322 b
  • d sd is the minimum distance between the first connection electrode M and the spacer 322 b.
  • L c is the length of the side of the first plate sub-block adjacent to the first gate line 321, that is, the length of the part of the first plate sub-block closest to the first gate line 321 in the first direction, that is, the length of the side of the first plate Ca closest to the first gate line 321
  • L p is the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction X
  • R l is the ratio of the length of the side of the first plate sub-block adjacent to the first gate line 321 to the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction X.
  • W c is the width of the storage capacitor in the first direction
  • d gc is the minimum distance between the first gate line 321 and the storage capacitor
  • Pitch is the width of one sub-pixel.
  • d gc 10.2 ⁇ m
  • d gd 7.9 ⁇ m
  • d sd 10.2 ⁇ m
  • d c1d 9.03 ⁇ m
  • Ast 5605 ⁇ m 2
  • Cst length 90.3 ⁇ m
  • Cst width 62.07 ⁇ m
  • THK ILD 0.5 ⁇ m
  • THK BUF 0.3 ⁇ m
  • THK GI 0.15 ⁇ m
  • Pitch 231 ⁇ m.
  • the proportional relationship between the size of the storage capacitor Cst and the size of the parasitic capacitance Cgc of the second plate Cb of the storage capacitor and the first gate line 321 is: Among them, Cgc is the size of the parasitic capacitance between the second plate Cb of the storage capacitor and the first gate line, Cst is the size of the storage capacitor, Ast is the area of the storage capacitor, dgc is the minimum spacing between the first gate line and the storage capacitor, Lc is the length of the side of the first plate sub-block adjacent to the first gate line, Wc is the width of the storage capacitor, dst is the thickness of the insulating medium corresponding to the storage capacitor, that is, the thickness THKILD of the interlayer insulating layer between the first plate and the second plate, ⁇ is the dielectric constant of the organic material forming the interlayer insulating layer, and Agc is the area of the parasitic capacitance formed between the first gate line and the second plate.
  • the size of P is related to the thickness of the interlayer insulating layer between the first electrode plate and the second electrode plate, and the parameters of the pixel in the horizontal direction.
  • P is a constant that is independent of the pixel in the vertical direction (W c and d gc ). Since W c and d gc are related to the pixel size and the aperture ratio, their sizes are positively correlated with the width of the pixel characteristic value sub-pixel, and are positively correlated with the ratio of the size C st of the storage capacitor to the size C gc of the parasitic capacitance of the second electrode plate Cb of the storage capacitor and the first gate line 321. The larger the ratio, the smaller the influence of the parasitic capacitance generated by the first gate line or the second gate line on the voltage of the first connection electrode M, and the more stable the voltage of the first connection electrode M.
  • Figure 20 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer and a second metal layer included in another display panel provided by at least one embodiment of the present invention
  • Figure 21 is a schematic diagram of the planar structure of the stack of a first metal layer and an active layer included in the display panel in Figure 20
  • Figure 22 is a schematic diagram of the planar structure of the second metal layer included in the display panel in Figure 20.
  • the display panel 30 includes a base substrate 31, a pixel circuit 32 disposed on the base substrate 31, the pixel circuit 32 includes a sensing transistor T2, a driving transistor T3, a switching transistor T1, a first gate line 321, a second gate line 323 and a storage capacitor Cst, a first source-drain electrode T2a of the sensing transistor T2 and a first source-drain electrode T3a of the driving transistor T3 are electrically connected through a first connecting electrode M; the first gate line 321 and the second gate line 323 extend in a first direction X, In the second direction Y intersecting the first direction X, a spacer 322 is provided between the first connection electrode M and the first gate line 321 and between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are provided on the same layer, the spacer 322 is provided on the first connection electrode M and the first
  • the display panel 30 further includes a first metal layer 301, an active layer 302, and a second metal layer 303 sequentially stacked on a base substrate 31, wherein the first metal layer 301 includes an initialization signal line 3011 extending in the second direction Y, a power supply voltage signal line 3012 at least partially extending in the second direction Y, a first electrode Ca, and a data line 3013 extending in the second direction Y.
  • the first metal layer 301 includes an initialization signal line 3011 extending in the second direction Y, a power supply voltage signal line 3012 at least partially extending in the second direction Y, a first electrode Ca, and a data line 3013 extending in the second direction Y.
  • the active layer 302 includes a channel region T2c of a sensing transistor T2, a channel region T3c of a driving transistor T3, and a channel region T1c of a switching transistor T1, wherein the channel region T1c of the switching transistor T1, the channel region T3c of the driving transistor T3, and the channel region T2c of the sensing transistor T2 are sequentially arranged in the second direction Y.
  • the second metal layer 303 includes a gate T2g of the sensing transistor T2, a gate T3g of the driving transistor T3, a gate T1g of the switching transistor T1, a second electrode Cb, a first connection electrode M, a second connection electrode K, a spacer 322, a second gate line 323 and a first gate line 321 extending in the first direction X and spaced apart from each other.
  • the second connection electrode K is between the first connection electrode M and the second gate line 323 located on the upper side
  • the gate T1g of the switching transistor T1 is electrically connected to the second gate line 323 located on the upper side
  • the gate T2g of the sensing transistor T2 is electrically connected to the first gate line 321 located on the lower side
  • the second gate line 323 located on the upper side connected to the gate T1g of the switching transistor T1 and the first gate line 321 located on the lower side connected to the gate T2g of the sensing transistor T2 are located on different sides of the first electrode plate Ca in the second direction Y.
  • the first source-drain electrode T1a of the switch transistor T1 is connected to the second connection electrode K, and the second connection electrode K is reused as the gate T3g of the driving transistor T3.
  • the first plate Ca of the storage capacitor Cst is connected to the second connection electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connection electrode M to form a whole pixel circuit.
  • the first source-drain electrode T2a of the sensing transistor T2 is removed.
  • the first metal layer 301 is partially connected to the first metal layer 301, so that the parasitic capacitance can be reduced. That is, the power supply voltage signal line 3012 is narrowed at the position corresponding to the first source-drain electrode T2a of the sensing transistor T2 and the first connecting electrode M, so that the overlapping area and parasitic capacitance of the power supply voltage signal line 3012 and the first source-drain electrode T2a of the sensing transistor T2 can be reduced.
  • the initialization signal line 3011 and the data line 3013 are both straight lines extending in the second direction Y.
  • the power supply voltage signal line 3012 includes a first power supply voltage signal line 3012a extending in the second direction Y
  • the first power supply voltage signal line 3012a includes a first portion 3012b, a second portion 3012c and a third portion 3012d extending in the second direction Y and connected in sequence
  • the first portion 3012b and the third portion 3012d have the same width in the first direction X
  • the second portion 3012c has a width in the first direction X that is smaller than the first portion 3012b in the first direction X
  • one end of the second portion 3012c in the second direction Y is connected to an edge of the first portion 3012b close to the third portion 3012d and away from the initialization signal line 3011
  • the other end of the second portion 3012c in the second direction Y is connected to an edge of the third portion 3012d close to the first portion 3012
  • the edge of the second portion 3012c farthest from the initialization signal line 3011, the edge of the first portion 3012b farthest from the initialization signal line 3011, and the edge of the third portion 3012d farthest from the initialization signal line 3011 are all aligned and on a straight line, so a notch is formed between the second portion 3012c and the initialization signal line 3011.
  • the plane shape of the first electrode Ca is a rectangle.
  • the first metal layer 301 and the active layer 302 are stacked.
  • the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 and the orthographic projection of the initialization signal line 3011 on the substrate 31 overlap each other.
  • the orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31 and the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 and the orthographic projection of the first electrode Ca on the substrate 31 all overlap each other.
  • the orthographic projection of the channel region T1c of the switch transistor T1 on the substrate 31 and the structure on the first metal layer 301 do not overlap.
  • the gate T1g of the driving transistor T3, the gate T2g of the sensing transistor T2, and the gate T1g of the switching transistor T1 are all in the shape of a long strip extending in a direction parallel to the second direction Y.
  • the gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y
  • the gate T1g of the switching transistor T1 extends from the channel region T1c of the switching transistor T1 in the second direction Y.
  • the gate T3g of the driving transistor T3 and the second connection electrode K form an integral structure.
  • the first connection electrode M and the second electrode plate Cb form an integral structure.
  • the second metal layer 303 further includes a first connection structure 3041 and a second connection structure 3042 extending in the second direction Y, and a third connection structure 3042 extending in the first direction X, and the second connection electrode K is reused as the second connection structure 3042.
  • the second gate line 323 and the first gate line 321 are both in the shape of an elongated strip and extend in the first direction X.
  • the first connection electrode M is also in the shape of an elongated strip and extends in the first direction X.
  • the first connection structure 3041, the second connection structure 3042 and the third connection structure 3043 are used to realize the connection between the third metal layer 304 and other layer structures.
  • first via structure 3071 and a second via structure 3072 are shown in FIG20 , and the connection relationship between the first via structure 3071 and the second via structure 3072 is described below.
  • first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e, and 3071f)
  • second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, and 3072f) are shown at the position corresponding to one sub-pixel in FIG20 .
  • the six first via structures 3071 respectively correspond to the positions of the two ends of the channel region T2c of the sensing transistor T2, the positions of the two ends of the channel region T3c of the driving transistor T3, and the positions of the two ends of the channel region T1c of the switching transistor T1.
  • first via structure 3071a and the first via structure 3071b respectively correspond to the positions of the two ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to the positions of the two ends of the channel region T3c of the driving transistor T3; the first via structure 3071e and the first via structure 3071f respectively correspond to the positions of the two ends of the channel region T1c of the switching transistor T1.
  • the orthographic projections of the second via hole structure 3072a and the second via hole structure 3072b on the substrate substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate substrate 31 in the second direction Y; the orthographic projections of the second via hole structure 3072c and the second via hole structure 3072d on the substrate substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 in the second direction Y.
  • the orthographic projection of the second via structure 3072e on the base substrate 31 is located within the orthographic projection of the second connecting electrode K and the first electrode plate Ca on the base substrate 31, and is not located within the orthographic projection of the second electrode plate Cb on the base substrate 31; the orthographic projection of the second via structure 3072f on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31.
  • the channel region T2c of the sensing transistor T2 is electrically connected to the first connection structure 3041 through the first via structure 3071a.
  • the channel region T3c of the driving transistor T3 is electrically connected to the spacer 322a through the first via structure 3071c, and is electrically connected to the second electrode plate Cb through the first via structure 3071d;
  • the channel region T1c of the switching transistor T1 is electrically connected to the second connection structure 3042 through the first via structure 3071e, and is electrically connected to the third connection structure 3043 through the first via structure 3071f.
  • the first connection structure 3041 is electrically connected to the initialization signal line 3011 located at the first metal layer 301 through the second via structure 3072a and the second via structure 3072b.
  • the spacer 322a is electrically connected to the first portion 3012b of the first power supply voltage signal line 3012a through the second via structure 3072c, and the spacer 322b is electrically connected to the third portion 3012d of the first power supply voltage signal line 3012a through the second via structure 3072d.
  • the second connection electrode K is electrically connected to the first electrode plate Ca through the second via structure 3072e.
  • the third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f.
  • Figure 23 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided by at least one embodiment of the present invention
  • Figure 24 is a schematic diagram of the planar structure of the first metal layer included in the display panel in Figure 23
  • Figure 25 is a schematic diagram of the planar structure of the stack of the first metal layer and the active layer included in the display panel in Figure 23
  • Figure 26 is a schematic diagram of the planar structure of the stack of the first metal layer, the active layer and the second metal layer included in the display panel in Figure 23
  • Figure 27 is a schematic diagram of the planar structure of a via structure formed in the stacked structure shown in Figure 26
  • Figure 28 is a schematic diagram of the planar structure of the third metal layer included in the display panel in Figure 23.
  • the display panel 30 includes a base substrate 31, a pixel circuit 32 disposed on the base substrate 31, the pixel circuit 32 including a sensing transistor T2, a driving transistor T3, a switching transistor T1, a first gate line 321, a second gate line 323 and a storage capacitor Cst, a first source-drain electrode T2a of the sensing transistor T2 and a first source-drain electrode T3a of the driving transistor T3 are electrically connected through a first connecting electrode M; the first gate line 321 and the second gate line 323 extend in a first direction X, and in a second direction Y intersecting the first direction X, between the first connecting electrode M and the first gate line 321 and at A spacer 322 is provided between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are provided on the same layer, the spacer 322 is provided between the first connection electrode M and the first gate line 321,
  • the first source-drain electrode T1a of the switch transistor T1 and the gate T3g of the driving transistor T3 are connected through the second connection electrode K, the first plate Ca of the storage capacitor Cst is connected to the second connection electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connection electrode M to form a whole pixel circuit.
  • a spacer 322a and a spacer 322b located in the third metal layer 304 are respectively provided between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on both sides thereof in the second direction Y.
  • the spacer 322b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321.
  • the first source-drain electrode T2a of the sensing transistor T2 is located in the third metal layer 304, the power supply voltage signal line 3012 is located in the first metal layer 301, the spacer 322b located in the third metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072d; the spacer 322a located in the third metal layer 304 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072c.
  • the switch transistor T1 can reduce the coupling between the second connection electrode K and the first gate line 321 or the second gate line 323 .
  • the pixel circuit corresponding to two sub-pixels arranged in the first direction X is used as an example for description.
  • the first metal layer 301 includes an initialization signal line 3011, a power supply voltage signal line 3012, a first electrode Ca and a data line 3013 extending in the second direction Y, and a light shielding portion 3014.
  • the initialization signal line 3011 and the data line 3013 are both straight lines extending in the second direction Y.
  • the power supply voltage signal line 3012 includes a first power supply voltage signal line 3012a extending in the second direction Y, and the first power supply voltage signal line 3012a includes a first part 3012b, a second part 3012c and a third part 3012d extending in the second direction Y and connected in sequence, the first part 3012b and the third part 3012d have the same width in the first direction X, the width of the second part 3012c in the first direction X is smaller than the width of the first part 3012b in the first direction X, and one end of the second part 3012c in the second direction Y is connected to an edge of the first part 3012b close to the third part 3012d and away from the initialization signal line 3011, and the other end of the second part 3012c in the second direction Y is connected to an edge of the third part 3012d close to the first part 3012b and away from the initialization signal line 3011.
  • the edge of the second part 3012c farthest from the initialization signal line 3011, the edge of the first part 3012b farthest from the initialization signal line 3011, and the edge of the third part 3012d farthest from the initialization signal line 3011 are all aligned and on a straight line, so a notch is formed between the second part 3012c and the initialization signal line 3011.
  • a portion of the first metal layer 301 is removed below the first source-drain electrode T2a of the sensing transistor T2, which can reduce parasitic capacitance, that is, the power supply voltage signal line 3012 is narrowed at a position corresponding to the first source-drain electrode T2a of the sensing transistor T2 and the first connecting electrode M, which can reduce the overlapping area and parasitic capacitance of the power supply voltage signal line 3012 and the first source-drain electrode T2a of the sensing transistor T2.
  • the first metal layer 301, the active layer 302 and the second metal layer 303 are stacked in sequence
  • the second metal layer 303 includes the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, the gate T1g of the switch transistor T1 and the first electrode Ca, and the gates of the two switch transistors T1 are an integrated structure.
  • the gate T2g of the sensing transistor T2 and the gate T1g of the switch transistor T1 are both in the shape of a long strip extending in a direction parallel to the second direction Y, and the gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, and the gate T1g of the switch transistor T1 extends from the channel region T1c of the switch transistor T1 located below in the second direction Y.
  • the gate T3g of the driving transistor T3 and the first electrode Ca form an integrated structure.
  • the first electrode plate Ca includes a first electrode plate sub-block Ca1 and a second electrode plate sub-block Ca2 connected to each other
  • the second electrode plate sub-block Ca2 includes a first extension portion 3031 and a second extension portion 3032 extending in the second direction Y
  • two second connection structures 3042 are respectively connected to the first extension portion 3031 and the second extension portion 3032.
  • the orthographic projections of the first extension portion 3031 and the second extension portion 3032 on the base substrate 31 have no overlapping parts with the orthographic projections of the first metal layer 301 on the base substrate 31.
  • first via structure 3071 a first via structure 3071, a second via structure 3072, and a third via structure 3073 are shown in FIG23, and the connection relationship between the first via structure 3071, the second via structure 3072, and the third via structure 3073 is described below.
  • eight first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e1, 3071e2, 3071f1, and 3071f2), five second via structures 3072 (3072a, 3072b, 3072c, 3072d, and 3072e), and four third via structures 3073 (3073a, 3073b, 3073c, and 3073d) are shown at the position corresponding to one sub-pixel in FIG23.
  • the eight first via structures 3071 respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2, the positions of both ends of the channel region T3c of the driving transistor T3 and the positions of both ends of the channel region T1c of the two switch transistors T1.
  • the first via structure 3071a and the first via structure 3071b respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to the positions of both ends of the channel region T3c of the driving transistor T3; the first via structure 3071e1 and the first via structure 3071f1 respectively correspond to the positions of both ends of the channel region T1c of one of the switch transistors T1; The first via structure 3071e2 and the first via structure 3071f2 correspond to the positions of the two ends of the channel region T1c of another switch transistor T1, respectively.
  • the orthographic projections of the second via structure 3072a and the second via structure 3072b on the substrate substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate substrate 31 in the second direction Y; the orthographic projections of the second via structure 3072c and the second via structure 3072d on the substrate substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate 31, and are located on both sides of the channel region T2c of the sensing transistor T2 in the second direction Y, that is, they correspond to the first part 3012b and the third part 3012d included in the first power supply voltage signal line 3012a, respectively; the orthographic projection of the second via structure 3072e on the substrate substrate 31 is located within the orthographic projection of the data line 3013 on the substrate substrate 31.
  • the orthographic projection of the third via structure 3073a on the base substrate 31 is located within the orthographic projection of the gate T2g of the sensing transistor T2 on the base substrate 31; the orthographic projections of the third via structure 3073b and the third via structure 3073c on the base substrate 31 are respectively located within the orthographic projections of the first extension portion 3031 and the second extension portion 3032 on the base substrate 31; the orthographic projection of the third via structure 3073d on the base substrate 31 is located within the orthographic projection of the gate T1g of the switching transistor T1 on the base substrate 31.
  • the switching transistor T1 is two thin film transistors in parallel, one of which is arranged at a position close to the second gate line 323 on the upper side, and the other is arranged at a position close to the first gate line 321 on the lower side, that is, arranged on both sides of the first connecting electrode M in the second direction Y, and at the same time, the length of a part of the second electrode sub-block Ca2 in the second direction Y is reduced.
  • the above design can increase the channel width-to-length ratio and driving current of the switching transistor T1, which is beneficial to the driving of the high-resolution display panel and reduces the charging time.
  • a portion of the first metal layer 301 under the first source-drain electrodes T1 a of the two switch transistors T1 is removed, thereby preventing the first connection electrode M and the bottom gate of the switch transistor T1 from coupling to generate leakage current.
  • the light shielding portion 3014 includes a light shielding portion 3014a located below the channel region T3c of the driving transistor T3, a light shielding portion 3014b located below the channel region T1c of the upper switching transistor T1, and a light shielding portion 3014c located below the channel region T1c of the lower switching transistor T1.
  • the other structures of the switch transistor T1 except the first source-drain electrode T1a are not covered by the third metal layer, which can reduce the switching transistor T1 and the first source-drain electrode T1a.
  • a coupling effect of the connecting electrode M is not covered by the third metal layer, which can reduce the switching transistor T1 and the first source-drain electrode T1a.
  • the display panel 30 includes a first metal layer 301, an active layer 302, a second metal layer 303, and a third metal layer 304 which are sequentially stacked on a base substrate 31.
  • the insulating layer is not directly shown in the plan views shown in FIGS. 23 to 28, and only the via structure is used to represent the insulating layer, a layer structure that plays an insulating role is also provided between the adjacent layers, and a via structure is provided in the layer structure that plays an insulating role, and the layer structures that need to be connected are connected through the via structure.
  • the first metal layer 301 and the active layer 302 are stacked, and the active layer 302 includes the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, and the channel region T1c of the two switch transistors T1.
  • the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 and the orthographic projection of the initialization signal line 3011 on the substrate 31 overlap with each other.
  • the orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31 and the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 and the orthographic projection of the light shielding portion 3014a on the substrate 31 all overlap with each other.
  • the orthographic projections of the channel regions T1c of the two switch transistors T1 on the base substrate 31 overlap with the orthographic projections of the data line 3013 on the base substrate 31, and overlap with the orthographic projections of the light shielding portion 3014b and the light shielding portion 3014c on the base substrate 31 respectively.
  • the third metal layer 304 includes a first connection electrode M, a spacer 322, a second gate line 323 and a first gate line 321 extending in the first direction X and in an elongated shape, a first connection structure 3041 and a third connection structure 3043 extending in the second direction Y, and two second connection structures 3042 extending in the first direction X.
  • the orthographic projection of the first connection structure 3041 on the base substrate 31 is located within the orthographic projection of the initialization signal line 3011 on the base substrate 31, and the orthographic projection of the third connection structure 3043 on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31.
  • the first connection electrode M is also in an elongated shape and extends in the first direction X.
  • the first connection structure 3041, the second connection structure 3042 and the third connection structure 3043 are used to realize the connection between the third metal layer 304 and other layer structures.
  • the spacer 322b is located between the first connection electrode M and the first gate line 321, so as to reduce the voltage change on the first connection electrode M caused by the voltage jump of the first gate line 321.
  • the spacer 322a is located between the first connection electrode M and the second gate line 323, so as to reduce the voltage change on the first connection electrode M caused by the voltage jump of the second gate line 323, thereby reducing the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode.
  • Figure 29 is a schematic diagram of the cross-sectional structure of the display panel in Figure 23.
  • the display panel 30 also includes a buffer layer 305 arranged on the side of the first metal layer 301 away from the base substrate 31, a gate insulation layer 306 arranged between the active layer 302 and the second metal layer 303, an interlayer insulation layer 307 arranged between the second metal layer 303 and the third metal layer 304, and a passivation layer 308 and a planarization layer 309 arranged on the side of the third metal layer 304 away from the base substrate 31.
  • a first via structure 3071 is provided in the interlayer insulating layer 307 , and the third metal layer 304 is electrically connected to the active layer 302 through the first via structure 3071 .
  • a storage capacitor is formed between the third metal layer 304 and the second metal layer 303.
  • the first source-drain electrode T1a of the switch transistor T1 and the first plate Ca of the storage capacitor Cst are connected through the second connection electrode K, that is, the first source-drain electrodes T1a of the two switch transistors T1 are respectively connected to the first extension portion 3031 and the second extension portion 3032 included in the second plate sub-block Ca2.
  • Figure 30 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer and a second metal layer included in another display panel provided by at least one embodiment of the present invention
  • Figure 31 is a schematic diagram of the planar structure of a stack of a first metal layer and an active layer included in the display panel in Figure 30
  • Figure 32 is a schematic diagram of the planar structure of the second metal layer in Figure 30
  • Figure 33 is a schematic diagram of the cross-sectional structure of the display panel in Figure 30.
  • the display panel 30 includes a base substrate 31, a pixel circuit 32 arranged on the base substrate 31, the pixel circuit 32 includes a sensing transistor T2, a driving transistor T3, a switching transistor T1, a first gate line 321, a second gate line 323 and a storage capacitor Cst, and the first source-drain electrode T2a of the sensing transistor T2 and the first source-drain electrode T3a of the driving transistor T3 are electrically connected through the first connecting electrode M.
  • the first gate line 321 and the second gate line 323 extend in a first direction X, and in a second direction Y intersecting the first direction X, a spacer 322 is provided between the first connection electrode M and the first gate line 321, and between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are provided on the same layer, the spacer 322 is provided on the first connection electrode M and the first gate line 321, and between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are provided on the same layer, which can reduce the voltage change on the first connection electrode M caused by the voltage jump of the first gate line 321 or the second gate line 323, and further reduce the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, so as to ensure the service life of the light-emitting diode.
  • the first source-drain electrode T1a of the switch transistor T1 and the gate T3g of the drive transistor T3 are connected via the second connection electrode K, and the first electrode Ca of the storage capacitor Cst is connected to the second connection electrode K.
  • the second electrode plate Cb of the storage capacitor Cst is connected to the first connection electrode M to form an integral pixel circuit.
  • a spacer 322a and a spacer 322b located in the second metal layer 303 are respectively provided between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on both sides thereof in the second direction Y.
  • the spacer 322b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321.
  • the first source-drain electrode T2a of the sensing transistor T2 is located in the second metal layer 303, the power supply voltage signal line 3012 is located in the first metal layer 301, the spacer 322b located in the second metal layer 303 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072d; the spacer 322a located in the second metal layer 303 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072c.
  • the switch transistor T1 can reduce the coupling between the second connection electrode K and the gate line (the first gate line 321 or the second gate line 323 ).
  • the storage capacitor Cst includes a first electrode Ca located in the active layer 302 and a second electrode Cb located in the second metal layer 303 .
  • a portion of the first metal layer 301 is removed below the first source-drain electrode T2a of the sensing transistor T2, which can reduce parasitic capacitance, that is, the power supply voltage signal line 3012 is narrowed at a position corresponding to the first source-drain electrode T2a of the sensing transistor T2 and the first connecting electrode M, which can reduce the overlapping area and parasitic capacitance of the power supply voltage signal line 3012 and the first source-drain electrode T2a of the sensing transistor T2.
  • a portion of the first metal layer 301 under the first source-drain electrode T1a, the channel region T1c and the second source-drain electrode T1b of the switching transistor T1 is removed, thereby preventing the bottom gate coupling of the first connecting electrode M and the switching transistor T1 from generating leakage current.
  • the display panel 30 includes a first metal layer 301, an active layer 302, and a second metal layer 303 which are sequentially stacked on a base substrate 31.
  • the insulating layer is not directly shown in the plan views shown in FIG. 30 to FIG. 32, and only the via structure is used to represent the insulating layer, a layer structure that plays an insulating role is also provided between the adjacent layers, and a via structure is provided in the layer structure that plays an insulating role, and the layer structures that need to be connected are connected through the via structure.
  • the pixel circuit corresponding to two sub-pixels arranged in the first direction X is used as an example for description.
  • the first metal layer 301 includes an initialization signal line 3011, a power supply voltage signal line 3012, and a data line 3013 extending in the second direction Y.
  • the initialization signal line 3011 and the data line 3013 are both straight lines extending in the second direction Y.
  • the power supply voltage signal line 3012 includes a first power supply voltage signal line 3012a extending in the second direction Y, the first power supply voltage signal line 3012a includes a first portion 3012b, a second portion 3012c and a third portion 3012d extending in the second direction Y and connected in sequence, the first portion 3012b and the third portion 3012d have the same width in the first direction X, the second portion 3012c has a smaller width in the first direction X than the first portion 3012b, one end of the second portion 3012c in the second direction Y is connected to an edge of the first portion 3012b close to the third portion 3012d and away from the initialization signal line 3011, and the other end of the second portion 3012c in the second direction Y is connected to an edge of the third portion 3012d close to the first portion 3012b and away from the initialization signal line 3011.
  • the edge of the second part 3012c farthest from the initialization signal line 3011, the edge of the first part 3012b farthest from the initialization signal line 3011, and the edge of the third part 3012d farthest from the initialization signal line 3011 are all aligned and on a straight line, so a notch is formed between the second part 3012c and the initialization signal line 3011.
  • the first metal layer 301 and the active layer 302 are stacked, and the active layer 302 includes the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, the channel region T1c of the switch transistor T1, and the first electrode Ca of the storage capacitor Cst, and the channel region T3c of the driving transistor T3 and the first electrode Ca of the storage capacitor Cst are an integrated structure.
  • the positive projection of the channel region T2c of the sensing transistor T2 on the substrate substrate 31 and the positive projection of the initialization signal line 3011 on the substrate substrate 31 overlap each other.
  • the edge of the first electrode Ca of the storage capacitor Cst on the side close to the second gate line 321 extends in the first direction X to the top of the power supply voltage signal line 3012.
  • the second metal layer 303 includes a gate T2g of the sensing transistor T2, a gate T3g of the driving transistor T3, a gate T1g of the switching transistor T1, a second electrode Cb, a first connection electrode M, a spacer 322, a second gate line 323, a first gate line 321, a first connection structure 3041, a second connection structure 3042, and a third connection structure 3043.
  • the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, and the gate T1g of the switching transistor T1 are all in the shape of a strip extending in a direction parallel to the second direction Y, and the gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, and the gate T1g of the switching transistor T1 extends from the channel region T1c of the switching transistor T1 in the second direction Y.
  • the orthographic projection of the second electrode Cb on the base substrate 31 is located within the orthographic projection of the first electrode Ca on the base substrate 31.
  • the second gate line 323 and the first gate line 321 are both in the shape of long strips and are arranged in the first direction X.
  • the first connection electrode M is also in the shape of an elongated strip and extends in the first direction X.
  • the first connection structure 3041 extends in the second direction Y, and the second connection structure 3042 and the third connection structure 3043 extend in the first direction X.
  • the first connection structure 3041, the second connection structure 3042 and the third connection structure 3043 are used to realize the connection between the third metal layer 304 and other layer structures.
  • the spacer 322b is located between the first connection electrode M and the first gate line 321, so that the voltage change caused to the first connection electrode M when the first gate line 321 generates a voltage jump can be reduced
  • the spacer 322a is located between the first connection electrode M and the second gate line 323, so that the voltage change caused to the first connection electrode M when the second gate line 323 generates a voltage jump can be reduced, thereby reducing the damage caused to the light-emitting diode by the voltage change of the first connection electrode M to ensure the service life of the light-emitting diode.
  • first via structure 3071 and a second via structure 3072 are shown in FIG30, and the connection relationship between the first via structure 3071 and the second via structure 3072 is described below.
  • first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e, and 3071f)
  • second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, and 3072f) are shown at the position corresponding to one sub-pixel in FIG30.
  • the six first via structures 3071 respectively correspond to the positions of the two ends of the channel region T2c of the sensing transistor T2, the positions of the two ends of the channel region T3c of the driving transistor T3, and the positions of the two ends of the channel region T1c of the two switching transistors T1.
  • first via structure 3071a and the first via structure 3071b respectively correspond to the positions of the two ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to the positions of the two ends of the channel region T3c of the driving transistor T3; the first via structure 3071e and the first via structure 3071f respectively correspond to the positions of the two ends of the channel region T1c of the switching transistor T1.
  • the orthographic projections of the second via structure 3072a and the second via structure 3072b on the substrate substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the substrate substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate substrate 31 in the second direction Y;
  • the orthographic projections of the second via structure 3072c and the second via structure 3072d on the substrate substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate 31, and are located on both sides of the channel region T2c of the sensing transistor T2 in the second direction Y, that is, they correspond to the first part 3012b and the third part 3012d included in the first power supply voltage signal line 3012a respectively;
  • the orthographic projection of the second via structure 3072e on the substrate substrate 31 is located within the orthographic projection of the first electrode plate Ca on the substrate substrate 31, and is not located within the orthographic projection of the second electrode plate Cb on the substrate substrate 31;
  • the channel region T2c of the sensing transistor T2 is electrically connected to the first connection structure 3041 through the first via structure 3071a, and is electrically connected to the first connection electrode M through the first via structure 3071b;
  • the channel region T3c of the driving transistor T3 is electrically connected to the spacer 322a through the first via structure 3071c, and is electrically connected to the second electrode plate Cb through the first via structure 3071d;
  • the channel region T1c of the switching transistor T1 is electrically connected to the second connection structure 3042 through the first via structure 3071e, and is electrically connected to the third connection structure 3043 through the first via structure 3071f.
  • the first connection structure 3041 is electrically connected to the initialization signal line 3011 located at the first metal layer 301 through the second via structure 3072a and the second via structure 3072b.
  • the spacer 322a is electrically connected to the first portion 3012b of the first power supply voltage signal line 3012a through the second via structure 3072c, and the spacer 322b is electrically connected to the third portion 3012d of the first power supply voltage signal line 3012a through the second via structure 3072d.
  • the second connection electrode K is electrically connected to the first electrode plate Ca through the second via structure 3072e.
  • the third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f.
  • the gate T2g of the sensing transistor T2 extends in the second direction Y to be directly electrically connected to the first gate line 321 or is integrally formed.
  • the gate T1g of the switch transistor T1 extends in a direction opposite to the second direction Y to be directly electrically connected to the second gate line 323 or is integrally formed, and the first gate line 321 connected to the gate T2g of the sensing transistor T2 and the second gate line 323 connected to the gate T1g of the switch transistor T1 are located on different sides of the spacer 322 in the second direction Y.
  • the orthographic projection of the first connection structure 3041 on the base substrate 31 is located within the orthographic projection of the initialization signal line 3011 on the base substrate 31, and the orthographic projection of the third connection structure 3043 on the base substrate 31 and the orthographic projection of the second connection structure 3042 on the base substrate 31 do not overlap with the orthographic projection of the first metal layer 301 on the base substrate 31.
  • the orthographic projections of the spacers 322a and 322b on the base substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the base substrate 31.
  • a spacer 322a and a spacer 322b located in the second metal layer 303 are respectively provided between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on both sides thereof in the second direction Y.
  • the spacer 322b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321.
  • the first source-drain electrode T2a of the sensing transistor T2 is located in the second metal layer 303.
  • the power supply voltage signal line 3012 is located in the first metal layer 301, and the spacing portion 322b located in the second metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072d; the spacing portion 322a located in the second metal layer 303 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072c.
  • the voltage change of the first connection electrode M will cause the voltage change of the second connection electrode K.
  • the voltage rise of the first connection electrode M is normal.
  • the rise of the voltage of the second connection electrode K is caused by the coupling of the voltage rise of the first connection electrode M.
  • the second connection electrode K and the power supply voltage signal line 3012 are equivalent to a capacitor, and the storage capacitor Cst is also a capacitor.
  • the voltage rise of the second connection electrode K is not as high as the voltage rise of the first connection electrode M.
  • the voltage of the first connection electrode M is more stable, so the first connection electrode M is protected and shielded by the spacer 322 to reduce the jump voltage.
  • the above design can make the spacer 322 set between the first connection electrode M and the first gate line 321, and the first connection electrode M is formed in the second metal layer 303, and is set in the same layer as the first gate line 321. Through the shielding effect of the spacer 322, the life of the organic light emitting diode display device can be extended.
  • the sensing transistor T2 and the first connection electrode M connected thereto have spacers 322 on both sides of the second direction Y, which respectively shield the influence of the first gate line 321 and the second gate line 323 on the voltage change of the first connection electrode M, that is, due to the existence of the spacers 322, a parasitic capacitance cannot be formed between the first gate line 321 or the second gate line 323 and the first connection electrode M.
  • the positive projection of the first source-drain electrode T2a of the sensing transistor T2 on the substrate 31 is spaced from the positive projection of the power supply voltage signal line 3012 on the substrate 31, that is, the first source-drain electrode T2a of the sensing transistor T2 is at the recess between the second part 3012c and the initialization signal line 3011.
  • the display panel 30 further includes a buffer layer 305 disposed on a side of the first metal layer 301 away from the base substrate 31, a gate insulating layer 306 and an interlayer insulating layer 307 disposed between the active layer 302 and the second metal layer 303, and a passivation layer 308 and a planarization layer 309 disposed on a side of the second metal layer 303 away from the base substrate 31, a first via structure 3071 is disposed in the interlayer insulating layer 307, and the second metal layer 303 is electrically connected to the active layer 302 through the first via structure 3071; a second via structure 3072 is penetrated in the interlayer insulating layer 307 and the buffer layer 305, and the second metal layer 303 is connected to the first metal layer 301 through the second via structure 3072.
  • the power supply voltage signal line 3012 is electrically connected.
  • Figure 34 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided by at least one embodiment of the present invention
  • Figure 35 is a schematic diagram of the planar structure of the stack of the first metal layer and the third metal layer included in the display panel in Figure 34.
  • the display panel shown in FIG. 34 is different from the display panel shown in FIG. 14 in that the display panel shown in FIG. 34 further includes a cathode voltage trace 324, and the cathode voltage trace 324 includes a first cathode voltage trace 3241 located between the first gate line 321 and the second gate line 323 in the third metal layer 304, and the first cathode voltage trace 3241 extends in the first direction X.
  • the cathode voltage trace 324 also includes a second cathode voltage trace 3242 located between two adjacent data lines 3013 in the first metal layer 301.
  • first cathode voltage trace 3241 extending in the first direction X (transverse) and the second cathode voltage trace 3242 extending in the second direction Y (longitudinal) intersect and are electrically connected, which can reduce the voltage drop of medium and large-sized organic light-emitting diode display devices.
  • the second cathode voltage trace 3242 is arranged between the two data lines 3013, and can also shield the crosstalk between the data signals.
  • the first cathode voltage wiring 3241 is disposed between the first gate line 321 and the second gate line 323 , and can also shield the crosstalk between the gate line signals.
  • the display panel shown in Figure 34 is different from the display panel shown in Figure 14 in that the third metal layer 304 also includes a power supply voltage signal line 3012 extending in the first direction X, that is, the power supply voltage signal line 3012 also includes a second power supply voltage signal line 3012e extending laterally, and the second power supply voltage signal line 3012e intersects and is electrically connected to the first power supply voltage signal line 3012a, which can reduce the voltage drop of medium and large-sized organic light-emitting diode display devices.
  • a first via structure 3071, a second via structure 3072, and a third via structure 3073 are shown in Fig. 34.
  • eight first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e1, 3071e2, 3071f1, and 3071f2)
  • eight second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, 3072f, 3072g, and 3072h)
  • four third via structures 3073 (3073a, 3073b2, 3073b2, and 3073c) are shown at a position corresponding to one sub-pixel in Fig. 34.
  • the difference between the above-mentioned via structures corresponding to the display panel shown in Figure 34 and the display panel shown in Figure 14 is that the display panel shown in Figure 34 has two more second via structures, namely, the second via structure 3072g and the second via structure 3072h.
  • the layer structure connected by the other second via structures, the first via structure and the third via structure can be referred to the above-mentioned description about Figure 14 and will not be repeated here.
  • the second power supply voltage signal line 3012e passes through the second via structure 3072g.
  • the first cathode voltage trace 3241 is electrically connected to the first power voltage signal line 3012a located in the first metal layer 301 through the second via structure 3072h and the second cathode voltage trace 3242 located in the first metal layer 301, which can further reduce the resistance between the first metal layer 301 and the third metal layer 304.
  • FIG36 is a schematic diagram of a planar structure of a stack of a first metal layer, an active layer, a second metal layer, and a third metal layer included in another display panel provided by at least one embodiment of the present invention.
  • FIG37 is a schematic diagram of a cross-sectional structure of a second cathode voltage trace of the display panel shown in FIG36 cut along a second direction
  • FIG38 is a schematic diagram of a cross-sectional structure of adding a cathode and a pixel defining layer to the structure shown in FIG37
  • FIG39 is a schematic diagram of a cross-sectional structure of adding an organic light emitting diode to the display panel shown in FIG36.
  • the display panel shown in FIG36 is different from the display panel shown in FIG34 in that the first cathode voltage trace 3241 includes a three-layer stacked structure.
  • the second cathode voltage trace 3242 includes a second cathode voltage trace first sublayer 3242a located in the first metal layer 301, a second cathode voltage trace second sublayer 3242b located in the second metal layer 303, and a second cathode voltage trace third sublayer 3242c located in the third metal layer 304, the second cathode voltage trace first sublayer 3242a and the second cathode voltage trace third sublayer 3242c are electrically connected through the fourth via structure 3074, and the second cathode voltage trace first sublayer 3242a and the second cathode voltage trace third sublayer 3242c are electrically connected at two locations through the fourth via structure 3074a and the fourth via structure 3074b, respectively.
  • the second sublayer 3242b of the second cathode voltage routing and the third sublayer 3242c of the second cathode voltage routing are electrically connected through the fifth via structure 3075.
  • the second sublayer 3242b of the second cathode voltage routing and the third sublayer 3241c of the second cathode voltage routing are electrically connected at two locations through the fifth via structure 3075a and the fifth via structure 3075b respectively, thereby reducing the resistance of the second cathode voltage routing.
  • first via structure 3071 a first via structure 3071, a second via structure 3072, and a third via structure 3073 are shown in FIG36.
  • eight first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e1, 3071e2, 3071f1, and 3071f2) are shown at positions corresponding to one sub-pixel in FIG36. 3071f2), seven second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, 3072f, 3072g and 3072j), four third via structures 3073 (3073a, 3073b2, 3073b2 and 3073c), two fourth via structures 3074 (3074a and 3074b), and two fifth via structures 3075 (3075a and 3075b). Except for the fourth via structure 3074 and the fifth via structure 3075, the relationship between other via structures and layer structures can be referred to the above description of FIG. 34, which will not be repeated here.
  • the display panel also includes an organic light emitting diode
  • the organic light emitting diode can be three luminescent materials of R, G, and B deposited in the corresponding pixel area, or can use a luminescent material, such as a blue OLED luminescent material and device combined with a photoluminescent quantum dot material.
  • the organic light emitting diode includes an anode 312, a light emitting functional layer 313 and a cathode 311, and the light emitting functional layer 313 is arranged in the opening area defined by the pixel defining layer 310.
  • any one of the first sublayer 3242a of the second cathode voltage routing, the second sublayer 3242b of the second cathode voltage routing, and the third sublayer 3242c of the second cathode voltage routing is electrically connected to the anode 312 through the sixth via structure 3076.
  • the third sublayer 3242c of the second cathode voltage routing is electrically connected to the anode 312 through the sixth via structure 3076, so that the step difference of the anode 312 can be reduced.
  • the display panel 30 further includes a buffer layer 305 disposed on a side of the first metal layer 301 away from the base substrate 31, the buffer layer 305 is formed in a whole layer on the base substrate 31, and a first sublayer 3242a of the second cathode voltage wiring is shown on the first metal layer 301.
  • a gate insulating layer 306 is disposed between the active layer 302 and the second metal layer 303, and an interlayer insulating layer 307 is disposed between the second metal layer 303 and the third metal layer 304.
  • a passivation layer 308, a planarization layer 309, and a pixel defining layer 310 are sequentially disposed on a side of the third metal layer 304 away from the base substrate 31.
  • the interlayer insulating layer 307, the passivation layer 308, and the planarization layer 309 are also formed in a whole layer.
  • FIG. 38 shows that the cathode 311 is directly electrically connected to the third metal layer 304 , which can also reduce the cathode step difference.
  • the material of active layer 302 may be low temperature polysilicon or oxide semiconductor, such as IGZO.
  • the materials of first metal layer 301, second metal layer 303 and third metal layer 304 may be copper, aluminum, molybdenum or alloys thereof.
  • FIG40 is a schematic diagram of a planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided by at least one embodiment of the present invention
  • FIG41 is a schematic diagram of a cross-sectional structure of the display panel shown in FIG40. As shown in FIGS.
  • the display panel further includes an encapsulation layer 314 disposed on the organic light emitting diode, a quantum dot layer 315 disposed on the encapsulation layer 314, and a protective layer 316 disposed on a side of the quantum dot layer 315 away from the base substrate 31, wherein
  • the quantum dot layer 315 is configured to process the light emitted from the organic light emitting diode to improve the purity of the emitted light and make the light mixing more uniform.
  • FIG42 is a block diagram of a display device provided by at least one embodiment of the present invention.
  • the display device includes any of the display panels described above, and the display device 200 includes a display panel 30.
  • the display panel 100 can be a display panel provided by any embodiment of the present invention.
  • the display device 200 may be a display device with a display function.
  • the display device 200 may be a display, an OLED display panel, an OLED TV, a liquid crystal display panel, a liquid crystal display TV, a QLED display panel, a QLED TV, an electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function and a touch function.
  • a display panel is provided, wherein a spacer located in the third metal layer is provided between the sensing transistor and the first gate line and the second gate line located on both sides of the sensing transistor in the second direction, respectively, and the spacer can shield the coupling between the first source-drain electrode of the sensing transistor and the first gate line.
  • the switching transistor is two thin film transistors connected in parallel, one of which is arranged at a position close to the second gate line on the upper side, and the other is arranged at a position close to the first gate line on the lower side, that is, they are arranged on both sides of the first connecting electrode in the second direction, and at the same time, a portion of the first electrode plate of the storage capacitor is reduced in length in the second direction.
  • This design can increase the channel width-to-length ratio and driving current of the switching transistor, which is beneficial to the driving of the high-resolution display panel and reduces the charging time.
  • a portion of the first metal layer is removed below the first source-drain electrode of the sensing transistor, thereby reducing parasitic capacitance. That is, the power supply voltage signal line is narrowed at the position corresponding to the first source-drain electrode and the first connecting electrode of the sensing transistor, thereby reducing the overlapping area and parasitic capacitance of the power supply voltage signal line and the first source-drain electrode of the sensing transistor.
  • the display panel provided by the second cathode voltage wiring includes The first sublayer of the second cathode voltage routing is located at the first metal layer, the second sublayer of the second cathode voltage routing is located at the second metal layer, and the third sublayer of the second cathode voltage routing is located at the third metal layer. In this way, the resistance can be reduced. Any one of the first sublayer of the second cathode voltage routing, the second sublayer of the second cathode voltage routing, and the third sublayer of the second cathode voltage routing is electrically connected to the anode through the sixth via structure, which can reduce the anode step difference.

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Abstract

本发明至少一实施例提供一种显示面板和显示装置，该显示面板包括衬底基板；设置在衬底基板上的像素电路，像素电路包括感应晶体管、驱动晶体管、第一栅线和第二栅线，其中，感应晶体管的第一源漏电极和驱动晶体管的第一源漏电极通过第一连接电极电连接；第一栅线和第二栅线在第一方向上延伸，在与第一方向交叉的第二方向上，在第一连接电极和第一栅线之间，第一连接电极和第二栅线之间均设置有间隔部，且第一连接电极、第一栅线、第二栅线和间隔部设置在同一层，感应晶体管和在第二方向上位于其两侧的第一栅线和第二栅线之间分别具有位于第三金属层的间隔部，该间隔部可以屏蔽感应晶体管的第一源漏电极与第一栅线或者第二栅线之间的耦合。

Description

显示面板和显示装置
本申请要求于2023年06月14日递交的中国专利申请第202310699370.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本发明的实施例涉及一种显示面板和显示装置。
背景技术
目前在显示领域中广泛使用的显示器件包括薄膜晶体管液晶显示器件(TFT-LCD)和有源矩阵有机发光二极管(AMOLED)显示器件等。有源矩阵有机发光二极管(AMOLED)显示器件具有寿命长、显示亮度高、对比度大和色域广的优点。
以有源矩阵有机发光二极管作为发光元件的有机发光二极管显示器件，比常规的液晶显示器件的厚度更薄，且重量比常规的液晶显示器件的重量更轻，有机发光二极管显示器件还具有响应速度快、视角宽和低电压驱动的特性，因此，有机发光二极管显示器件可以广泛应用于蜂窝电话、便携信息终端、电视和监视器中。有机发光二极管显示器件的结构主要包括阴极和阳极，和夹设在阴极和阳极之间的发光功能层。在有源矩阵有机发光二极管显示器件中，每个子像素中都具有开关晶体管和驱动晶体管，通过调整开关晶体管和驱动晶体管使得有机发光二极管显示器件中的发光层发光。
发明内容
本发明至少一实施例提供一种显示面板和显示装置，该显示面板包括：设置在衬底基板上的像素电路，像素电路包括感应晶体管、驱动晶体管、第一栅线和第二栅线，其中，感应晶体管的第一源漏电极和驱动晶体管的第一源漏电极通过第一连接电极电连接；第一栅线和第二栅线在第一方向上延伸，在与第一方向交叉的第二方向上，在第一连接电极和第一栅线之间，第一连接电极和第二栅线之间均设置有间隔部，且第一连接电极、第一栅线、第二栅线和间隔 部设置在同一层，本发明的实施例通过在第一连接电极和第一栅线之间，以及在第一连接电极和第二栅线之间设置间隔部，且使得第一连接电极、第一栅线、第二栅线和间隔部设置在同一层，可以减小第一栅线或者第二栅线产生电压跳变时对第一连接电极带来的电压变化，从而可以降低对发光二极管造成的损伤，以保证发光二极管的使用寿命。
本发明至少一实施例提供一种显示面板，该显示面板包括：衬底基板；设置在所述衬底基板上的像素电路，所述像素电路包括感应晶体管、驱动晶体管、第一栅线和第二栅线，其中，所述感应晶体管的第一源漏电极和所述驱动晶体管的第一源漏电极通过第一连接电极电连接；所述第一栅线和所述第二栅线在第一方向上延伸，在与所述第一方向交叉的第二方向上，在所述第一连接电极和所述第一栅线之间，以及在所述第一连接电极和所述第二栅线之间均设置有间隔部，且所述第一连接电极、所述第一栅线、所述第二栅线和所述间隔部设置在同一层。
例如，本发明至少一实施例提供的显示面板，还包括设置在所述衬底基板上的开关晶体管和存储电容，其中，所述开关晶体管的第一源漏电极和所述驱动晶体管的栅极通过第二连接电极连接，所述存储电容的第一极板和所述第二连接电极连接，所述存储电容的第二极板和所述第一连接电极连接。
例如，本发明至少一实施例提供的显示面板，还包括依次层叠设置在所述衬底基板上的第一金属层、有源层、第二金属层和第三金属层，其中，所述第一金属层包括在所述第二方向上延伸的初始化信号线、至少部分在所述第二方向上延伸的电源电压信号线、所述第一极板和数据线；所述有源层包括所述感应晶体管的沟道区、所述驱动晶体管的沟道区和所述开关晶体管的沟道区；所述第二金属层包括所述感应晶体管的栅极、所述驱动晶体管的栅极、所述开关晶体管的栅极和所述第二极板；所述第三金属层包括所述第一连接电极、所述间隔部、在所述第一方向上延伸的所述第二栅线和所述第一栅线。
例如，在本发明至少一实施例提供的显示面板中，所述感应晶体管的栅极在所述第二方向上延伸至和所述第一栅线电连接，所述开关晶体管的栅极在与所述第二方向相反的方向上延伸至和所述第二栅线电连接，且和所述感应晶体管的栅极连接的所述第一栅线与和所述开关晶体管的栅极连接的所述第二栅线在所述第二方向上位于任一所述间隔部的不同侧。
例如，在本发明至少一实施例提供的显示面板中，所述第三金属层还包括 在所述第二方向上延伸的第一连接结构、第二连接结构和第三连接结构，其中，所述第一连接结构在所述衬底基板上的正投影位于所述初始化信号线在所述衬底基板上的正投影之内，所述第二连接结构在所述衬底基板上的正投影位于所述第一极板在所述衬底基板上的正投影之内，所述第三连接结构在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影之内。
例如，本发明至少一实施例提供的显示面板，还包括设置在所述第一金属层的远离所述衬底基板的一侧的缓冲层，设置在所述有源层和所述第二金属层之间的栅绝缘层，设置在所述第二金属层和所述第三金属层之间的层间绝缘层，以及设置在所述第三金属层的远离所述衬底基板的一侧的钝化层和平坦化层。
例如，在本发明至少一实施例提供的显示面板中，在所述层间绝缘层中设置有第一过孔结构和第三过孔结构，所述第三金属层通过所述第一过孔结构和所述有源层电连接，所述第三金属层通过所述第三过孔结构和所述第二金属层电连接；在所述层间绝缘层和所述缓冲层中贯穿有第二过孔结构，所述第三金属层通过所述第二过孔结构和所述第一金属层电连接。
例如，在本发明至少一实施例提供的显示面板中，所述第一连接结构通过所述第二过孔结构和所述初始化信号线电连接，且通过所述第一过孔结构和所述感应晶体管的第二源漏电极电连接；所述第二连接结构通过所述第一过孔结构和所述开关晶体管的所述第一源漏电极电连接，且通过所述第三过孔结构和所述第二极板电连接；所述第三连接结构通过所述第二过孔结构和所述数据线电连接，且通过所述第一过孔结构和所述开关晶体管的第二源漏电极电连接。
例如，在本发明至少一实施例提供的显示面板中，所述第三金属层的至少一部分和所述第一金属层、所述第二金属层均存在交叠区域，以在所述第一金属层和所述第二金属层之间形成所述存储电容，在所述第二金属层和所述第三金属层之间形成电容结构。
例如，在本发明至少一实施例提供的显示面板中，所述感应晶体管的所述第一源漏电极在所述衬底基板上的正投影和所述电源电压信号线在所述衬底基板上的正投影相交叠。
例如，在本发明至少一实施例提供的显示面板中，所述电源电压信号线包括在所述第二方向上延伸的第一电源电压信号线，所述第一电源电压信号线 包括在所述第二方向上延伸且依次连接的第一部分、第二部分和第三部分，所述第一部分和所述第三部分在所述第一方向上的宽度相等，所述第二部分在所述第一方向上的宽度小于所述第一部分在所述第一方向上的宽度，且所述第二部分在所述第二方向上的一端和所述第一部分的靠近所述第三部分且远离所述初始化信号线的边缘连接，所述第二部分在所述第二方向上的另一端和所述第三部分的靠近所述第一部分且远离所述初始化信号线的边缘连接。
例如，在本发明至少一实施例提供的显示面板中，所述感应晶体管的所述第一源漏电极在所述衬底基板上的正投影和所述电源电压信号线的所述第二部分在所述衬底基板上的正投影相间隔。
例如，在本发明至少一实施例提供的显示面板中，所述第一极板包括在所述第一方向上相互连接的第一极板子块和第二极板子块，所述第二金属层包括在所述第二方向上从所述第二极板的对应于所述第二极板子块的部分延伸的第一延伸部和第二延伸部，两个所述第二连接电极分别和所述第一延伸部、所述第二延伸部连接。
例如，本发明至少一实施例提供的显示面板，还包括有机发光二极管，其中，Ast为所述存储电容的面积，dgc为所述第一栅线和所述存储电容之间的最小间距，Lc为所述第一极板子块的和所述第一栅线相邻的边的长度，Wg为所述第一栅线在所述第二方向上的宽度，THKILD为所述存储电容对应的层间绝缘层的厚度。
例如，在本发明至少一实施例提供的显示面板中，VgON为所述第二栅线的开启电压，VgOFF为所述第二栅线的关闭电压，Voled为所述有机发光二极管两端的电压，γ为光学常数。
例如，在本发明至少一实施例提供的显示面板中，所述存储电容为所述第一金属层、所述第二金属层和所述第三金属层形成的三层结构，THKBUF为所述存储电容中所述第一金属层和所述第二金属层之间的缓冲层的厚度。
例如，在本发明至少一实施例提供的显示面板中，
例如，在本发明至少一实施例提供的显示面板中，WDD为在所述第一栅线和所述第一连接电极之间的所述间隔部在所述第二方向上的长度，dgd为所述第一栅线和在所述第一栅线和所述第一连接电极之间的所述间隔部之间的最小间距，dsd为所述第一连接电极和在所述第一栅线和所述第一连接电极之间的所述间隔部之间的最小间距。
例如，在本发明至少一实施例提供的显示面板中，Lc为所述第一极板子块的和所述第一栅线相邻的边的长度，Lp为所述第一极板子块和所述第二极板子块在所述第一方向上的长度之和，Rl为所述第一极板子块的和所述第一栅线相邻的边的长度与所述第一极板子块和所述第二极板子块在所述第一方向上的长度之和的比值。
例如，在本发明至少一实施例提供的显示面板中，Wc为所述存储电容在所述第一方向上的宽度，Pitch为一个子像素在所述第一方向上的宽度。
例如，本发明至少一实施例提供的显示面板，还包括依次层叠设置在所述衬底基板上的第一金属层、有源层和第二金属层，其中，所述第一金属层包括在所述第二方向上延伸的初始化信号线、至少部分在所述第二方向上延伸的电源电压信号线、所述第一极板和数据线；所述有源层包括所述感应晶体管的沟道区、所述驱动晶体管的沟道区和所述开关晶体管的沟道区；所述第二金属层包括所述感应晶体管的栅极、所述驱动晶体管的栅极、所述开关晶体管的栅极、所述第二极板、所述第一连接电极、所述间隔部、在所述第一方向上延伸的所述第二栅线和所述第一栅线。
例如，在本发明至少一实施例提供的显示面板中，所述开关晶体管的栅极和所述第二栅线电连接，所述感应晶体管的栅极和所述第一栅线电连接，且和所述开关晶体管的栅极连接的所述第二栅线与和所述感应晶体管的栅极连接的所述第一栅线在所述第二方向上位于所述第一极板的不同侧，在所述第二方向上，所述第二连接电极在所述第一连接电极和与所述开关晶体管的栅极连接的所述第二栅线之间。
例如，本发明至少一实施例提供的显示面板，还包括设置在所述衬底基板 上的开关晶体管，其中，所述开关晶体管的第一源漏电极和所述驱动晶体管的栅极通过第二连接电极连接。
例如，本发明至少一实施例提供的显示面板，还包括依次层叠设置在所述衬底基板上的第一金属层、有源层、第二金属层和第三金属层，其中，所述第一金属层包括在所述第二方向上延伸的初始化信号线、电源电压信号线和数据线，以及遮光部；所述有源层包括所述感应晶体管的沟道区、所述驱动晶体管的沟道区和所述开关晶体管的沟道区；所述第二金属层包括所述感应晶体管的栅极、所述驱动晶体管的栅极和所述开关晶体管的栅极；所述第三金属层包括所述第一连接电极、所述间隔部、在所述第一方向上延伸的所述第二栅线和所述第一栅线。
例如，在本发明至少一实施例提供的显示面板中，所述第三金属层还包括在所述第二方向上延伸的第一连接结构和第二连接结构，所述第一连接结构在所述衬底基板上的正投影位于所述初始化信号线在所述衬底基板上的正投影之内，所述第二连接结构在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影之内。
例如，本发明至少一实施例提供的显示面板，还包括设置在所述第一金属层的远离所述衬底基板的一侧的缓冲层，设置在所述有源层和所述第二金属层之间的栅绝缘层，设置在所述第二金属层和所述第三金属层之间的层间绝缘层，以及设置在所述第三金属层的远离所述衬底基板的一侧的钝化层和平坦化层。
例如，在本发明至少一实施例提供的显示面板中，在所述层间绝缘层中设置有第一过孔结构，所述第三金属层通过所述第一过孔结构和所述有源层电连接；在所述层间绝缘层和所述缓冲层中贯穿有第二过孔结构，所述第三金属层通过所述第二过孔结构和所述电源电压信号线电连接。
例如，在本发明至少一实施例提供的显示面板中，在所述第三金属层和所述第二金属层之间形成有存储电容。
例如，本发明至少一实施例提供的显示面板，还包括设置在所述衬底基板上的开关晶体管和存储电容，其中，所述开关晶体管的第一源漏电极和所述存储电容的第一极板通过第二连接电极连接。
例如，本发明至少一实施例提供的显示面板，还包括依次层叠设置在所述衬底基板上的第一金属层、有源层和第二金属层，其中，所述第一金属层包括 在所述第二方向上延伸的初始化信号线、电源电压信号线和数据线；所述有源层包括所述感应晶体管的沟道区、所述驱动晶体管的沟道区、所述开关晶体管的沟道区和所述第一极板；所述第二金属层包括所述感应晶体管的栅极、所述驱动晶体管的栅极和所述开关晶体管的栅极、所述第一连接电极、所述间隔部、所述存储电容的第二极板、在所述第一方向上延伸的所述第二栅线和所述第一栅线。
例如，在本发明至少一实施例提供的显示面板中，所述存储电容的所述第一极板的靠近所述第二栅线的一侧的边缘在所述第一方向上延伸至所述电源电压信号线的正上方。
例如，在本发明至少一实施例提供的显示面板中，所述第二金属层还包括在所述第二方向上延伸的第一连接结构，所述第一连接结构在所述衬底基板上的正投影位于所述初始化信号线在所述衬底基板上的正投影之内。
例如，本发明至少一实施例提供的显示面板，还包括设置在所述第一金属层的远离所述衬底基板的一侧的缓冲层，设置在所述有源层和所述第二金属层之间的栅绝缘层、层间绝缘层，以及设置在所述第二金属层的远离所述衬底基板的一侧的钝化层和平坦化层，其中，在所述层间绝缘层中设置有第一过孔结构，所述第二金属层通过所述第一过孔结构和所述有源层电连接；在所述层间绝缘层和所述缓冲层中贯穿有第二过孔结构，所述第二金属层通过所述第二过孔结构和所述电源电压信号线电连接。
例如，本发明至少一实施例提供的显示面板，还包括阴极电压走线，其中，所述阴极电压走线包括在所述第一方向上延伸的第一阴极电压走线和在所述第二方向上延伸的第二阴极电压走线，所述第一阴极电压走线和所述第二阴极电压走线相交；所述电源电压信号线还包括在所述第一方向上延伸的第二电源电压信号线，所述第一电源电压信号线和所述第二电源电压信号线相交。
例如，在本发明至少一实施例提供的显示面板中，所述第二阴极电压走线包括三层层叠结构，且所述第二阴极电压走线包括位于所述第一金属层的第二阴极电压走线第一子层，位于所述第二金属层的第二阴极电压走线第二子层，和位于所述第三金属层的第二阴极电压走线第三子层，所述第二阴极电压走线第一子层和所述第二阴极电压走线第三子层通过第四过孔结构电连接，所述第二阴极电压走线第二子层和所述第二阴极电压走线第三子层通过第五过孔结构电连接。
例如，本发明至少一实施例提供的显示面板，还包括有机发光二极管，其中所述有机发光二极管包括阳极，所述第二阴极电压走线第一子层、所述第二阴极电压走线第二子层和所述第二阴极电压走线第三子层中的任意一个通过第六过孔结构和所述阳极电连接。
例如，在本发明至少一实施例提供的显示面板中，所述第一阴极电压走线第三子层通过所述第六过孔结构和所述阳极电连接。
例如，本发明至少一实施例提供的显示面板，还包括设置在所述有机发光二极管上封装层，和设置在封装层上的量子点层，其中，所述量子点层配置为对从所述有机发光二极管出射的光线进行处理。
本发明至少一实施例还提供一种显示装置，该显示装置包括上述任一实施例提供的显示面板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明至少一实施例提供的显示面板的框图；
图2示出了一种用于该显示面板的一种3T1C像素电路的示意图；
图3示出了图2中像素电路在显示过程的信号时序图；
图4示出了图2中像素电路在检测过程的一种信号时序图；
图5示出了图2中像素电路在检测过程的另一种信号时序图；
图6为一种显示面板包括的多层结构层叠设置的版图；
图7为本发明至少一实施例提供的一种显示面板包括的第一金属层的平面结构示意图；
图8为本发明至少一实施例提供的一种显示面板包括的第一金属层和有源层叠层的平面结构示意图；
图9为本发明至少一实施例提供的一种显示面板包括的第一金属层、有源层和第二金属层叠层的平面结构示意图；
图10为在图9所示的层叠结构中形成过孔结构的平面结构示意图；
图11为本发明至少一实施例提供的一种显示面板包括的第三金属层的平面结构示意图；
图12为本发明至少一实施例提供的一种显示面板包括的第一金属层、有源层、第二金属层和第三金属层的叠层的平面结构示意图；
图13为本发明至少一实施例提供的一种显示面板的截面结构示意图；
图14为本发明至少一实施例提供的再一种显示面板包括的第一金属层、有源层、第二金属层和第三金属层的叠层的平面结构示意图；
图15为图14中的显示面板包括的第一金属层的平面结构示意图；
图16为图14中的显示面板包括的第一金属层和有源层叠层的平面结构示意图；
图17为图14中的显示面板包括的第一金属层、有源层和第二金属层叠层的平面结构示意图；
图18为在图14所示的层叠结构中形成过孔结构的平面结构示意图；
图19为图14中的显示面板包括的第三金属层的平面结构示意图；
图20为本发明至少一实施例提供的又一种显示面板包括的第一金属层、有源层和第二金属层的叠层的平面结构示意图；
图21为图20中的显示面板包括的第一金属层和有源层叠层的平面结构示意图；
图22为图20中的显示面板包括的第二金属层的平面结构示意图；
图23为本发明至少一实施例提供的又一种显示面板包括的第一金属层、有源层、第二金属层和第三金属层的叠层的平面结构示意图；
图24为图23中的显示面板包括的第一金属层的平面结构示意图；
图25为图23中的显示面板包括的第一金属层和有源层叠层的平面结构示意图；
图26为图23中的显示面板包括的第一金属层、有源层和第二金属层叠层的平面结构示意图；
图27为在图26所示的层叠结构中形成过孔结构的平面结构示意图；
图28为图23中的显示面板包括的第三金属层的平面结构示意图；
图29为图23中显示面板的截面结构示意图；
图30为本发明至少一实施例提供的又一种显示面板包括的第一金属层、有源层和第二金属层的叠层的平面结构示意图；
图31为图30中的显示面板包括的第一金属层和有源层叠层的平面结构示意图；
图32为图30中第二金属层的平面结构示意图；
图33为图30中显示面板的截面结构示意图；
图34为本发明至少一实施例提供的又一种显示面板包括的第一金属层、有源层、第二金属层和第三金属层的叠层的平面结构示意图；
图35为图34中的显示面板包括的第一金属层和第三金属层层叠的平面结构示意图；
图36为本发明至少一实施例提供的又一种显示面板包括的第一金属层、有源层、第二金属层和第三金属层的叠层的平面结构示意图；
图37为图36所示显示面板的第二阴极电压走线沿着第二方向切割的截面结构示意图；
图38为在图37所示的结构中增加阴极和像素界定层的截面结构示意图；
图39为在图36所示显示面板上增加有机发光二极管后的截面结构示意图；
图40为本发明至少一实施例提供的又一种显示面板包括的第一金属层、有源层、第二金属层和第三金属层的叠层的平面结构示意图；
图41为图40所示显示面板的截面结构示意图；以及
图42为本发明至少一实施例提供的一种显示装置的框图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本发明使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还 是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
除非另外定义，本发明实施例中使用的“平行”、“垂直”和“相同”等特征均包括严格意义上的“平行”、“垂直”、“相同”等情况，以及“大致平行”、“大致垂直”、“大致相同”等包含一定误差的情况。例如，上述的“大致”可表示所比较的对象的差值为所比较的对象的平均值的10％，或者5％之内。在本发明实施例的下文中没有特别指出一个部件或元件的数量时，意味着该部件或元件可以是一个也可以是多个，或可理解为至少一个。“至少一个”指一个或多个，“多个”指至少两个。本发明实施例中的“同层设置”指同一材料在经过同一步骤(例如，一步图案化工艺)后形成的多个膜层之间的关系。这里的“同层”并不总是指多个膜层的厚度相同或者多个膜层在截面图中的高度相同。
图1为本发明至少一实施例提供的显示面板的框图。如图1所示，显示面板10包括呈阵列排布的多个子像素100，例如，每个子像素100包括发光元件以及驱动该发光元件发光的像素电路。例如，该显示面板是有机发光二极管(OLED)显示面板，该发光元件为有机发光二极管。该显示面板还可以包括多条扫描线、多条数据线以用于为多个子像素提供扫描信号(控制信号)和数据信号，从而驱动该多个子像素以进行显示。根据需要，该显示面板还可以进一步包括电源线、检测线等。
例如，该像素电路包括用于驱动发光元件发光的驱动子电路和用于检测该子像素电特性以实现外部补偿的检测子电路。本发明的实施例对于该像素电路的具体结构不作限制。
例如，图2示出了一种用于该显示面板的一种3T1C像素电路的示意图。根据应用场景的不同，该像素电路还可以进一步包括补偿电路和复位电路等，本发明的实施例对此不作限定。
结合上述图1和图2，该像素电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容Cst。第一晶体管T1的第一极与存储电容Cst的第一电容电极和第三晶体管T3的栅极电连接，第一晶体管T1的第二极配置为接收数据信号GT，第一晶体管T1配置为响应于第一控制信号G1将该数据信号DT写入第三晶体管T3的栅极和存储电容Cst；第三晶体管T3的第一极与存储电容Cst的第二电容电极电连接，并配置为与发光元件的第一电极电连接，第三晶体管T3的第二极配置为接收第一电源电压V1(例如为高电源 电压VDD)，第三晶体管T3配置为在第三晶体管T3的栅极的电压的控制下控制用于驱动发光元件的电流；第二晶体管T2的第一极与第三晶体管T3的第一极以及存储电容Cst的第二电容电极电连接，第二晶体管T2的第二极配置为与检测线230连接以连到外部检测电路21，第二晶体管T2配置为响应于第二控制信号G2检测所属的子像素的电特性以实现外部补偿；该电特性例如包括第三晶体管T3的阈值电压和/或载流子迁移率，或者发光元件的阈值电压、驱动电流等。该外部检测电路21例如为包括数模转换器(DAC)和模数转换器(ADC)等的常规电路，本发明的实施例对此不作赘述。
本发明的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本发明的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本发明的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。需要说明的是，在下面的描述中均以图2中的晶体管为N型晶体管为例进行说明，然而不作为对本发明的限制。
下面结合图3～图5所示的信号时序图对图2所示的像素电路的工作原理进行说明，其中图3示出了图2中像素电路在显示过程的信号时序图，图4示出了图2中像素电路在检测过程的信号时序图，图5示出了图2中像素电路在检测过程的另一种信号时序图。
例如，如图3所示，每一帧图像的显示过程包括数据写入和复位阶段1以及发光阶段2。图3示出了每个阶段中各个信号的时序波形。该3T1C像素电路的一种工作过程包括：在数据写入和复位阶段1，第一控制信号G1和第二控制信号G2均为开启信号，第一晶体管T1和第二晶体管T2导通，数据信号DT经第一晶体管T1传输至第三晶体管T3的栅极，第一开关K1关闭，模数转换器通过检测线130及第二晶体管T2向 发光元件的第一电极(例如OLED的阳极)写入复位信号，第三晶体管T3导通并产生驱动电流将发光元件的第一电极充电至工作电压；在发光阶段2，第一控制信号G1和第二控制信号G2均为关闭信号，由于存储电容Cst的自举效应，存储电容Cst两端的电压保持不变，第三晶体管T3工作在饱和状态且电流不变，并驱动发光元件发光。
例如，图4示出了该像素电路在进行阈值电压的检测时的信号时序图。该3T1C像素电路的一种工作过程包括：第一控制信号G1和第二控制信号G2均为开启信号，第一晶体管T1和第二晶体管T2导通，数据信号DT经第一晶体管T1传输至第三晶体管T3的栅极；第一开关K1关闭，模数转换器通过检测线230及第二晶体管T2向发光元件的第一电极(节点N3)写入复位信号，第三晶体管T3导通并对节点N3进行充电直至第三晶体管T3截止，数模转换器对检测线230上的电压取样即可得到第三晶体管T3的阈值电压。该过程例如可以在显示装置关机时进行。
例如，图5示出了该像素电路在进行载流子迁移率的检测时的信号时序图。该3T1C像素电路的一种工作过程包括：在第一阶段，第一控制信号G1和第二控制信号G2均为开启信号，第一晶体管T1和第二晶体管T2导通，数据信号DT经第一晶体管T1传输至第三晶体管T3的栅极；第一开关K1关闭，模数转换器通过检测线230及第二晶体管T2向发光元件的第一电极(节点N3)写入复位信号；在第二阶段，第一控制信号G1为关闭信号，第二控制信号G1为开启信号，第一晶体管T1关断，第二晶体管T2导通，并将第一开关K1、第二开关K2断开以将检测线130浮置；由于存储电容Cst的自举效应，存储电容Cst两端的电压保持不变，第三晶体管T3工作在饱和状态且电流不变并驱动发光元件发光，然后数模转换器对检测线130上的电压取样，并结合发光电流的大小和持续时间可以计算出第三晶体管T3中的载流子迁移率。例如，该过程可以在显示阶段之间的消隐阶段进行。
通过上述检测可以得到第三晶体管T3的电特性并实现相应的补偿算法。
例如，如图1所示，显示面板10还可以包括数据驱动电路23和扫描驱动电路24。数据驱动电路23配置为根据需要(例如输入显示装置的图像信号)可发出数据信号，例如上述数据信号DT；每个子像素的像素电路还配置为接收该数据信号并将该数据信号施加至该第一晶体管的栅极。扫描驱动电路24配置为输出各种扫描信号，例如包括上述第一控制信号G1和第二控制 信号G2，其例如为集成电路芯片(IC)或者为直接制备在显示基板上的栅驱动电路(GOA)。
例如，结合图1，显示面板10还包括控制电路22。例如，控制电路22配置为控制数据驱动电路23施加数据信号，以及控制栅极驱动电路施加扫描信号。该控制电路22的一个示例为时序控制电路(T-con)。控制电路22可以为各种形式，例如包括处理器121和存储器127，存储器121包括可执行代码，处理器121运行该可执行代码以执行上述检测方法。
例如，处理器121可以是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理装置，例如可以包括微处理器、可编程逻辑控制器(PLC)等。
例如，存储器127可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器121可以运行该程序指令期望的功能。在计算机可读存储介质中还可以存储各种应用程序和各种数据，例如在上述检测方法中获取的电特性参数等。
例如，图6为一种显示面板包括的多层结构层叠设置的版图，如图6所示，感应晶体管T2的第一源漏电极T2a和驱动晶体管T3的第一源漏电极T3a通过N3节点对应的连接电极电连接，该N3节点对应的连接电极和感应栅线201在第二方向Y上相邻设置，开关晶体管T1的第一源漏电极T1a和驱动晶体管T3的第二源漏电极T3b通过N1节点对应的连接电极电连接。本发明的发明人注意到，由于感应栅线201与N3节点对应的连接电极在第二方向Y上的距离相距较近，当感应栅线201产生电压跳变时，会在N3节点处引起电压跳变，从而在N3节点处会产生很大的瞬时电流来冲击有机发光二极管，以对有机发光二极管造成损伤并降低有机发光二极管的寿命，N3节点处电压跳变也会引起N1节点处电压变化。由于N3节点处电压变化比N1节点处电压变化的幅度更大，相对于N1节点处电压变化对有机发光二极管器件带来的损伤，N3节点处电压变化对有机发光二极管器件的损伤更大，因此，可以考虑在N3节点对 应的连接电极和感应栅线之间设置间隔部，以减小感应栅线产生电压跳变时对N3节点处带来的电压变化。
本发明至少一实施例提供一种显示面板，该显示面板包括：衬底基板；设置在衬底基板上的像素电路，像素电路包括感应晶体管、驱动晶体管、第一栅线和第二栅线，其中，感应晶体管的第一源漏电极和驱动晶体管的第一源漏电极通过第一连接电极电连接；第一栅线和第二栅线在第一方向上延伸，在与第一方向交叉的第二方向上，在第一连接电极和第一栅线之间，第一连接电极和第二栅线之间均设置有间隔部，且第一连接电极、第一栅线、第二栅线和间隔部设置在同一层，本发明的实施例通过在第一连接电极和第一栅线之间，以及在第一连接电极和第二栅线之间设置间隔部，且使得第一连接电极、第一栅线、第二栅线和间隔部设置在同一层，可以减小第一栅线或者第二栅线产生电压跳变时对第一连接电极带来的电压变化，从而可以降低对发光二极管造成的损伤，保证发光二极管的使用寿命。
例如，图7为本发明至少一实施例提供的一种显示面板包括的第一金属层的平面结构示意图，图8为本发明至少一实施例提供的一种显示面板包括的第一金属层和有源层叠层的平面结构示意图，图9为本发明至少一实施例提供的一种显示面板包括的第一金属层、有源层和第二金属层叠层的平面结构示意图，图10为在图9所示的层叠结构中形成过孔结构的平面结构示意图，图11为本发明至少一实施例提供的一种显示面板包括的第三金属层的平面结构示意图，图12为本发明至少一实施例提供的一种显示面板包括的第一金属层、有源层、第二金属层和第三金属层的叠层的平面结构示意图。
例如，结合图2和图12所示，该显示面板30包括衬底基板31，设置在衬底基板31上的像素电路32，该像素电路32包括感应晶体管T2、驱动晶体管T3、第一栅线321和第二栅线323，感应晶体管T2的第一源漏电极T2a和驱动晶体管T3的第一源漏电极T3a通过第一连接电极M电连接；第一栅线321和第二栅线323在第一方向X上延伸，在与第一方向X交叉的第二方向Y上，在第一连接电极M和第一栅线321之间、第一连接电极M和第二栅线323之间均设置有间隔部322，且该第一连接电极M、第一栅线321、第二栅线323和间隔部322设置在同一层，该间隔部322设置在第一连接电极M和第一栅线321之间，以及设置在第一连接电极M和第二栅线323之间，且使得第一连接电极M、第一栅线321、第二栅线323和间隔部322设置在同一 层，可以减小第一栅线321或者第二栅线323产生电压跳变时对第一连接电极M带来的电压变化，进而可以降低第一连接电极M发生的电压变化对发光二极管造成的损伤，以保证发光二极管的使用寿命。
例如，在一个示例中，该第一栅线321为感应栅线，第二栅线323为开关栅线，但本发明的实施例不限于此，该第一栅线321和第二栅线323还可以是其他的栅线。
例如，本发明的实施例以第一方向X为行方向，第二方向Y为列方向为例进行说明。在其他的实施例中，也可以是第一方向X为列方向，而第二方向Y为行方向，本发明的实施例对此不作限定。
例如，结合图2和图12所示，该显示面板30还包括设置在衬底基板31上的开关晶体管T1和存储电容Cst，该开关晶体管T1的第一源漏电极T1a和驱动晶体管T3的栅极T3g通过第二连接电极K连接，存储电容Cst的第一极板Ca也和第二连接电极K连接，存储电容Cst的第二极板Cb和第一连接电极M连接。
需要说明的是，在图12所示的实施例中，第一连接电极M和第二连接电极K均为设置在第三金属层上的长条形。在后续的实施例中，第一连接电极M和第二连接电极K设置的位置不同，但是也均为长条形。
例如，结合图7～图12，该显示面板30包括依次层叠设置在衬底基板31上的第一金属层301、有源层302、第二金属层303和第三金属层304。尽管在图7～图12所示的平面图中没有直接示出绝缘层，只是用过孔结构代表了绝缘层，但是在上述相邻层之间还设置有起到绝缘作用的层结构，该起到绝缘作用的层结构中设置有过孔结构，需要连接的层结构通过过孔结构进行连接。
例如，在图7和图12中是以在第一方向X上排列的两个子像素对应的像素电路为例进行说明的。如图7和图12所示，该第一金属层301包括在第二方向Y上延伸的初始化信号线3011、电源电压信号线3012、第一极板Ca和数据线3013。在一个像素电路中，该初始化信号线3011、电源电压信号线3012和数据线3013在第二方向Y上的长度相等或者大致相等，第一极板Ca在第二方向Y上的长度小于初始化信号线3011、电源电压信号线3012和数据线3013在第二方向Y上的长度。该初始化信号线3011和数据线3013在第一方向X上的宽度相等或者大致相等， 且均小于电源电压信号线3012在第一方向X上的宽度，该电源电压信号线3012在第一方向X上的宽度小于第一极板Ca在第一方向X上的宽度。该第一极板Ca和与之相邻的电源电压信号线3012在第一方向X上的最小距离小于初始化信号线3011和电源电压信号线3012在第一方向X上的最小距离，且小于该第一极板Ca和与之相邻的数据线3013在第一方向X上的最小距离。
需要说明的是，尽管在图7和图12中只示出了电源电压信号线3012包括在第二方向Y上延伸的部分，在其他的实施例中该电源电压信号线3012也可以包括在第一方向X上延伸的部分。
例如，如图8所示，第一金属层301和有源层302叠层，有源层302包括感应晶体管T2的沟道区T2c、驱动晶体管T3的沟道区T3c和开关晶体管T1的沟道区T1c。例如，结合图8和图12，该感应晶体管T2的沟道区T2c在衬底基板31上的正投影和初始化信号线3011在衬底基板31上的正投影、电源电压信号线3012在衬底基板31上的正投影均相互交叠。驱动晶体管T3的沟道区T3c在衬底基板31上的正投影和电源电压信号线3012在衬底基板31上的正投影、第一极板Ca在衬底基板31上的正投影均相互交叠。开关晶体管T1的沟道区T1c在衬底基板31上的正投影和第一极板Ca在衬底基板31上的正投影、数据线3013在衬底基板31上的正投影均相互交叠。
例如，如图9所示，第一金属层301、有源层302和第二金属层303依次叠层，该第二金属层303包括感应晶体管T2的栅极T2g、驱动晶体管T3的栅极T3g、开关晶体管T1的栅极T1g和第二极板Cb。该感应晶体管T2的栅极T2g和开关晶体管T1的栅极T1g均呈在平行于第二方向Y的方向上延伸的长条形，且感应晶体管T2的栅极T2g从感应晶体管T2的沟道区T2c沿着与第二方向Y相反的方向延伸，开关晶体管T1的栅极T1g从开关晶体管T1的沟道区T1c沿着第二方向Y延伸。驱动晶体管T3的栅极T3g和第二极板Cb形成为一体结构。结合图9和图12，第二极板Cb在衬底基板31上的正投影小于第一极板Ca在衬底基板31上的正投影。
例如，在图10中示出了过孔结构包括第一过孔结构3071、第二过孔结构3072和第三过孔结构3073，该第一过孔结构3071、第二过孔结构3072和第三过孔结构3073对应的连接关系在下述中进行描述。例如，在图10中对应于一个子像素的位置处示出了六个第一过孔结构3071(3071a、3071b、3071c、 3071d、3071e和3071f)，六个第二过孔结构3072(3072a、3072b、3072c、3072d、3072e和3072f)和三个第三过孔结构3073(3073a、3073b和3073c)。
例如，结合图10和图12，该六个第一过孔结构3071分别对应于感应晶体管T2的沟道区T2c的两端的位置、驱动晶体管T3的沟道区T3c的两端的位置和开关晶体管T1的沟道区T1c的两端的位置，具体地，第一过孔结构3071a和第一过孔结构3071b分别对应于感应晶体管T2的沟道区T2c的两端的位置；第一过孔结构3071c和第一过孔结构3071d分别对应于驱动晶体管T3的沟道区T3c的两端的位置；第一过孔结构3071e和第一过孔结构3071f分别对应于开关晶体管T1的沟道区T1c的两端的位置。该第二过孔结构3072a和第二过孔结构3072b在衬底基板31上的正投影位于初始化信号线3011在衬底基板31上的正投影内，且在第二方向Y上位于感应晶体管T2的沟道区T2c在衬底基板31上的正投影的两侧；该第二过孔结构3072c和第二过孔结构3072d在衬底基板31上的正投影位于电源电压信号线3012在衬底基板31上的正投影之内，且在第二方向Y上位于感应晶体管T2的沟道区T2c的两侧；该第二过孔结构3072e在衬底基板31上的正投影位于第一极板Ca在衬底基板31上的正投影之内，且不位于第二极板Cb在衬底基板31上的正投影之内；该第二过孔结构3072f在衬底基板31上的正投影位于数据线3013在衬底基板31上的正投影之内。该第三过孔结构3073a在衬底基板31上的正投影位于感应晶体管T2的栅极T2g在衬底基板31上的正投影之内；该第三过孔结构3073b在衬底基板31上的正投影位于第一极板Ca在衬底基板31上的正投影之内，且位于第二极板Cb在衬底基板31上的正投影之内；该第三过孔结构3073c在衬底基板31上的正投影位于开关晶体管T1的栅极T1g在衬底基板31上的正投影之内。
例如，结合图11所示，第三金属层304包括第一连接电极M、间隔部322、在第一方向X上延伸的第二栅线323和第一栅线321，以及在第二方向Y上延伸的第一连接结构3041、第二连接结构3042和第三连接结构3043。该第二栅线323和第一栅线321均呈长条形，且在第一方向X上延伸。该第一连接电极M也呈长条形且在第一方向X上延伸。该第一连接结构3041、第二连接结构3042和第三连接结构3043用于实现第三金属层304和其他的层结构之间的连接。在第二方向Y上，该间隔部 322b位于第一连接电极M和第一栅线321之间，从而可以减小第一栅线321产生电压跳变时对第一连接电极M带来的电压变化，该间隔部322a位于第一连接电极M和第二栅线323之间，从而可以减小第二栅线323产生电压跳变时对第一连接电极M带来的电压变化，进而可以降低第一连接电极M发生的电压变化对发光二极管造成的损伤，以保证发光二极管的使用寿命。
例如，结合图7～图12，在该显示面板30中，感应晶体管T2的沟道区T2c通过第一过孔结构3071a和第一连接结构3041电连接，通过第一过孔结构3071b和第一连接电极M电连接；驱动晶体管T3的沟道区T3c通过第一过孔结构3071c和间隔部322a电连接，通过第一过孔结构3071d和主体部326电连接；开关晶体管T1的沟道区T1c通过第一过孔结构3071e和第二连接结构3042电连接，并通过第一过孔结构3071f和第三连接结构3043电连接。
例如，结合图7～图12，在该显示面板30中，第一连接结构3041通过第二过孔结构3072a和第二过孔结构3072b和位于第一金属层301的初始化信号线3011电连接。间隔部322a通过第二过孔结构3072c和电源电压信号线3012电连接，间隔部322b通过第二过孔结构3072d和电源电压信号线3012电连接。第一连接电极M通过第二过孔结构3072e和第一极板Ca电连接。第三连接结构3043通过第二过孔结构3072f和数据线3013电连接。
例如，结合图7～图12，在该显示面板30中，感应晶体管T2的栅极T2g在第二方向Y上延伸至和第一栅线321电连接，且该感应晶体管T2的栅极T2g和第一栅线321通过第三过孔结构3073a实现电连接。该开关晶体管T1的栅极T1g在与第二方向Y相反的方向上延伸至和第二栅线323电连接，且和感应晶体管T2的栅极T2g连接的第一栅线321与和开关晶体管T1的栅极T1g连接的第二栅线323在第二方向Y上位于间隔部322的不同侧。该开关晶体管T1的栅极T1g和第二栅线323通过第三过孔结构3073c实现电连接。驱动晶体管T3的栅极T3g和第二极板Cb为一体结构，且第二极板Cb通过第三过孔结构3073b和第二连接结构3042电连接。
需要说明的是，在图12所示的结构中，第二连接结构3042复用作第二连接电极K。
例如，结合图7～图12，该第一连接结构3041在衬底基板31上的正投影位于初始化信号线3011在衬底基板31上的正投影之内，第二连接结构3042 在衬底基板31上的正投影位于第一极板Ca在衬底基板31上的正投影之内，第三连接结构3043在衬底基板31上的正投影位于数据线3013在衬底基板31上的正投影之内。间隔部322a和间隔部322b在衬底基板31上的正投影位于电源电压信号线3012在衬底基板31上的正投影之内。
例如，在图12中，感应晶体管T2和在第二方向Y上位于其两侧的第一栅线321和第二栅线323之间分别具有位于第三金属层304的间隔部322a和间隔部322b，该间隔部322b可以屏蔽感应晶体管T2的第一源漏电极T2a和与与之连接的第一栅线321之间的耦合。感应晶体管T2的第一源漏电极T2a位于第三金属层304，电源电压信号线3012位于第一金属层301，在第一栅线321和感应晶体管T2之间的位于第三金属层304的间隔部322b通过第二过孔结构3072d和位于第一金属层301的电源电压信号线3012电连接；在第二栅线323和感应晶体管T2之间的位于第三金属层304的间隔部322a通过第二过孔结构3072c和位于第一金属层301的电源电压信号线3012电连接。开关晶体管T1可以减少第二连接电极K和栅线(第一栅线321或者第二栅线323)的耦合。存储电容Cst为双层电容，该双层电容分别在第三金属层304和第二金属层303之间，以及在第一金属层301和第二金属层303之间。
需要说明的第，第一连接电极M的电压变化，会引起第二连接电极K的电压变化。在写数据阶段，希望第一连接电极M的电压更稳定，但是在点亮阶段，第一连接电极M的电压上升是正常的。在点亮阶段，第二连接电极K的电压的上升是由于第一连接电极M的电压上升耦合引起的，这时驱动晶体管T3的栅极和电源电压信号线3012之间当于一个电容，存储电容Cst也是一个电容，在耦合过程中，会有一个电容分压，所以第二连接电极K的电压上升没有第一连接电极M的电压上升高。在写数据阶段希望第一连接电极M的电压更稳定，所以对于第一连接电极M通过间隔部322进行保护屏蔽，以减小跳变电压。上述设计可以使得，第一连接电极M和第一栅线321之间设置了间隔部322，且第一连接电极M形成在第三金属层304，与第一栅线321设置在同一层，通过间隔部322的屏蔽作用，可以延长有机发光二极管显示器件的寿命。感应晶体管T2及其连接的第一连接电极M在第二方向Y的两侧均有间隔部322，分别屏蔽了第一栅线321和第二栅线323对第一连接电极M的电 压变化的影响，即由于间隔部322的存在使得无法形成第一栅线321或者第二栅线323和第一连接电极M之间的寄生电容。
例如，图13为本发明至少一实施例提供的一种显示面板的截面结构示意图，如图13所示，该显示面板30还包括设置在第一金属层301的远离衬底基板31的一侧的缓冲层305，该缓冲层305在衬底基板31上整层形成，在该第一金属层301上示出了电源电压信号线3012。在有源层302和第二金属层303之间设置有栅绝缘层306，在第二金属层303和第三金属层304之间设置有层间绝缘层307。在第三金属层304的远离衬底基板31的一侧依次设置有钝化层308和平坦化层309。层间绝缘层307、钝化层308和平坦化层309也均整层形成。
例如，结合图12和图13，在层间绝缘层307中设置有第一过孔结构3071，第三金属层304通过第一过孔结构3071和有源层302电连接，在层间绝缘层307和缓冲层305中贯穿有第二过孔结构3072，第三金属层304通过第二过孔结构3072和第一金属层301电连接。尽管在图13中未示出，但是，结合图12，在层间绝缘层307中设置有第三过孔结构3073，第三金属层304通过第三过孔结构3073和第二金属层303电连接。
例如，在图13的左侧示出了双层电容结构，即第三金属层304和第二金属层303之间形成第一电容结构，第二金属层303和第一金属层301之间形成第二电容结构，第三金属层304、第二金属层303和第一金属层301在衬底基板31上的正投影均存在交叠部分。
例如，结合图12，在该显示面板30中，第一连接结构3041通过第一过孔结构3071a和感应晶体管T2的第二源漏电极T2b电连接。第二连接结构3042通过第一过孔结构3071e和开关晶体管T1的第一源漏电极T1a电连接，且通过第三过孔结构3073b和第二极板Cb电连接；第三连接结构3043通过第二过孔结构3072f和数据线3013电连接，且通过第一过孔结构3071f和开关晶体管T1的第二源漏电极T1b电连接。
例如，结合图12，该第三金属层304的至少一部分和第一金属层301、第二金属层303均存在交叠区域，以在第一金属层301和第二金属层303之间形成存储电容Cst，在第二金属层303和第三金属层304之间形成电容结构，从而可以形成双电容结构。
例如，结合图12，该感应晶体管T2的第一源漏电极T2a在衬底基板31 上的正投影和电源电压信号线3012在衬底基板31上的正投影相交叠。
例如，图14为本发明至少一实施例提供的再一种显示面板包括的第一金属层、有源层、第二金属层和第三金属层的叠层的平面结构示意图，图15为图14中的显示面板包括的第一金属层的平面结构示意图，图16为图14中的显示面板包括的第一金属层和有源层叠层的平面结构示意图，图17为图14中的显示面板包括的第一金属层、有源层和第二金属层叠层的平面结构示意图，图18为在图14所示的层叠结构中形成过孔结构的平面结构示意图，图19为图14中的显示面板包括的第三金属层的平面结构示意图。
例如，结合图2和图14所示，该显示面板30包括衬底基板31，设置在衬底基板31上的像素电路32，该像素电路32包括感应晶体管T2、驱动晶体管T3、开关晶体管T1、第一栅线321、第二栅线323和存储电容Cst，感应晶体管T2的第一源漏电极T2a和驱动晶体管T3的第一源漏电极T3a通过第一连接电极M电连接；第一栅线321和第二栅线323在第一方向X上延伸，在与第一方向X交叉的第二方向Y上，在第一连接电极M和第一栅线321之间、在第一连接电极M和第二栅线323之间均设置有间隔部322，且该第一连接电极M、第一栅线321、第二栅线323和间隔部322设置在同一层，该间隔部322设置在第一连接电极M和第一栅线321，以及设置在第一连接电极M和第二栅线323之间，且使得第一连接电极M、第一栅线321、第二栅线323和间隔部322设置在同一层，可以减小第一栅线321或者第二栅线323产生电压跳变时对第一连接电极M带来的电压变化，进而可以降低第一连接电极M发生的电压变化对发光二极管造成的损伤，以保证发光二极管的使用寿命。该开关晶体管T1的第一源漏电极T1a和驱动晶体管T3的栅极T3g通过第二连接电极K连接，存储电容Cst的第一极板Ca和第二连接电极K连接，存储电容Cst的第二极板Cb和第一连接电极M连接，以形成一个像素电路的整体。
例如，在图14中，感应晶体管T2和在第二方向Y上位于其两侧的第一栅线321和第二栅线323之间分别具有位于第三金属层304的间隔部322a和间隔部322b，该间隔部322b可以屏蔽感应晶体管T2的第一源漏电极T2a与第一栅线321之间的耦合。感应晶体管T2的第一源漏电 极T2a位于第三金属层304，电源电压信号线3012位于第一金属层301，在第一栅线321和感应晶体管T2之间的位于第三金属层304的间隔部322b通过第二过孔结构3072d和位于第一金属层301的电源电压信号线3012电连接；在第二栅线323和感应晶体管T2之间的位于第三金属层304的间隔部322a通过第二过孔结构3072c和位于第一金属层301的电源电压信号线3012电连接。开关晶体管T1可以减少第二连接电极K和栅线(第一栅线321或者第二栅线323)的耦合。存储电容Cst为双层电容，该双层电容分别在第三金属层304和第二金属层303之间，以及在第一金属层301和第二金属层303之间。
例如，在图14所示的显示面板中，在感应晶体管T2的第一源漏电极T2a的下方去除了第一金属层301的一部分，这样可以减少寄生电容，即电源电压信号线3012在对应于感应晶体管T2的第一源漏电极T2a和第一连接电极M的位置处变窄，这样可以减少电源电压信号线3012与感应晶体管T2的第一源漏电极T2a的交叠面积和寄生电容。
例如，在图14所示的显示面板中，开关晶体管T1为并联的两个薄膜晶体管，其中一个设置在靠近上侧的第二栅线323的位置处，另外一个设置在靠近下侧的第一栅线321的位置处，即在第二方向设置在第一连接电极M的两侧，同时存储电容Cst的第一极板Ca的一部分在第二方向Y上的长度减小了，上述设计可以实现增大开关晶体管T1的沟道宽长比和驱动电流，从而有利于高分辨率显示面板的驱动，使得充电的时间减少，此外，还可以增大一部分存储电容对应的第三金属层的部分与在第二方向Y上位于其两侧的第一栅线321或者第二栅线323之间的间距，以减小和第一连接电极M连接的存储电容Cst的第一极板Ca与第一栅线321或者第二栅线323的耦合，并减少第一连接电极M与栅线耦合寄生电容的长度。
例如，在图14所示的显示面板中，感应晶体管T2的第一源漏电极T2a下方的第一金属层301的一部分被去除了，这样可以防止第一连接电极M和感应晶体管T2的底栅耦合产生漏电流。
例如，在图14所示的显示面板中，开关晶体管T1的除了第一源漏电极T1a之外的其他结构均无第三金属层覆盖，这样可以减小开关晶体管T1和第一连接电极M的耦合作用。
例如，结合图14～图19，在该显示面板30中，该显示面板30包括依次 层叠设置在衬底基板31上的第一金属层301、有源层302、第二金属层303和第三金属层304。尽管在图14～图19所示的平面图中没有直接示出绝缘层，只是用过孔结构代表了绝缘层，但是在上述相邻层之间还设置有起到绝缘作用的层结构，该起到绝缘作用的层结构中设置有过孔结构，需要连接的层结构通过过孔结构进行连接。
例如，在图14和图15中是以在第一方向X上排列的两个子像素对应的像素电路为例进行说明的。如图14和图15所示，该第一金属层301包括在第二方向Y上延伸的初始化信号线3011、电源电压信号线3012、第一极板Ca和数据线3013。该初始化信号线3011和数据线3013均为在第二方向Y上延伸的直线状。电源电压信号线3012包括在第二方向Y上延伸的第一电源电压信号线3012a，第一电源电压信号线3012a包括在第二方向Y上延伸且依次连接的第一部分3012b、第二部分3012c和第三部分3012d，第一部分3012b和第三部分3012d在第一方向X上的宽度相等，第二部分3012c在第一方向X上的宽度小于第一部分3012b在第一方向X上的宽度，且第二部分3012c在第二方向Y上的一端和第一部分3012b的靠近第三部分3012d且远离初始化信号线3011的边缘连接，第二部分3012c在第二方向Y上的另一端和第三部分3012d的靠近第一部分3012b且远离初始化信号线3011的边缘连接。第二部分3012c的最远离初始化信号线3011的边缘和第一部分3012b的最远离初始化信号线3011的边缘、第三部分3012d的最远离初始化信号线3011的边缘均对齐且在一条直线上，因此，在第二部分3012c和初始化信号线3011之间形成了一个凹口。第一极板Ca包括在第一方向X上相互连接的第一极板子块Ca1和第二极板子块Ca2，第二极板子块Ca2相对于第一极板子块Ca1更靠近数据线3013，且第二极板子块Ca2在第二方向Y上的长度小于第一极板子块Ca1在第二方向Y上的长度，且在图15中，第二极板子块Ca2的上边缘低于第一极板子块Ca1的上边缘，第二极板子块Ca2的下边缘高于第一极板子块Ca1的下边缘。
例如，如图14和图16所示，第一金属层301和有源层302叠层，有源层302包括感应晶体管T2的沟道区T2c、驱动晶体管T3的沟道区T3c和两个开关晶体管T1的沟道区T1c。例如，结合图14和图16，该感应晶体管T2的沟道区T2c在衬底基板31上的正投影和初始化信号线 3011在衬底基板31上的正投影相互交叠。驱动晶体管T3的沟道区T3c在衬底基板31上的正投影和电源电压信号线3012在衬底基板31上的正投影、第一极板Ca在衬底基板31上的正投影均相互交叠。两个开关晶体管T1的沟道区T1c在衬底基板31上的正投影均和数据线3013在衬底基板31上的正投影相互交叠。
例如，如图17所示，第一金属层301、有源层302和第二金属层303依次叠层，该第二金属层303包括感应晶体管T2的栅极T2g、驱动晶体管T3的栅极T3g、开关晶体管T1的栅极T1g和第二极板Cb，两个开关晶体管T1的栅极为一体结构。该感应晶体管T2的栅极T2g和开关晶体管T1的栅极T1g均呈在平行于第二方向Y的方向上延伸的长条形，且感应晶体管T2的栅极T2g从感应晶体管T2的沟道区T2c沿着与第二方向Y相反的方向延伸，开关晶体管T1的栅极T1g从位于下方的开关晶体管T1的沟道区T1c沿着第二方向Y延伸。驱动晶体管T3的栅极T3g和第二极板Cb形成为一体结构。结合图17和图14，第二金属层303包括在第二方向Y上从第二极板Cb的对应于第二极板子块Ca2的部分延伸的第一延伸部3031和第二延伸部3032，两个第二连接结构3042分别和第一延伸部3031、第二延伸部3032连接。该第一延伸部3031和第二延伸部3032在衬底基板31上的正投影与第一极板Ca在衬底基板31上的正投影没有交叠部分。
例如，在一个示例中，该第一延伸部3031和第二延伸部3032均为长条形，当然本发明的实施例不限于此，第一延伸部3031和第二延伸部3032还可以是块状等其他形状。
例如，在图18中示出了第一过孔结构3071、第二过孔结构3072和第三过孔结构3073，该第一过孔结构3071、第二过孔结构3072和第三过孔结构3073对应的连接关系在下述中进行描述。例如，在图18中对应于一个子像素的位置处示出了八个第一过孔结构3071(3071a、3071b、3071c、3071d、3071e1、3071e2、3071f1和3071f2)，六个第二过孔结构3072(3072a、3072b、3072c、3072d、3072e和3072f)和四个第三过孔结构3073(3073a、3073b、3073c和3073d)。
例如，结合图18和图14，该八个第一过孔结构3071分别对应于感应晶体管T2的沟道区T2c的两端的位置、驱动晶体管T3的沟道区T3c的两端的位置和两个开关晶体管T1的沟道区T1c的两端的位置，具体地，第一过孔结 构3071a和第一过孔结构3071b分别对应于感应晶体管T2的沟道区T2c的两端的位置；第一过孔结构3071c和第一过孔结构3071d分别对应于驱动晶体管T3的沟道区T3c的两端的位置；第一过孔结构3071e1和第一过孔结构3071f1分别对应于其中一个开关晶体管T1的沟道区T1c的两端的位置；第一过孔结构3071e2和第一过孔结构3071f2分别对应于另一个开关晶体管T1的沟道区T1c的两端的位置。该第二过孔结构3072a和第二过孔结构3072b在衬底基板31上的正投影位于初始化信号线3011在衬底基板31上的正投影内，且在第二方向Y上位于感应晶体管T2的沟道区T2c在衬底基板31上的正投影的两侧；该第二过孔结构3072c和第二过孔结构3072d在衬底基板31上的正投影位于电源电压信号线3012在衬底基板31上的正投影之内，且在第二方向Y上位于感应晶体管T2的沟道区T2c的两侧，即分别对应于第一电源电压信号线3012a包括的第一部分3012b和第三部分3012d；该第二过孔结构3072e在衬底基板31上的正投影位于第一极板Ca在衬底基板31上的正投影之内，且不位于第二极板Cb在衬底基板31上的正投影之内；该第二过孔结构3072f在衬底基板31上的正投影位于数据线3013在衬底基板31上的正投影之内。该第三过孔结构3073a在衬底基板31上的正投影位于感应晶体管T2的栅极T2g在衬底基板31上的正投影之内；该第三过孔结构3073b1和第三过孔结构3073b2在衬底基板31上的正投影分别位于第一延伸部3031和第二延伸部3032在衬底基板31上的正投影之内；该第三过孔结构3073c在衬底基板31上的正投影位于开关晶体管T1的栅极T1g在衬底基板31上的正投影之内。
例如，结合图19所示，第三金属层304包括第一连接电极M、间隔部322、在第一方向X上延伸的第二栅线323和第一栅线321，在第二方向Y上延伸的第一连接结构3041和第三连接结构3043，以及在第一方向X上延伸的两个第二连接结构3042。该第二栅线323和第一栅线321均呈长条形，且在第一方向X上延伸。该第一连接电极M也呈长条形且在第一方向X上延伸。该第一连接结构3041、第二连接结构3042和第三连接结构3043用于实现第三金属层304和其他的层结构之间的连接。在第二方向Y上，该间隔部322b位于第一连接电极M和第一栅线321之间，从而可以减小第一栅线321产生电压跳变时对第一连接电极M带 来的电压变化，该间隔部322a位于第一连接电极M和第二栅线323之间，从而可以减小第二栅线323产生电压跳变时对第一连接电极M带来的电压变化，进而可以降低第一连接电极M发生的电压变化对发光二极管造成的损伤，以保证发光二极管的使用寿命。
需要说明的是，在图14所示的实施例中，第二连接电极K复用作第二连接结构3042。
例如，结合图14～图19，在该显示面板30中，感应晶体管T2的沟道区T2c通过第一过孔结构3071a和第一连接结构3041电连接，通过第一过孔结构3071b和第一连接电极M电连接；驱动晶体管T3的沟道区T3c通过第一过孔结构3071c和间隔部322a电连接，通过第一过孔结构3071d和主体部326电连接；位于上侧的开关晶体管T1的沟道区T1c通过第一过孔结构3071e1和位于上侧的第二连接结构3042电连接，并通过第一过孔结构3071f1和第三连接结构3043电连接；位于下侧的开关晶体管T1的沟道区T1c通过第一过孔结构3071e2和位于下侧的第二连接结构3042电连接，并通过第一过孔结构3071f2和第三连接结构3043电连接。
例如，结合图14～图19，在该显示面板30中，第一连接结构3041通过第二过孔结构3072a和第二过孔结构3072b和位于第一金属层301的初始化信号线3011电连接。间隔部322a通过第二过孔结构3072c和第一电源电压信号线3012a的第一部分3012b电连接，间隔部322b通过第二过孔结构3072d和第一电源电压信号线3012a的第三部分3012d电连接。第一连接电极M通过第二过孔结构3072e和第一极板Ca电连接。第三连接结构3043通过第二过孔结构3072f和数据线3013电连接。
例如，结合图14～图19，在该显示面板30中，感应晶体管T2的栅极T2g在第二方向Y上延伸至和第一栅线321电连接，且该感应晶体管T2的栅极T2g和第一栅线321通过第三过孔结构3073a实现电连接。该开关晶体管T1的栅极T1g在与第二方向Y相反的方向上延伸至和第二栅线323电连接，且和感应晶体管T2的栅极T2g连接的第一栅线321与和开关晶体管T1的栅极T1g连接的第二栅线323在第二方向Y上位于间隔部322的不同侧。该开关晶体管T1的栅极T1g和第二栅线323通过第三过孔结构3073c实现电连接。第一延伸部3031通过第三过孔结构3073b1和位于上侧的第二连接结构3042电连接，第二延伸部3032通过第三过孔结构3073b2和位于下侧的第二连接 结构3042电连接。
例如，结合图14～图19，该第一连接结构3041在衬底基板31上的正投影位于初始化信号线3011在衬底基板31上的正投影之内，第三连接结构3043在衬底基板31上的正投影位于数据线3013在衬底基板31上的正投影之内。间隔部322a和间隔部322b在衬底基板31上的正投影位于电源电压信号线3012在衬底基板31上的正投影之内。
例如，在图14中，感应晶体管T2和在第二方向Y上位于其两侧的第一栅线321和第二栅线323之间分别具有位于第三金属层304的间隔部322a和间隔部322b，该间隔部322b可以屏蔽感应晶体管T2的第一源漏电极T2a和与之连接的第一栅线321之间的耦合。感应晶体管T2的第一源漏电极T2a位于第三金属层304，电源电压信号线3012位于第一金属层301，在第一栅线321和感应晶体管T2之间的位于第三金属层304的间隔部322b通过第二过孔结构3072d和位于第一金属层301的电源电压信号线3012电连接；在第二栅线323和感应晶体管T2之间的位于第三金属层304的间隔部322a通过第二过孔结构3072c和位于第一金属层301的电源电压信号线3012电连接。开关晶体管T1可以减少第二连接电极K和栅线(第一栅线321或者第二栅线323)的耦合。存储电容Cst为双层电容，该双层电容分别在第三金属层304和第二金属层303之间，以及在第一金属层301和第二金属层303之间。
需要说明的第，第一连接电极M的电压变化，会引起第二连接电极K的电压变化。在写数据阶段，希望第一连接电极M的电压更稳定，但是在点亮阶段，第一连接电极M的电压上升是正常的。在点亮阶段，第二连接电极K的电压的上升是由于第一连接电极M的电压上升耦合引起的，这时第二连接电极K和电源电压信号线3012之间当于一个电容，存储电容Cst也是一个电容，耦合过程中，会有一个电容分压，所以第二连接电极K的电压上升没有第一连接电极M的电压上升高。在写数据阶段希望第一连接电极M的电压更稳定，所以对于第一连接电极M用间隔部322进行保护屏蔽，以减小跳变电压。上述设计可以使得，第一连接电极M和第一栅线321之间设置了间隔部322，且第一连接电极M形成在第三金属层304，与第一栅线321设置在同一层，通过间隔部322的屏蔽作用，可以延长有机发光二极管显示器件的寿命。感应晶体管T2及其 连接的第一连接电极M在第二方向Y的两侧均有间隔部322，分别屏蔽了第一栅线321和第二栅线323对第一连接电极M的电压变化的影响，即由于间隔部322的存在使得无法形成第一栅线321或者第二栅线323和第一连接电极M之间的寄生电容。
例如，结合图14，感应晶体管T2的第一源漏电极T2a在衬底基板31上的正投影和电源电压信号线3012在衬底基板31上的正投影相间隔，即感应晶体管T2的第一源漏电极T2a在第二部分3012c和初始化信号线3011之间的凹口处。
例如，结合图2，图14～图19，数据线3013被配置为向像素电路提供数据信号(数据电压)，第二栅线323被配置为向像素电路提供第一扫描信号，第一栅线321被配置为向像素电路提供第二扫描信号，初始化信号线3011被配置为向像素电路提供初始化信号，电源电压信号线3012被配置为向像素电路提供第一电源电压VDD。
例如，图14～图19的平面图所示的实施例对应的截面结构可以参见上述关于图13的相关描述，在此不再赘述。
例如，结合图14，驱动晶体管T3的驱动电流 其中，W为驱动晶体管T3的沟道的宽度(在第二方向上的宽度)，L为驱动晶体管T3的沟道的长度(在第一方向上的长度)，μn为驱动晶体管T3的载流子迁移率，VTH为驱动晶体管T3的阈值电压，CGI为栅绝缘层的电容，VGS为驱动晶体管T3的栅极T3g和第一源漏电极T3a之间的电压差，VDS为驱动晶体管T3的第一源漏电极T3a和第二源漏电极T3b之间的电压差。
例如，结合图2和图14，该显示面板30还包括有机发光二极管，该显示面板30包括一个存储电容Cst，且满足大于或者等于0.013，ΔVdr为第一连接电极M没有被屏蔽时的跳变电压，ΔVg为第一栅线321的跳变电压，Cgc为第一栅线321和存储电容Cst之间的寄生电容，Cst为存储电容的大小，Ast为存储电容Cst的面积，dgc为第一栅线321和存储电容Cst之间的最小间距(在第二方向Y上的最小间距)，Lc为第一极板子块的最靠近第 一栅线321的部分在第一方向上的长度(即第一极板Ca的最靠近第一栅线321的边的长度)，Wg为第一栅线321的宽度，dst为存储电容Cst对应的绝缘介质的厚度，即为第一极板Ca和第二极板Cb之间的层间绝缘层的厚度THKILD,ε为形成层间绝缘层的有机材料的介电系数，Agc为第一栅线和存储电极之间形成寄生电容的面积。
例如，在一个示例中，VgON为第二栅线的开启电压，VgOFF为第二栅线的关闭电压，Voled为有机发光二极管两端的电压，γ为光学常数，ΔVgray为灰阶电压的变化。
例如，在一个示例中，该存储电容为第一金属层、第二金属层和第三金属层形成的三层结构，且满足大于或者等于0.006，ΔVdr为第一连接电极M的跳变电压，ΔVg为第一栅线321的跳变电压，Cgc为第一栅线321和存储电容Cst之间的寄生电容，Cst为存储电容的大小，Ast为存储电容的面积，dgc为第一栅线321和存储电容之间的最小间距(在第二方向Y上的最小间距)，dstu为存储电容中的上层电容对应的绝缘介质的厚度，即为第一极板Ca和第二极板Cb之间的层间绝缘层的厚度THKILD，dstd为存储电容中下层电容即第一金属层和第二金属层之间的绝缘介质的厚度，即为缓冲层的厚度THKBUF，Lc为第一极板子块的和第一栅线321相邻的边的长度(即第一极板Ca的最靠近第一栅线321的边的长度)，Wg为第一栅线的宽度，dst为存储电容对应的绝缘介质的厚度，即为第一极板Ca和第二极板Cb之间的层间绝缘层的厚度THKILD，ε为形成层间绝缘层的有机材料的介电系数，Agc为第一栅线和存储电极之间形成寄生电容的面积。
例如，在一个示例中，VgON为第一栅线321的开启电压，VgOFF为第一栅线321的关闭电压，Voled为有机发光二极管两端的电压，γ为光学常数，ΔVgray为灰阶电压的变化。
例如，在一个示例中，
例如，在一个示例中，WDD为在第一栅线321和第一连接电极M之间的间隔部322b在第二方向Y上的长度，dgd为第一栅线321和间隔部322b之间的最小间距，dsd为第一连接电极M和间隔部322b之间的最小间距。
例如，在一个示例中，Lc为第一极板子块的和第一栅线321相邻的边的长度，即第一极板子块的和第一栅线321最靠近的部分在第一方向上的长度，也即第一极板Ca的最靠近第一栅线321的边的长度，Lp为第一极板子块和第二极板子块在第一方向X上的长度之和，Rl为第一极板子块的和第一栅线321相邻的边的长度与第一极板子块和第二极板子块在第一方向X上的长度之和的比值。
例如，在一个示例中，Wc为存储电容在第一方向上的宽度，dgc为第一栅线321和存储电容之间的最小间距，Pitch为一个子像素的宽度。
例如，结合图14，在一个示例中，dgc＝10.2μm，dgd＝7.9μm，dsd＝10.2μm，dc1d＝9.03μm，Ast＝5605μm2，Cst的长度＝90.3μm，Cst的宽度＝62.07μm，THKILD＝0.5μm，THKBUF＝0.3μm，THKGI＝0.15μm，Pitch＝231μm。





例如，在上述实施例所示的显示面板中，存储电容的大小Cst和存储电容的第二极板Cb与第一栅线321的寄生电容的大小Cgc的比例关系为： 其中，Cgc为存储电容的第二极板Cb与第一栅线的寄生电容的大小，Cst为存储电容的大小，Ast为存储电容的面积，dgc为第一栅线和存储电容之间的最小间距，Lc为第一极板子块的和第一栅线相邻的边的长度，Wc为存储电容的宽度，dst为存储电容对应的绝缘介质的厚度，即为第一极板和第二极板之间的层间绝缘层的厚度THKILD,ε为形成层间绝缘层的有机材料的介电系数，Agc为第一栅线和第二极板之间形成寄生电容的面积。
例如，P的大小涉及第一极板和第二极板之间的层间绝缘层的厚度，以及像素横向的参数，在计算时假定P为与像素纵向(Wc和dgc)无关的常数。由于Wc和dgc与像素大小以及开口率有关，它们的大小与像素特征值子像素的宽度正相关，和存储电容的大小Cst与存储电容的第二极板Cb和第一栅线321的寄生电容的大小Cgc的比值正相关，该比值越大，则第一连接电极M电压受第一栅线或者第二栅线产生的寄生电容的影响越小，第一连接电极M的电压越稳定。
例如，图20为本发明至少一实施例提供的又一种显示面板包括的第一金属层、有源层和第二金属层的叠层的平面结构示意图，图21为图20中的显示面板包括的第一金属层和有源层叠层的平面结构示意图，图22为图20中的显示面板包括的第二金属层的平面结构示意图。
例如，结合图2和图20所示，该显示面板30包括衬底基板31，设置在衬底基板31上的像素电路32，该像素电路32包括感应晶体管T2、驱动晶体管T3、开关晶体管T1、第一栅线321、第二栅线323和存储电容Cst，感应晶体管T2的第一源漏电极T2a和驱动晶体管T3的第一源漏电极T3a通过第一连接电极M电连接；第一栅线321和第二栅线323在第一方向X上延伸， 在与第一方向X交叉的第二方向Y上，在第一连接电极M和第一栅线321之间、在第一连接电极M和第二栅线323之间均设置有间隔部322，且该第一连接电极M、第一栅线321、第二栅线323和间隔部322设置在同一层，该间隔部322设置在第一连接电极M和第一栅线321，以及设置在第一连接电极M和第二栅线323之间，且使得第一连接电极M、第一栅线321、第二栅线323和间隔部322设置在同一层，可以减小第一栅线321或者第二栅线323产生电压跳变时对第一连接电极M带来的电压变化，进而可以降低第一连接电极M发生的电压变化对发光二极管造成的损伤，以保证发光二极管的使用寿命。
例如，如图20所示，该显示面板30还包括依次层叠设置在衬底基板31上的第一金属层301、有源层302和第二金属层303，该第一金属层301包括在第二方向Y上延伸的初始化信号线3011、至少部分在第二方向Y上延伸的电源电压信号线3012、第一极板Ca和在第二方向Y上延伸的数据线3013。该有源层302包括感应晶体管T2的沟道区T2c、驱动晶体管T3的沟道区T3c和开关晶体管T1的沟道区T1c，该开关晶体管T1的沟道区T1c、驱动晶体管T3的沟道区T3c和感应晶体管T2的沟道区T2c在第二方向Y上依次排列。该第二金属层303包括感应晶体管T2的栅极T2g、驱动晶体管T3的栅极T3g、开关晶体管T1的栅极T1g、第二极板Cb、第一连接电极M、第二连接电极K、间隔部322、在第一方向X上延伸且相互间隔的第二栅线323和第一栅线321。
例如，结合图20和图21，在第二方向Y上，第二连接电极K在第一连接电极M和位于上侧的第二栅线323之间，开关晶体管T1的栅极T1g和该位于上侧的第二栅线323电连接，感应晶体管T2的栅极T2g和位于下侧的第一栅线321电连接，且和开关晶体管T1的栅极T1g连接的位于上侧的第二栅线323与和感应晶体管T2的栅极T2g连接的位于下侧的第一栅线321在第二方向Y上位于第一极板Ca的不同侧。
例如，结合图20和图21所示，该开关晶体管T1的第一源漏电极T1a和第二连接电极K连接，该第二连接电极K复用作驱动晶体管T3的栅极T3g。存储电容Cst的第一极板Ca和第二连接电极K连接，存储电容Cst的第二极板Cb和第一连接电极M连接，以形成一个像素电路的整体。
例如，如图20所示，在感应晶体管T2的第一源漏电极T2a的下方去除 了第一金属层301的一部分，这样可以减少寄生电容，即电源电压信号线3012在对应于感应晶体管T2的第一源漏电极T2a和第一连接电极M的位置处变窄，这样可以减少电源电压信号线3012与感应晶体管T2的第一源漏电极T2a的交叠面积和寄生电容。
例如，结合图20和图21，该初始化信号线3011和数据线3013均为在第二方向Y上延伸的直线状。电源电压信号线3012包括在第二方向Y上延伸的第一电源电压信号线3012a，第一电源电压信号线3012a包括在第二方向Y上延伸且依次连接的第一部分3012b、第二部分3012c和第三部分3012d，第一部分3012b和第三部分3012d在第一方向X上的宽度相等，第二部分3012c在第一方向X上的宽度小于第一部分3012b在第一方向X上的宽度，且第二部分3012c在第二方向Y上的一端和第一部分3012b的靠近第三部分3012d且远离初始化信号线3011的边缘连接，第二部分3012c在第二方向Y上的另一端和第三部分3012d的靠近第一部分3012b且远离初始化信号线3011的边缘连接。第二部分3012c的最远离初始化信号线3011的边缘和第一部分3012b的最远离初始化信号线3011的边缘、第三部分3012d的最远离初始化信号线3011的边缘均对齐且在一条直线上，因此，在第二部分3012c和初始化信号线3011之间形成了一个凹口。该第一极板Ca的平面形状为矩形。
例如，如图21所示，第一金属层301和有源层302叠层，例如，结合图20和图21，该感应晶体管T2的沟道区T2c在衬底基板31上的正投影和初始化信号线3011在衬底基板31上的正投影相互交叠。驱动晶体管T3的沟道区T3c在衬底基板31上的正投影和电源电压信号线3012在衬底基板31上的正投影、第一极板Ca在衬底基板31上的正投影均相互交叠。开关晶体管T1的沟道区T1c在衬底基板31上的正投影和第一金属层301上的结构不存在交叠部分。
例如，结合图20和图22所示，该驱动晶体管T3的栅极T1g、感应晶体管T2的栅极T2g和开关晶体管T1的栅极T1g均呈在平行于第二方向Y的方向上延伸的长条形。感应晶体管T2的栅极T2g从感应晶体管T2的沟道区T2c沿着与第二方向Y相反的方向延伸，开关晶体管T1的栅极T1g从开关晶体管T1的沟道区T1c沿着第二方向Y延伸。驱动晶体管T3的栅极T3g和第二连接电极K形成为一体结构。第一连接电极M和第二极板Cb形成为一体结构。
例如，结合图20和图22所示，该第二金属层303还包括在第二方向Y上延伸的第一连接结构3041和第二连接结构3042，以及在第一方向X上延伸的第三连接结构3042，第二连接电极K复用作第二连接结构3042。该第二栅线323和第一栅线321均呈长条形，且在第一方向X上延伸。该第一连接电极M也呈长条形且在第一方向X上延伸。该第一连接结构3041、第二连接结构3042和第三连接结构3043用于实现第三金属层304和其他的层结构之间的连接。
例如，在图20中示出了第一过孔结构3071和第二过孔结构3072，该第一过孔结构3071和第二过孔结构3072对应的连接关系在下述中进行描述。例如，在图20中对应于一个子像素的位置处示出了六个第一过孔结构3071(3071a、3071b、3071c、3071d、3071e和3071f)和六个第二过孔结构3072(3072a、3072b、3072c、3072d、3072e和3072f)。
例如，结合图20和图21，该六个第一过孔结构3071分别对应于感应晶体管T2的沟道区T2c的两端的位置、驱动晶体管T3的沟道区T3c的两端的位置和开关晶体管T1的沟道区T1c的两端的位置，具体地，第一过孔结构3071a和第一过孔结构3071b分别对应于感应晶体管T2的沟道区T2c的两端的位置；第一过孔结构3071c和第一过孔结构3071d分别对应于驱动晶体管T3的沟道区T3c的两端的位置；第一过孔结构3071e和第一过孔结构3071f分别对应于开关晶体管T1的沟道区T1c的两端的位置。该第二过孔结构3072a和第二过孔结构3072b在衬底基板31上的正投影位于初始化信号线3011在衬底基板31上的正投影内，且在第二方向Y上位于感应晶体管T2的沟道区T2c在衬底基板31上的正投影的两侧；该第二过孔结构3072c和第二过孔结构3072d在衬底基板31上的正投影位于电源电压信号线3012在衬底基板31上的正投影之内，且在第二方向Y上位于感应晶体管T2的沟道区T2c的两侧，即分别对应于第一电源电压信号线3012a包括的第一部分3012b和第三部分3012d；该第二过孔结构3072e在衬底基板31上的正投影位于第二连接电极K和第一极板Ca在衬底基板31上的正投影之内，且不位于第二极板Cb在衬底基板31上的正投影之内；该第二过孔结构3072f在衬底基板31上的正投影位于数据线3013在衬底基板31上的正投影之内。
例如，结合图20～图22，在该显示面板30中，感应晶体管T2的沟道区T2c通过第一过孔结构3071a和第一连接结构3041电连接，通过第一过孔结 构3071b和第一连接电极M电连接；驱动晶体管T3的沟道区T3c通过第一过孔结构3071c和间隔部322a电连接，通过第一过孔结构3071d和第二极板Cb电连接；开关晶体管T1的沟道区T1c通过第一过孔结构3071e和第二连接结构3042电连接，并通过第一过孔结构3071f和第三连接结构3043电连接。
例如，结合图20～图22，在该显示面板30中，第一连接结构3041通过第二过孔结构3072a和第二过孔结构3072b和位于第一金属层301的初始化信号线3011电连接。间隔部322a通过第二过孔结构3072c和第一电源电压信号线3012a的第一部分3012b电连接，间隔部322b通过第二过孔结构3072d和第一电源电压信号线3012a的第三部分3012d电连接。第二连接电极K通过第二过孔结构3072e和第一极板Ca电连接。第三连接结构3043通过第二过孔结构3072f和数据线3013电连接。
例如，图23为本发明至少一实施例提供的又一种显示面板包括的第一金属层、有源层、第二金属层和第三金属层的叠层的平面结构示意图，图24为图23中的显示面板包括的第一金属层的平面结构示意图，图25为图23中的显示面板包括的第一金属层和有源层叠层的平面结构示意图，图26为图23中的显示面板包括的第一金属层、有源层和第二金属层叠层的平面结构示意图，图27为在图26所示的层叠结构中形成过孔结构的平面结构示意图，图28为图23中的显示面板包括的第三金属层的平面结构示意图。
例如，如图23所示，该显示面板30包括衬底基板31，设置在衬底基板31上的像素电路32，该像素电路32包括感应晶体管T2、驱动晶体管T3、开关晶体管T1、第一栅线321、第二栅线323和存储电容Cst，感应晶体管T2的第一源漏电极T2a和驱动晶体管T3的第一源漏电极T3a通过第一连接电极M电连接；第一栅线321和第二栅线323在第一方向X上延伸，在与第一方向X交叉的第二方向Y上，在第一连接电极M和第一栅线321之间、在第一连接电极M和第二栅线323之间均设置有间隔部322，且该第一连接电极M、第一栅线321、第二栅线323和间隔部322设置在同一层，该间隔部322设置在第一连接电极M和第一栅线321之间，以及设置在第一连接电极M和第二栅线323之间，且使得第一连接电极M、第一栅线321、第二栅线323和间隔部322设置在同一层，可以减小第一栅线321或者第二栅线323产生电压跳变时对第一连接电极M带来的电压变化，进而可以降低第一连接电 极M发生的电压变化对发光二极管造成的损伤，以保证发光二极管的使用寿命。该开关晶体管T1的第一源漏电极T1a和驱动晶体管T3的栅极T3g通过第二连接电极K连接，存储电容Cst的第一极板Ca和第二连接电极K连接，存储电容Cst的第二极板Cb和第一连接电极M连接，以形成一个像素电路的整体。
例如，在图23中，感应晶体管T2和在第二方向Y上位于其两侧的第一栅线321和第二栅线323之间分别具有位于第三金属层304的间隔部322a和间隔部322b，该间隔部322b可以屏蔽感应晶体管T2的第一源漏电极T2a与第一栅线321之间的耦合。感应晶体管T2的第一源漏电极T2a位于第三金属层304，电源电压信号线3012位于第一金属层301，在第一栅线321和感应晶体管T2之间的位于第三金属层304的间隔部322b通过第二过孔结构3072d和位于第一金属层301的电源电压信号线3012电连接；在第二栅线323和感应晶体管T2之间的位于第三金属层304的间隔部322a通过第二过孔结构3072c和位于第一金属层301的电源电压信号线3012电连接。开关晶体管T1可以减少第二连接电极K和第一栅线321或者第二栅线323的耦合。
例如，在图23和图24中是以在第一方向X上排列的两个子像素对应的像素电路为例进行说明的。如图23和图24所示，该第一金属层301包括在第二方向Y上延伸的初始化信号线3011、电源电压信号线3012、第一极板Ca和数据线3013，以及遮光部3014。该初始化信号线3011和数据线3013均为在第二方向Y上延伸的直线状。电源电压信号线3012包括在第二方向Y上延伸的第一电源电压信号线3012a，第一电源电压信号线3012a包括在第二方向Y上延伸且依次连接的第一部分3012b、第二部分3012c和第三部分3012d，第一部分3012b和第三部分3012d在第一方向X上的宽度相等，第二部分3012c在第一方向X上的宽度小于第一部分3012b在第一方向X上的宽度，且第二部分3012c在第二方向Y上的一端和第一部分3012b的靠近第三部分3012d且远离初始化信号线3011的边缘连接，第二部分3012c在第二方向Y上的另一端和第三部分3012d的靠近第一部分3012b且远离初始化信号线3011的边缘连接。第二部分3012c的最远离初始化信号线3011的边缘和第一部分3012b的最远离初始化信号线3011的边缘、第三部分3012d的最远离初始化信号线3011的边缘均对齐且在一条直线上，因此，在第二部分3012c和初始化信号线3011之间形成了一个凹口。
例如，结合图23和图24，在图23所示的显示面板中，在感应晶体管T2的第一源漏电极T2a的下方去除了第一金属层301的一部分，这样可以减少寄生电容，即电源电压信号线3012在对应于感应晶体管T2的第一源漏电极T2a和第一连接电极M的位置处变窄，这样可以减少电源电压信号线3012与感应晶体管T2的第一源漏电极T2a的交叠面积和寄生电容。
例如，结合图26，第一金属层301、有源层302和第二金属层303依次叠层，该第二金属层303包括感应晶体管T2的栅极T2g、驱动晶体管T3的栅极T3g、开关晶体管T1的栅极T1g和第一极板Ca，两个开关晶体管T1的栅极为一体结构。该感应晶体管T2的栅极T2g和开关晶体管T1的栅极T1g均呈在平行于第二方向Y的方向上延伸的长条形，且感应晶体管T2的栅极T2g从感应晶体管T2的沟道区T2c沿着与第二方向Y相反的方向延伸，开关晶体管T1的栅极T1g从位于下方的开关晶体管T1的沟道区T1c沿着第二方向Y延伸。驱动晶体管T3的栅极T3g和第一极板Ca形成为一体结构。结合图23和图26，第一极板Ca包括相互连接的第一极板子块Ca1和第二极板子块Ca2，第二极板子块Ca2包括在第二方向Y上延伸的第一延伸部3031和第二延伸部3032，两个第二连接结构3042分别和第一延伸部3031、第二延伸部3032连接。该第一延伸部3031和第二延伸部3032在衬底基板31上的正投影与第一金属层301在衬底基板31上的正投影没有交叠部分。
例如，在图23中示出了第一过孔结构3071、第二过孔结构3072和第三过孔结构3073，该第一过孔结构3071、第二过孔结构3072和第三过孔结构3073对应的连接关系在下述中进行描述。例如，在图23中对应于一个子像素的位置处示出了八个第一过孔结构3071(3071a、3071b、3071c、3071d、3071e1、3071e2、3071f1和3071f2)，五个第二过孔结构3072(3072a、3072b、3072c、3072d和3072e)和四个第三过孔结构3073(3073a、3073b、3073c和3073d)。
例如，结合图23、图26和图27，该八个第一过孔结构3071分别对应于感应晶体管T2的沟道区T2c的两端的位置、驱动晶体管T3的沟道区T3c的两端的位置和两个开关晶体管T1的沟道区T1c的两端的位置，具体地，第一过孔结构3071a和第一过孔结构3071b分别对应于感应晶体管T2的沟道区T2c的两端的位置；第一过孔结构3071c和第一过孔结构3071d分别对应于驱动晶体管T3的沟道区T3c的两端的位置；第一过孔结构3071e1和第一过孔结构3071f1分别对应于其中一个开关晶体管T1的沟道区T1c的两端的位置； 第一过孔结构3071e2和第一过孔结构3071f2分别对应于另一个开关晶体管T1的沟道区T1c的两端的位置。该第二过孔结构3072a和第二过孔结构3072b在衬底基板31上的正投影位于初始化信号线3011在衬底基板31上的正投影内，且在第二方向Y上位于感应晶体管T2的沟道区T2c在衬底基板31上的正投影的两侧；该第二过孔结构3072c和第二过孔结构3072d在衬底基板31上的正投影位于电源电压信号线3012在衬底基板31上的正投影之内，且在第二方向Y上位于感应晶体管T2的沟道区T2c的两侧，即分别对应于第一电源电压信号线3012a包括的第一部分3012b和第三部分3012d；该第二过孔结构3072e在衬底基板31上的正投影位于数据线3013在衬底基板31上的正投影之内。该第三过孔结构3073a在衬底基板31上的正投影位于感应晶体管T2的栅极T2g在衬底基板31上的正投影之内；该第三过孔结构3073b和第三过孔结构3073c在衬底基板31上的正投影分别位于第一延伸部3031和第二延伸部3032在衬底基板31上的正投影之内；该第三过孔结构3073d在衬底基板31上的正投影位于开关晶体管T1的栅极T1g在衬底基板31上的正投影之内。
例如，结合图26和图27，在图23所示的显示面板中，开关晶体管T1为并联的两个薄膜晶体管，其中一个设置在靠近上侧的第二栅线323的位置处，另外一个设置在靠近下侧的第一栅线321的位置处，即在第二方向Y上设置在第一连接电极M的两侧，同时第二极板子块Ca2的一部分在第二方向Y上的长度减小了，上述设计可以实现增大开关晶体管T1的沟道宽长比和驱动电流，从而有利于高分辨率显示面板的驱动，使得充电的时间减少。
例如，在图23所示的显示面板中，两个开关晶体管T1的第一源漏电极T1a下方的第一金属层301的一部分被去除了，这样可以防止第一连接电极M和开关晶体管T1的底栅耦合产生漏电流。
例如，结合图24和图25，在图23所示的显示面板中，在电源电压信号线3012和数据线3013之间，除了遮光部3014之外不存在其他的结构。该遮光部3014包括位于驱动晶体管T3的沟道区T3c的下方的遮光部3014a，位于上侧的开关晶体管T1的沟道区T1c的下方的遮光部3014b，位于下侧的开关晶体管T1的沟道区T1c的下方的遮光部3014c。
例如，在图23所示的显示面板中，开关晶体管T1的除了第一源漏电极T1a之外的其他结构均无第三金属层覆盖，这样可以减小开关晶体管T1和第 一连接电极M的耦合作用。
例如，结合图23～图28，在该显示面板30中，该显示面板30包括依次层叠设置在衬底基板31上的第一金属层301、有源层302、第二金属层303和第三金属层304。尽管在图23～图28所示的平面图中没有直接示出绝缘层，只是用过孔结构代表了绝缘层，但是在上述相邻层之间还设置有起到绝缘作用的层结构，该起到绝缘作用的层结构中设置有过孔结构，需要连接的层结构通过过孔结构进行连接。
例如，如图23和图25所示，第一金属层301和有源层302叠层，有源层302包括感应晶体管T2的沟道区T2c、驱动晶体管T3的沟道区T3c和两个开关晶体管T1的沟道区T1c。例如，结合图23和图25，该感应晶体管T2的沟道区T2c在衬底基板31上的正投影和初始化信号线3011在衬底基板31上的正投影相互交叠。驱动晶体管T3的沟道区T3c在衬底基板31上的正投影和电源电压信号线3012在衬底基板31上的正投影、遮光部3014a在衬底基板31上的正投影均相互交叠。两个开关晶体管T1的沟道区T1c在衬底基板31上的正投影均和数据线3013在衬底基板31上的正投影相互交叠，并分别和遮光部3014b、遮光部3014c在衬底基板31上的正投影相互交叠。
例如，结合图28所示，在图23所示的显示面板中，第三金属层304包括第一连接电极M、间隔部322、在第一方向X上延伸且呈长条形的第二栅线323和第一栅线321，在第二方向Y上延伸的第一连接结构3041和第三连接结构3043，以及在第一方向X上延伸的两个第二连接结构3042。该第一连接结构3041在衬底基板31上的正投影位于初始化信号线3011在衬底基板31上的正投影之内，第三连接结构3043在衬底基板31上的正投影位于数据线3013在衬底基板31上的正投影之内。该第一连接电极M也呈长条形且在第一方向X上延伸。该第一连接结构3041、第二连接结构3042和第三连接结构3043用于实现第三金属层304和其他的层结构之间的连接。在第二方向Y上，该间隔部322b位于第一连接电极M和第一栅线321之间，从而可以减小第一栅线321产生电压跳变时对第一连接电极M带来的电压变化，该间隔部322a位于第一连接电极M和第二栅线323之间，从而可以减小第二栅线323产生电压跳变时对第一连接电极M带来的电压变化，进而可以降低第一连接电极M发生的电压变化对发光二极管造成的损伤，以保证发光二极管的使用寿命。
例如，图29为图23中显示面板的截面结构示意图，如图29所示，该显示面板30还包括设置在第一金属层301的远离衬底基板31的一侧的缓冲层305，设置在有源层302和第二金属层303之间的栅绝缘层306，设置在第二金属层303和第三金属层304之间的层间绝缘层307，以及设置在第三金属层304的远离衬底基板31的一侧的钝化层308和平坦化层309。
例如，结合图29所示，在层间绝缘层307中设置有第一过孔结构3071，第三金属层304通过第一过孔结构3071和有源层302电连接。
例如，如图29所示，该第三金属层304和第二金属层303之间形成有存储电容。结合图23和图29，开关晶体管T1的第一源漏电极T1a和存储电容Cst的第一极板Ca通过第二连接电极K连接，即两个开关晶体管T1的第一源漏电极T1a分别和第二极板子块Ca2包括的第一延伸部3031和第二延伸部3032连接。
例如，图30为本发明至少一实施例提供的又一种显示面板包括的第一金属层、有源层和第二金属层的叠层的平面结构示意图，图31为图30中的显示面板包括的第一金属层和有源层叠层的平面结构示意图，图32为图30中第二金属层的平面结构示意图，图33为图30中显示面板的截面结构示意图。
例如，结合图2和图30所示，该显示面板30包括衬底基板31，设置在衬底基板31上的像素电路32，该像素电路32包括感应晶体管T2、驱动晶体管T3、开关晶体管T1、第一栅线321、第二栅线323和存储电容Cst，感应晶体管T2的第一源漏电极T2a和驱动晶体管T3的第一源漏电极T3a通过第一连接电极M电连接。第一栅线321和第二栅线323在第一方向X上延伸，在与第一方向X交叉的第二方向Y上，在第一连接电极M和第一栅线321之间、在第一连接电极M和第二栅线323之间均设置有间隔部322，且该第一连接电极M、第一栅线321、第二栅线323和间隔部322设置在同一层，该间隔部322设置在第一连接电极M和第一栅线321，以及设置在第一连接电极M和第二栅线323之间，且使得第一连接电极M、第一栅线321、第二栅线323和间隔部322设置在同一层，可以减小第一栅线321或者第二栅线323产生电压跳变时对第一连接电极M带来的电压变化，进而可以降低第一连接电极M发生的电压变化对发光二极管造成的损伤，以保证发光二极管的使用寿命。该开关晶体管T1的第一源漏电极T1a和驱动晶体管T3的栅极T3g通过第二连接电极K连接，存储电容Cst的第一极板Ca和第二连接电极K连接， 存储电容Cst的第二极板Cb和第一连接电极M连接，以形成一个像素电路的整体。
例如，在图30中，感应晶体管T2和在第二方向Y上位于其两侧的第一栅线321和第二栅线323之间分别具有位于第二金属层303的间隔部322a和间隔部322b，该间隔部322b可以屏蔽感应晶体管T2的第一源漏电极T2a与第一栅线321之间的耦合。感应晶体管T2的第一源漏电极T2a位于第二金属层303，电源电压信号线3012位于第一金属层301，在第一栅线321和感应晶体管T2之间的位于第二金属层303的间隔部322b通过第二过孔结构3072d和位于第一金属层301的电源电压信号线3012电连接；在第二栅线323和感应晶体管T2之间的位于第二金属层303的间隔部322a通过第二过孔结构3072c和位于第一金属层301的电源电压信号线3012电连接。开关晶体管T1可以减少第二连接电极K和栅线(第一栅线321或者第二栅线323)的耦合。存储电容Cst包括位于有源层302的第一极板Ca和位于第二金属层303的第二极板Cb。
例如，在图30所示的显示面板中，在感应晶体管T2的第一源漏电极T2a的下方去除了第一金属层301的一部分，这样可以减少寄生电容，即电源电压信号线3012在对应于感应晶体管T2的第一源漏电极T2a和第一连接电极M的位置处变窄，这样可以减少电源电压信号线3012与感应晶体管T2的第一源漏电极T2a的交叠面积和寄生电容。
例如，在图30所示的显示面板中，开关晶体管T1的第一源漏电极T1a、沟道区T1c和第二源漏电极T1b下方的第一金属层301的一部分被去除了，这样可以防止第一连接电极M和开关晶体管T1的底栅耦合产生漏电流。
例如，结合图30～图32，在该显示面板30中，该显示面板30包括依次层叠设置在衬底基板31上的第一金属层301、有源层302和第二金属层303。尽管在图30～图32所示的平面图中没有直接示出绝缘层，只是用过孔结构代表了绝缘层，但是在上述相邻层之间还设置有起到绝缘作用的层结构，该起到绝缘作用的层结构中设置有过孔结构，需要连接的层结构通过过孔结构进行连接。
例如，在图30和图31中是以在第一方向X上排列的两个子像素对应的像素电路为例进行说明的。如图30和图31所示，该第一金属层301包括在第二方向Y上延伸的初始化信号线3011、电源电压信号线3012和数据线3013。 该初始化信号线3011和数据线3013均为在第二方向Y上延伸的直线状。电源电压信号线3012包括在第二方向Y上延伸的第一电源电压信号线3012a，第一电源电压信号线3012a包括在第二方向Y上延伸且依次连接的第一部分3012b、第二部分3012c和第三部分3012d，第一部分3012b和第三部分3012d在第一方向X上的宽度相等，第二部分3012c在第一方向X上的宽度小于第一部分3012b在第一方向X上的宽度，且第二部分3012c在第二方向Y上的一端和第一部分3012b的靠近第三部分3012d且远离初始化信号线3011的边缘连接，第二部分3012c在第二方向Y上的另一端和第三部分3012d的靠近第一部分3012b且远离初始化信号线3011的边缘连接。第二部分3012c的最远离初始化信号线3011的边缘和第一部分3012b的最远离初始化信号线3011的边缘、第三部分3012d的最远离初始化信号线3011的边缘均对齐且在一条直线上，因此，在第二部分3012c和初始化信号线3011之间形成了一个凹口。
例如，如图30和图31所示，第一金属层301和有源层302叠层，有源层302包括感应晶体管T2的沟道区T2c、驱动晶体管T3的沟道区T3c、开关晶体管T1的沟道区T1c和存储电容Cst的第一极板Ca，且驱动晶体管T3的沟道区T3c和存储电容Cst的第一极板Ca为一体结构。例如，结合图30和图31，该感应晶体管T2的沟道区T2c在衬底基板31上的正投影和初始化信号线3011在衬底基板31上的正投影相互交叠。驱动晶体管T3的沟道区T3c在衬底基板31上的正投影和电源电压信号线3012在衬底基板31上的正投影相互交叠。例如，存储电容Cst的第一极板Ca的靠近第二栅线321的一侧的边缘在第一方向X上延伸至电源电压信号线3012的正上方。
例如，如图32所示，该第二金属层303包括感应晶体管T2的栅极T2g、驱动晶体管T3的栅极T3g、开关晶体管T1的栅极T1g、第二极板Cb、第一连接电极M、间隔部322、第二栅线323、第一栅线321、第一连接结构3041、第二连接结构3042和第三连接结构3043。结合图30和图32，该感应晶体管T2的栅极T2g、驱动晶体管T3的栅极T3g和开关晶体管T1的栅极T1g均呈在平行于第二方向Y的方向上延伸的长条形，且感应晶体管T2的栅极T2g从感应晶体管T2的沟道区T2c沿着与第二方向Y相反的方向延伸，开关晶体管T1的栅极T1g从该开关晶体管T1的沟道区T1c沿着第二方向Y延伸。第二极板Cb在衬底基板31上的正投影位于第一极板Ca在衬底基板31上的正投影之内。该第二栅线323和第一栅线321均呈长条形，且在第一方向X 上延伸。该第一连接电极M也呈长条形且在第一方向X上延伸。第一连接结构3041在第二方向Y上延伸，第二连接结构3042和第三连接结构3043在第一方向X上延伸，该第一连接结构3041、第二连接结构3042和第三连接结构3043用于实现第三金属层304和其他的层结构之间的连接。在第二方向Y上，该间隔部322b位于第一连接电极M和第一栅线321之间，从而可以减小第一栅线321产生电压跳变时对第一连接电极M带来的电压变化，该间隔部322a位于第一连接电极M和第二栅线323之间，从而可以减小第二栅线323产生电压跳变时对第一连接电极M带来的电压变化，进而可以降低第一连接电极M发生的电压变化对发光二极管造成的损伤，以保证发光二极管的使用寿命。
例如，在图30中示出了第一过孔结构3071和第二过孔结构3072，该第一过孔结构3071和第二过孔结构3072对应的连接关系在下述中进行描述。例如，在图30中对应于一个子像素的位置处示出了六个第一过孔结构3071(3071a、3071b、3071c、3071d、3071e和3071f)和六个第二过孔结构3072(3072a、3072b、3072c、3072d、3072e和3072f)。
例如，结合图30和图31，该六个第一过孔结构3071分别对应于感应晶体管T2的沟道区T2c的两端的位置、驱动晶体管T3的沟道区T3c的两端的位置和两个开关晶体管T1的沟道区T1c的两端的位置，具体地，第一过孔结构3071a和第一过孔结构3071b分别对应于感应晶体管T2的沟道区T2c的两端的位置；第一过孔结构3071c和第一过孔结构3071d分别对应于驱动晶体管T3的沟道区T3c的两端的位置；第一过孔结构3071e和第一过孔结构3071f分别对应于开关晶体管T1的沟道区T1c的两端的位置。该第二过孔结构3072a和第二过孔结构3072b在衬底基板31上的正投影位于初始化信号线3011在衬底基板31上的正投影内，且在第二方向Y上位于感应晶体管T2的沟道区T2c在衬底基板31上的正投影的两侧；该第二过孔结构3072c和第二过孔结构3072d在衬底基板31上的正投影位于电源电压信号线3012在衬底基板31上的正投影之内，且在第二方向Y上位于感应晶体管T2的沟道区T2c的两侧，即分别对应于第一电源电压信号线3012a包括的第一部分3012b和第三部分3012d；该第二过孔结构3072e在衬底基板31上的正投影位于第一极板Ca在衬底基板31上的正投影之内，且不位于第二极板Cb在衬底基板31上的正投影之内；该第二过孔结构3072f在衬底基板31上的正投影位于数据线 3013在衬底基板31上的正投影之内。
例如，结合图30～图32，在该显示面板30中，感应晶体管T2的沟道区T2c通过第一过孔结构3071a和第一连接结构3041电连接，通过第一过孔结构3071b和第一连接电极M电连接；驱动晶体管T3的沟道区T3c通过第一过孔结构3071c和间隔部322a电连接，通过第一过孔结构3071d和第二极板Cb电连接；开关晶体管T1的沟道区T1c通过第一过孔结构3071e和第二连接结构3042电连接，并通过第一过孔结构3071f和第三连接结构3043电连接。
例如，结合图30～图32，在该显示面板30中，第一连接结构3041通过第二过孔结构3072a和第二过孔结构3072b和位于第一金属层301的初始化信号线3011电连接。间隔部322a通过第二过孔结构3072c和第一电源电压信号线3012a的第一部分3012b电连接，间隔部322b通过第二过孔结构3072d和第一电源电压信号线3012a的第三部分3012d电连接。第二连接电极K通过第二过孔结构3072e和第一极板Ca电连接。第三连接结构3043通过第二过孔结构3072f和数据线3013电连接。
例如，结合图30～图32，在该显示面板30中，感应晶体管T2的栅极T2g在第二方向Y上延伸至和第一栅线321直接电连接，或者一体成型。该开关晶体管T1的栅极T1g在与第二方向Y相反的方向上延伸至和第二栅线323直接电连接，或者一体成型，且和感应晶体管T2的栅极T2g连接的第一栅线321与和开关晶体管T1的栅极T1g连接的第二栅线323在第二方向Y上位于间隔部322的不同侧。
例如，结合图30～图32，该第一连接结构3041在衬底基板31上的正投影位于初始化信号线3011在衬底基板31上的正投影之内，第三连接结构3043在衬底基板31上的正投影和第二连接结构3042在衬底基板31上的正投影均与第一金属层301在衬底基板31上的正投影无交叠。间隔部322a和间隔部322b在衬底基板31上的正投影位于电源电压信号线3012在衬底基板31上的正投影之内。
例如，在图30中，感应晶体管T2和在第二方向Y上位于其两侧的第一栅线321和第二栅线323之间分别具有位于第二金属层303的间隔部322a和间隔部322b，该间隔部322b可以屏蔽感应晶体管T2的第一源漏电极T2a与第一栅线321之间的耦合。感应晶体管T2的第一源漏电极T2a位于第二金属 层303，电源电压信号线3012位于第一金属层301，在第一栅线321和感应晶体管T2之间的位于第二金属层304的间隔部322b通过第二过孔结构3072d和位于第一金属层301的电源电压信号线3012电连接；在第二栅线323和感应晶体管T2之间的位于第二金属层303的间隔部322a通过第二过孔结构3072c和位于第一金属层301的电源电压信号线3012电连接。
需要说明的第，第一连接电极M的电压变化，会引起第二连接电极K的电压变化。在写数据阶段，希望第一连接电极M的电压更稳定，但是在点亮阶段，第一连接电极M的电压上升是正常的。在点亮阶段，第二连接电极K的电压的上升是由于第一连接电极M的电压上升耦合引起的，这时第二连接电极K和电源电压信号线3012之间当于一个电容，存储电容Cst也是一个电容，耦合过程中，会有一个电容分压，所以第二连接电极K的电压上升没有第一连接电极M的电压上升高。在写数据阶段希望第一连接电极M的电压更稳定，所以对于第一连接电极M用间隔部322进行保护屏蔽，以减小跳变电压。上述设计可以使得，第一连接电极M和第一栅线321之间设置了间隔部322，且第一连接电极M形成在第二金属层303，与第一栅线321设置在同一层，通过间隔部322的屏蔽作用，可以延长有机发光二极管显示器件的寿命。感应晶体管T2及其连接的第一连接电极M在第二方向Y的两侧均有间隔部322，分别屏蔽了第一栅线321和第二栅线323对第一连接电极M的电压变化的影响，即由于间隔部322的存在使得无法形成第一栅线321或者第二栅线323和第一连接电极M之间的寄生电容。
例如，结合图30，感应晶体管T2的第一源漏电极T2a在衬底基板31上的正投影和电源电压信号线3012在衬底基板31上的正投影相间隔，即感应晶体管T2的第一源漏电极T2a在第二部分3012c和初始化信号线3011之间的凹口处。
例如，在图33所示的截面结构示意图中，该显示面板30还包括设置在第一金属层301的远离衬底基板31的一侧的缓冲层305，设置在有源层302和第二金属层303之间的栅绝缘层306、层间绝缘层307，以及设置在第二金属层303的远离衬底基板31的一侧的钝化层308和平坦化层309，在层间绝缘层307中设置有第一过孔结构3071，第二金属层303通过第一过孔结构3071和有源层302电连接；在层间绝缘层307和缓冲层305中贯穿有第二过孔结构3072，第二金属层303通过第二过孔结构3072和位于第一金属层301 的电源电压信号线3012电连接。
例如，图34为本发明至少一实施例提供的又一种显示面板包括的第一金属层、有源层、第二金属层和第三金属层的叠层的平面结构示意图，图35为图34中显示面板包括的第一金属层和第三金属层层叠的平面结构示意图。
例如，结合图35，图34所示的显示面板和图14所示的显示面板的不同之处在于，图34所示的显示面板还包括阴极电压走线324，阴极电压走线324包括在第三金属层304且位于第一栅线321和第二栅线323之间的第一阴极电压走线3241，该第一阴极电压走线3241在第一方向X上延伸。该阴极电压走线324还包括在第一金属层301且位于相邻的两条数据线3013之间的第二阴极电压走线3242。例如，在第一方向X(横向)上延伸的第一阴极电压走线3241和在第二方向Y(纵向)上延伸的第二阴极电压走线3242相交且电连接，可以降低中大尺寸有机发光二极管显示器件的电压降。此外，第二阴极电压走线3242设置在两条数据线3013之间，还可以屏蔽数据信号之间的的串扰。第一阴极电压走线3241设置在第一栅线321和第二栅线323之间之间，还可以屏蔽栅线信号之间的的串扰。
例如，图34所示的显示面板和图14所示的显示面板的不同之处还在于，该第三金属层304还包括在第一方向X上延伸的电源电压信号线3012，即该电源电压信号线3012还包括横向上延伸的第二电源电压信号线3012e，该第二电源电压信号线3012e和第一电源电压信号线3012a相交且电连接，可以降低中大尺寸有机发光二极管显示器件的电压降。
例如，在图34中示出了第一过孔结构3071、第二过孔结构3072和第三过孔结构3073。例如，在图34中对应于一个子像素的位置处示出了八个第一过孔结构3071(3071a、3071b、3071c、3071d、3071e1、3071e2、3071f1和3071f2)，八个第二过孔结构3072(3072a、3072b、3072c、3072d、3072e、3072f、3072g和3072h)和四个第三过孔结构3073(3073a、3073b2、3073b2和3073c)。
例如，图34所示的显示面板和图14所示的显示面板对应的上述过孔结构的不同之处在于，图34所示的显示面板中多出了两个第二过孔结构，即第二过孔结构3072g和第二过孔结构3072h，其他的第二过孔结构、第一过孔结构和第三过孔结构所连接的层结构可以参见上述关于图14的相关描述，在此不再赘述。
例如，在图34中，第二电源电压信号线3012e通过第二过孔结构3072g 和位于第一金属层301的第一电源电压信号线3012a电连接。第一阴极电压走线3241通过第二过孔结构3072h和位于第一金属层301的第二阴极电压走线3242电连接，这样可以进一步减小第一金属层301和第三金属层304之间的电阻。
例如，图35中所示的感应晶体管T2、驱动晶体管T3、开关晶体管T1、第一栅线321、第二栅线323、存储电容Cst、第一连接电极M、间隔部322、第二连接电极K、初始化信号线3011、电源电压信号线3012、第一极板Ca和数据线3013、感应晶体管T2的沟道区T2c、驱动晶体管T3的沟道区T3c、两个开关晶体管T1的沟道区T1c、感应晶体管T2的栅极T2g、驱动晶体管T3的栅极T3g、开关晶体管T1的栅极T1g和第二极板Cb等结构的位置关系可以参见上述中关于图14的相关描述，在此不再赘述。
例如，图36为本发明至少一实施例提供的又一种显示面板包括的第一金属层、有源层、第二金属层和第三金属层的叠层的平面结构示意图。图37为图36所示显示面板的第二阴极电压走线沿着第二方向切割的截面结构示意图，图38为在图37所示的结构中增加阴极和像素界定层的截面结构示意图，图39为在图36所示显示面板上增加有机发光二极管后的截面结构示意图。
例如，图36所示的显示面板和图34所示的显示面板的不同之处在于，第一阴极电压走线3241包括三层层叠结构。结合图36和图37，第二阴极电压走线3242包括位于第一金属层301的第二阴极电压走线第一子层3242a，位于第二金属层303的第二阴极电压走线第二子层3242b，和位于第三金属层304的第二阴极电压走线第三子层3242c，第二阴极电压走线第一子层3242a和第二阴极电压走线第三子层3242c通过第四过孔结构3074电连接，第二阴极电压走线第一子层3242a和第二阴极电压走线第三子层3242c分别通过第四过孔结构3074a和第四过孔结构3074b在两处实现电连接。第二阴极电压走线第二子层3242b和第二阴极电压走线第三子层3242c通过第五过孔结构3075电连接，该第二阴极电压走线第二子层3242b和第二阴极电压走线第三子层3241c分别通过第五过孔结构3075a和第五过孔结构3075b在两处实现电连接，这样可以实现降低第二阴极电压走线的电阻。
例如，在图36中示出了第一过孔结构3071、第二过孔结构3072和第三过孔结构3073。例如，在图36中对应于一个子像素的位置处示出了八个第一过孔结构3071(3071a、3071b、3071c、3071d、3071e1、3071e2、3071f1和 3071f2)，七个第二过孔结构3072(3072a、3072b、3072c、3072d、3072e、3072f、3072g和3072j)，四个第三过孔结构3073(3073a、3073b2、3073b2和3073c)，两个第四过孔结构3074(3074a和3074b)，两个第五过孔结构3075(3075a和3075b)。除了第四过孔结构3074和第五过孔结构3075之外，其他的过孔结构与层结构之间的关系可以参见上述关于图34的相关描述，在此不再赘述。
例如，如图39所示，显示面板还包括有机发光二极管，例如，该有机发光二极管可以是R、G、B三种发光材料沉积在对应的像素区，也可以是使用一种发光材料，例如蓝色OLED发光材料及器件与光致发光的量子点材料结合。该有机发光二极管包括阳极312、发光功能层313和阴极311，该发光功能层313设置在像素界定层310限定的开口区域中。第二阴极电压走线第一子层3242a、第二阴极电压走线第二子层3242b和第二阴极电压走线第三子层3242c中的任意一个通过第六过孔结构3076和阳极312电连接，例如，在图39所示的截面图中，第二阴极电压走线第三子层3242c通过第六过孔结构3076和阳极312电连接，这样可以减小阳极312段差。
例如，如图39所示，该显示面板30还包括设置在第一金属层301的远离衬底基板31的一侧的缓冲层305，该缓冲层305在衬底基板31上整层形成，在该第一金属层301上示出了第二阴极电压走线第一子层3242a。在有源层302和第二金属层303之间设置有栅绝缘层306，在第二金属层303和第三金属层304之间设置有层间绝缘层307。在第三金属层304的远离衬底基板31的一侧依次设置有钝化层308、平坦化层309和像素界定层310。层间绝缘层307、钝化层308和平坦化层309也均整层形成。
例如，在图38中示出了阴极311直接和第三金属层304进行电连接，这样也可以减小阴极段差。
例如，在图39所示的结构中，有源层302的材料可以是低温多晶硅或者氧化物半导体，例如IGZO。第一金属层301、第二金属层303和第三金属层304的材料可以是铜、铝、钼等金属，或者它们的合金。
例如，图40为本发明至少一实施例提供的又一种显示面板包括的第一金属层、有源层、第二金属层和第三金属层的叠层的平面结构示意图，图41为图40所示显示面板的截面结构示意图，如图40和图41所示，该显示面板还包括设置在有机发光二极管上的封装层314，设置在封装层314上的量子点层315，以及设置在量子点层315的远离衬底基板31的一侧的保护层316，其 中，该量子点层315配置为对从有机发光二极管出射的光线进行处理，以提高出射光线的纯度，使得混光更加均匀。
例如，图40所示显示面板的其他结构可以参见上述实施例的相关描述，在此不再赘述。
例如，图42为本发明至少一实施例提供的一种显示装置的框图，如图42所示，该显示装置该显示装置包括上述任一项所述显示面板，该显示装置200包括显示面板30。例如，该显示面板100可以为本发明任一实施例提供的显示面板。
例如，该显示装置200可以为具有显示功能的显示设备。例如，该显示装置200可以为显示器、OLED显示面板、OLED电视、液晶显示面板、液晶显示电视、QLED显示面板、QLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能和触控功能的产品或者部件。
本发明至少一实施例提供的显示面板和显示装置，具有以下至少一项有益技术效果：
(1)本发明至少一实施例提供的显示面板，感应晶体管和在第二方向上位于其两侧的第一栅线和第二栅线之间分别具有位于第三金属层的间隔部，该间隔部可以屏蔽感应晶体管的第一源漏电极与第一栅线之间的耦合。
(2)本发明至少一实施例提供的显示面板，开关晶体管为并联的两个薄膜晶体管，其中一个设置在靠近上侧的第二栅线的位置处，另外一个设置在靠近下侧的第一栅线的位置处，即在第二方向设置在第一连接电极的两侧，同时存储电容的第一极板的一部分在第二方向上的长度减小了，该设计可以实现增大开关晶体管的沟道宽长比和驱动电流，从而有利于高分辨率显示面板的驱动，使得充电的时间减少。
(3)本发明至少一实施例提供的显示面板，在感应晶体管的第一源漏电极的下方去除了第一金属层的一部分，这样可以减少寄生电容，即电源电压信号线在对应于感应晶体管的第一源漏电极和第一连接电极的位置处变窄，这样可以减少电源电压信号线与感应晶体管的第一源漏电极的交叠面积和寄生电容。
(4)本发明至少一实施例提供的显示面板，第二阴极电压走线包括 位于第一金属层的第二阴极电压走线第一子层，位于第二金属层的第二阴极电压走线第二子层，和位于第三金属层的第二阴极电压走线第三子层，这样可以减小电阻，第二阴极电压走线第一子层、第二阴极电压走线第二子层和第二阴极电压走线第三子层中的任意一个通过第六过孔结构和阳极电连接，可以减小阳极段差。
有以下几点需要说明：
(1)本发明实施例附图只涉及到与本发明实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本发明的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (39)

  1. 一种显示面板，包括：
    衬底基板；
    设置在所述衬底基板上的像素电路，所述像素电路包括感应晶体管、驱动晶体管、第一栅线和第二栅线，其中，
    所述感应晶体管的第一源漏电极和所述驱动晶体管的第一源漏电极通过第一连接电极电连接；
    所述第一栅线和所述第二栅线在第一方向上延伸，在与所述第一方向交叉的第二方向上，在所述第一连接电极和所述第一栅线之间，以及在所述第一连接电极和所述第二栅线之间均设置有间隔部，且所述第一连接电极、所述第一栅线、所述第二栅线和所述间隔部设置在同一层。
  2. 根据权利要求1所述的显示面板，还包括设置在所述衬底基板上的开关晶体管和存储电容，其中，所述开关晶体管的第一源漏电极和所述驱动晶体管的栅极通过第二连接电极连接，所述存储电容的第一极板和所述第二连接电极连接，所述存储电容的第二极板和所述第一连接电极连接。
  3. 根据权利要求2所述的显示面板，还包括依次层叠设置在所述衬底基板上的第一金属层、有源层、第二金属层和第三金属层，其中，
    所述第一金属层包括在所述第二方向上延伸的初始化信号线、至少部分在所述第二方向上延伸的电源电压信号线、所述第一极板和数据线；
    所述有源层包括所述感应晶体管的沟道区、所述驱动晶体管的沟道区和所述开关晶体管的沟道区；
    所述第二金属层包括所述感应晶体管的栅极、所述驱动晶体管的栅极、所述开关晶体管的栅极和所述第二极板；
    所述第三金属层包括所述第一连接电极、所述间隔部、在所述第一方向上延伸的所述第二栅线和所述第一栅线。
  4. 根据权利要求3所述的显示面板，其中，所述感应晶体管的栅极在所述第二方向上延伸至和所述第一栅线电连接，所述开关晶体管的栅极在与所述第二方向相反的方向上延伸至和所述第二栅线电连接，且和所述感应晶体管的栅极连接的所述第一栅线与和所述开关晶体管的栅极连接的所述第二栅线在所述第二方向上位于任一所述间隔部的不同侧。
  5. 根据权利要求3所述的显示面板，其中，所述第三金属层还包括在所述第二方向上延伸的第一连接结构、第二连接结构和第三连接结构，其中，所述第一连接结构在所述衬底基板上的正投影位于所述初始化信号线在所述衬底基板上的正投影之内，所述第二连接结构在所述衬底基板上的正投影位于所述第一极板在所述衬底基板上的正投影之内，所述第三连接结构在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影之内。
  6. 根据权利要求5所述的显示面板，还包括设置在所述第一金属层的远离所述衬底基板的一侧的缓冲层，设置在所述有源层和所述第二金属层之间的栅绝缘层，设置在所述第二金属层和所述第三金属层之间的层间绝缘层，以及设置在所述第三金属层的远离所述衬底基板的一侧的钝化层和平坦化层。
  7. 根据权利要求6所述的显示面板，其中，在所述层间绝缘层中设置有第一过孔结构和第三过孔结构，所述第三金属层通过所述第一过孔结构和所述有源层电连接，所述第三金属层通过所述第三过孔结构和所述第二金属层电连接；在所述层间绝缘层和所述缓冲层中贯穿有第二过孔结构，所述第三金属层通过所述第二过孔结构和所述第一金属层电连接。
  8. 根据权利要求7所述的显示面板，其中，所述第一连接结构通过所述第二过孔结构和所述初始化信号线电连接，且通过所述第一过孔结构和所述感应晶体管的第二源漏电极电连接；所述第二连接结构通过所述第一过孔结构和所述开关晶体管的所述第一源漏电极电连接，且通过所述第三过孔结构和所述第二极板电连接；所述第三连接结构通过所述第二过孔结构和所述数据线电连接，且通过所述第一过孔结构和所述开关晶体管的第二源漏电极电连接。
  9. 根据权利要求4～8中任一项所述的显示面板，其中，所述第三金属层的至少一部分和所述第一金属层、所述第二金属层均存在交叠区域，以在所述第一金属层和所述第二金属层之间形成所述存储电容，在所述第二金属层和所述第三金属层之间形成电容结构。
  10. 根据权利要求3所述的显示面板，其中，所述感应晶体管的所述第一源漏电极在所述衬底基板上的正投影和所述电源电压信号线在所述衬底基板上的正投影相交叠。
  11. 根据权利要求3所述的显示面板，其中，所述电源电压信号线包括在所述第二方向上延伸的第一电源电压信号线，所述第一电源电压信号线包括 在所述第二方向上延伸且依次连接的第一部分、第二部分和第三部分，所述第一部分和所述第三部分在所述第一方向上的宽度相等，所述第二部分在所述第一方向上的宽度小于所述第一部分在所述第一方向上的宽度，且所述第二部分在所述第二方向上的一端和所述第一部分的靠近所述第三部分且远离所述初始化信号线的边缘连接，所述第二部分在所述第二方向上的另一端和所述第三部分的靠近所述第一部分且远离所述初始化信号线的边缘连接。
  12. 根据权利要求11所述的显示面板，其中，所述感应晶体管的所述第一源漏电极在所述衬底基板上的正投影和所述电源电压信号线的所述第二部分在所述衬底基板上的正投影相间隔。
  13. 根据权利要求11所述的显示面板，其中，所述第一极板包括在所述第一方向上相互连接的第一极板子块和第二极板子块，所述第二金属层包括在所述第二方向上从所述第二极板的对应于所述第二极板子块的部分延伸的第一延伸部和第二延伸部，两个所述第二连接电极分别和所述第一延伸部、所述第二延伸部连接。
  14. 根据权利要求13所述的显示面板，还包括有机发光二极管，其中，Ast为所述存储电容的面积，dgc为所述第一栅线和所述存储电容之间的最小间距，Lc为所述第一极板子块的和所述第一栅线相邻的边的长度，Wg为所述第一栅线在所述第二方向上的宽度，THKILD为所述存储电容对应的层间绝缘层的厚度。
  15. 根据权利要求14所述的显示面板，其中， VgON为所述第二栅线的开启电压，VgOFF为所述第二栅线的关闭电压，Voled为所述有机发光二极管两端的电压，γ为光学常数。
  16. 根据权利要求15所述的显示面板，其中，所述存储电容为所述第一金属层、所述第二金属层和所述第三金属层形成的三层结构，
    THKBUF为所述存储电容中所述第一金属层和所述第二金属层之间的缓冲层的厚度。
  17. 根据权利要求16所述的显示面板，其中，
  18. 根据权利要求14～17中任一项所述的显示面板，其中， WDD为在所述第一栅线和所述第一连接电极之间的所述间隔部在所述第二方向上的长度，dgd为所述第一栅线和在所述第一栅线和所述第一连接电极之间的所述间隔部之间的最小间距，dsd为所述第一连接电极和在所述第一栅线和所述第一连接电极之间的所述间隔部之间的最小间距。
  19. 根据权利要求14～17中任一项所述的显示面板，其中，Lc为所述第一极板子块的和所述第一栅线相邻的边的长度，Lp为所述第一极板子块和所述第二极板子块在所述第一方向上的长度之和，Rl为所述第一极板子块的和所述第一栅线相邻的边的长度与所述第一极板子块和所述第二极板子块在所述第一方向上的长度之和的比值。
  20. 根据权利要求14～17中任一项所述的显示面板，其中， Wc为所述存储电容在所述第一方向上的宽度，Pitch为一个子像素在所述第一方向上的宽度。
  21. 根据权利要求2所述的显示面板，还包括依次层叠设置在所述衬底基板上的第一金属层、有源层和第二金属层，其中，
    所述第一金属层包括在所述第二方向上延伸的初始化信号线、至少部分在所述第二方向上延伸的电源电压信号线、所述第一极板和数据线；
    所述有源层包括所述感应晶体管的沟道区、所述驱动晶体管的沟道区和所述开关晶体管的沟道区；
    所述第二金属层包括所述感应晶体管的栅极、所述驱动晶体管的栅极、所述开关晶体管的栅极、所述第二极板、所述第一连接电极、所述间隔部、在所述第一方向上延伸的所述第二栅线和所述第一栅线。
  22. 根据权利要求21所述的显示面板，其中，所述开关晶体管的栅极和所述第二栅线电连接，所述感应晶体管的栅极和所述第一栅线电连接，且和所述开关晶体管的栅极连接的所述第二栅线与和所述感应晶体管的栅极连接的所述第一栅线在所述第二方向上位于所述第一极板的不同侧，在所述第二方向上，所述第二连接电极在所述第一连接电极和与所述开关晶体管的栅极连接的所述第二栅线之间。
  23. 根据权利要求1所述的显示面板，还包括设置在所述衬底基板上的开关晶体管，其中，所述开关晶体管的第一源漏电极和所述驱动晶体管的栅极通 过第二连接电极连接。
  24. 根据权利要求23所述的显示面板，还包括依次层叠设置在所述衬底基板上的第一金属层、有源层、第二金属层和第三金属层，其中，
    所述第一金属层包括在所述第二方向上延伸的初始化信号线、电源电压信号线和数据线，以及遮光部；
    所述有源层包括所述感应晶体管的沟道区、所述驱动晶体管的沟道区和所述开关晶体管的沟道区；
    所述第二金属层包括所述感应晶体管的栅极、所述驱动晶体管的栅极和所述开关晶体管的栅极；
    所述第三金属层包括所述第一连接电极、所述间隔部、在所述第一方向上延伸的所述第二栅线和所述第一栅线。
  25. 根据权利要求24所述的显示面板，其中，所述第三金属层还包括在所述第二方向上延伸的第一连接结构和第二连接结构，所述第一连接结构在所述衬底基板上的正投影位于所述初始化信号线在所述衬底基板上的正投影之内，所述第二连接结构在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影之内。
  26. 根据权利要求25所述的显示面板，还包括设置在所述第一金属层的远离所述衬底基板的一侧的缓冲层，设置在所述有源层和所述第二金属层之间的栅绝缘层，设置在所述第二金属层和所述第三金属层之间的层间绝缘层，以及设置在所述第三金属层的远离所述衬底基板的一侧的钝化层和平坦化层。
  27. 根据权利要求26所述的显示面板，其中，在所述层间绝缘层中设置有第一过孔结构，所述第三金属层通过所述第一过孔结构和所述有源层电连接；在所述层间绝缘层和所述缓冲层中贯穿有第二过孔结构，所述第三金属层通过所述第二过孔结构和所述电源电压信号线电连接。
  28. 根据权利要求25～27中任一项所述的显示面板，其中，在所述第三金属层和所述第二金属层之间形成有存储电容。
  29. 根据权利要求1所述的显示面板，还包括设置在所述衬底基板上的开关晶体管和存储电容，其中，所述开关晶体管的第一源漏电极和所述存储电容的第一极板通过第二连接电极连接。
  30. 根据权利要求29所述的显示面板，还包括依次层叠设置在所述衬底基板上的第一金属层、有源层和第二金属层，其中，所述第一金属层包括在所 述第二方向上延伸的初始化信号线、电源电压信号线和数据线；所述有源层包括所述感应晶体管的沟道区、所述驱动晶体管的沟道区、所述开关晶体管的沟道区和所述第一极板；所述第二金属层包括所述感应晶体管的栅极、所述驱动晶体管的栅极和所述开关晶体管的栅极、所述第一连接电极、所述间隔部、所述存储电容的第二极板、在所述第一方向上延伸的所述第二栅线和所述第一栅线。
  31. 根据权利要求30所述的显示面板，其中，所述存储电容的所述第一极板的靠近所述第二栅线的一侧的边缘在所述第一方向上延伸至所述电源电压信号线的正上方。
  32. 根据权利要求30所述的显示面板，其中，所述第二金属层还包括在所述第二方向上延伸的第一连接结构，所述第一连接结构在所述衬底基板上的正投影位于所述初始化信号线在所述衬底基板上的正投影之内。
  33. 根据权利要求32所述的显示面板，还包括设置在所述第一金属层的远离所述衬底基板的一侧的缓冲层，设置在所述有源层和所述第二金属层之间的栅绝缘层、层间绝缘层，以及设置在所述第二金属层的远离所述衬底基板的一侧的钝化层和平坦化层，其中，在所述层间绝缘层中设置有第一过孔结构，所述第二金属层通过所述第一过孔结构和所述有源层电连接；在所述层间绝缘层和所述缓冲层中贯穿有第二过孔结构，所述第二金属层通过所述第二过孔结构和所述电源电压信号线电连接。
  34. 根据权利要求11所述的显示面板，还包括阴极电压走线，其中，所述阴极电压走线包括在所述第一方向上延伸的第一阴极电压走线和在所述第二方向上延伸的第二阴极电压走线，所述第一阴极电压走线和所述第二阴极电压走线相交；所述电源电压信号线还包括在所述第一方向上延伸的第二电源电压信号线，所述第一电源电压信号线和所述第二电源电压信号线相交。
  35. 根据权利要求34所述的显示面板，其中，所述第二阴极电压走线包括三层层叠结构，且所述第二阴极电压走线包括位于所述第一金属层的第二阴极电压走线第一子层，位于所述第二金属层的第二阴极电压走线第二子层，和位于所述第三金属层的第二阴极电压走线第三子层，所述第二阴极电压走线第一子层和所述第二阴极电压走线第三子层通过第四过孔结构电连接，所述第二阴极电压走线第二子层和所述第二阴极电压走线第三子层通过第五过孔结构电连接。
  36. 根据权利要求35所述的显示面板，还包括有机发光二极管，其中所述有机发光二极管包括阳极，所述第二阴极电压走线第一子层、所述第二阴极电压走线第二子层和所述第二阴极电压走线第三子层中的任意一个通过第六过孔结构和所述阳极电连接。
  37. 根据权利要求36所述的显示面板，其中，所述第一阴极电压走线第三子层通过所述第六过孔结构和所述阳极电连接。
  38. 根据权利要求37所述的显示面板，还包括设置在所述有机发光二极管上封装层，和设置在封装层上的量子点层，其中，所述量子点层配置为对从所述有机发光二极管出射的光线进行处理。
  39. 一种显示装置，包括：权利要求1～38中任一项所述的显示面板。
PCT/CN2024/094893 2023-06-14 2024-05-23 显示面板和显示装置 Ceased WO2024255557A1 (zh)

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