WO2024254935A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2024254935A1
WO2024254935A1 PCT/CN2023/107821 CN2023107821W WO2024254935A1 WO 2024254935 A1 WO2024254935 A1 WO 2024254935A1 CN 2023107821 W CN2023107821 W CN 2023107821W WO 2024254935 A1 WO2024254935 A1 WO 2024254935A1
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WO
WIPO (PCT)
Prior art keywords
layer
substrate
via hole
display panel
anode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/107821
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English (en)
French (fr)
Inventor
宋志伟
郑帅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to JP2023545342A priority Critical patent/JP7785087B2/ja
Priority to EP23744035.9A priority patent/EP4727312A1/en
Priority to US18/264,423 priority patent/US20260090207A1/en
Publication of WO2024254935A1 publication Critical patent/WO2024254935A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape

Definitions

  • the present invention relates to the field of display, and in particular to a display panel and a manufacturing method thereof.
  • OLED Organic Light-Emitting Diode
  • the OLED display panel uses an opening in the pixel definition layer formed as a whole layer to form a light-emitting element in the opening.
  • the pixel definition layer has a technical problem that stress is difficult to release, resulting in a reduction in the quality of the display panel.
  • the present invention provides a display panel and a manufacturing method thereof, which can alleviate the technical problem that stress is difficult to release due to the formation of a pixel definition layer on the entire display panel, thereby affecting the product quality of the display panel.
  • the present invention provides a display panel, comprising:
  • a plurality of pixel definition parts wherein the pixel definition parts cover the edge of the anode and expose a portion of the anode;
  • one of the pixel definition parts is arranged around one of the anodes, and adjacent pixel definition parts are arranged at intervals;
  • the pixel definition portion includes a first side surface away from the anode, and the first side surface close to the substrate has a first angle with the substrate, the first angle is greater than or equal to 35 degrees, and the first angle is less than or equal to 45 degrees.
  • the display panel further comprises a first metal layer, wherein the first metal layer is located between the anode and the substrate;
  • the display panel also includes a first insulating layer, which is located between the first metal layer and the anode.
  • the first insulating layer includes a first via hole.
  • the anode includes a first connecting portion located in the first via hole, the first connecting portion is connected to the first metal layer, and the pixel definition portion covers the first connecting portion.
  • the display panel further comprises an active layer, the active layer is located between the first metal layer and the substrate, the active layer comprises a channel portion and a first conductor sub-portion and a second conductor sub-portion respectively located at opposite sides of the channel portion;
  • the first metal layer includes a source electrode and a drain electrode, the source electrode is located on the first conductor sub-portion, and the drain electrode is located on the second conductor sub-portion;
  • At least a part of the source electrode near the active layer contacts the first conductor sub-portion, and at least a part of the drain electrode near the active layer contacts the second conductor sub-portion.
  • the display panel further comprises a gate, the gate is located between the source electrode and the drain electrode, and the orthographic projection of the gate on the active layer covers the channel portion;
  • the display panel further includes a gate insulating layer, and the gate insulating layer is at least spaced between the gate and the channel portion.
  • the gate is located in the first metal layer, the gate insulating layer includes a first insulating portion, a second insulating portion and a third insulating portion which are arranged separately, the first insulating portion is spaced between the channel portion and the gate, the second insulating portion is spaced between a portion of the source and the first conductor sub-portion, and the third insulating portion is spaced between a portion of the drain and the second conductor sub-portion;
  • One end of the source electrode close to the gate electrode contacts the first conductor sub-portion, and one end of the drain electrode close to the gate electrode contacts the second conductor sub-portion.
  • the gate is located on a side of the first metal layer away from the substrate, no insulating layer is provided between the source and the first conductor sub-portion, and no insulating layer is provided between the drain and the second conductor sub-portion.
  • an edge of a side of the source electrode away from the gate exceeds an edge of a side of the first conductor sub-portion away from the channel portion;
  • an edge of a side of the drain away from the gate exceeds an edge of a side of the second conductor sub-portion away from the channel portion.
  • the display panel further comprises a second metal layer, the second metal layer is located between the active layer and the substrate, the second metal layer comprises a first light shielding portion, and the orthographic projection of the active layer on the substrate is located within the orthographic projection of the first light shielding portion on the substrate;
  • the display panel further includes a buffer layer, which is located on a side of the active layer close to the substrate, and covers the second metal layer.
  • the first insulating layer includes a passivation layer close to the substrate, the buffer layer is spaced between the second metal layer and the active layer, and the buffer layer is in direct contact with the active layer and the passivation layer on a side away from the substrate;
  • a side of the buffer layer close to the substrate is in direct contact with the second metal layer and the substrate.
  • the gate insulating layer includes a first insulating portion, a second insulating portion and a third insulating portion that are separately arranged, an end of the second insulating portion away from the first insulating portion contacts the buffer layer, and an end of the third insulating portion away from the first insulating portion contacts the buffer layer.
  • the first insulating layer further includes a second via hole, and the second via hole is located on one side of the active layer;
  • the buffer layer includes a third via hole, the third via hole is connected to the second via hole, and the anode is connected to the first light shielding portion through the second via hole and the third via hole;
  • the anode includes a second connection portion, and an orthographic projection of the pixel definition portion on the substrate covers an orthographic projection of the second connection portion on the substrate.
  • the gate insulation layer includes a fourth via hole, the fourth via hole is located on the side of the second insulation portion away from the active layer, the buffer layer includes a fifth via hole, the fourth via hole is connected to the fifth via hole, and the source is connected to the first light shielding portion through the fourth via hole and the fifth via hole.
  • the gate insulation layer includes a sixth via hole, the sixth via hole is located on the side of the third insulation portion away from the active layer, the buffer layer includes a seventh via hole, the sixth via hole is connected to the seventh via hole, and the drain is connected to the first light shielding portion through the sixth via hole and the seventh via hole.
  • the display panel includes a display area and a non-display area located at least on one side of the display area, and the display panel further includes a terminal located in the non-display area, and the terminal is located in the first metal layer;
  • the terminals include first-type terminals, and the first-type terminals are connected to the second metal layer.
  • the gate insulating layer when the gate insulating layer includes the first insulating portion, the second insulating portion and the third insulating portion which are arranged separately, the gate insulating layer also includes a fourth insulating portion located between the terminal and the buffer layer, the gate insulating layer also includes an eighth via hole, the eighth via hole passes through the fourth insulating portion, the buffer layer includes a ninth via hole, the ninth via hole passes through the buffer layer between the second metal layer routing and the fourth insulating portion, and the orthographic projection of the eighth via hole on the substrate covers the orthographic projection of the ninth via hole on the substrate;
  • the first-type terminal includes a first-type terminal connecting portion, which is located in the eighth via and the ninth via.
  • the eighth via and the ninth via expose the second metal layer routing, and the first-type terminal connecting portion is in contact with the second metal layer routing.
  • the pixel defining portion and the anode have an overlapping portion, and a width of an orthographic projection of the overlapping portion on the substrate is greater than 2 microns.
  • the display panel further comprises an organic layer located on a side of the anode away from the substrate, and the organic layer comprises a light-emitting layer;
  • the pixel definition portion includes a second side surface close to the anode, and the orthographic projection of the anode on the substrate and the orthographic projection of the second side surface on the substrate jointly cover the orthographic projection of the light-emitting layer on the substrate.
  • a side of the second side surface close to the anode has a second angle with the anode, and the second angle is greater than or equal to 35 degrees, and the second angle is less than or equal to 45 degrees.
  • the present invention also provides a method for manufacturing a display panel, comprising:
  • the anode material layer and the pixel definition material layer are subjected to a first patterning process to form a plurality of anodes and a plurality of pixel definition portions respectively;
  • the pixel definition part covers the edge of the anode and exposes part of the anode.
  • One pixel definition part is arranged around one anode, and adjacent pixel definition parts are arranged at intervals.
  • the method before forming the anode material layer on the substrate, the method further comprises:
  • the semiconductor material layer and the first metal material layer are subjected to a second patterning process to form a semiconductor layer and a first metal layer respectively;
  • the first metal layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively located at two opposite sides of the semiconductor layer.
  • the present invention arranges pixel definition parts and anodes in one-to-one correspondence and spaces adjacent pixel definition parts, thereby reducing stress on the pixel definition parts and making the slope of the first side surface of the pixel definition parts gentler, thereby increasing the contact area between the pixel definition parts and adjacent film layers, enhancing the firmness of the connection between the pixel definition parts and adjacent film layers, and improving the product quality of the display panel.
  • FIG1 is a schematic structural diagram of a first structure of a display panel provided by an embodiment of the present invention.
  • FIG2 is a schematic structural diagram of a second structure of a display panel provided by an embodiment of the present invention.
  • FIG. 3 is a flowchart of the steps of a method for manufacturing a display panel provided by an embodiment of the present invention.
  • 4a to 4m are schematic flow charts of a method for manufacturing a display panel provided in an embodiment of the present invention.
  • the pixel definition layer in the display panel is integrally formed, and there is a technical problem that the stress of the pixel definition layer is difficult to release, resulting in the quality of the display panel being affected.
  • an embodiment of the present invention provides a display panel 100, including:
  • a plurality of pixel definition parts 103 wherein the pixel definition parts 103 cover the edge of the anode 102 and expose a portion of the anode 102;
  • one of the pixel definition parts 103 is disposed around one of the anodes 102, and adjacent pixel definition parts 103 are disposed at intervals;
  • the pixel definition portion 103 includes a first side surface 103a away from the anode 102, and the first side surface 103a close to the substrate 101 has a first angle ⁇ with the substrate 101, and the first angle ⁇ is greater than or equal to 35 degrees, and the first angle ⁇ is less than or equal to 45 degrees.
  • the pixel definition parts 103 and the anodes 102 are arranged in a one-to-one correspondence, and adjacent pixel definition parts 103 are spaced apart, thereby reducing the stress on the pixel definition parts 103, and the slope of the first side surface 103a of the pixel definition part 103 is gentler, thereby increasing the contact area between the pixel definition part 103 and the adjacent film layer, enhancing the firmness of the connection between the pixel definition part 103 and the adjacent film layer, and improving the product quality of the display panel 100.
  • the display panel 100 further includes a first metal layer 104 .
  • the first metal layer 104 is located between the anode 102 and the substrate 101 .
  • the display panel 100 also includes a first insulating layer, which is located between the first metal layer 104 and the anode 102.
  • the first insulating layer includes a first via hole H1.
  • the anode 102 includes a first connecting portion located in the first via hole H1, and the first connecting portion is connected to the first metal layer 104.
  • the pixel definition portion 103 covers the first connecting portion.
  • the first metal layer 104 may be a plurality of layers or a single layer formed of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or alloys thereof.
  • the first metal layer 104 may be a molybdenum-titanium alloy/copper/molybdenum-titanium alloy (MoTi/Cu/MoTi) three-layer stacked structure formed of molybdenum-titanium alloy and copper.
  • the thickness of the MoTi layer close to the substrate 101 is 250 angstroms to 350 angstroms
  • the thickness of the Cu layer is 4200 angstroms to 6500 angstroms
  • the thickness of the MoTi layer away from the substrate 101 is 400 angstroms to 500 angstroms.
  • the anode 102 includes a material with a high work function.
  • the anode 102 includes one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), etc., which are conductive materials with relatively high work functions and are transparent.
  • the anode 102 may also include reflective materials such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a combination thereof.
  • the anode 102 may be composed of a single layer or multiple layers of a transparent conductive material and/or a reflective conductive material.
  • the anode 102 may be a three-layer stack of IZO/Ag/IZO formed by IZO and Ag.
  • the thickness of the IZO layer close to the substrate 101 may be 100 angstroms to 200 angstroms
  • the thickness of the Ag layer may be 1000 angstroms to 1500 angstroms
  • the thickness of the IZO layer away from the substrate 101 may be 700 angstroms to 1000 angstroms.
  • the pixel definition portion 103 is disposed around the anode 102 and has a pixel definition opening.
  • the pixel definition opening exposes the anode 102 .
  • the material of the pixel definition portion 103 is selected from organic materials, such as positive photoresist materials or negative photoresist materials, so that the material of the pixel definition portion 103 can be used as a photoresist, and the pixel definition portion 103 and the anode 102 are formed by the same patterning process, which saves process technology and reduces process costs.
  • the thickness of the pixel definition portion 103 can be 2.8 microns to 3.7 microns, for example, 3 microns, 3.2 microns, 3.4 microns, 3.5 microns, 3.6 microns, etc., so as to form a sufficiently deep pixel definition opening.
  • the first insulating layer includes a passivation layer 112 on a side close to the substrate 101 and a flat layer 113 on a side away from the substrate 101, the passivation layer 112 at least covers the first metal layer 104, and the flat layer 113 serves to provide a flat surface for the formation of the anode 102, and the anode 102 can be directly formed on the side of the flat layer 113 away from the substrate 101.
  • the first insulating layer can be composed of the passivation layer 112 and the flat layer 113.
  • the material of the passivation layer 112 is selected from inorganic materials, such as nitrogen silicon compounds or oxygen silicon compounds, etc.
  • the material of the planar layer 113 can be selected from organic materials, such as positive photoresist materials or negative photoresist materials, etc., so that the passivation layer 112 and the planar layer 113 can be formed by one patterning process, saving process technology and reducing process cost.
  • the thickness of the passivation layer 112 is 3500 angstroms to 5000 angstroms, for example, it can be 3600 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, 4500 angstroms, 4800 angstroms, etc., so as to completely cover the first metal layer 104; the thickness of the planarization layer 113 is 3500 angstroms to 5000 angstroms, for example, it can be 3600 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, 4500 angstroms, 4800 angstroms, etc., so as to provide a flat surface.
  • the first via hole H1 exposes the first metal layer 104
  • the anode 102 includes a first connection portion located in the first via hole H1, and the first connection portion contacts the first metal layer 104 in the first via hole H1, thereby achieving connection between the anode 102 and the first metal layer 104. Since the first connection portion is filled in the first via hole H1 to facilitate connection with the first metal layer 104, in order to prevent the organic layer (such as the light-emitting layer) formed on the anode 102 from falling into the first via hole H1, the pixel definition portion 103 covers the first via hole H1.
  • the first via hole H1 includes a first sub-via hole located in the passivation layer 112 and a second sub-via hole located in the planar layer 113 .
  • the substrate 101 may be a hard substrate or a flexible substrate.
  • the substrate 101 may be a glass substrate; when the substrate 101 is a flexible substrate, the material of the substrate 101 may be polyimide.
  • the first metal layer 104 includes a source 106 and a drain 107.
  • the first via H1 exposes the source 106, and the first connecting portion contacts the source 106; or, the first metal layer 104 exposes the drain 107, and the first connecting portion contacts the drain 107.
  • the display panel 100 further includes an active layer 105 , wherein the active layer 105 is located between the first metal layer 104 and the substrate 101 , and the active layer 105 includes a channel portion 105 a and a first conductor sub-portion 105 b and a second conductor sub-portion 105 c respectively located on opposite sides of the channel portion 105 a .
  • the source electrode 106 is located on the first conductor sub-portion 105 b
  • the drain electrode 107 is located on the second conductor sub-portion 105 c .
  • At least a part of the source electrode 106 close to the active layer 105 contacts the first conductor sub-portion 105 b , and at least a part of the drain electrode 107 close to the active layer 105 contacts the second conductor sub-portion 105 c .
  • the material of the active layer 105 can be selected from conductive oxide materials, such as indium gallium zinc oxide (IGZO).
  • conductive oxide materials such as indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the first conductor sub-section 105b and the second conductor sub-section 105c can be made conductive by ion implantation or plasma bombardment.
  • ion implantation specific elements or particles are doped, including but not limited to H, He, B, Al, N, F, P, Ar, S, etc.; by plasma bombardment, the surface of the active layer 105 material is bombarded by high-energy particles to form defects (oxygen vacancies). Oxygen vacancies can generate carriers to increase the conductive properties, thereby achieving the conductive properties of the first conductor sub-section 105b and the second conductor sub-section 105c.
  • the material of the active layer 105 may be selected from polysilicon.
  • the thickness of the active layer 105 may be 200 angstroms to 500 angstroms, for example, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, etc.
  • the display panel 100 also includes a gate 108.
  • the gate 108 is located on a side of the active layer 105 away from the substrate 101.
  • the gate 108 is located between the source 106 and the drain 107.
  • the orthographic projection of the gate 108 on the active layer 105 covers the channel portion 105a.
  • the display panel 100 further includes a gate insulating layer 109, which is located on a side of the gate 108 close to the active layer 105, and the gate insulating layer 109 is at least spaced between the gate 108 and the channel portion 105a.
  • the planar layer 113 covers the gate insulating layer 109, the first metal layer 104 and/or the gate 108.
  • the material of the gate 108 can be selected from low resistance materials such as Al, Ti, Mo, Cu, Ni, or alloys thereof, and the gate 108 can be a single-layer or multi-layer structure formed of the above metals or alloys.
  • the gate 108 is located at the first metal layer 104 .
  • the source 106 , the drain 107 , and the gate 108 can be formed using the same material in the same process, which is beneficial to saving process technology and reducing process cost.
  • the gate insulating layer 109 is made of at least one of silicon nitride and silicon oxide.
  • the gate insulating layer 109 may be one or more layers of silicon nitride or silicon oxide, for example, a single layer of silicon oxide.
  • the thickness of the gate insulating layer 109 is 1000 angstroms to 2000 angstroms, for example, 1200 angstroms, 1500 angstroms, 1800 angstroms, etc.
  • the gate insulating layer 109 includes a first insulating portion, a second insulating portion, and a third insulating portion that are separately arranged, the first insulating portion is spaced between the channel portion 105a and the gate 108, the second insulating portion is spaced between a portion of the source 106 and the first conductor sub-portion 105b, and the third insulating portion is spaced between a portion of the drain 107 and the second conductor sub-portion 105c.
  • the first insulating portion, the second insulating portion and the third insulating portion are arranged separately, that is, the orthographic projections of the three on the substrate 101 are separated from each other; the first insulating portion is disconnected from the second insulating portion, and the first insulating portion is disconnected from the third insulating portion.
  • the gate insulating layer 109 includes a first opening located between the first insulating portion and the second insulating portion, and the gate insulating layer 109 includes a second opening located between the first insulating portion and the third insulating portion.
  • the first insulating portion is spaced between the channel portion 105a and the gate 108, that is, along the direction from the substrate 101 to the first metal layer 104, the channel portion 105a and the gate 108 are respectively located on both sides of the first insulating portion.
  • the side of the gate 108 close to the first insulating portion is in direct contact with the first insulating portion, and the side of the first insulating portion close to the active layer 105 is in direct contact with the channel portion 105a.
  • the orthographic projection of the gate 108 on the substrate 101 is located within the orthographic projection of the first insulating portion on the substrate 101, and the orthographic projection of the channel portion 105a on the substrate 101 is located within the orthographic projection of the first insulating portion on the substrate 101.
  • the second insulating portion is spaced between part of the source 106 and the first conductor sub-portion 105b, the side of the second insulating portion close to the substrate 101 is in direct contact with an end of the first conductor sub-portion 105b away from the channel portion 105a, the second insulating portion at least covers a part of the end of the first conductor sub-portion 105b away from the channel portion 105a, the end of the source 106 close to the gate 108 is in contact with the first conductor sub-portion 105b through the first opening, and the end of the source 106 close to the gate 108 covers an end of the second insulating portion close to the first insulating portion.
  • the third insulating portion is separated between part of the source 106 and the second conductor sub-portion 105c, and the side of the third insulating portion close to the substrate 101 is in direct contact with the end of the second conductor sub-portion 105c away from the channel portion 105a, and the third insulating portion at least covers part of the end of the second conductor sub-portion 105c away from the channel portion 105a.
  • the end of the drain 107 close to the gate 108 is in contact with the second conductor sub-portion 105c through the second opening, and the end of the drain 107 close to the gate 108 covers the end of the third insulating portion close to the first insulating portion.
  • Fig. 2 there is no insulating layer between the source electrode 106 and the first conductor sub-section 105b, and there is no insulating layer between the drain electrode 107 and the second conductor sub-section 105c. That is, the source electrode 106 is directly located on the first conductor sub-section 105b, and the drain electrode 107 is directly located on the second conductor sub-section 105c, which is conducive to the first metal layer 104 and the active layer 105 being formed through a single patterning process, which is convenient for simplifying the process technology and reducing the process cost.
  • the gate 108 When there is no insulating layer between the source 106 and the first conductor sub-portion 105b, and there is no insulating layer between the drain 107 and the second conductor sub-portion 105c, the gate 108 is located on the side of the first metal layer 104 away from the substrate 101, and the gate insulating layer 109 is spaced between the channel portion 105a and the gate 108.
  • the orthographic projection of the gate 108 on the substrate 101 is located within the orthographic projection of the gate insulating layer 109 on the substrate 101, and the orthographic projection of the channel portion 105a on the substrate 101 is located within the orthographic projection of the gate insulating layer 109 on the substrate 101.
  • the material of the gate 108 can be a double-layer structure composed of a Cu layer and a MoTi alloy layer, wherein the Cu layer is located on the side of the gate 108 close to the substrate 101, and the MoTi alloy layer is located on the side of the gate 108 away from the substrate 101.
  • the thickness of the Cu layer is 1800 angstroms to 4200 angstroms, for example, 1900 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, etc.
  • the thickness of the MoTi alloy layer is 250 angstroms to 350 angstroms, for example, 280 angstroms, 300 angstroms, 320 angstroms, 340 angstroms, etc.
  • the gate electrode 108 , the source electrode 106 , the drain electrode 107 , and the active layer 105 constitute a thin film transistor device of the display panel 100 .
  • the display panel 100 further includes a second metal layer 110, the second metal layer 110 is located between the active layer 105 and the substrate 101, the second metal layer 110 includes a first light shielding portion 110a, and the orthographic projection of the active layer 105 on the substrate 101 is located within the orthographic projection of the first light shielding portion 110a on the substrate 101.
  • the provision of the first light shielding portion 110a is conducive to preventing light from the substrate 101 from irradiating the active layer 105, thereby affecting the working performance of the active layer 105.
  • the material of the second metal layer 110 can be selected from metal materials, such as Al, Ti, Mo, Cu, Ni, or alloys including the above metals.
  • the second metal layer 110 can be a single layer or multiple layers formed by the above metal materials or alloys including the above metal materials.
  • the second metal layer 110 can be a double-layer stacked structure of MoTi/Cu formed by a MoTi alloy layer and a Cu layer, the MoTi alloy layer is located on the side close to the substrate 101, and the Cu layer is located on the side away from the substrate 101.
  • the thickness of the MoTi alloy layer can be 250 angstroms to 350 angstroms, for example, 280 angstroms, 300 angstroms, 320 angstroms, 340 angstroms, etc.; the thickness of the Cu layer can be 2800 angstroms to 8000 angstroms, for example, 2900 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms, etc.
  • the display panel 100 further includes a buffer layer 111 .
  • the buffer layer 111 is located on a side of the active layer 105 close to the substrate 101 .
  • the buffer layer 111 covers the second metal layer 110 .
  • the buffer layer 111 is spaced between the second metal layer 110 and the active layer 105 .
  • the side of the buffer layer 111 away from the substrate 101 is in direct contact with the active layer 105 .
  • the side of the buffer layer 111 away from the substrate 101 is in direct contact with the passivation layer 112 .
  • a side of the buffer layer 111 close to the substrate 101 is in direct contact with the second metal layer 110
  • a side of the buffer layer 111 close to the substrate 101 is in direct contact with the substrate 101 .
  • the material of the buffer layer 111 is selected from at least one of silicon nitride compounds and silicon oxide compounds.
  • the buffer layer 111 may be a single layer or a stacked layer formed of silicon nitride compounds or silicon oxide compounds.
  • the buffer layer 111 may include a first buffer sublayer and a second buffer sublayer, the material of the first buffer sublayer is a silicon nitride compound, the material of the second buffer sublayer is a silicon oxide compound, the first buffer sublayer is located on the side of the buffer layer 111 close to the substrate 101, and the second buffer sublayer is located on the side of the buffer layer 111 away from the substrate 101.
  • the thickness of the first buffer sublayer is 500 angstroms to 2000 angstroms, for example, 800 angstroms, 1000 angstroms, 1200 angstroms, 1500 angstroms, 1800 angstroms, etc.; the thickness of the second buffer sublayer is 2000 angstroms to 3000 angstroms, for example, 2200 angstroms, 2500 angstroms, 2600 angstroms, 2800 angstroms, etc.
  • the gate insulating layer 109 includes the first insulating portion, the second insulating portion and the third insulating portion which are arranged separately, an end of the second insulating portion away from the first insulating portion contacts the buffer layer 111 , and an end of the third insulating portion away from the first insulating portion contacts the buffer layer 111 .
  • the first light shielding portion 110a is connected to the source 106; or, the first light shielding portion 110a is connected to the drain 107.
  • the connection between the first light shielding portion 110a and the source 106 or the drain 107 avoids electrical drift of the thin film transistor device caused by the first light shielding portion 110a, thereby improving the working performance of the thin film transistor device.
  • the gate electrode 108 when the gate electrode 108 is located at a side of the first metal layer 104 away from the substrate 101, there is no insulating layer between the source electrode 106 and the first conductor sub-portion 105b, and there is no insulating layer between the drain electrode 107 and the second conductor sub-portion 105c, the source electrode 106 is connected to the first light shielding portion 110a through the anode 102; or, the drain electrode 107 is connected to the first light shielding portion 110a through the anode 102.
  • the first insulating layer further includes a second via hole, the second via hole is located at one side of the active layer 105, the buffer layer 111 includes a third via hole of the buffer layer 111, the third via hole is connected to the second via hole, the anode 102 is connected to the first light shielding portion 110a through the second via hole and the third via hole; the anode 102 includes a second connecting portion, and the orthographic projection of the pixel defining portion 103 on the substrate 101 covers the orthographic projection of the second connecting portion on the substrate 101.
  • the buffer layer 111 includes a buffer portion covering the first light shielding portion 110a, the second via hole penetrates the first insulating layer, the third via hole penetrates the buffer portion of the buffer layer 111, and the orthographic projection of the second via hole on the substrate 101 covers the orthographic projection of the third via hole on the substrate 101.
  • the second via hole and the third via hole expose the first light shielding portion 110a, and the second connecting portion contacts the first light shielding portion 110a.
  • the gate insulating layer 109 includes the first insulating portion, the second insulating portion, and the third insulating portion that are separated from each other, the gate insulating layer 109 includes a fourth via hole, the fourth via hole is located on a side of the second insulating portion away from the active layer 105, the buffer layer 111 includes a fifth via hole, the fifth via hole is located on the buffer layer 111, the fourth via hole is connected to the fifth via hole, and the source 106 is connected to the first light shielding portion 110a through the fourth via hole and the fifth via hole.
  • the buffer layer 111 includes a buffer portion covering the first light shielding portion 110a, the fourth via hole penetrates a side of the second insulating portion away from the active layer 105, the fifth via hole penetrates the buffer portion, and the orthographic projection of the fourth via hole on the substrate 101 covers the orthographic projection of the fifth via hole on the substrate 101.
  • the source 106 includes a source 106 connecting portion, which is located in the fourth via hole and the fifth via hole. The fourth via hole and the fifth via hole expose the first light shielding portion 110a. The source 106 connecting portion contacts the first light shielding portion 110a to achieve connection between the source 106 and the first light shielding portion 110a.
  • the gate insulating layer 109 when the gate insulating layer 109 includes the first insulating portion, the second insulating portion, and the third insulating portion that are separated from each other, the gate insulating layer 109 includes a sixth via hole, the sixth via hole penetrates the side of the third insulating portion away from the active layer 105, the buffer layer 111 includes a seventh via hole, the seventh via hole penetrates the buffer layer 111, the sixth via hole is connected to the seventh via hole, and the drain 107 is connected to the first light shielding portion 110a through the sixth via hole and the seventh via hole.
  • the sixth via hole penetrates the side of the third insulating portion away from the active layer 105
  • the seventh via hole penetrates the buffer portion
  • the orthographic projection of the sixth via hole on the substrate 101 covers the orthographic projection of the seventh via hole on the substrate 101.
  • the drain 107 includes a drain 107 connecting portion, which is located in the sixth via hole and the seventh via hole.
  • the sixth via hole and the seventh via hole expose the first light shielding portion 110a.
  • the drain 107 connecting portion contacts the first light shielding portion 110a to achieve connection between the drain 107 and the first light shielding portion 110a.
  • the display panel 100 includes a display area and a non-display area located at least on one side of the display area.
  • the display panel 100 also includes a terminal located in the non-display area. The terminal is located in the first metal layer 104 .
  • the non-display area has a plurality of terminals, including first-type terminals connected to the second metal layer 110.
  • the second metal layer 110 also includes second metal layer wirings, and the first-type terminals are connected to the second metal layer wirings.
  • the gate insulating layer 109 When the gate insulating layer 109 includes the first insulating portion, the second insulating portion and the third insulating portion which are separated from each other, the gate insulating layer 109 also includes a fourth insulating portion located between the terminal and the buffer layer 111, the gate insulating layer 109 also includes an eighth via hole, the eighth via hole penetrates the fourth insulating portion, the buffer layer 111 includes a ninth via hole, the ninth via hole penetrates the buffer layer 111 between the second metal layer routing and the fourth insulating portion, and the orthographic projection of the eighth via hole on the substrate 101 covers the orthographic projection of the ninth via hole on the substrate 101.
  • the first-type terminal includes a first-type terminal connection portion, the first-type terminal connection portion is located in the eighth via hole and the ninth via hole, the eighth via hole and the ninth via hole expose the second metal layer routing, and the first-type terminal connection portion is in contact with the second metal layer routing.
  • the buffer layer 111 includes a tenth via hole, the tenth via hole penetrates the buffer layer 111 between the second metal layer routing and the first type of terminal, the first type of terminal includes a first type of terminal connecting portion, the first type of terminal connecting portion is located in the tenth via hole, the tenth via hole exposes the second metal layer routing, and the first type of terminal connecting portion is in contact with the second metal layer routing.
  • the pixel definition portion 103 and the anode 102 have an overlapping portion, and the width of the orthographic projection of the overlapping portion on the substrate 101 is greater than 2 microns, so as to avoid exposure of the edge of the anode 102 due to process errors and to cover the first connection portion and/or the second connection portion.
  • the anode 102 has a central portion not covered by the pixel definition portion 103 and a peripheral portion covered by the pixel definition portion 103, and the orthographic projection of the peripheral portion on the substrate 101 coincides with the orthographic projection of the overlapping portion on the substrate 101.
  • the overlapping portion includes a first side close to the central portion and a second side away from the central portion, and the width of the orthographic projection of the overlapping portion on the substrate 101 is greater than 2 microns, that is, the minimum spacing between the first side and the second side is greater than 2 microns.
  • the spacing between adjacent anodes 102 is greater than 7 microns, so that the pixel definition parts 103 are spaced a sufficient distance apart while ensuring sufficient resolution, which helps to relieve the stress on the pixel definition parts 103 and improve the light output rate of the display panel 100.
  • the flat layer 113 is parallel to the substrate 101, the pixel definition part 103 is in direct contact with the flat layer 113, and the first angle ⁇ is equal to the angle formed by the first side surface 103a and the flat layer 113.
  • the first angle ⁇ is greater than or equal to 35 degrees, and the first angle ⁇ is less than or equal to 45 degrees.
  • the first angle ⁇ can be 36 degrees, 37 degrees, 38 degrees, 39 degrees, 40 degrees, 41 degrees, 42 degrees, 43 degrees, 44 degrees, etc.
  • the angle value of the first angle ⁇ is within the above range, so that the slope of the first side surface 103a is gentler, and when the height remains unchanged, the total surface area of the pixel definition part 103 is increased, which is conducive to increasing the contact area between the pixel definition part 103 and the adjacent film layer, and enhancing the firmness of the combination between the pixel definition part 103 and the adjacent film layer, so that the film layer of the display panel 100 is not easy to separate when applied to a bending scene, thereby improving the product quality of the display panel 100.
  • the display panel 100 further includes an organic layer 119 located on a side of the anode 102 away from the substrate 101, and the organic layer 119 includes a light-emitting layer 120.
  • the pixel definition portion 103 includes a second side surface 103b close to the anode 102, and the orthographic projection of the anode 102 on the substrate 101 and the orthographic projection of the second side surface 103b on the substrate 101 jointly cover the orthographic projection of the light-emitting layer 120 on the substrate 101.
  • the light-emitting layer 120 is located in the pixel definition opening, and the edge of the light-emitting layer 120 does not exceed the second side surface 103b.
  • the orthographic projection of the anode 102 on the substrate 101 and the orthographic projection of the second side surface 103b on the substrate 101 jointly cover the orthographic projection of the light-emitting layer 120 on the substrate 101, which is conducive to preventing light-emitting layers of different light-emitting colors (for example, red, green, and blue) from mixing outside the pixel definition portion 103, thereby affecting the display quality of the display panel 100.
  • the second side surface 103b has a second angle ⁇ with the anode 102 on the side close to the anode 102, and the second angle ⁇ is greater than or equal to 35 degrees, and the second angle ⁇ is less than or equal to 45 degrees.
  • the second angle ⁇ can be 36 degrees, 37 degrees, 38 degrees, 39 degrees, 40 degrees, 41 degrees, 42 degrees, 43 degrees, 44 degrees, etc.
  • the second side surface 103b is more gentle, which is conducive to the formation of the light-emitting layer 120 not exceeding the second side surface 103b.
  • the organic layer 119 includes a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer located in the pixel definition opening.
  • the hole injection layer is located on the side of the anode 102 away from the substrate 101, and the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer and the electron injection layer are stacked in sequence.
  • the display panel 100 further includes a cathode, and the cathode at least covers a side of the organic layer away from the substrate 101 .
  • the anode 102 , the cathode and the organic layer constitute a light-emitting element.
  • the embodiment of the present invention reduces the stress on the pixel definition portion 103 by arranging the pixel definition portion 103 and the anode 102 in a one-to-one correspondence and spacing adjacent pixel definition portions 103.
  • the slope of the first side surface 103a of the pixel definition portion 103 is gentler, thereby increasing the contact area between the pixel definition portion 103 and the adjacent film layer, enhancing the firmness of the connection between the pixel definition portion 103 and the adjacent film layer, and improving the product quality of the display panel 100.
  • an embodiment of the present invention further provides a method for manufacturing a display panel 100 , including:
  • the anode material layer and the pixel definition material layer are subjected to a first patterning process to form a plurality of anodes 102 and a plurality of pixel definition portions 103 , respectively.
  • the pixel definition part 103 covers the edge of the anode 102 and exposes part of the anode 102.
  • One pixel definition part 103 is arranged around one anode 102, and adjacent pixel definition parts 103 are arranged at intervals.
  • the pixel definition portion 103 includes a first side surface 103a away from the anode 102, and the first side surface 103a close to the substrate 101 has a first angle ⁇ with the substrate 101, and the first angle ⁇ is greater than or equal to 35 degrees, and the first angle ⁇ is less than or equal to 45 degrees.
  • the material of the substrate 101 has been described in detail in the aforementioned display panel 100 and will not be repeated here.
  • the anode material layer includes a material with a high work function.
  • the anode material layer includes one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), etc., and the above materials are conductive materials with relatively high work functions and transparency.
  • the anode material layer may also include reflective materials such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a combination thereof.
  • the anode material layer may be composed of a single layer or multiple layers of a transparent conductive material and/or a reflective conductive material.
  • the anode material layer may be a three-layer stack of IZO material layer/Ag material layer/IZO material layer formed by an IZO material layer and an Ag material layer.
  • the anode material layer may be formed by physical vapor deposition or chemical vapor deposition.
  • the material of the pixel definition material layer is selected from organic materials, such as positive photoresist materials or negative photoresist materials, so that the pixel definition material layer can be used as a photoresist.
  • the pixel definition portion 103 and the anode 102 are formed by the same patterning process, saving process technology and reducing process costs.
  • step S400 includes:
  • the first mask may be a half-tone mask.
  • the pixel definition material layer is developed to form a first photoresist region, a second photoresist region and a first non-photoresist region.
  • the thickness of the pixel definition material layer in the first photoresist area is greater than the thickness of the pixel definition material layer in the second photoresist area.
  • the first etching process can be a wet etching process.
  • a first etchant is used in the first etching process.
  • the first etchant includes phosphoric acid, nitric acid, etc., which is used to etch the Ag material layer and the IZO material layer.
  • the pixel definition material layer in the second photoresist region may be removed by an ashing process.
  • step S400 further includes:
  • the material, thickness, and structure of the anode 102 and the pixel defining portion 103 have been described in detail in the aforementioned display panel 100 and will not be repeated here.
  • step S200 the following steps are included:
  • the material, thickness, structure, etc. of the second metal layer 110 have been described in detail in the aforementioned display panel 100 and will not be repeated here.
  • the buffer material layer 115 covers the second metal layer 110 and the substrate 101 .
  • the material, thickness, structure, etc. of the passivation layer 112 and the planar layer 113 have been described in detail in the aforementioned display panel 100 and will not be repeated here.
  • the passivation material layer covers the thin film transistor layer, and the planarization material layer covers the passivation material layer.
  • the planarization material layer is made of a positive photoresist material or a negative photoresist material.
  • step S700 includes:
  • Step S710 includes:
  • the semiconductor material layer 116 and the first metal material layer 117 are subjected to a second patterning process to form a semiconductor layer 114 and a first metal layer 104 , respectively.
  • the first metal layer 104 includes a source electrode 106 and a drain electrode 107 .
  • the source electrode 106 and the drain electrode 107 are respectively located on two opposite sides of the semiconductor layer 114 .
  • Step S713 includes:
  • the second mask Mask may be a half-tone mask.
  • the first photoresist material layer 118 forms a third photoresist region, a fourth photoresist region and a second non-photoresist region.
  • the thickness of the first photoresist material layer 118 in the third photoresist region is greater than the thickness of the first photoresist material layer 118 in the fourth photoresist region.
  • the second etching process may be a wet etching process.
  • the third etching process can be a wet etching process.
  • a second etchant is used in the third etching process.
  • the second etchant does not contain fluorine elements to avoid damaging the semiconductor layer 114.
  • the second etchant includes components such as hydrogen peroxide and is used for the first metal material layer.
  • Step S720 includes:
  • the gate insulating material layer and the gate material layer are subjected to a third patterning process to form the gate insulating layer 109 and the gate 108 .
  • Step S723 includes:
  • the fourth etching process may be a wet etching process.
  • the fifth etching process may be a dry etching process.
  • the conductorization treatment may be performed by ion implantation or plasma bombardment to form the active layer 105 .
  • the active layer 105 includes a channel portion 105 a and a first conductor sub-portion 105 b and a second conductor sub-portion 105 c respectively located at opposite sides of the channel portion 105 a .
  • the materials, thicknesses, and structures of the gate insulating layer 109 , the first metal layer 104 , and the active layer 105 have been described in detail in the aforementioned display panel 100 , and will not be described again herein.
  • step S800 when the thin film transistor layer is formed through steps S710 to S730 , step S800 includes:
  • Step S810 includes:
  • the third photoresist material layer is developed to form a sixth photoresist region and a fourth non-photoresist region.
  • the fourth non-light-resistance region includes a first non-light-resistance sub-region and a second non-light-resistance sub-region.
  • the sixth etching process may be a dry etching process.
  • Step S820 includes:
  • the planar material layer is developed to form a first planar layer 113 via hole and a second planar layer 113 via hole.
  • the planar layer 113 and the passivation layer 112 form a first insulating layer, the first planar layer 113 via hole and the passivation material layer corresponding to the first non-light-resistance sub-region are removed to form a first via hole H1 of the first insulating layer, and the anode 102 is connected to the source 106 or the drain 107 through the first via hole H1.
  • the second planar layer 113 via hole and the passivation material layer corresponding to the second non-light-resistance sub-region are removed to form a second via hole of the first insulating layer, and the buffer material layer 115 corresponding to the second non-light-resistance sub-region is removed to form a third via hole, the third via hole is connected to the second via hole, and the anode 102 is connected to the first light shielding portion 110a in the second metal layer 110 through the second via hole and the third via hole.
  • the passivation material layer corresponding to the first non-photoresistor sub-region is removed to expose the source 106 or the drain 107. Due to the removal of the passivation material layer corresponding to the first non-photoresistor sub-region and the removal of the passivation material layer and the buffer material layer 115 corresponding to the second non-photoresistor sub-region, the source 106 or the drain 107 is over-etched. The dry etching causes slight damage to the metal material. Therefore, the passivation layer 112 and the buffer layer 111 can be formed by the same etching process, thereby reducing the process cost.
  • step S700 includes:
  • step S740 includes:
  • the semiconductor material layer is subjected to a fourth patterning process to form the semiconductor layer 114 .
  • Step S742 includes:
  • the fourth photoresist material layer is developed to form a seventh photoresist region and a fifth non-photoresist region.
  • the seventh etching process may be a wet etching process.
  • Step S750 includes:
  • the gate insulating material layer is subjected to a fifth patterning process to form the semiconductor layer 114 .
  • Step S752 includes:
  • the sixth non-light-resistance region includes a third non-light-resistance sub-region, a fourth non-light-resistance sub-region, and a fourth non-light-resistance sub-region.
  • the eighth etching process may be a dry etching process.
  • the gate insulating layer 109 includes a first insulating portion, a second insulating portion and a third insulating portion.
  • the gate insulating material layer and the buffer layer 111 corresponding to the third non-light-resistance sub-region, the fourth non-light-resistance sub-region and the fifth non-light-resistance sub-region are removed to form a first opening, a second opening and a fourth via hole or a sixth via hole of the gate insulating layer 109, and a fifth via hole or a seventh via hole of the buffer layer 111, respectively.
  • the fourth via is located on a side of the second insulating portion away from the active layer 105
  • the buffer layer 111 includes a fifth via
  • the fourth via is connected to the fifth via
  • the source 106 is connected to the first light shielding portion 110a of the second metal layer 110 through the fourth via and the fifth via
  • the sixth via is located on a side of the third insulating portion away from the active layer 105
  • the buffer layer 111 includes a seventh via
  • the sixth via is connected to the seventh via
  • the drain 107 is connected to the first light shielding portion 110a through the sixth via and the seventh via.
  • the semiconductor layer 114 forms an active layer 105 .
  • the semiconductor layer 114 is conductively processed by using the first opening and the second opening to form the active layer 105 .
  • the conductorization treatment may be performed by ion implantation or plasma bombardment.
  • the first metal layer 104 includes the source 106 , the drain 107 , and the gate 108 .
  • Step S770 includes:
  • the first metal material layer is subjected to a sixth patterning process to form the first metal layer 104 .
  • Step S772 includes:
  • the ninth light-blocking region includes a first light-blocking sub-region, a second light-blocking sub-region, and a third light-blocking sub-region.
  • the first metal material layer corresponding to the first photoresistance sub-region, the second photoresistance sub-region, and the third photoresistance sub-region respectively forms the source 106 , the drain 107 , and the gate 108 .
  • the ninth etching process may be a wet etching process.
  • the materials, thicknesses, and structures of the gate insulating layer 109 , the first metal layer 104 , and the active layer 105 have been described in detail in the aforementioned display panel 100 , and will not be described again herein.
  • step S800 when the thin film transistor layer is formed through steps S740 to S770 , step S800 includes:
  • Step S830 includes:
  • the material of the planar material layer is selected from positive photoresist material or negative photoresist material.
  • the passivation material layer and the planar material layer are subjected to a seventh patterning process to form the passivation layer 112 and the planar layer 113 .
  • Step S834 includes:
  • the tenth etching process may be a dry etching process.
  • the planar layer 113 and the passivation layer 112 form a first insulating layer.
  • the eighth non-photoresistive region and the passivation material layer corresponding to the eighth non-photoresistive region are removed to form a first via hole H1 in the first insulating layer.
  • the anode 102 is connected to the first metal layer 104 through the first via hole H1.
  • step S500 may include:
  • the second metal material layer is subjected to an eighth patterning process to form the second metal layer 110 .
  • Step S520 includes:
  • the eleventh etching process may be a wet etching process.
  • the film layer between the substrate 101 and the pixel definition portion 103 only needs to undergo six patterning processes, thereby reducing the process cost and improving the process efficiency.
  • the pixel definition portion 103 and the anode 102 are arranged in a one-to-one correspondence, and adjacent pixel definition portions 103 are spaced apart, thereby reducing the stress on the pixel definition portion 103, and the first side surface 103a of the pixel definition portion 103 has a gentler slope, thereby increasing the contact area between the pixel definition portion 103 and the adjacent film layer, enhancing the firmness of the bonding between the pixel definition portion 103 and the adjacent film layer, and improving the product quality of the manufactured display panel.
  • An embodiment of the present invention discloses a display panel and a method for manufacturing the same;
  • the display panel includes a substrate, a plurality of anodes located on the substrate, and a plurality of pixel definition parts covering the edges of the anodes and exposing parts of the anodes, wherein a pixel definition part is arranged around an anode, and adjacent pixel definition parts are arranged at intervals, and along a direction parallel to the substrate, the pixel definition part includes a first side surface away from the anode, and a side of the first side surface close to the substrate has a first angle with the substrate, the first angle is greater than or equal to 35 degrees, and the first angle is less than or equal to 45 degrees.
  • the present invention reduces the stress on the pixel definition part by arranging the pixel definition part and the anode in a one-to-one correspondence, and the adjacent pixel definition parts are spaced apart, and the slope of the first side surface of the pixel definition part is gentler, thereby increasing the contact area between the pixel definition part and the adjacent film layer, enhancing the firmness of the combination between the pixel definition part and the adjacent film layer, and improving the product quality of the display panel.

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Abstract

本发明实施例公开了一种显示面板及其制作方法；该显示面板包括衬底、位于衬底上的多个阳极、覆盖阳极的边缘的多个间隔设置的像素定义部，一像素定义部环绕一阳极设置，沿平行于衬底的方向，像素定义部包括远离阳极的第一侧面，第一侧面靠近衬底的一侧与衬底具有第一夹角，第一夹角大于或等于35度且小于或等于45度。

Description

显示面板及其制作方法 技术领域
本发明涉及显示领域，具体涉及一种显示面板及其制作方法。
 背景技术
随着显示技术的发展，OLED(Organic Light‑Emitting Diode，有机发光二极管)显示面板因具有亮度高、功耗低、响应快、清晰度高、发光效率高等优点得到了广泛的应用。
然而，OLED显示面板中采用的在整层形成的像素定义层中开口，从而在开口内形成发光元件，像素定义层存在应力难以释放，导致显示面板质量受影响的技术问题。
因此，亟需一种显示面板及其制作方法以解决上述技术问题。
 发明概述
本发明提供一种显示面板及其制作方法，可以缓解目前显示面板整层形成像素定义层导致的应力难以释放，从而影响显示面板的产品质量的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本发明提供一种显示面板，包括：
衬底；
多个阳极，位于所述衬底上；
多个像素定义部，所述像素定义部覆盖所述阳极的边缘并裸露部分所述阳极；
其中，一所述像素定义部环绕一所述阳极设置，相邻所述像素定义部间隔设置；
沿平行于所述衬底的方向，所述像素定义部包括远离所述阳极的第一侧面，所述第一侧面靠近所述衬底的一侧与所述衬底具有第一夹角，所述第一夹角大于或等于35度，所述第一夹角小于或等于45度。
优选的，所述显示面板还包括第一金属层，所述第一金属层位于所述阳极与所述衬底之间；
所述显示面板还包括第一绝缘层，所述第一绝缘层位于所述第一金属层与所述阳极之间，所述第一绝缘层包括第一过孔，所述阳极包括位于所述第一过孔内的第一连接部，所述第一连接部与所述第一金属层连接，所述像素定义部覆盖所述第一连接部。
优选的，所述显示面板还包括有源层，所述有源层位于所述第一金属层与所述衬底之间，所述有源层包括沟道部以及分别位于所述沟道部相对两侧的第一导体子部及第二导体子部；
所述第一金属层包括源极及漏极，所述源极位于所述第一导体子部上，所述漏极位于所述第二导体子部上；
其中，至少部分所述源极靠近所述有源层的一侧与所述第一导体子部接触，至少部分所述漏极靠近所述有源层的一侧与所述第二导体子部接触。
优选的，所述显示面板还包括栅极，所述栅极位于所述源极与所述漏极之间，所述栅极在所述有源层上的正投影覆盖所述沟道部；
所述显示面板还包括栅极绝缘层，所述栅极绝缘层至少间隔于所述栅极与所述沟道部之间。
优选的，所述栅极位于所述第一金属层，所述栅极绝缘层包括相离设置的第一绝缘部、第二绝缘部及第三绝缘部，所述第一绝缘部间隔于所述沟道部与所述栅极之间，所述第二绝缘部间隔于部分所述源极与所述第一导体子部之间，所述第三绝缘部间隔于部分所述漏极与所述第二导体子部之间；
所述源极靠近所述栅极的一端与所述第一导体子部接触，所述漏极靠近所述栅极的一端与所述第二导体子部接触。
优选的，所述栅极位于所述第一金属层远离所述衬底的一侧，所述源极与所述第一导体子部之间无绝缘层，所述漏极与所述第二导体子部之间无绝缘层。
优选的，在平行于所述衬底的平面内，沿所述沟道部至所述第一导体子部的方向，所述源极远离所述栅极的一侧边缘超出所述第一导体子部远离所述沟道部的一侧边缘；
在平行于所述衬底的平面内，沿所述沟道部至所述第二导体子部的方向，所述漏极远离所述栅极的一侧边缘超出所述第二导体子部远离所述沟道部的一侧边缘。
优选的，所述显示面板还包括位于第二金属层，所述第二金属层位于所述有源层与所述衬底之间，所述第二金属层包括第一遮光部，所述有源层在所述衬底上的正投影位于所述第一遮光部在所述衬底上的正投影内；
所述显示面板还包括缓冲层，所述缓冲层位于所述有源层靠近所述衬底的一侧，所述缓冲层覆盖所述第二金属层。
优选的，所述第一绝缘层包括靠近所述衬底一侧的钝化层，所述缓冲层间隔于所述第二金属层与所述有源层之间，所述缓冲层远离所述衬底的一侧与所述有源层及所述钝化层直接接触；
所述缓冲层靠近所述衬底的一侧与所述第二金属层及所述衬底直接接触。
优选的，当所述栅极绝缘层包括相离设置的第一绝缘部、第二绝缘部及第三绝缘部时，所述第二绝缘部远离所述第一绝缘部的一端与所述缓冲层接触，所述第三绝缘部远离所述第一绝缘部的一端与所述缓冲层接触。
优选的，所述第一绝缘层还包括第二过孔，所述第二过孔位于有源层的一侧；
所述缓冲层包括第三过孔，所述第三过孔与所述第二过孔相连通，所述阳极与所述第一遮光部通过所述第二过孔及所述第三过孔连接；
所述阳极包括第二连接部，所述像素定义部在所述衬底上的正投影覆盖所述第二连接部在所述衬底上的正投影。
优选的，栅极绝缘层包括第四过孔，所述第四过孔位于第二绝缘部远离有源层的一侧，所述缓冲层包括第五过孔，所述第四过孔与所述第五过孔相连通，源极与所述第一遮光部通过所述第四过孔及所述第五过孔连接。
优选的，栅极绝缘层包括第六过孔，所述第六过孔位于第三绝缘部远离所述有源层的一侧，所述缓冲层包括第七过孔，所述第六过孔与所述第七过孔相连通，漏极与所述第一遮光部通过所述第六过孔及所述第七过孔连接。
优选的，所述显示面板包括显示区及位于所述显示区至少一侧的非显示区，所述显示面板还包括位于所述非显示区内的端子，所述端子位于所述第一金属层；
其中，所述端子包括第一类端子，所述第一类端子与所述第二金属层连接。
优选的，当栅极绝缘层包括相离设置的所述第一绝缘部、所述第二绝缘部及所述第三绝缘部时，所述栅极绝缘层还包括位于所述端子与缓冲层之间的第四绝缘部，所述栅极绝缘层还包括第八过孔，所述第八过孔贯穿所述第四绝缘部，所述缓冲层包括第九过孔，所述第九过孔贯穿所述第二金属层走线与所述第四绝缘部之间的所述缓冲层，所述第八过孔在所述衬底上的正投影覆盖所述第九过孔在所述衬底上的正投影；
所述第一类端子包括第一类端子连接部，所述第一类端子连接部位于所述第八过孔及所述第九过孔内，所述第八过孔及所述第九过孔裸露所述第二金属层走线，所述第一类端子连接部与所述第二金属层走线接触。
优选的，所述像素定义部与所述阳极具有重叠部，所述重叠部在所述衬底上的正投影的宽度大于2微米。
优选的，所述显示面板还包括位于所述阳极远离所述衬底一侧的有机层，所述有机层包括发光层；
沿平行于所述衬底的方向，所述像素定义部包括靠近所述阳极的第二侧面，所述阳极在所述衬底上的正投影及所述第二侧面在所述衬底上的正投影共同覆盖所述发光层在所述衬底上的正投影。
优选的，所述第二侧面靠近所述阳极的一侧与所述阳极具有第二夹角，所述第二夹角大于或等于35度，所述第二夹角小于或等于45度。
本发明还提供一种显示面板的制作方法，包括：
提供一衬底；
在所述衬底上形成阳极材料层；
在所述阳极材料层上形成像素定义材料层；
所述阳极材料层及所述像素定义材料层经第一图案化处理分别形成多个阳极及多个像素定义部；
其中，所述像素定义部覆盖所述阳极的边缘并裸露部分所述阳极，一所述像素定义部环绕一所述阳极设置，相邻所述像素定义部间隔设置。
优选的，所述在所述衬底上形成阳极材料层之前，还包括：
在所述衬底上形成半导体材料层；
在所述半导体材料层上形成第一金属材料层，所述第一金属材料层与所述半导体材料层直接接触；
所述半导体材料层及所述第一金属材料层经第二图案化处理分别形成半导体层及第一金属层；
其中，所述第一金属层包括源极及漏极，所述源极及所述漏极分别位于所述半导体层的相对两侧。
有益效果
本发明通过将像素定义部与阳极一一对应设置，相邻像素定义部间隔，减少了像素定义部所受应力，并且像素定义部的第一侧面坡度更缓，增大了像素定义部与相邻膜层之间的接触面积，增强了像素定义部与相邻膜层之间结合的牢固程度，改善了显示面板的产品质量。
 附图说明
图1是本发明实施例提供的显示面板的第一种结构的结构示意图；
图2是本发明实施例提供的显示面板的第二种结构的结构示意图；
图3是本发明实施例提供的显示面板的制作方法的步骤流程图；
图4a至图4m是本发明实施例提供的显示面板的制作方法的一种流程示意图。
 本发明的实施方式
本申请提供一种显示模组，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
目前，显示面板中的像素定义层整成形成，存在像素定义层的应力难以释放，导致显示面板质量受影响的技术问题。
请参阅图1及图2，本发明实施例提供一种显示面板100，包括：
衬底101；
多个阳极102，位于所述衬底101上；
多个像素定义部103，所述像素定义部103覆盖所述阳极102的边缘并裸露部分所述阳极102；
其中，一所述像素定义部103环绕一所述阳极102设置，相邻所述像素定义部103间隔设置；
沿平行于所述衬底101的方向，所述像素定义部103包括远离所述阳极102的第一侧面103a，所述第一侧面103a靠近所述衬底101的一侧与所述衬底101具有第一夹角α，所述第一夹角α大于或等于35度，所述第一夹角α小于或等于45度。
本发明实施例通过将像素定义部103与阳极102一一对应设置，相邻像素定义部103间隔，减少了像素定义部103所受应力，并且像素定义部103的第一侧面103a坡度更缓，增大了像素定义部103与相邻膜层之间的接触面积，增强了像素定义部103与相邻膜层之间结合的牢固程度，改善了显示面板100的产品质量。
现结合具体实施例对本发明的技术方案进行描述。
请参阅图1及图2，本实施例中，所述显示面板100还包括第一金属层104，所述第一金属层104位于所述阳极102与所述衬底101之间。
所述显示面板100还包括第一绝缘层，所述第一绝缘层位于所述第一金属层104与所述阳极102之间，所述第一绝缘层包括第一过孔H1，所述阳极102包括位于所述第一过孔H1内的第一连接部，所述第一连接部与所述第一金属层104连接，所述像素定义部103覆盖所述第一连接部。
在一些实施例中，所述第一金属层104可以为低电阻材料如Al、Ti、Mo、Cu、Ni、或包括上述金属的合金形成的多个层或单层，例如，所述第一金属层104可以为钼钛合金、铜形成的钼钛合金/铜/钼钛合金(MoTi/Cu/MoTi)三层叠层结构。
当所述第一金属层104为MoTi层、Cu层、MoTi层形成的MoTi/Cu/MoTi三层叠层结构时，靠近所述衬底101一侧的MoTi层的厚度为250埃米至350埃米，Cu层的厚度为4200埃米至6500埃米，远离所述衬底101一侧的MoTi层的厚度为400埃米至500埃米。
在一些实施例中，所述阳极102包括具有高功函数的材料。所述阳极102包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In 2O 3)等中的一种，上述材料为具有相对高的功函数并且透明的导电材料。除了以上列出的导电材料之外，所述阳极102还可以包括诸如银(Ag)、镁(Mg)、铝(Al)、铂(Pt)、钯(Pb)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、锂(Li)、钙(Ca)或者它们的组合的反射材料。所述阳极102可以由透明导电材料和/或反射性导电材料的单层或多层组成。例如，所述阳极102可以是IZO、Ag形成的IZO/Ag/IZO三层叠构。此时，靠近所述衬底101一侧的IZO层的厚度可以为100埃米至200埃米，Ag层的厚度为1000埃米至1500埃米，远离所述衬底101一侧的IZO层的厚度可以为700埃米至1000埃米。
请参阅图1及图2，本实施例中，所述像素定义部103环绕所述阳极102设置并具有像素定义开口，所述像素定义开口裸露所述阳极102。
在一些实施例中，所述像素定义部103的材料选自有机材料，如正性光阻材料或负性光阻材料，以便于利用所述像素定义部103的材料作为光阻，所述像素定义部103和所述阳极102经同一图案化处理形成，节省制程工艺、降低制程成本。所述像素定义部103的厚度可以为2.8微米至3.7微米，例如，可以为3微米、3.2微米、3.4微米、3.5微米、3.6微米等，以便于形成足够深的所述像素定义开口。
在一些实施例中，所述第一绝缘层包括靠近所述衬底101一侧的钝化层112及远离所述衬底101一侧的平坦层113，所述钝化层112至少覆盖所述第一金属层104，所述平坦层113起到为所述阳极102的形成提供平坦表面的作用，所述阳极102可以直接形成与所述平坦层113远离所述衬底101的一侧。进一步的，所述第一绝缘层可以由所述钝化层112及所述平坦层113组成。
所述钝化层112的材料选自无机材料，如氮硅化合物或氧硅化合物等。所述平坦层113的材料可以选自有机材料，如正性光阻材料或负性光阻材料等，以便于所述钝化层112和所述平坦层113通过一次图案化处理形成，节省制程工艺、降低制程成本。
所述钝化层112的厚度为3500埃米至5000埃米，例如，可以为3600埃米、3800埃米、4000埃米、4200埃米、4500埃米、4800埃米等，以便于完全覆盖所述第一金属层104；所述平坦层113的厚度为3500埃米至5000埃米，例如，可以为3600埃米、3800埃米、4000埃米、4200埃米、4500埃米、4800埃米等，以便于提供平坦表面。
所述第一过孔H1暴露所述第一金属层104，所述阳极102包括位于所述第一过孔H1内的第一连接部，所述第一连接部于所述第一过孔H1内与所述第一金属层104接触，从而实现所述阳极102与所述第一金属层104的连接。由于所述第一连接部填充于所述第一过孔H1内以便于连接所述第一金属层104，为避免在所述阳极102上形成的有机层(如发光层)等落入所述第一过孔H1内，所述像素定义部103覆盖所述第一过孔H1。
当所述第一绝缘层由所述钝化层112及所述平坦层113组成时，所述第一过孔H1包括位于所述钝化层112的第一子过孔及位于所述平坦层113内的第二子过孔。
在一些实施例中，所述衬底101可以为硬质衬底或柔性衬底，当所述衬底101为硬质衬底时，所述衬底101可以为玻璃衬底；当所述衬底101为柔性衬底时，所述衬底101的材料可以为聚酰亚胺。
请参阅图1及图2，本实施例中，所述第一金属层104包括源极106和漏极107，所述第一过孔H1裸露所述源极106，所述第一连接部与所述源极106接触；或者，所述第一金属层104裸露所述漏极107，所述第一连接部与所述漏极107接触。
请参阅图1及图2，本实施例中，所述显示面板100还包括有源层105，所述有源层105位于所述第一金属层104与所述衬底101之间，所述有源层105包括沟道部105a以及分别位于所述沟道部105a相对两侧的第一导体子部105b及第二导体子部105c。
所述源极106位于所述第一导体子部105b上，所述漏极107位于所述第二导体子部105c上。
其中，至少部分所述源极106靠近所述有源层105的一侧与所述第一导体子部105b接触，至少部分所述漏极107靠近所述有源层105的一侧与所述第二导体子部105c接触。
在一些实施例中，所述有源层105的材料可以选自导电的氧化物材料，例如：铟镓锌氧化物(IGZO)等。所述有源层105的形成过程中，可以通过离子注入或等离子轰击等方式完成所述第一导体子部105b及所述第二导体子部105c的导体化。采用离子注入的方式，掺杂特定元素或粒子包含但不限于H、He、B、Al、N、F、P、Ar、S等；采用等离子轰击导体化方式是通过高能粒子对有源层105材料表面的轰击，形成缺陷(氧空位)，氧空位可以产生载流子从而增加导电特性，实现所述第一导体子部105b及所述第二导体子部105c的导体化。
在一些实施例中，所述有源层105的材料可以选自多晶硅。
本实施例中，所述有源层105的厚度可以为200埃米至500埃米，例如，可以为250埃米、300埃米、350埃米、400埃米、450埃米等。
请参阅图1及图2，本实施例中，所述显示面板100还包括栅极108，所述栅极108位于所述有源层105远离所述衬底101的一侧，所述栅极108位于所述源极106与所述漏极107之间，所述栅极108在所述有源层105上的正投影覆盖所述沟道部105a。
本实施例中，所述显示面板100还包括栅极绝缘层109，所述栅极绝缘层109位于所述栅极108靠近所述有源层105的一侧，所述栅极绝缘层109至少间隔于所述栅极108与所述沟道部105a之间。所述平坦层113覆盖所述栅极绝缘层109、所述第一金属层104和/或所述栅极108。
在一些实施例中，所述栅极108的材料可以选自低电阻材料如Al、Ti、Mo、Cu、Ni、或包括以上金属的合金，所述栅极108可以为上述金属或合金形成的单层或多层结构。
请参阅图1，在一些实施例中，所述栅极108位于所述第一金属层104，所述源极106、所述漏极107、所述栅极108可以使用同材料在同工序中形成，有利于节省制程工艺、降低制程成本。
在一些实施例中，所述栅极绝缘层109的材料选自硅氮化合物、硅氧化合物中的至少一种。所述栅极绝缘层109可以为硅氮化合物或硅氧化合物形成的一层或多层，例如，所述栅极绝缘层109可以为硅氧化物形成的单层结构。
所述栅极绝缘层109的厚度为1000埃米至2000埃米，例如，可以为1200埃米、1500埃米、1800埃米等。
在一些实施例中，所述栅极绝缘层109包括相离设置的第一绝缘部、第二绝缘部及第三绝缘部，所述第一绝缘部间隔于所述沟道部105a与所述栅极108之间，所述第二绝缘部间隔于部分所述源极106与所述第一导体子部105b之间，所述第三绝缘部间隔于部分所述漏极107与所述第二导体子部105c之间。
第一绝缘部、第二绝缘部及第三绝缘部相离设置，即，三者在所述衬底101上的正投影相互分离；所述第一绝缘部与所述第二绝缘部之间断开，所述第一绝缘部与所述第三绝缘部之间断开。所述栅极绝缘层109包括位于所述第一绝缘部与所述第二绝缘部之间的第一开口，所述栅极绝缘层109包括位于所述第一绝缘部与所述第三绝缘部之间的第二开口。
所述第一绝缘部间隔于所述沟道部105a与所述栅极108之间，即，沿所述衬底101至所述第一金属层104的方向，所述沟道部105a与所述栅极108分别位于所述第一绝缘部的两侧。所述栅极108靠近所述第一绝缘部的一侧与所述第一绝缘部直接接触，所述第一绝缘部靠近所述有源层105的一侧与所述沟道部105a直接接触。所述栅极108在所述衬底101上的正投影位于所述第一绝缘部在所述衬底101上的正投影内，所述沟道部105a在所述衬底101上的正投影位于所述第一绝缘部在所述衬底101上的正投影内。
所述第二绝缘部间隔于部分所述源极106与所述第一导体子部105b之间，所述第二绝缘部靠近所述衬底101的一侧与所述第一导体子部105b远离所述沟道部105a的一端直接接触，所述第二绝缘部至少覆盖部分所述第一导体子部105b远离所述沟道部105a的一端，所述源极106靠近所述栅极108的一端通过所述第一开口与所述第一导体子部105b接触，所述源极106靠近所述栅极108的一端覆盖所述第二绝缘部靠近所述第一绝缘部的一端。
所述第三绝缘部间隔于部分所述源极106与所述第二导体子部105c之间，所述第三绝缘部靠近所述衬底101的一侧与所述第二导体子部105c远离所述沟道部105a的一端直接接触，所述第三绝缘部至少覆盖部分所述第二导体子部105c远离所述沟道部105a的一端，所述漏极107靠近所述栅极108的一端通过所述第二开口与所述第二导体子部105c接触，所述漏极107靠近所述栅极108的一端覆盖所述第三绝缘部靠近所述第一绝缘部的一端。
请参阅图2，在一些实施例中，所述源极106与所述第一导体子部105b之间无绝缘层，所述漏极107与所述第二导体子部105c之间无绝缘层。即，所述源极106直接位于所述第一导体子部105b上，所述漏极107直接位于所述第二导体子部105c上，有利于所述第一金属层104与所述有源层105经过一次图案化处理形成，便于简化制程工艺，降低制程成本。
当所述源极106与所述第一导体子部105b之间无绝缘层，所述漏极107与所述第二导体子部105c之间无绝缘层时，所述栅极108位于所述第一金属层104远离所述衬底101的一侧，所述栅极绝缘层109间隔于所述沟道部105a与所述栅极108之间。所述栅极108在所述衬底101上的正投影位于所述栅极绝缘层109在所述衬底101上的正投影内，所述沟道部105a在所述衬底101上的正投影位于所述栅极绝缘层109在所述衬底101上的正投影内。此时，所述栅极108的材料可以为Cu层和MoTi合金层组成的双层结构，其中，Cu层位于所述栅极108中靠近所述衬底101的一侧，MoTi合金层位于所述栅极108中远离所述衬底101的一侧。Cu层的厚度为1800埃米至4200埃米，例如，可以为1900埃米、2500埃米、3000埃米、3500埃米、4000埃米等。MoTi合金层的厚度为250埃米至350埃米，例如，可以为280埃米、300埃米、320埃米、340埃米等。
当所述源极106与所述第一导体子部105b之间无绝缘层，所述漏极107与所述第二导体子部105c之间无绝缘层时，在平行于所述衬底101的平面内，沿所述沟道部105a至所述第一导体子部105b的方向，所述源极106远离所述栅极108的一侧边缘超出所述第一导体子部105b远离所述沟道部105a的一侧边缘；在平行于所述衬底101的平面内，沿所述沟道部105a至所述第二导体子部105c的方向，所述漏极107远离所述栅极108的一侧边缘超出所述第二导体子部105c远离所述沟道部105a的一侧边缘。
本实施例中，所述栅极108、所述源极106、所述漏极107、所述有源层105组成所述显示面板100的薄膜晶体管器件。
请参阅图1及图2，本实施例中，所述显示面板100还包括位于第二金属层110，所述第二金属层110位于所述有源层105与所述衬底101之间，所述第二金属层110包括第一遮光部110a，所述有源层105在所述衬底101上的正投影位于所述第一遮光部110a在所述衬底101上的正投影内。所述第一遮光部110a的设置，有利于避免来自所述衬底101的光线照射至所述有源层105，从而影响所述有源层105的工作性能。
在一些实施例中，所述第二金属层110的材料可以选自金属材料，如Al、Ti、Mo、Cu、Ni、或包括上述金属的合金。所述第二金属层110可以为上述金属材料或包括上述金属材料的合金形成的单层或多层。例如，所述第二金属层110可以为MoTi合金层、Cu层形成MoTi/Cu的双层叠构，MoTi合金层位于靠近所述衬底101的一侧，Cu层位于远离所述衬底101的一侧。将所述第二金属层110设置为MoTi/Cu，结合MoTi的遮光性能与Cu的导电性能，在实现遮光的同时，有利于保持所述第二金属层110中的走线的导电性。优选的，MoTi合金层的厚度可以为250埃米至350埃米，例如，可以为280埃米、300埃米、320埃米、340埃米等；Cu层的厚度可以为2800埃米至8000埃米，例如，可以为2900埃米、3000埃米、3500埃米、4000埃米、4500埃米、5000埃米、5500埃米、6000埃米、6500埃米、7000埃米、7500埃米等。
所述显示面板100还包括缓冲层111，所述缓冲层111位于所述有源层105靠近所述衬底101的一侧，所述缓冲层111覆盖所述第二金属层110。
所述缓冲层111间隔于所述第二金属层110与所述有源层105之间，所述缓冲层111远离所述衬底101的一侧与所述有源层105直接接触，所述缓冲层111远离所述衬底101的一侧与钝化层112直接接触。
在一些实施例中，所述缓冲层111靠近所述衬底101的一侧与所述第二金属层110直接接触，所述缓冲层111靠近所述衬底101的一侧与所述衬底101直接接触。
在一些实施例中，所述缓冲层111的材料选自硅氮化合物、硅氧化合物中的至少一种。所述缓冲层111可以为硅氮化合物或硅氧化合物形成的单层或叠层。例如，所述缓冲层111可以包括第一缓冲子层和第二缓冲子层，所述第一缓冲子层的材料为硅氮化合物，所述第二缓冲子层的材料为硅氧化合物，所述第一缓冲子层位于所述缓冲层111中靠近所述衬底101一侧，所述第二缓冲子层位于所述缓冲层111中远离所述衬底101一侧。所述第一缓冲子层的厚度为500埃米至2000埃米，例如，可以为800埃米、1000埃米、1200埃米、1500埃米、1800埃米等；所述第二缓冲子层的厚度为2000埃米至3000埃米，例如，可以为2200埃米、2500埃米、2600埃米、2800埃米等。
当所述栅极绝缘层109包括相离设置的所述第一绝缘部、所述第二绝缘部及所述第三绝缘部时，所述第二绝缘部远离所述第一绝缘部的一端与所述缓冲层111接触，所述第三绝缘部远离所述第一绝缘部的一端与所述缓冲层111接触。
在一些实施例中，所述第一遮光部110a与所述源极106连接；或者，所述第一遮光部110a与所述漏极107连接。所述第一遮光部110a与所述源极106或所述漏极107的连接，避免所述第一遮光部110a造成的所述薄膜晶体管器件的电性漂移，从而改善所述薄膜晶体管器件工作性能。
请参阅图2，当所述栅极108位于所述第一金属层104远离所述衬底101的一侧，所述源极106与所述第一导体子部105b之间无绝缘层，所述漏极107与所述第二导体子部105c之间无绝缘层时，所述源极106与所述第一遮光部110a通过所述阳极102连接；或者，所述漏极107与所述第一遮光部110a通过所述阳极102连接。此时，所述第一绝缘层还包括第二过孔，所述第二过孔位于有源层105的一侧，所述缓冲层111包括所述缓冲层111的第三过孔，所述第三过孔与所述第二过孔相连通，所述阳极102与所述第一遮光部110a通过所述第二过孔及所述第三过孔连接；所述阳极102包括第二连接部，所述像素定义部103在所述衬底101上的正投影覆盖所述第二连接部在所述衬底101上的正投影。具体的，所述缓冲层111包括覆盖所述第一遮光部110a的缓冲部，所述第二过孔贯穿所述第一绝缘层，所述第三过孔贯穿所述缓冲层111的所述缓冲部，所述第二过孔在所述衬底101上的正投影覆盖所述第三过孔在所述衬底101上的正投影。所述第二过孔及所述第三过孔暴露所述第一遮光部110a，所述第二连接部与所述第一遮光部110a接触。当所述阳极102与所述源极106连接时，所述源极106与所述第一遮光部110a通过所述阳极102连接；当所述阳极102与所述漏极107连接时，所述漏极107与所述第一遮光部110a通过所述阳极102连接。
当所述栅极绝缘层109包括相离设置的所述第一绝缘部、所述第二绝缘部及所述第三绝缘部时，所述栅极绝缘层109包括第四过孔，所述第四过孔位于第二绝缘部远离有源层105的一侧，所述缓冲层111包括第五过孔，所述第五过孔位于所述缓冲层111，所述第四过孔与所述第五过孔相连通，所述源极106与所述第一遮光部110a通过所述第四过孔及所述第五过孔连接。具体的，所述缓冲层111包括覆盖所述第一遮光部110a的缓冲部，所述第四过孔贯穿所述第二绝缘部远离所述有源层105的一侧，所述第五过孔贯穿所述缓冲部，所述第四过孔在所述衬底101上的正投影覆盖所述第五过孔在所述衬底101上的正投影。所述源极106包括源极106连接部，所述源极106连接部位于所述第四过孔及所述第五过孔内，所述第四过孔及所述第五过孔裸露所述第一遮光部110a，所述源极106连接部与所述第一遮光部110a接触，以实现所述源极106与所述第一遮光部110a的连接。
或者，请参阅图1，当所述栅极绝缘层109包括相离设置的所述第一绝缘部、所述第二绝缘部及所述第三绝缘部时，所述栅极绝缘层109包括第六过孔，所述第六过孔贯穿第三绝缘部远离所述有源层105的一侧，所述缓冲层111包括第七过孔，所述第七过孔贯穿所述缓冲层111，所述第六过孔与所述第七过孔相连通，所述漏极107与所述第一遮光部110a通过所述第六过孔及所述第七过孔连接。具体的，所述第六过孔贯穿所述第三绝缘部远离所述有源层105的一侧，所述第七过孔贯穿所述缓冲部，所述第六过孔在所述衬底101上的正投影覆盖所述第七过孔在所述衬底101上的正投影。所述漏极107包括漏极107连接部，所述漏极107连接部位于所述第六过孔及所述第七过孔内，所述第六过孔及所述第七过孔裸露所述第一遮光部110a，所述漏极107连接部与所述第一遮光部110a接触，以实现所述漏极107与所述第一遮光部110a的连接。
本实施例中，所述显示面板100包括显示区及位于所述显示区至少一侧的非显示区，所述显示面板100还包括位于所述非显示区内的端子，所述端子位于所述第一金属层104。
所述非显示区内具有多个端子，所述端子包括第一类端子，所述第一类端子与所述第二金属层110连接。所述第二金属层110还包括第二金属层走线，所述第一类端子与所述第二金属层走线连接。
当所述栅极绝缘层109包括相离设置的所述第一绝缘部、所述第二绝缘部及所述第三绝缘部时，所述栅极绝缘层109还包括位于所述端子与所述缓冲层111之间的第四绝缘部，所述栅极绝缘层109还包括第八过孔，所述第八过孔贯穿所述第四绝缘部，所述缓冲层111包括第九过孔，所述第九过孔贯穿所述第二金属层走线与所述第四绝缘部之间的所述缓冲层111，所述第八过孔在所述衬底101上的正投影覆盖所述第九过孔在所述衬底101上的正投影。所述第一类端子包括第一类端子连接部，所述第一类端子连接部位于所述第八过孔及所述第九过孔内，所述第八过孔及所述第九过孔裸露所述第二金属层走线，所述第一类端子连接部与所述第二金属层走线接触。
当所述栅极108位于所述第一金属层104远离所述衬底101的一侧，所述源极106与所述第一导体子部105b之间无绝缘层，所述漏极107与所述第二导体子部105c之间无绝缘层时，所述缓冲层111包括第十过孔，所述第十过孔贯穿所述第二金属层走线与所述第一类端子之间的所述缓冲层111，所述第一类端子包括第一类端子连接部，所述第一类端子连接部位于所述十过孔内，所述第十过孔裸露所述第二金属层走线，所述第一类端子连接部与所述第二金属层走线接触。
在一些实施例中，所述像素定义部103与所述阳极102具有重叠部，所述重叠部在所述衬底101上的正投影的宽度大于2微米，以便于避免工艺误差导致所述阳极102的边缘的暴露，以及便于覆盖所述第一连接部和/或所述第二连接部。所述阳极102具有未被所述像素定义部103覆盖的中心部及被所述像素定义部103覆盖的周围部，所述周围部在所述衬底101上的正投影与所述重叠部在所述衬底101上的正投影重合。所述重叠部包括靠近所述中心部的第一侧及远离所述中心部的第二侧，所述重叠部在所述衬底101上的正投影的宽度大于2微米，即，所述第一侧与所述第二侧之间的最小间距大于2微米。
在一些实施例中，相邻所述阳极102之间的间距大于7微米，在保证足够的分辨率的情况下，以便于所述像素定义部103之间间隔足够的距离，有助于缓解所述像素定义部103所受应力，并改善所述显示面板100的出光率。
请参阅图1及图2，本实施例中，所述平坦层113与所述衬底101平行，所述像素定义部103与所述平坦层113直接接触，所述第一夹角α与所述第一侧面103a和所述平坦层113形成的夹角等同。所述第一夹角α大于或等于35度，所述第一夹角α小于或等于45度，例如，所述第一夹角α可以为36度、37度、38度、39度、40度、41度、42度、43度、44度等。所述第一夹角α的角度值在上述范围，使所述第一侧面103a的坡度更为和缓，且在高度保持不变的情形下，所述像素定义部103的总表面积增大，有利于增大所述像素定义部103与相邻膜层之间的接触面积，增强了像素定义部103与相邻膜层之间结合的牢固程度，从而使所述显示面板100在应用于弯折场景时不易膜层分离，改善了显示面板100的产品质量。
请参阅图1及图2，本实施例中，所述显示面板100还包括位于所述阳极102远离所述衬底101一侧的有机层119，所述有机层119包括发光层120。沿平行于所述衬底101的方向，所述像素定义部103包括靠近所述阳极102的第二侧面103b，所述阳极102在所述衬底101上的正投影及所述第二侧面103b在所述衬底101上的正投影共同覆盖所述发光层120在所述衬底101上的正投影。即，所述发光层120位于所述像素定义开口内，所述发光层120的边缘不超出所述第二侧面103b。所述阳极102在所述衬底101上的正投影及所述第二侧面103b在所述衬底101上的正投影共同覆盖所述发光层120在所述衬底101上的正投影，有利于避免不同发光颜色的发光层（例如：红色、绿色、蓝色）在所述像素定义部103外发生混合，影响所述显示面板100的显示质量。
请参阅图1及图2，在一些实施例中，所述第二侧面103b靠近所述阳极102的一侧与所述阳极102具有第二夹角β，所述第二夹角β大于或等于35度，所述第二夹角β小于或等于45度。例如，所述第二夹角β可以为36度、37度、38度、39度、40度、41度、42度、43度、44度等。所述第二夹角β在上述范围时，所述第二侧面103b更为和缓，有利于所述发光层120的形成不超出所述第二侧面103b。
本实施例中，所述有机层119包括位于所述像素定义开口内的空穴注入层、空穴传输层、电子传输层及电子注入层。所述空穴注入层位于所述阳极102远离所述衬底101的一侧，所述空穴注入层、所述空穴传输层、所述发光层、所述电子传输层及所述电子注入层依次叠层设置。
本实施例中，所述显示面板100还包括阴极，所述阴极至少覆盖所述有机层远离所述衬底101的一侧。
所述阳极102、所述阴极及所述有机层组成发光元件。
本发明实施例通过将所述像素定义部103与所述阳极102一一对应设置，相邻所述像素定义部103间隔，减少了所述像素定义部103所受应力，并且像素定义部103的第一侧面103a坡度更缓，增大了像素定义部103与相邻膜层之间的接触面积，增强了像素定义部103与相邻膜层之间结合的牢固程度，改善了所述显示面板100的产品质量。
请参阅1至图3、图4a至图4m本发明实施例还提供一种显示面板100的制作方法，包括：
S100、提供一衬底101。
S200、在所述衬底101上形成阳极材料层。
S300、在所述阳极材料层上形成像素定义材料层。
S400、所述阳极材料层及所述像素定义材料层经第一图案化处理分别形成多个阳极102及多个像素定义部103。
其中，所述像素定义部103覆盖所述阳极102的边缘并裸露部分所述阳极102，一所述像素定义部103环绕一所述阳极102设置，相邻所述像素定义部103间隔设置；
沿平行于所述衬底101的方向，所述像素定义部103包括远离所述阳极102的第一侧面103a，所述第一侧面103a靠近所述衬底101的一侧与所述衬底101具有第一夹角α，所述第一夹角α大于或等于35度，所述第一夹角α小于或等于45度。
本实施例中，所述衬底101的材料已在前述的显示面板100中详述，在此不再赘述。
本实施例中，所述阳极材料层包括具有高功函数的材料。所述阳极材料层包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In 2O 3)等中的一种，上述材料为具有相对高的功函数并且透明的导电材料。除了以上列出的导电材料之外，所述阳极材料层还可以包括诸如银(Ag)、镁(Mg)、铝(Al)、铂(Pt)、钯(Pb)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、锂(Li)、钙(Ca)或者它们的组合的反射材料。所述阳极材料层可以由透明导电材料和/或反射性导电材料的单层或多层组成。例如，所述阳极材料层可以是IZO材料层、Ag材料层形成的IZO材料层/Ag材料层/IZO材料层三层叠构。所述阳极材料层可以通过物理气相沉积或化学气相沉积的方式形成。
本实施例中，所述像素定义材料层的材料选自有机材料，如正性光阻材料或负性光阻材料，以便于利用所述像素定义材料层作为光阻，所述像素定义部103和所述阳极102经同一图案化处理形成，节省制程工艺、降低制程成本。
在一些实施例中，步骤S400包括：
S410、利用一第一掩模版对所述像素定义材料层曝光。
所述第一掩模版可以为半色调掩模版。
S420、所述像素定义材料层经显影后形成第一光阻区、第二光阻区以及第一无光阻区。
其中，所述第一光阻区内所述像素定义材料层的厚度大于所述第二光阻区内的所述像素定义材料层的厚度。
S430、利用第一蚀刻工艺去除所述第一无光阻区对应的所述阳极材料层，以形成所述阳极102。
所述第一蚀刻工艺可以为湿法蚀刻工艺，当所述阳极材料层为IZO材料层、Ag材料层形成的IZO材料层/Ag材料层/IZO材料层三层叠构时，所述第一刻蚀工艺中使用到第一蚀刻剂，所述第一蚀刻剂包括磷酸、硝酸等，用于刻蚀Ag材料层、IZO材料层。
S440、去除所述第二光阻区内的所述像素定义材料层，保留所述第一光阻区内的所述像素定义材料层形成所述像素定义部103。
所述第二光阻区内的所述像素定义材料层可以通过灰化工艺去除。
在一些实施例中，步骤S400还包括：
S450、清洗所述像素定义部103及所述阳极102。
S460、对所述像素定义部103进行加热处理。
所述阳极102、所述像素定义部103的材料、厚度及结构等已在前述的显示面板100中详述，在此不再赘述。
本实施例中，在步骤S200之前，包括：
请参阅图4b，S500、在所述衬底101上形成第二金属层110。
本实施例中，所述第二金属层110的材料、厚度及结构等已在前述的显示面板100中详述，在此不再赘述。
请参阅图4c，S600、在所述第二金属层110上形成缓冲材料层115。
所述缓冲材料层115覆盖所述第二金属层110及所述衬底101。
S700、在所述缓冲材料层115上形成薄膜晶体管层。
S800、在所述薄膜晶体管层上形成钝化层112及平坦层113。
本实施例中，所述钝化层112及平坦层113的材料、厚度及结构等已在前述的显示面板100中详述，在此不再赘述。
所述钝化材料层覆盖所述薄膜晶体管层，所述平坦材料层覆盖所述钝化材料层。所述平坦化材料层的材料为正性光阻材料或负性光阻材料。
请参阅图4d至图4h，在一些实施例中，步骤S700包括：
S710、在所述缓冲层111上形成半导体层114及第一金属层104。
步骤S710包括：
S711、在所述衬底101上形成半导体材料层116。
S712、在所述半导体材料层116上形成第一金属材料层117，所述第一金属材料层117与所述半导体材料层116直接接触。
S713、所述半导体材料层116及所述第一金属材料层117经第二图案化处理分别形成半导体层114及第一金属层104。
其中，所述第一金属层104包括源极106及漏极107，所述源极106及所述漏极107分别位于所述半导体层114的相对两侧。
所述源极106与所述第一导体子部105b之间无绝缘层，所述漏极107与所述第二导体子部105c之间无绝缘层。
步骤S713包括：
S713a、在所述第一金属材料层上形成一第一光阻材料层118。
S713b、利用一第二掩模版Mask对所述第一光阻材料层118曝光。
第二掩模版Mask可以为半色调掩模版。
S713c、所述第一光阻材料层118经显影后形成第三光阻区、第四光阻区以及第二无光阻区。
其中，所述第三光阻区内所述第一光阻材料层118的厚度大于所述第四光阻区内的所述第一光阻材料层118的厚度。
S713d、利用第二蚀刻工艺去除所述第二无光阻区对应的所述半导体材料层116及所述第一金属材料层117，以形成所述半导体层114。
所述第二蚀刻工艺可以为湿法蚀刻工艺。
S713e、利用灰化工艺去除所述第四光阻区内的所述第一光阻材料层118。
S713f、利用第三蚀刻工艺去除所述第四光阻区对应的所述第一金属材料层117以形成所述第一金属层104。
所述第三蚀刻工艺可以为湿法蚀刻工艺，当所述第一金属材料层为MoTi层、Cu层、MoTi层形成的MoTi/Cu/MoTi三层叠层结构时，所述第三刻蚀工艺中使用到第二蚀刻剂，所述第二蚀刻剂不含氟元素以避免对所述半导体层114造成损伤，所述第二蚀刻剂包括双氧水等组分，用于所述第一金属材料层。
S713g、去除所述第一光阻材料层118。
S720、在所述源极106及所述漏极107之间形成栅极绝缘层109及栅极108。
步骤S720包括：
S721、在所述第一金属层104上形成栅极绝缘材料层。
S722、在所述栅极绝缘材料层上形成栅极材料层。
S723、所述栅极绝缘材料层及所述栅极材料层经第三图案化处理形成所述栅极绝缘层109及所述栅极108。
步骤S723包括：
S723a、在所述栅极材料层上形成一第二光阻材料层。
S723b、利用一第三掩模版对所述第二光阻材料层曝光。
S723c、所述第二光阻材料层经显影后形成第五光阻区及第三无光阻区。
S723d、利用第四蚀刻工艺去除所述第三无光阻区对应的所述栅极材料层，以形成所述栅极108。
所述第四蚀刻工艺可以为湿法蚀刻工艺。
S723e、利用第五蚀刻工艺去除所述第三无光阻区对应的所述栅极绝缘材料层，以形成所述栅极绝缘层109。
所述第五蚀刻工艺可以为干法蚀刻工艺。
S723f、去除所述第二光阻材料层。
S730、对所述半导体层114进行导体化处理以形成有源层105。
所述导体化处理可以为离子注入或等离子轰击等方式，以形成所述有源层105，所述有源层105包括沟道部105a及分别位于所述沟道部105a相对两侧的第一导体子部105b及第二导体子部105c。
本实施例中，所述栅极绝缘层109、所述第一金属层104、所述有源层105的材料、厚度及结构等已在前述的显示面板100中详述，在此不再赘述。
请参阅图4i，当所述薄膜晶体管层以步骤S710至步骤S730形成时，步骤S800包括：
S810、形成钝化层112及缓冲层111。
步骤S810包括：
S811、在所述钝化材料层上形成一第三光阻材料层。
S812、利用一第四掩模版对所述第三光阻材料层曝光。
S813、所述第三光阻材料层经显影后形成第六光阻区及第四无光阻区。
所述第四无光阻区包括第一无光阻子区及第二无光阻子区。
S814、利用第六蚀刻工艺去除所述第一无光阻子区对应的所述钝化材料层，及去除所述第二无光阻子区对应的所述钝化材料层及所述缓冲材料层115，以形成所述钝化层112及所述缓冲层111。
所述第六蚀刻工艺可以为干法蚀刻工艺。
S815、去除所述第三光阻材料层。
S820、形成平坦层113。
步骤S820包括：
S821、利用一第五掩模版对所述平坦材料层曝光。
S822、所述平坦材料层经显影后形成第一平坦层113过孔及第二平坦层113过孔。
所述平坦层113及所述钝化层112组成第一绝缘层，所述第一平坦层113过孔及去除所述第一无光阻子区对应的所述钝化材料层形成所述第一绝缘层的第一过孔H1，所述阳极102通过所述第一过孔H1与所述源极106或所述漏极107连接。所述第二平坦层113过孔及去除所述第二无光阻子区对应的所述钝化材料层形成所述第一绝缘层的第二过孔，去除所述二无光阻子区对应的所述缓冲材料层115形成第三过孔，所述第三过孔与所述第二过孔相连通，所述阳极102与所述第二金属层110中的第一遮光部110a通过所述第二过孔及所述第三过孔连接。
去除所述第一无光阻子区对应的所述钝化材料层使所述源极106或所述漏极107裸露，且由于去除所述第一无光阻子区对应的所述钝化材料层与去除所述第二无光阻子区对应的所述钝化材料层及所述缓冲材料层115，导致所述源极106或所述漏极107遭遇过刻，采用干法刻蚀对金属材料的损伤轻微，因此可以使所述钝化层112及所述缓冲层111经同一蚀刻工艺形成，降低制程成本。
请参阅图4j至图4l，在一些实施例中，步骤S700包括：
S740、在所述缓冲层111上形成半导体层114。
在一些实施例中，步骤S740包括：
S741、在所述缓冲层111上形成半导体材料层。
S742、所述半导体材料层经第四图案化处理形成所述半导体层114。
步骤S742包括：
S742a、在所述半导体材料层上形成一第四光阻材料层。
S742b、利用一第六掩模版对所述第四光阻材料层曝光。
S742c、所述第四光阻材料层经显影后形成第七光阻区及第五无光阻区。
S742d、利用第七蚀刻工艺去除所述第五无光阻区对应的所述半导体材料层，以形成所述半导体层114。
所述第七蚀刻工艺可以为湿法蚀刻工艺。
S742e、去除所述第四光阻材料层。
S750、形成栅极绝缘层109及缓冲层111。
步骤S750包括：
S751、在所述半导体层114上形成栅极绝缘材料层，所述栅极绝缘材料层覆盖所述半导体层114及所述缓冲材料层115。
S752、所述栅极绝缘材料层经第五图案化处理形成所述半导体层114。
步骤S752包括：
S752a、在所述栅极绝缘材料层上形成一第五光阻材料层。
S752b、利用一第七掩模版对所述第五光阻材料层曝光。
S752c、所述第五光阻材料层经显影后形成有第八光阻区及第六无光阻区。
所述第六无光阻区包括第三无光阻子区、第四无光阻子区及第四无光阻子区。
S752d、利用第八蚀刻工艺去除所述第三无光阻子区及所述第四无光阻子区对应的所述栅极绝缘材料层、所述第五无光阻子区对应的所述栅极绝缘材料层及所述缓冲材料层115，以形成所述栅极绝缘层109及所述缓冲层111。
所述第八蚀刻工艺可以为干法蚀刻工艺。
所述栅极绝缘层109包括第一绝缘部、第二绝缘部及第三绝缘部，去除所述第三无光阻子区、所述第四无光阻子区、所述第五无光阻子区对应的所述栅极绝缘材料层及所述缓冲层111，分别形成所述栅极绝缘层109的第一开口、第二开口及第四过孔或第六过孔，以及所述缓冲层111的第五过孔或第七过孔。
所述第四过孔位于第二绝缘部远离有源层105的一侧，所述缓冲层111包括第五过孔，所述第四过孔与所述第五过孔相连通，所述源极106与所述第二金属层110的第一遮光部110a通过所述第四过孔及所述第五过孔连接；或者，所述第六过孔位于第三绝缘部远离所述有源层105的一侧，所述缓冲层111包括第七过孔，所述第六过孔与所述第七过孔相连通，所述漏极107与所述第一遮光部110a通过所述第六过孔及所述第七过孔连接。
S760、所述半导体层114形成有源层105。
利用所述第一开口及所述第二开口，所述半导体层114通过导体化处理形成所述有源层105。
所述导体化处理可以为离子注入或等离子轰击等方式。
S770、在所述栅极绝缘层109上形成第一金属层104。
所述第一金属层104包括所述源极106、所述漏极107及所述栅极108。
步骤S770包括：
S771、在所述栅极绝缘层109上形成第一金属材料层。
S772、所述第一金属材料层经第六图案化处理形成所述第一金属层104。
步骤S772包括：
S772a、在所述第一金属材料层上形成一第六光阻材料层。
S772b、利用一第八掩模版对所述第六光阻材料层曝光。
S772c、所述第六光阻材料层经显影后形成有第九光阻区及第七无光阻区。
所述第九光阻区包括第一光阻子区、第二光阻子区及第三光阻子区。
S772d、利用第九蚀刻工艺去除所述第七无光阻区对应的所述第一金属材料层，以形成所述第一金属层104。
所述第一光阻子区、所述第二光阻子区及所述第三光阻子区对应的所述第一金属材料层分别形成所述源极106、所述漏极107及所述栅极108。
所述第九蚀刻工艺可以为湿法蚀刻工艺。
S772e、去除所述第六光阻材料层。
本实施例中，所述栅极绝缘层109、所述第一金属层104、所述有源层105的材料、厚度及结构等已在前述的显示面板100中详述，在此不再赘述。
请参阅图4m，当所述薄膜晶体管层以步骤S740至步骤S770形成时，步骤S800包括：
S830、在所述薄膜晶体管层上形成钝化层112及平坦层113。
步骤S830包括：
S831、在所述薄膜晶体管层上形成钝化材料层。
S832、在所述钝化材料层上形成平坦材料层。
所述平坦材料层的材料选自正性光阻材料或负性光阻材料。
S834、所述钝化材料层及所述平坦材料层经第七图案化处理形成所述钝化层112及所述平坦层113。
步骤S834包括：
S834a、利用一第八掩模版对所述平坦材料层曝光。
S834b、所述平坦材料层经显影后形成有第十光阻区及第八无光阻区，以形成所述平坦层113。
S834c、利用第十蚀刻工艺去除所述第八无光阻区对应的所述钝化材料层以形成所述钝化层112。
所述第十蚀刻工艺可以为干法蚀刻工艺。
所述平坦层113及所述钝化层112组成第一绝缘层，所述第八无光阻区及去除所述第八无光阻区对应的所述钝化材料层形成所述第一绝缘层的第一过孔H1，所述阳极102与所述第一金属层104通过所述第一过孔H1连接。
本实施例中，步骤S500可以包括：
S510、在所述衬底101上形成第二金属材料层。
S520、所述第二金属材料层经第八图案化处理形成所述第二金属层110。
步骤S520包括：
S520a、在所述第二金属材料层上形成一第七光阻材料层。
S520b、利用一第十掩模版对所述第七光阻材料层曝光。
S520c、所述第七光阻材料层经显影后形成有第十一光阻区及第九无光阻区。
S520d、利用第十一蚀刻工艺去除所述第九无光阻区对应的所述第二金属材料层，以形成所述第二金属层110。
所述第十一蚀刻工艺可以为湿法蚀刻工艺。
S520e、去除所述第七光阻材料层。
本发明实施例提供的显示面板的制作方法，所述衬底101与所述像素定义部103之间的膜层的制作只需要经过六次图案化处理，降低了制程成本并提高了制程效率，同时，所述像素定义部103与所述阳极102一一对应设置，相邻所述像素定义部103间隔，减少了所述像素定义部103所受应力，并且像素定义部103的第一侧面103a坡度更缓，增大了像素定义部103与相邻膜层之间的接触面积，增强了像素定义部103与相邻膜层之间结合的牢固程度，改善了制作的显示面板的产品质量。
本发明实施例公开了一种显示面板及其制作方法；该显示面板包括衬底、位于衬底上的多个阳极、覆盖阳极的边缘并裸露部分阳极的多个像素定义部，一像素定义部环绕一阳极设置，相邻像素定义部间隔设置，沿平行于衬底的方向，像素定义部包括远离阳极的第一侧面，第一侧面靠近衬底的一侧与衬底具有第一夹角，第一夹角大于或等于35度，第一夹角小于或等于45度，本发明通过将像素定义部与阳极一一对应设置，相邻像素定义部间隔，减少了像素定义部所受应力，并且像素定义部的第一侧面坡度更缓，增大了像素定义部与相邻膜层之间的接触面积，增强了像素定义部与相邻膜层之间结合的牢固程度，改善了显示面板的产品质量。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，其中，包括：
    衬底；
    多个阳极，位于所述衬底上；
    多个像素定义部，所述像素定义部覆盖所述阳极的边缘并裸露部分所述阳极；
    其中，一所述像素定义部环绕一所述阳极设置，相邻所述像素定义部间隔设置；
    沿平行于所述衬底的方向，所述像素定义部包括远离所述阳极的第一侧面，所述第一侧面靠近所述衬底的一侧与所述衬底具有第一夹角，所述第一夹角大于或等于35度，所述第一夹角小于或等于45度。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括第一金属层，所述第一金属层位于所述阳极与所述衬底之间；
    所述显示面板还包括第一绝缘层，所述第一绝缘层位于所述第一金属层与所述阳极之间，所述第一绝缘层包括第一过孔，所述阳极包括位于所述第一过孔内的第一连接部，所述第一连接部与所述第一金属层连接，所述像素定义部覆盖所述第一连接部。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板还包括有源层，所述有源层位于所述第一金属层与所述衬底之间，所述有源层包括沟道部以及分别位于所述沟道部相对两侧的第一导体子部及第二导体子部；
    所述第一金属层包括源极及漏极，所述源极位于所述第一导体子部上，所述漏极位于所述第二导体子部上；
    其中，至少部分所述源极靠近所述有源层的一侧与所述第一导体子部接触，至少部分所述漏极靠近所述有源层的一侧与所述第二导体子部接触。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板还包括栅极，所述栅极位于所述源极与所述漏极之间，所述栅极在所述有源层上的正投影覆盖所述沟道部；
    所述显示面板还包括栅极绝缘层，所述栅极绝缘层至少间隔于所述栅极与所述沟道部之间。
  5. 根据权利要求4所述的显示面板，其中，所述栅极位于所述第一金属层，所述栅极绝缘层包括相离设置的第一绝缘部、第二绝缘部及第三绝缘部，所述第一绝缘部间隔于所述沟道部与所述栅极之间，所述第二绝缘部间隔于部分所述源极与所述第一导体子部之间，所述第三绝缘部间隔于部分所述漏极与所述第二导体子部之间；
    所述源极靠近所述栅极的一端与所述第一导体子部接触，所述漏极靠近所述栅极的一端与所述第二导体子部接触。
  6. 根据权利要求4所述的显示面板，其中，所述栅极位于所述第一金属层远离所述衬底的一侧，所述源极与所述第一导体子部之间无绝缘层，所述漏极与所述第二导体子部之间无绝缘层。
  7. 根据权利要求6所述的显示面板，其中，在平行于所述衬底的平面内，沿所述沟道部至所述第一导体子部的方向，所述源极远离所述栅极的一侧边缘超出所述第一导体子部远离所述沟道部的一侧边缘；
    在平行于所述衬底的平面内，沿所述沟道部至所述第二导体子部的方向，所述漏极远离所述栅极的一侧边缘超出所述第二导体子部远离所述沟道部的一侧边缘。
  8. 根据权利要求3所述的显示面板，其中，所述显示面板还包括第二金属层，所述第二金属层位于所述有源层与所述衬底之间，所述第二金属层包括第一遮光部，所述有源层在所述衬底上的正投影位于所述第一遮光部在所述衬底上的正投影内；
    所述显示面板还包括缓冲层，所述缓冲层位于所述有源层靠近所述衬底的一侧，所述缓冲层覆盖所述第二金属层。
  9. 根据权利要求8所述的显示面板，其中，所述第一绝缘层包括靠近所述衬底一侧的钝化层，所述缓冲层间隔于所述第二金属层与所述有源层之间，所述缓冲层远离所述衬底的一侧与所述有源层及所述钝化层直接接触；
    所述缓冲层靠近所述衬底的一侧与所述第二金属层及所述衬底直接接触。
  10. 根据权利要求9所述的显示面板，其中，当所述栅极绝缘层包括相离设置的第一绝缘部、第二绝缘部及第三绝缘部时，所述第二绝缘部远离所述第一绝缘部的一端与所述缓冲层接触，所述第三绝缘部远离所述第一绝缘部的一端与所述缓冲层接触。
  11. 根据权利要求8所述的显示面板，其中，所述第一绝缘层还包括第二过孔，所述第二过孔位于有源层的一侧；
    所述缓冲层包括第三过孔，所述第三过孔与所述第二过孔相连通，所述阳极与所述第一遮光部通过所述第二过孔及所述第三过孔连接；
    所述阳极包括第二连接部，所述像素定义部在所述衬底上的正投影覆盖所述第二连接部在所述衬底上的正投影。
  12. 根据权利要求8所述的显示面板，其中，栅极绝缘层包括第四过孔，所述第四过孔位于第二绝缘部远离有源层的一侧，所述缓冲层包括第五过孔，所述第四过孔与所述第五过孔相连通，源极与所述第一遮光部通过所述第四过孔及所述第五过孔连接。
  13. 根据权利要求8所述的显示面板，其中，栅极绝缘层包括第六过孔，所述第六过孔位于第三绝缘部远离所述有源层的一侧，所述缓冲层包括第七过孔，所述第六过孔与所述第七过孔相连通，漏极与所述第一遮光部通过所述第六过孔及所述第七过孔连接。
  14. 根据权利要求2所述的显示面板，其中，所述显示面板包括显示区及位于所述显示区至少一侧的非显示区，所述显示面板还包括位于所述非显示区内的端子，所述端子位于所述第一金属层；
    其中，所述端子包括第一类端子，所述第一类端子与所述第二金属层连接。
  15. 根据权利要求14所述的显示面板，其中，当栅极绝缘层包括相离设置的所述第一绝缘部、所述第二绝缘部及所述第三绝缘部时，所述栅极绝缘层还包括位于所述端子与缓冲层之间的第四绝缘部，所述栅极绝缘层还包括第八过孔，所述第八过孔贯穿所述第四绝缘部，所述缓冲层包括第九过孔，所述第九过孔贯穿所述第二金属层走线与所述第四绝缘部之间的所述缓冲层，所述第八过孔在所述衬底上的正投影覆盖所述第九过孔在所述衬底上的正投影；
    所述第一类端子包括第一类端子连接部，所述第一类端子连接部位于所述第八过孔及所述第九过孔内，所述第八过孔及所述第九过孔裸露所述第二金属层走线，所述第一类端子连接部与所述第二金属层走线接触。
  16. 根据权利要求1至15中任一项所述的显示面板，其中，所述像素定义部与所述阳极具有重叠部，所述重叠部在所述衬底上的正投影的宽度大于2微米。
  17. 根据权利要求16所述的显示面板，其中，所述显示面板还包括位于所述阳极远离所述衬底一侧的有机层，所述有机层包括发光层；
    沿平行于所述衬底的方向，所述像素定义部包括靠近所述阳极的第二侧面，所述阳极在所述衬底上的正投影及所述第二侧面在所述衬底上的正投影共同覆盖所述发光层在所述衬底上的正投影。
  18. 根据权利要求17所述的显示面板，其中，所述第二侧面靠近所述阳极的一侧与所述阳极具有第二夹角，所述第二夹角大于或等于35度，所述第二夹角小于或等于45度。
  19. 一种显示面板的制作方法，其中，包括：
    提供一衬底；
    在所述衬底上形成阳极材料层；
    在所述阳极材料层上形成像素定义材料层；
    所述阳极材料层及所述像素定义材料层经第一图案化处理分别形成多个阳极及多个像素定义部；
    其中，所述像素定义部覆盖所述阳极的边缘并裸露部分所述阳极，一所述像素定义部环绕一所述阳极设置，相邻所述像素定义部间隔设置；
    沿平行于所述衬底的方向，所述像素定义部包括远离所述阳极的第一侧面，所述第一侧面靠近所述衬底的一侧与所述衬底具有第一夹角，所述第一夹角大于或等于35度，所述第一夹角小于或等于45度。
  20. 根据权利要求19所述的显示面板的制作方法，其中，所述在所述衬底上形成阳极材料层之前，还包括：
    在所述衬底上形成半导体材料层；
    在所述半导体材料层上形成第一金属材料层，所述第一金属材料层与所述半导体材料层直接接触；
    所述半导体材料层及所述第一金属材料层经第二图案化处理分别形成半导体层及第一金属层；
    其中，所述第一金属层包括源极及漏极，所述源极及所述漏极分别位于所述半导体层的相对两侧。
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