WO2024254908A1 - 驱动基板及显示面板 - Google Patents

驱动基板及显示面板 Download PDF

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Publication number
WO2024254908A1
WO2024254908A1 PCT/CN2023/104223 CN2023104223W WO2024254908A1 WO 2024254908 A1 WO2024254908 A1 WO 2024254908A1 CN 2023104223 W CN2023104223 W CN 2023104223W WO 2024254908 A1 WO2024254908 A1 WO 2024254908A1
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Prior art keywords
metal layer
channel
gate
contact portion
layer
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PCT/CN2023/104223
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English (en)
French (fr)
Inventor
占晓军
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to DE112023000066.2T priority Critical patent/DE112023000066T5/de
Priority to US18/263,533 priority patent/US20250089362A1/en
Publication of WO2024254908A1 publication Critical patent/WO2024254908A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • the present application relates to the field of display technology, and in particular to a driving substrate and a display panel.
  • TFT Thin Film Transistor
  • TFT In TFT, a high electric field is generated between the channel region and the drain region, and hot carriers are generated in this part. Due to the influence of hot carriers, the threshold voltage (Vth) of the TFT changes. This phenomenon can be alleviated by forming a lightly doped drain (LDD) region with a resistance transition between the channel region and the drain region.
  • LDD lightly doped drain
  • the inventors of the present application found that in a top-gate TFT, the top gate is usually used as a mask, the source region and the drain region are formed by plasma treatment of an oxide semiconductor, and the LDD region is formed by contacting a SiN film.
  • the length of the channel depends on the length of the top gate.
  • the embodiments of the present application provide a driving substrate and a display panel, which can narrow the channel length of the active layer.
  • the embodiment of the present application provides a driving substrate, which includes:
  • a thin film transistor structure wherein the thin film transistor structure is disposed on the substrate, and the thin film transistor structure comprises:
  • an active layer the active layer being arranged on the substrate, the active layer comprising a first contact portion, a transition portion, a channel, and a second contact portion, the transition portion being arranged between the first contact portion and the channel, the second contact portion being arranged on a side of the channel away from the first contact portion, the resistance value of the first contact portion being smaller than the resistance value of the transition portion, and the resistance value of the transition portion being smaller than the resistance value of the channel;
  • a gate insulating layer disposed on the active layer
  • a gate the gate being disposed on the gate insulating layer, the gate comprising a first portion and a second portion connected to the first portion, the first portion being overlapped with the channel, the second portion being overlapped with the transition portion, the first portion being used to completely block doping ions, and the second portion being used to partially transmit the doping ions;
  • a first electrode and a second electrode wherein the first electrode is connected to the first contact portion, and the second electrode is connected to the second contact portion.
  • the density of the first part is greater than the density of the second part.
  • the thickness of the first part is greater than the thickness of the second part.
  • the gate is a single-film layer structure.
  • the gate includes a first metal layer and a second metal layer, the first metal layer is arranged on the gate insulating layer, the first metal layer blocks the channel and the transition portion, and the second metal layer is arranged on a side of the first metal layer away from the gate insulating layer, the second metal layer blocks the channel.
  • the thickness of the first metal layer is less than the thickness of the second metal layer.
  • the gate includes a first metal layer and a second metal layer, the first metal layer is arranged on the gate insulating layer, the first metal layer only blocks the channel, and the second metal layer is arranged on a side of the first metal layer away from the gate insulating layer, the second metal layer blocks the channel and the transition portion.
  • the thickness of the first portion is greater than or equal to 250 nanometers, and the thickness of the second portion is less than or equal to 100 nanometers and greater than or equal to 10 nanometers.
  • a mass ratio of the doping ions in the first contact portion is greater than a mass ratio of the doping ions in the transition portion.
  • the first electrode is used to connect the light-emitting device, the channel is directly connected to the second contact portion, or another transition portion is connected between the channel and the second contact portion.
  • an embodiment of the present application further provides a display panel, which includes the driving substrate described in any one of the above embodiments and a light-emitting device arranged on the driving substrate, wherein the driving substrate includes:
  • a thin film transistor structure wherein the thin film transistor structure is disposed on the substrate, and the thin film transistor structure comprises:
  • an active layer the active layer being arranged on the substrate, the active layer comprising a first contact portion, a transition portion, a channel, and a second contact portion, the transition portion being arranged between the first contact portion and the channel, the second contact portion being arranged on a side of the channel away from the first contact portion, the resistance value of the first contact portion being smaller than the resistance value of the transition portion, and the resistance value of the transition portion being smaller than the resistance value of the channel;
  • a gate insulating layer disposed on the active layer
  • a gate the gate being disposed on the gate insulating layer, the gate comprising a first portion and a second portion connected to the first portion, the first portion being overlapped with the channel, the second portion being overlapped with the transition portion, the first portion being used to completely block doping ions, and the second portion being used to partially transmit the doping ions;
  • a first electrode and a second electrode wherein the first electrode is connected to the first contact portion, and the second electrode is connected to the second contact portion.
  • the density of the first part is greater than the density of the second part.
  • the gate is a single-film layer structure.
  • the thickness of the first metal layer is less than the thickness of the second metal layer.
  • the gate includes a first metal layer and a second metal layer, the first metal layer is arranged on the gate insulating layer, the first metal layer only blocks the channel, and the second metal layer is arranged on a side of the first metal layer away from the gate insulating layer, the second metal layer blocks the channel and the transition portion.
  • a mass ratio of the doping ions in the first contact portion is greater than a mass ratio of the doping ions in the transition portion.
  • the first electrode is used to connect the light-emitting device, the channel is directly connected to the second contact portion, or another transition portion is connected between the channel and the second contact portion.
  • the active layer is arranged on the substrate, and the active layer includes a first contact portion, a transition portion, a channel, and a second contact portion, the transition portion is arranged between the first contact portion and the channel, the second contact portion is arranged on a side of the channel away from the first contact portion, the resistance value of the first contact portion is smaller than the resistance value of the transition portion, and the resistance value of the transition portion is smaller than the resistance value of the channel;
  • the gate insulating layer is arranged on the active layer;
  • the gate is arranged on the gate insulating layer, the gate includes a first part and a second part connected to the first part, the first part is arranged to overlap with the channel, the second part is arranged to overlap with the transition portion, the first part is used to completely block doped ions, and the second part is used to transmit part of the doped ions;
  • the first electrode is connected to the first contact portion, and the second electrode is connected to the second contact portion.
  • the first part of the gate is used to block the channel
  • the second part is used to block the transition part, so that during the ion implantation process, part of the doped ions penetrate through the second part and enter the transition part, while the doped ions corresponding to the channel area are completely blocked by the first part. Therefore, in this embodiment, the gate is used as a mask to implement doping of the transition part under the mask. Compared with the prior art using the gate as a mask, the channel of this embodiment can be made narrower and the stability of the threshold voltage of the thin film transistor is improved.
  • FIG1 is a schematic structural diagram of a driving substrate provided in a first embodiment of the present application.
  • FIG. 2 is a schematic diagram of step B12 of the method for preparing a drive substrate provided in the first embodiment of the present application;
  • step B13 is a schematic diagram of step B13 of the method for preparing a drive substrate provided in the first embodiment of the present application;
  • FIG4 is a schematic structural diagram of a driving substrate provided in a second embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a drive substrate provided in a third embodiment of the present application.
  • FIG6 is a schematic structural diagram of a drive substrate provided in a fourth embodiment of the present application.
  • FIG7 is a schematic structural diagram of a driving substrate provided in a fifth embodiment of the present application.
  • FIG. 8 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application.
  • the embodiments of the present application provide a driving substrate and a display panel.
  • the driving substrate can be used for a liquid crystal display panel, an organic light emitting diode display panel, a micro light emitting diode display panel or an electronic paper, etc.
  • the following is a detailed description. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.
  • the first embodiment of the present application provides a driving substrate 100 , which includes a substrate 11 and a thin film transistor structure 12 .
  • the thin film transistor structure 12 is disposed on the substrate 11 .
  • the thin film transistor structure 12 includes an active layer 121 , a gate insulating layer 122 , a gate 123 , a first electrode 124 and a second electrode 125 .
  • the active layer 121 is disposed on the substrate 11.
  • the active layer 121 includes a first contact portion 12a, a transition portion 12b, a channel 12c, and a second contact portion 12d.
  • the transition portion 12b is disposed between the first contact portion 12a and the channel 12c.
  • the second contact portion 12d is disposed on a side of the channel 12c away from the first contact portion 12a.
  • the resistance value of the first contact portion 12a is smaller than the resistance value of the transition portion 12b.
  • the resistance value of the transition portion 12b is smaller than the resistance value of the channel 12c.
  • the gate insulating layer 122 is disposed on the active layer 121.
  • the gate 123 is disposed on the gate insulating layer 122.
  • the gate 123 includes a first portion g1 and a second portion g2 connected to the first portion g1, wherein the first portion g1 overlaps with the channel 12c, and the second portion g2 overlaps with the transition portion 12b.
  • the first portion g1 is used to completely block doped ions
  • the second portion g2 is used to partially transmit the doped ions.
  • the first electrode 124 is connected to the first contact portion 12a, and the second electrode 125 is connected to the second contact portion 12d.
  • the first part g1 of the gate 123 is used to block the channel 12c
  • the second part g2 is used to block the transition part 12b, so that during the ion implantation process, part of the doped ions penetrate through the second part g2 and enter the transition part 12b, while the doped ions corresponding to the channel 12c region are completely blocked by the first part g1. Therefore, in this embodiment, the gate 123 is used as a mask to implement doping of the transition part 12b under the mask. Compared with the prior art using the gate as a mask, the channel 12c of this embodiment can be made narrower, and the stability of the threshold voltage of the thin film transistor is improved.
  • the thickness of the first portion g1 is greater than the thickness of the second portion g2. It is understandable that as the thickness of the film increases, the film layer has a better effect of blocking doped ions. Therefore, in this embodiment, the thinner second portion g2 can be used to achieve under-film ion doping, and the thicker first portion g1 can achieve complete blocking of doped ions.
  • the gate 123 is a single-layer structure.
  • the gate 123 is a single-layer structure, and the first portion g1 and the second portion g2 can be made of the same material or different materials.
  • the first portion g1 and the second portion g2 of the gate 123 are made of the same material, the first portion g1 and the second portion g2 can be formed using a halftone or grayscale mask.
  • the gate 123 of the first embodiment is a single-layer structure, which can simplify the preparation process of the gate 123.
  • the first portion g1 and the second portion g2 of the gate 123 are made of different materials, the first portion g1 and the second portion g2 are formed separately.
  • the thickness of the first portion g1 is greater than or equal to 250 nanometers, and the thickness of the second portion g2 is less than or equal to 100 nanometers and greater than or equal to 10 nanometers.
  • the gate 123 is generally prepared by physical vapor deposition, so the density of the gate 123 is relatively high. Therefore, in the general process, when the thickness of the first part g1 is above 250 nanometers, the doping ions can be prevented from penetrating through the first part g1. When the second part g2 is below 100 nanometers, the permeability of the doping ions can be guaranteed and the doping efficiency can be improved; when the second part g2 is above 10 nanometers, the resistance of the transition part 12b can be prevented from being too low and converging to the first contact part 12a. Therefore, when the resistance value of the transition part 12b is converging to the first contact part 12a, the stability of the threshold voltage of the thin film transistor will be reduced.
  • the thickness of the first portion g1 may be 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm or 1000 nm.
  • the thickness of the second portion g2 may be 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, 20 nm or 10 nm.
  • the material of the gate 123 can be copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), nickel (Ni), zinc (Zn), chromium (Cr), alloys containing any of the above metals or alloys combining any of the above metals.
  • the gate insulating layer 122 is formed of a plurality of inorganic layers stacked in an alternating manner.
  • the gate insulating layer 122 may be formed as a double layer formed by stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide, or a multilayer formed by alternately stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide.
  • the present disclosure is not limited thereto, and the gate insulating layer 122 may be formed as a single inorganic layer including the above insulating materials.
  • the material of the active layer 121 may be formed of single crystal silicon, polycrystalline silicon (poly-Si) or an oxide semiconductor.
  • the oxide semiconductor may include an oxide based on titanium, hafnium, zirconium, aluminum, tantalum, germanium, zinc, gallium, tin or indium and a composite oxide thereof (such as indium gallium zinc oxide, indium zinc oxide, zinc tin oxide, indium gallium oxide, indium tin oxide, indium zirconium oxide, indium zirconium zinc oxide, indium zirconium tin oxide, indium zirconium gallium oxide, indium aluminum oxide, indium zinc aluminum oxide, indium tin aluminum oxide, indium aluminum gallium oxide, indium tantalum oxide, indium tantalum zinc oxide, indium tantalum tin oxide, indium tantalum gallium oxide, indium germanium oxide, indium germanium zinc oxide, indium germanium tin oxide, indium germanium gallium oxide, titanium indium zinc oxide and hafnium in
  • the mass ratio of the doped ions in the first contact portion 12a is greater than the mass ratio of the doped ions in the transition portion 12b.
  • Such a configuration makes the resistance value of the first contact portion 12a smaller than the resistance value of the transition portion 12b.
  • the mass ratio of the doped ions in the second contact portion 12 d is greater than the mass ratio of the doped ions in the transition portion 12 b , so that the resistance value of the second contact portion 12 d is smaller than the resistance value of the transition portion 12 b .
  • the first electrode 124 is used to connect the light-emitting device, and the channel 12c is directly connected to the second contact portion 12d.
  • the driving substrate 100 may further include a buffer layer 126 disposed between the active layer 121 and the substrate 11 .
  • the driving substrate 100 may further include an interlayer dielectric layer 127 and a passivation layer 128, wherein the interlayer dielectric layer 127 covers the gate 123, the active layer 121, and the substrate 11.
  • the first electrode 124 and the second electrode 125 are disposed on the interlayer dielectric layer 127.
  • the first electrode 124 is connected to the first contact portion 12a, and the second electrode 125 is connected to the second contact portion 12d.
  • the passivation layer 128 covers the first electrode 124 and the second electrode 125.
  • the driving substrate 100 may also save the interlayer dielectric layer 127 , that is, the first electrode 124 is directly formed on the first contact portion 12 a , and the second electrode 125 is directly formed on the second contact portion 12 d .
  • the manufacturing process of the driving substrate 100 of the first embodiment is as follows:
  • Step B11 forming a buffer layer 126 , a semiconductor layer 12 k , a gate insulating layer 122 and a gate 123 in sequence on the substrate 11 .
  • the first part g1 and the second part g2 are formed by using a halftone mask, and the thickness of the first part g1 is greater than that of the second part g2.
  • the semiconductor layer 12k includes a channel region corresponding to the first part g1, a transition portion corresponding to the second part g2, and a first electrode region and a second electrode region exposed outside the gate 123.
  • step B12 the first electrode region and the second electrode region of the semiconductor layer 12k are subjected to conductorization treatment using the gate electrode 123 as a mask.
  • the first electrode region and the second electrode region of the semiconductor layer 12k may be bombarded with Ar to form high-concentration oxygen vacancies, thereby achieving conductorization.
  • the square resistance of the first electrode region and the second electrode region of the semiconductor layer 12k is between 300 ohms and 3000 ohms, for example, 300 ohms, 1000 ohms, 2000 ohms or 3000 ohms.
  • step B13 continuing to use the gate 123 as a mask, ion implantation is performed on the first electrode region, the second electrode region and the transition region of the semiconductor layer 12k to form a first contact portion 12a , a via portion 12b , a channel 12c and a second contact portion 12d .
  • the doping ions may be B or P, etc.
  • the doping concentration is between E17 and E22, for example, E17, E18, E19, E20, E21 or E22.
  • step B14 the process proceeds to step B14 to form a first electrode 124 and a second electrode 125 on the substrate.
  • the first electrode 124 is connected to the first contact portion 12 a
  • the second electrode 125 is connected to the second contact portion 12 d .
  • the driving substrate 100 of the second embodiment is different from that of the first embodiment in that another transition portion 12 b is connected between the channel 12 c and the second contact portion 12 d .
  • the gate 123 of the driving substrate 100 of the second embodiment has two second portions g2 to cover the two transition portions 12 b in a one-to-one correspondence.
  • the second embodiment uses two transition portions 12 b to further narrow the length of the channel 12 c and improve the stability of the threshold voltage of the thin film transistor.
  • the driving substrate 100 of the third embodiment is different from any of the above embodiments in that the density of the first portion g1 is greater than the density of the second portion g2 .
  • the thickness of the first part g1 may be equal to the thickness of the second part g2.
  • the density of the film layer can be adjusted by adjusting the parameters of the vapor deposition process, such as adjusting the bombardment energy or deposition rate, etc., which will not be elaborated here.
  • the driving substrate 100 of the fourth embodiment is different from any of the above embodiments in that the gate 123 includes a first metal layer 23a and a second metal layer 23b.
  • the first metal layer 23a is disposed on the gate insulating layer 122.
  • the first metal layer 23a blocks the channel 12c and the transition portion 12b.
  • the second metal layer 23b is disposed on a side of the first metal layer 23a away from the gate insulating layer 122.
  • the second metal layer 23b blocks the channel 12c.
  • the first metal layer 23 a is disposed between the second metal layer 23 b and the gate insulating layer 122 , so as to improve the adhesion between the gate 123 and the gate insulating layer 122 .
  • the thickness of the first metal layer 23a is less than the thickness of the second metal layer 23b.
  • setting a thicker second metal layer 23b can increase the conductivity of the gate 123 and improve the effect of the first portion g1 blocking the penetration of doped ions; setting a thinner first metal layer 23a for passing part of the doped ions, and the area of the first metal layer 23a is larger, which can meet the demand for improving the adhesion of the gate 123.
  • the first metal layer 23a includes at least one of molybdenum and titanium
  • the second metal layer 23b includes at least one of copper and aluminum.
  • the thickness of the first metal layer 23a may be between 10 nanometers and 50 nanometers, such as 10 nanometers, 20 nanometers, 30 nanometers, 40 nanometers or 50 nanometers.
  • the thickness of the second metal layer 23b is between 350 nanometers and 1000 nanometers, for example, 350 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, 800 nanometers, 900 nanometers or 1000 nanometers. If the second metal layer 23b adopts a strengthening process to increase its density, the required thickness of the second metal layer 23b can be further reduced. In addition, the thickness of the second metal layer 23b is less than 1000 nanometers to prevent the gate 123 from being too thick, resulting in too high terrain.
  • the gate 123 may also be a three-layer stacked structure, such as Ti/Al/Ti, Mo/Al/Mo, Ti/Cu/Ti, Mo/Cu/Mo, Mo&Ti/Al/Mo&Ti or Mo&Ti/Cu/Mo&Ti, etc.
  • the driving substrate 100 of the fifth embodiment is different from any of the above embodiments in that the gate 123 includes a first metal layer 23a and a second metal layer 23b.
  • the first metal layer 23a is disposed on the gate insulating layer 122.
  • the first metal layer 23a only blocks the channel 12c.
  • the second metal layer 23b is disposed on a side of the first metal layer 23a away from the gate insulating layer 122.
  • the second metal layer 23b blocks the channel 12c and the transition portion 12b.
  • This embodiment uses a multi-layered gate 123 to facilitate controlling the thickness of the first portion g1 and the second portion g2, so as to achieve precise control of the resistance value of the transition portion 12b.
  • the thickness of the first metal layer 23 a should not be too large, as a too large thickness may lead to the risk of the second metal layer 23 b covering the first metal layer 23 a being broken.
  • the embodiment of the present application further provides a display panel 1000 , which includes the driving substrate 100 according to any one of the above embodiments.
  • the display panel 1000 may be a liquid crystal display panel, an organic light emitting diode display panel, a micro light emitting diode display panel, a quantum dot light emitting diode display panel, or the like.
  • this embodiment is illustrated by taking the display panel 1000 as a micro light emitting diode panel as an example.
  • the display panel 1000 further includes a light emitting device 200 disposed on the driving substrate 100 .
  • the structure of the driving substrate 100 of the display panel 1000 of this embodiment is similar to or the same as the structure of the driving substrate 100 of any of the above embodiments, and will not be described in detail herein.
  • the display panel 1000 of the present embodiment uses the first part g1 of the gate 123 to block the channel 12c, and the second part g2 to block the transition part 12b, so that during the ion implantation process, part of the doped ions penetrate through the second part g2 and enter the transition part 12b, while the doped ions corresponding to the channel 12c region are completely blocked by the first part g1. Therefore, the present embodiment uses the gate 123 as a mask to implement doping of the transition part 12b under the mask. Compared with the prior art using the gate as a mask, the channel 12c of the present embodiment can be made narrower, and the stability of the threshold voltage of the thin film transistor is improved.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请实施例公开了一种驱动基板及显示面板，有源层的过渡部设置在有源层的第一接触部和沟道之间，栅极的第一部分与沟道重叠设置，栅极的第二部分与过渡部重叠设置，栅极的第一部分用于完全阻挡掺杂离子，栅极的第二部分用于透过部分所述掺杂离子；第一电极连接于第一接触部，第二电极连接于第二接触部。

Description

驱动基板及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种驱动基板及显示面板。
 背景技术
薄膜晶体管(Thin Film Transistor，TFT)广泛用于液晶显示装置、有机发光二极管显示装置等中，除此以外，也可以用于微LED显示装置、电子纸等。
TFT中，在沟道区域与漏极区域之间产生高电场，在该部分中，产生热载流子。因热载流子的影响，发生TFT的阈值电压(Vth)变动的问题。该现象可以通过在沟道区域与漏极区域之间形成电阻过渡的轻掺杂漏极( Lightly Doped Drain，LDD)区域来减轻。
在对现有技术的研究和实践过程中，本申请的发明人发现，在顶栅型TFT中，通常以顶栅为掩模，源极区域和漏极区域通过对氧化物半导体进行等离子体处理而形成，LDD区域通过接触SiN膜而形成。也就是说，沟道的长度取决于顶栅的长度。
 发明概述
本申请实施例提供一种驱动基板及显示面板，可以缩窄有源层的沟道长度。
本申请实施例提供一种驱动基板，其包括：
基板；
薄膜晶体管结构，所述薄膜晶体管结构设置在所述基板上，所述薄膜晶体管结构包括：
有源层，所述有源层设置在所述基板上，所述有源层包括第一接触部、过渡部、沟道和第二接触部，所述过渡部设置在所述第一接触部和所述沟道之间，所述第二接触部设置在所述沟道远离所述第一接触部的一侧，所述第一接触部的电阻值小于所述过渡部的电阻值，所述过渡部的电阻值小于所述沟道的电阻值；
栅极绝缘层，所述栅极绝缘层设置在所述有源层上；
栅极，所述栅极设置在所述栅极绝缘层上，所述栅极包括第一部分和连接于所述第一部分的第二部分，所述第一部分与所述沟道重叠设置，所述第二部分与所述过渡部重叠设置，所述第一部分用于完全阻挡掺杂离子，所述第二部分用于透过部分所述掺杂离子；
第一电极和第二电极，所述第一电极连接于所述第一接触部，所述第二电极连接于所述第二接触部。
可选的，在本申请的一些实施例中，所述第一部分的致密度大于所述第二部分的致密度。
可选的，在本申请的一些实施例中，所述第一部分的厚度大于所述第二部分的厚度。
可选的，在本申请的一些实施例中，所述栅极为单膜层结构。
可选的，在本申请的一些实施例中，所述栅极包括第一金属层和第二金属层，所述第一金属层设置在所述栅极绝缘层上，所述第一金属层遮挡所述沟道和所述过渡部，所述第二金属层设置在所述第一金属层远离所述栅极绝缘层的一侧，所述第二金属层遮挡所述沟道。
可选的，在本申请的一些实施例中，所述第一金属层的厚度小于所述第二金属层的厚度。
可选的，在本申请的一些实施例中，所述栅极包括第一金属层和第二金属层，所述第一金属层设置在所述栅极绝缘层上，所述第一金属层仅遮挡所述沟道，所述第二金属层设置在所述第一金属层远离所述栅极绝缘层的一侧，所述第二金属层遮挡所述沟道和所述过渡部。
可选的，在本申请的一些实施例中，所述第一部分的厚度大于或等于250纳米，所述第二部分的厚度小于或等于100纳米且大于或等于10纳米。
可选的，在本申请的一些实施例中，所述掺杂离子占所述第一接触部的质量比大于所述掺杂离子占所述过渡部的质量比。
可选的，在本申请的一些实施例中，所述第一电极用于连接发光器件，所述沟道直接连接所述第二接触部，或所述沟道与所述第二接触部之间连接有另一所述过渡部。
相应的，本申请实施例还提供一种显示面板，其包括上述任意一项实施例所述的驱动基板和设置在所述驱动基板上的发光器件，所述驱动基板包括：
基板；
薄膜晶体管结构，所述薄膜晶体管结构设置在所述基板上，所述薄膜晶体管结构包括：
有源层，所述有源层设置在所述基板上，所述有源层包括第一接触部、过渡部、沟道和第二接触部，所述过渡部设置在所述第一接触部和所述沟道之间，所述第二接触部设置在所述沟道远离所述第一接触部的一侧，所述第一接触部的电阻值小于所述过渡部的电阻值，所述过渡部的电阻值小于所述沟道的电阻值；
栅极绝缘层，所述栅极绝缘层设置在所述有源层上；
栅极，所述栅极设置在所述栅极绝缘层上，所述栅极包括第一部分和连接于所述第一部分的第二部分，所述第一部分与所述沟道重叠设置，所述第二部分与所述过渡部重叠设置，所述第一部分用于完全阻挡掺杂离子，所述第二部分用于透过部分所述掺杂离子；
第一电极和第二电极，所述第一电极连接于所述第一接触部，所述第二电极连接于所述第二接触部。
可选的，在本申请的一些实施例中，所述第一部分的致密度大于所述第二部分的致密度。
可选的，在本申请的一些实施例中，所述第一部分的厚度大于所述第二部分的厚度。
可选的，在本申请的一些实施例中，所述栅极为单膜层结构。
可选的，在本申请的一些实施例中，所述栅极包括第一金属层和第二金属层，所述第一金属层设置在所述栅极绝缘层上，所述第一金属层遮挡所述沟道和所述过渡部，所述第二金属层设置在所述第一金属层远离所述栅极绝缘层的一侧，所述第二金属层遮挡所述沟道。
可选的，在本申请的一些实施例中，所述第一金属层的厚度小于所述第二金属层的厚度。
可选的，在本申请的一些实施例中，所述栅极包括第一金属层和第二金属层，所述第一金属层设置在所述栅极绝缘层上，所述第一金属层仅遮挡所述沟道，所述第二金属层设置在所述第一金属层远离所述栅极绝缘层的一侧，所述第二金属层遮挡所述沟道和所述过渡部。
可选的，在本申请的一些实施例中，所述第一部分的厚度大于或等于250纳米，所述第二部分的厚度小于或等于100纳米且大于或等于10纳米。
可选的，在本申请的一些实施例中，所述掺杂离子占所述第一接触部的质量比大于所述掺杂离子占所述过渡部的质量比。
可选的，在本申请的一些实施例中，所述第一电极用于连接发光器件，所述沟道直接连接所述第二接触部，或所述沟道与所述第二接触部之间连接有另一所述过渡部。
有益效果
本申请实施例提供一种驱动基板，其包括基板和薄膜晶体管结构，薄膜晶体管结构设置在基板上，薄膜晶体管结构包括有源层、栅极绝缘层、栅极、第一电极和第二电极。有源层设置在基板上，有源层包括第一接触部、过渡部、沟道和第二接触部，过渡部设置在第一接触部和沟道之间，第二接触部设置在沟道远离第一接触部的一侧，第一接触部的电阻值小于过渡部的电阻值，过渡部的电阻值小于沟道的电阻值；栅极绝缘层设置在有源层上；栅极设置在栅极绝缘层上，栅极包括第一部分和连接于第一部分的第二部分，第一部分与沟道重叠设置，第二部分与过渡部重叠设置，第一部分用于完全阻挡掺杂离子，第二部分用于透过部分所述掺杂离子；第一电极连接于第一接触部，第二电极连接于第二接触部。
本实施例采用栅极的第一部分遮挡沟道，第二部分遮挡过渡部，使得在进行离子注入工艺中，使得部分的掺杂离子渗透过第二部分进入过渡部，而对应于沟道区域的掺杂离子被第一部分完全阻挡。故本实施例采用栅极作为掩模实现掩模下过渡部的掺杂，相较于以栅极作为掩模的现有技术，本实施例的沟道可以做到更窄，且提高薄膜晶体管阈值电压的稳定性。
 附图说明
图1是本申请第一实施例提供的驱动基板的结构示意图；
图2是本申请第一实施例提供的驱动基板的制备方法的步骤B12的示意图；
图3是本申请第一实施例提供的驱动基板的制备方法的步骤B13的示意图；
图4是本申请第二实施例提供的驱动基板的结构示意图；
图5是本申请第三实施例提供的驱动基板的结构示意图；
图6是本申请第四实施例提供的驱动基板的结构示意图；
图7为本申请第五实施例提供的驱动基板的结构示意图；
图8为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
本申请实施例提供一种驱动基板及显示面板，需要说明的是，驱动基板可以用于液晶显示面板、有机发光二极管显示面板、微型发光二极管显示面板或电子纸等。下文进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参照图1，本申请第一实施例提供一种驱动基板100，其包括基板11和薄膜晶体管结构12。薄膜晶体管结构12设置在基板11上。
薄膜晶体管结构12包括有源层121、栅极绝缘层122、栅极123、第一电极124和第二电极125。
有源层121设置在基板11上。有源层121包括第一接触部12a、过渡部12b、沟道12c和第二接触部12d。过渡部12b设置在第一接触部12a和沟道12c之间。第二接触部12d设置在沟道12c远离第一接触部12a的一侧。第一接触部12a的电阻值小于过渡部12b的电阻值。过渡部12b的电阻值小于沟道12c的电阻值。
栅极绝缘层122设置在有源层121上。栅极123设置在栅极绝缘层122上。
栅极123包括第一部分g1和连接于第一部分g1的第二部分g2，第一部分g1与沟道12c重叠设置。第二部分g2与过渡部12b重叠设置。第一部分g1用于完全阻挡掺杂离子。第二部分g2用于透过部分所述掺杂离子。
第一电极124连接于第一接触部12a。第二电极125连接于第二接触部12d。
本实施例采用栅极123的第一部分g1遮挡沟道12c，第二部分g2遮挡过渡部12b，使得在进行离子注入工艺中，使得部分的掺杂离子渗透过第二部分g2进入过渡部12b，而对应于沟道12c区域的掺杂离子被第一部分g1完全阻挡。故本实施例采用栅极123作为掩模实现掩模下过渡部12b的掺杂，相较于以栅极作为掩模的现有技术，本实施例的沟道12c可以做到更窄，且提高薄膜晶体管阈值电压的稳定性。
可选的，在第一实施例中，第一部分g1的厚度大于第二部分g2的厚度。可以理解的是，随着膜层厚度的增大，膜层阻挡掺杂离子的效果就越好，故本实施例可通过较薄的第二部分g2实现膜下离子掺杂，较厚的第一部分g1实现掺杂离子的完全阻挡。
可选的，栅极123为单膜层结构。
需要说明的是，栅极123为单膜层结构，第一部分g1和第二部分g2可以是由相同材料制备形成，也可以有不同材料制备形成。
当栅极123的第一部分g1和第二部分g2由相同的材料制备形成时，第一部分g1和第二部分g2的形成可采用半色调或灰度掩模板实现。本第一实施例的栅极123为单膜层结构，可简化栅极123的制备过程。
当栅极123的第一部分g1和第二部分g2由不同的材料制备形成时，则第一部分g1和第二部分g2各自单独形成。
可选的，第一部分g1的厚度大于或等于250纳米。第二部分g2的厚度小于或等于100纳米且大于或等于10纳米。
可以理解的是，在面板用途的驱动基板中，栅极123一般采用物理气相沉积法制备，故栅极123的致密性相对较高。故在一般制程中，当第一部分g1的厚度在250纳米以上时，则可以避免掺杂离子渗透过第一部分g1。而第二部分g2在100纳米以下，可保证掺杂离子的渗透率，提高掺杂效率；第二部分g2在10纳米以上，可避免过渡部12b的电阻过低而趋同于第一接触部12a，因此当过渡部12b的电阻值趋同于第一接触部12a时，会降低薄膜晶体管阈值电压的稳定性。
可选的，第一部分g1的厚度可以是250纳米、300纳米、350纳米、400纳米、450纳米、500纳米、550纳米、600纳米、650纳米、700纳米、750纳米、800纳米、850纳米、900纳米、950纳米或1000纳米。第二部分g2的厚度可以是100纳米、90纳米、80纳米、70纳米、60纳米、50纳米、40纳米、30纳米、20纳米或10纳米。
可选的，栅极123的材料可以是铜（Cu）、铝（Al）、钼（Mo）、钛（Ti）、镍（Ni）、锌（Zn）、铬（Cr），以及上述任意金属为成分的合金或者组合上述任意金属的合金等形式。
可选的，栅极绝缘层122由以交替的方式堆叠的多个无机层形成。例如，栅极绝缘层122可以形成为通过堆叠包括氧化硅、氮化硅、氮氧化硅、氧化铝、氧化镁和氧化钛中的至少一种的无机层而形成的双层，或者通过交替堆叠包括氧化硅、氮化硅、氮氧化硅、氧化铝、氧化镁和氧化钛中的至少一种的无机层而形成的多层。然而，本公开不限于此，栅极绝缘层122可以形成为包含上述绝缘材料的单层无机层。
可选的，有源层121的材料可以由单晶硅、多晶硅(poly-Si)或氧化物半导体形成。氧化物半导体可以包括基于钛、铪、锆、铝、钽、锗、锌、镓、锡或铟的氧化物以及它们的复合氧化物(诸如铟镓锌氧化物、铟锌氧化物、锌锡氧化物、铟镓氧化物、铟锡氧化物、铟锆氧化物、铟锆锌氧化物、铟锆锡氧化物、铟锆镓氧化物、铟铝氧化物、铟锌铝氧化物、铟锡铝氧化物、铟铝镓氧化物、铟钽氧化物、铟钽锌氧化物、铟钽锡氧化物、铟钽镓氧化物、铟锗氧化物、铟锗锌氧化物、铟锗锡氧化物、铟锗镓氧化物、钛铟锌氧化物和铪铟锌氧化物)中的一种。
可选的，掺杂离子占第一接触部12a的质量比大于掺杂离子占过渡部12b的质量比。这样的设置使得第一接触部12a的电阻值小于过渡部12b的电阻值。
另外，掺杂离子占第二接触部12d的质量比大于掺杂离子占过渡部12b的质量比，以使第二接触部12d的电阻值小于过渡部12b的电阻值。
可选的，在本第一实施例中，第一电极124用于连接发光器件，沟道12c直接连接第二接触部12d。
可选的，驱动基板100还可以包括缓冲层126，缓冲层126设置在有源层121和基板11之间。
可选的，驱动基板100还可以包括层间介质层127和钝化层128，层间介质层127覆盖栅极123、有源层121和基板11。第一电极124和第二电极125设置在层间介质层127上。第一电极124连接于第一接触部12a，第二电极125连接于第二接触部12d。钝化层128覆盖第一电极124和第二电极125。
在一些实施例中，驱动基板100也可以节省层间介质层127，也即第一电极124直接形成在第一接触部12a上，第二电极125直接在第二接触部12d上。
本第一实施例的驱动基板100的制备过程如下：
步骤B11，在基板11上依次形成缓冲层126、半导体层12k、栅极绝缘层122和栅极123。
其中，采用半色调掩模板形成第一部分g1和第二部分g2，第一部分g1的厚度大于第二部分g2的厚度。半导体层12k包括对应于第一部分g1的沟道区域、对应于第二部分g2的过渡部分和裸露在栅极123之外的第一电极区和第二电极区。
随后转入步骤B12。
请参照图2，步骤B12，以栅极123为掩模，对所述半导体层12k的第一电极区和第二电极区进行导体化处理。可选的，可通过Ar轰击半导体层12k的第一电极区和第二电极区，形成高浓度的氧空位，进而实现导体化。此时半导体层12k的第一电极区和第二电极区的方阻在300欧姆~3000欧姆之间，比如可以是300欧姆、1000欧姆、2000欧姆或3000欧姆。
随后转入步骤B13。
请参照图3，步骤B13，继续以栅极123为掩模，对半导体层12k的第一电极区、第二电极区和过渡区进行离子注入处理，以形成第一接触部12a、过部12b、沟道12c和第二接触部12d。
可选的，掺杂离子可以是B或P等。掺杂浓度在E17~E22之间，比如可以是E17、E18、 E19、E20、E21或E22。
随后转入步骤B14，在基板上形成第一电极124和第二电极125，第一电极124连接于第一接触部12a，第二电极125连接于第二接触部12d。
这样便完成了本第一实施例的驱动基板100的部分制备过程。
请参照图4，本第二实施例的驱动基板100与第一实施例的不同之处在于，沟道12c与第二接触部12d之间连接有另一过渡部12b。
也就是说，相较于第一实施例的驱动基板100，本第二实施例的驱动基板100的栅极123具有两个第二部分g2以一一对应遮挡两个过渡部12b。
本第二实施例采用两个过渡部12b相较于第一实施例，进一步缩窄沟道12c长度，且提高了薄膜晶体管阈值电压的稳定性。
请参照图5，本第三实施例的驱动基板100与上述任一实施例的不同之处在于，第一部分g1的致密度大于第二部分g2的致密度。
可选的，第一部分g1的厚度可等于第二部分g2的厚度。其中，膜层的致密度可通过调整气相沉积工艺的参数进行调节，比如可调整轰击能量的大小或沉积速率等等，此处不再详细阐述。
请参照图6，第四实施例的驱动基板100与上述任一实施例的不同之处在于：栅极123包括第一金属层23a和第二金属层23b。第一金属层23a设置在栅极绝缘层122上。第一金属层23a遮挡沟道12c和过渡部12b。第二金属层23b设置在第一金属层23a远离栅极绝缘层122的一侧。第二金属层23b遮挡沟道12c。
可选的，第一金属层23a设置在第二金属层23b和栅极绝缘层122之间，提高了栅极123和栅极绝缘层122的附着力。
可选的，第一金属层23a的厚度小于第二金属层23b的厚度。其中，在一定的厚度限定下，由于第一金属层23a的导电率小于第二金属层23b的导电率，设置较厚的第二金属层23b可增加栅极123的导电性能，且提高第一部分g1阻挡掺杂离子渗透的效果；设置较薄的第一金属层23a用于透过部分的掺杂离子，且第一金属层23a的面积较大，可满足提高栅极123附着力的需求。
可选的，第一金属层23a包括钼和钛中的至少一种，第二金属层23b包括铜和铝中的至少一种。
比如，当第一金属层23a的材料为钛或钼钛合金时，第一金属层23a的厚度可介于10纳米至50纳米之间，比如可以是10纳米、20纳米、30纳米、40纳米或50纳米。
当第二金属层23b的材料为铜或铝时，第二金属层23b的厚度介于350纳米至1000纳米之间，比如可以是350纳米、400纳米、500纳米、600纳米、700纳米、800纳米、900纳米或1000纳米。若第二金属层23b采用加强工艺增加其致密度，则第二金属层23b需求的厚度可以进一步缩小。另外，第二金属层23b的厚度小于1000纳米，是为避免栅极123过厚，导致地势过高。
在一些实施例中，栅极123也可以是三层堆叠结构，比如Ti/Al/Ti 、Mo/Al/Mo、Ti/Cu/Ti 、Mo/ Cu /Mo、Mo&Ti/Al/ Mo&Ti 或Mo&Ti /Cu/ Mo&Ti 等。
请参照图7，本第五实施例的驱动基板100与上述任一实施例的不同之处在于：栅极123包括第一金属层23a和第二金属层23b。第一金属层23a设置在栅极绝缘层122上。第一金属层23a仅遮挡沟道12c。第二金属层23b设置在第一金属层23a远离栅极绝缘层122的一侧。第二金属层23b遮挡沟道12c和过渡部12b。
本实施例采用多层结构的栅极123，便于控制第一部分g1和第二部分g2的厚度，以达到精准调控过渡部12b的电阻值。
需要说明的是，在本实施例中，第一金属层23a的厚度不宜过大，过大会导致覆盖第一金属层23a的第二金属层23b出现断裂的风险。
请参照图8，相应的，本申请实施例还提供一种显示面板1000，其包括上述任意一项实施例驱动基板100。
可选的，显示面板1000可以是液晶显示面板、有机发光二极管显示面板、微型发光二极管显示面板或量子点发光二极管显示面板等。
如图8所示，本实施例以显示面板1000为微型发光二极管面板为例进行示意。
显示面板1000还包括设置在驱动基板100上的发光器件200。
本实施例的显示面板1000的驱动基板100的结构与上述任一项实施例的驱动基板100的结构相似或相同，此处不再赘述。
本实施例的显示面板1000采用栅极123的第一部分g1遮挡沟道12c，第二部分g2遮挡过渡部12b，使得在进行离子注入工艺中，使得部分的掺杂离子渗透过第二部分g2进入过渡部12b，而对应于沟道12c区域的掺杂离子被第一部分g1完全阻挡。故本实施例采用栅极123作为掩模实现掩模下过渡部12b的掺杂，相较于以栅极作为掩模的现有技术，本实施例的沟道12c可以做到更窄，且提高薄膜晶体管阈值电压的稳定性。
以上对本申请实施例所提供的一种驱动基板及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种驱动基板，其包括：
    基板；
    薄膜晶体管结构，所述薄膜晶体管结构设置在所述基板上，所述薄膜晶体管结构包括：
    有源层，所述有源层设置在所述基板上，所述有源层包括第一接触部、过渡部、沟道和第二接触部，所述过渡部设置在所述第一接触部和所述沟道之间，所述第二接触部设置在所述沟道远离所述第一接触部的一侧，所述第一接触部的电阻值小于所述过渡部的电阻值，所述过渡部的电阻值小于所述沟道的电阻值；
    栅极绝缘层，所述栅极绝缘层设置在所述有源层上；
    栅极，所述栅极设置在所述栅极绝缘层上，所述栅极包括第一部分和连接于所述第一部分的第二部分，所述第一部分与所述沟道重叠设置，所述第二部分与所述过渡部重叠设置，所述第一部分用于完全阻挡掺杂离子，所述第二部分用于透过部分所述掺杂离子；
    第一电极和第二电极，所述第一电极连接于所述第一接触部，所述第二电极连接于所述第二接触部。
  2. 根据权利要求1所述的驱动基板，其中，所述第一部分的致密度大于所述第二部分的致密度。
  3. 根据权利要求2所述的驱动基板，其中，所述第一部分的厚度大于所述第二部分的厚度。
  4. 根据权利要求3所述的驱动基板，其中，所述栅极为单膜层结构。
  5. 根据权利要求3所述的驱动基板，其中，所述栅极包括第一金属层和第二金属层，所述第一金属层设置在所述栅极绝缘层上，所述第一金属层遮挡所述沟道和所述过渡部，所述第二金属层设置在所述第一金属层远离所述栅极绝缘层的一侧，所述第二金属层遮挡所述沟道。
  6. 根据权利要求5所述的驱动基板，其中，所述第一金属层的厚度小于所述第二金属层的厚度。
  7. 根据权利要求3所述的驱动基板，其中，所述栅极包括第一金属层和第二金属层，所述第一金属层设置在所述栅极绝缘层上，所述第一金属层仅遮挡所述沟道，所述第二金属层设置在所述第一金属层远离所述栅极绝缘层的一侧，所述第二金属层遮挡所述沟道和所述过渡部。
  8. 根据权利要求3所述的驱动基板，其中，所述第一部分的厚度大于或等于250纳米，所述第二部分的厚度小于或等于100纳米且大于或等于10纳米。
  9. 根据权利要求1所述的驱动基板，其中，所述掺杂离子占所述第一接触部的质量比大于所述掺杂离子占所述过渡部的质量比。
  10. 根据权利要求1所述的驱动基板，其中，所述第一电极用于连接发光器件，所述沟道直接连接所述第二接触部，或所述沟道与所述第二接触部之间连接有另一所述过渡部。
  11. 一种显示面板，其包括驱动基板和设置在所述驱动基板上的发光器件，所述驱动基板包括：
    基板；
    薄膜晶体管结构，所述薄膜晶体管结构设置在所述基板上，所述薄膜晶体管结构包括：
    有源层，所述有源层设置在所述基板上，所述有源层包括第一接触部、过渡部、沟道和第二接触部，所述过渡部设置在所述第一接触部和所述沟道之间，所述第二接触部设置在所述沟道远离所述第一接触部的一侧，所述第一接触部的电阻值小于所述过渡部的电阻值，所述过渡部的电阻值小于所述沟道的电阻值；
    栅极绝缘层，所述栅极绝缘层设置在所述有源层上；
    栅极，所述栅极设置在所述栅极绝缘层上，所述栅极包括第一部分和连接于所述第一部分的第二部分，所述第一部分与所述沟道重叠设置，所述第二部分与所述过渡部重叠设置，所述第一部分用于完全阻挡掺杂离子，所述第二部分用于透过部分所述掺杂离子；
    第一电极和第二电极，所述第一电极连接于所述第一接触部，所述第二电极连接于所述第二接触部。
  12. 根据权利要求11所述的显示面板，其中，所述第一部分的致密度大于所述第二部分的致密度。
  13. 根据权利要求11所述的显示面板，其中，所述第一部分的厚度大于所述第二部分的厚度。
  14. 根据权利要求13所述的显示面板，其中，所述栅极为单膜层结构。
  15. 根据权利要求13所述的显示面板，其中，所述栅极包括第一金属层和第二金属层，所述第一金属层设置在所述栅极绝缘层上，所述第一金属层遮挡所述沟道和所述过渡部，所述第二金属层设置在所述第一金属层远离所述栅极绝缘层的一侧，所述第二金属层遮挡所述沟道。
  16. 根据权利要求15所述的显示面板，其中，所述第一金属层的厚度小于所述第二金属层的厚度。
  17. 根据权利要求13所述的显示面板，其中，所述栅极包括第一金属层和第二金属层，所述第一金属层设置在所述栅极绝缘层上，所述第一金属层仅遮挡所述沟道，所述第二金属层设置在所述第一金属层远离所述栅极绝缘层的一侧，所述第二金属层遮挡所述沟道和所述过渡部。
  18. 根据权利要求13所述的显示面板，其中，所述第一部分的厚度大于或等于250纳米，所述第二部分的厚度小于或等于100纳米且大于或等于10纳米。
  19. 根据权利要求11所述的显示面板，其中，所述掺杂离子占所述第一接触部的质量比大于所述掺杂离子占所述过渡部的质量比。
  20. 根据权利要求11所述的显示面板，其中，所述第一电极用于连接发光器件，所述沟道直接连接所述第二接触部，或所述沟道与所述第二接触部之间连接有另一所述过渡部。
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