Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/435—Cross-sectional shapes or dispositions of interconnections

Definitions

• the present invention relates to a memory device using semiconductor elements.
• LSI Large Scale Integration
• the channel In a normal planar MOS transistor, the channel extends horizontally along the upper surface of the semiconductor substrate. In contrast, the channel of an SGT extends perpendicular to the upper surface of the semiconductor substrate (see, for example, Patent Document 1 and Non-Patent Document 1). For this reason, SGTs allow for higher density semiconductor devices compared to planar MOS transistors.
• this SGT As a selection transistor, it is possible to achieve high integration of DRAM (Dynamic Random Access Memory, see Non-Patent Document 2) connected to a capacitor, PCM (Phase Change Memory, see Non-Patent Document 3) connected to a resistive variable element, RRAM (Resistive Random Access Memory, see Non-Patent Document 4), and MRAM (Magneto-resistive Random Access Memory, see Non-Patent Document 5) that changes resistance by changing the direction of magnetic spins using electric current.
• DRAM Dynamic Random Access Memory
• PCM Phase Change Memory
• RRAM Resistive Random Access Memory
• MRAM Magnetic-resistive Random Access Memory
• DRAM memory cells that do not have a capacitor and are composed of a single MOS transistor. For example, holes and electrons generated in the channel by the impact ionization phenomenon caused by the source-drain current of an N-channel MOS transistor are retained in the channel as some or all of the holes, and logical memory data "1" is written. Then, the holes are removed from the channel and logical memory data "0" is written.
• the issues with this memory cell are how to improve the decrease in operating margin caused by floating body channel voltage fluctuations, and how to improve the decrease in data retention characteristics caused by the removal of some of the holes, which are the signal charges stored in the channel.
• Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in an SOI layer (see, for example, Patent Documents 2 and 3, and Non-Patent Document 11).
• DFM dynamic flash memory
• Non-Patent Document 12 the carrier concentration in the floating body is changed by manipulating the voltage of the four electrodes to create a conductive or non-conductive state, and memory operation is performed.
• Patent Document 4 a structure in which a body that accumulates carriers is connected to the bottom of the MOS transistor has been proposed (see Patent Document 4), and there is a demand for high integration and high performance in this memory.
• This application relates to a memory device using semiconductor elements that can be composed of only MOS transistors without a resistance change element or capacitor.
• the objective of the present invention is to provide a memory element that has a MOS transistor that writes and reads data, and a MOS structure connected to the substrate of the MOS transistor, and that stores signal charges that become memory data "1" and "0", with high accuracy, high integration, and low cost.
• a memory device using a semiconductor element comprises: a first semiconductor region; a first impurity region on the first semiconductor region; a second semiconductor region extending in a vertical direction in contact with the first impurity region and having a concave vertical cross section of a surface; a first gate insulating layer covering a portion of the second semiconductor region; a first gate conductor layer in contact with the first gate insulating layer; a second gate insulating layer having a concave vertical cross section formed along at least the concave portion of the second semiconductor region; a second gate conductor layer formed inside the recess of the second gate insulating layer; a second impurity region and a third impurity region formed so as to be in contact with an upper surface of a protruding portion of the recess of the third semiconductor region, an upper surface of the second gate conductor layer is located lower than upper surfaces of the second impurity region and the third impurity region; It is characterized by:
• the second invention is the first invention described above, characterized in that the second impurity region and the third impurity region are in contact with a second gate insulating layer.
• the third invention is characterized in that in the first invention, either or both of the contact surface between the second semiconductor region and the second impurity region and the contact surface between the second semiconductor region and the third impurity region are located higher than the bottom of the second gate insulating layer.
• the fourth invention is the first invention described above, characterized in that there is a portion in the horizontal direction between the second impurity region and the third impurity region where only an insulating layer exists.
• the fifth invention is the first invention, characterized in that the minimum distance between the second impurity region and the third impurity region is longer than the horizontal length of the vertical cross section of the second gate conductor layer.
• the sixth invention is the first invention, characterized in that the majority carriers in the first impurity region are different from the majority carriers in the first semiconductor region.
• the seventh invention is the first invention, characterized in that the majority carriers in the second semiconductor region are the same as the majority carriers in the first semiconductor region.
• the eighth invention is the first invention, characterized in that the majority carriers in the second impurity region and the third impurity region are the same as the majority carriers in the first impurity region.
• the ninth invention is the first invention described above, characterized in that the first impurity region is shared by a plurality of adjacent memory cells.
• the tenth invention is the first invention, characterized in that the second impurity region or the third impurity region is shared by a plurality of adjacent memory cells.
• the eleventh invention is the first invention described above, characterized in that the top surface of the first impurity region is located higher than the top surface of the first gate insulating layer in the vertical direction.
• the twelfth invention is the first invention, characterized in that the bottom surfaces of the second impurity region and the third impurity region are located higher in the vertical direction than the top surface of the first gate conductor layer.
• the thirteenth invention is the first invention described above, characterized in that the threshold voltage of a MOS transistor consisting of the second semiconductor region, the second impurity region, the third impurity region, the second gate insulating layer, and the second gate conductor layer is changed by changing the voltage applied to the first gate conductor layer.
• the second invention is the above-mentioned first invention, a first wiring conductor layer connected to the second impurity region; a second wiring conductor layer connected to the third impurity region; a third wiring conductor layer connected to the second gate conductor layer; a fourth wiring conductor layer connected to the first gate conductor layer; a fifth wiring conductor layer connected to the first impurity region; a memory write operation is performed by controlling voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the fifth wiring conductor layer to generate electron groups and positive hole groups in the third semiconductor region and the second semiconductor region by an impact ionization phenomenon or a gate induced drain leakage current caused by a current flowing between the third impurity region and the fourth impurity region, removing minority carriers in the third semiconductor region and the second semiconductor region from the generated electron groups and positive hole groups, and causing a part or all of the majority carriers in the third semiconductor region and the second semiconductor region to remain in the third semiconductor region and the
• the 15th invention is the 14th invention, characterized in that the first wiring conductor layer connected to the third impurity region is a source line, the second wiring conductor layer connected to the fourth impurity region is a bit line, the third wiring conductor layer connected to the second gate conductor layer is a word line, the fourth wiring conductor layer connected to the first gate conductor layer is a plate line, and the fifth wiring conductor layer is a control line, and the memory write operation and the memory erase operation are performed by applying voltages to the source line, bit line, plate line, word line, and control line, respectively.
• 1 is a diagram showing a cross-sectional structure of a memory device using a semiconductor element according to a first embodiment
• 1A to 1C are diagrams for explaining the accumulation of hole carries and the cell current during a write operation of the memory device using the semiconductor element according to the first embodiment.
• 4A to 4C are diagrams illustrating an erase operation of a memory device using a semiconductor device according to a first embodiment
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• 13A to 13C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment.
• FIG. 1(a) shows the vertical cross-sectional structure of a memory using a semiconductor element according to the first embodiment of the present invention.
• a p-layer 1 an example of the "first semiconductor region” in the claims
• silicon having p-type conductivity containing acceptor impurities.
• n-layer 3 an example of the "first impurity region” in the claims
• donor impurities In contact with a part of it is a columnar p-layer 4 (an example of the "second semiconductor region” in the claims) containing acceptor impurities, with a rectangular horizontal cross section and a concave upper surface.
• first gate insulating layer 11 (an example of the "first gate insulating layer” in the claims) covering the p-layer 1, the n-layer 3, and a part of the p-layer 4.
• first gate conductor layer 21 (an example of the "first gate conductor layer” in the claims) is in contact with the first gate insulating layer 11.
• n+ layers 5a an example of the "second impurity region” in the claims
• n+ layers 5b an example of the "third impurity region” in the claims
• the semiconductor region containing a high concentration of donor impurities will be referred to as the "n+ layer”
• a second gate insulating layer 13 (an example of the "second gate insulating layer” in the claims) also has a concave upper portion along the upper surface of the concave portion of the p-layer 4 and along parts of the n+ layers 5a and 5b. This gate insulating layer 13 is in contact with the n+ layers 5a and 5b, respectively.
• a second gate conductor layer 22 (an example of the "second gate conductor layer” in the claims) is located inside the concave upper portion of the gate insulating layer 13. The upper surface of this gate conductor layer 22 is located lower than the upper surface of the n+ layer 5a or n+ layer 5b. This is to ensure that if an inversion layer is formed in a MOSFET having the gate conductor layer 22 and the gate insulating layer 13, it will be connected to the n+ layer 5a or n+ layer 5b.
• the upper part of the gate conductor layer 22 is covered with an insulating layer 15, but from here on, the gate insulating layer 13 and the insulating layer 15 may be collectively referred to as the gate insulating layer 13.
• the upper part of the gate conductor layer 22 is covered with an insulating layer 15 for electrical isolation from the wiring above it.
• the n+ layer 5b is connected to the source line SL (an example of the "source line” in the claims) which is the first wiring conductive layer
• the n+ layer 5a is connected to the bit line BL (an example of the "bit line” in the claims) which is the second wiring conductive layer
• the gate conductor layer 22 is connected to the word line WL (an example of the "word line” in the claims) which is the third wiring conductive layer
• the gate conductor layer 21 is connected to the plate line PL (an example of the "plate line” in the claims) which is the fourth wiring conductive layer
• the n layer 3 is connected to the control line CDC (an example of the "control line” in the claims) which is the fifth wiring conductive layer.
• the memory is operated by manipulating the voltages applied to the source line SL, bit line BL, plate line BL, word line WL, and control line CDC.
• the concave shapes of the vertical cross section of the p-layer 4 are shown as straight lines, but they may be U-shaped or semi-elliptical in shape, with curved corners or vertical cross section. Accordingly, the surface of the p-layer 4 is curved.
• the bottom surfaces of the second gate insulating layer 13 and the second gate conductor layer 22, which are formed along this line, may also have curved shapes.
• the memory cell is described as having a rectangular vertical cross-sectional structure of the p-layer 4 relative to the page, but it may be a trapezoid, polygon, circle, or ellipse.
• the n+ layer 5a connected to the source line and the n+ layer 5b connected to the bit line BL are in contact with each other on the top surface of the p layer 4, but they may also be in contact with each other on the side of the p layer 4. They may also be in contact with each other on both the top surface and the side surface.
• the first semiconductor region 1 is a p-type semiconductor, but the memory can also operate by using an n-type semiconductor substrate as another semiconductor substrate, forming a p-well, and using this as the first semiconductor region 1 to place the memory cell of the present invention.
• the top of the n-layer 3 may be at the same level as or higher than the bottom of the gate conductor layer 21.
• the n-layer 3 is electrically connected to an inversion layer that is formed at the interface between the p-layer 4 and the gate insulating layer 11 when a positive voltage is applied to the gate conductor layer 21.
• the n-layer 3 may be located over the entire surface of the memory cell region in a plan view, or may be located in only a part of the memory cell region.
• the n-layer 3 may be formed by an n-well in the p-layer 1.
• the gate insulating layer 11 is described as being integrated at the bottom and the inner side of the gate conductor layer 21, but the insulating layer may be formed separately for the part that contacts the bottom of the gate conductor layer 21 and the part that contacts the inner side. In this case, the thickness of the gate insulating layer 11 may differ depending on the part.
• the p-layer 4 is a p-type semiconductor, but the optimum impurity concentration of the p-layer 4 is determined by the volume of the p-layer 4, the thickness of the first gate insulating layer 11, the material of the first gate conductor layer 21, and the amount of surplus holes stored in the memory, which are parameters such as the applied voltage.
• the p-layer 4 may have a profile, and depending on the material and thickness of the gate insulating layer 13 and the material of the gate conductor layer 22, the surface vicinity of the p-layer 4 may be any of the p-type, n-type, or i-type types.
• any material can be used to support the p-layer 1, whether it is an insulator, semiconductor, or conductor, underneath the p-layer 1.
• the present invention can also be applied when memory components such as the substrate 1, p-layer 4, and gate conductor layers 21 and 22 are first formed by extending them horizontally onto a separate support substrate.
• an LDD (Lightly Doped Drain) region having a donor concentration lower than the donor impurity concentration of the n+ layers 5a and 5b may be provided between the p-layer 4 and the n+ layers 5a and 5b.
• first through fifth wiring conductive layers may be formed in multiple layers as long as they do not contact each other.
• the gate insulating layers 11 and 13 can be made of any insulating film used in normal MOS processes, such as a SiO2 film, a SiON film, a HfSiON film, or a laminated film of SiO2/SiN.
• the first gate conductor layer 21 can change the potential of a portion of the memory cell via the gate insulating layer 11
• the second gate conductor layer 22 can change the potential of a portion of the memory cell via the gate insulating layer 13
• they may be made of metals such as W, Pd, Ru, Al, TiN, TaN, and WN, metal nitrides, or alloys thereof (including silicides), such as a layered structure such as TiN/W/TaN, or may be made of a highly doped semiconductor.
• the first gate conductor layer 21 may surround the entire p-layer 4 via the insulating layer 11 in a plan view, or may cover a portion of it.
• the first gate conductor layer 21 may be divided into multiple pieces in a plan view.
• the first gate conductor layer 21 may also be divided into multiple pieces in the vertical direction.
• the first gate conductor layer 21 is present on both sides of the p-layer 4, but the memory of the present invention can operate if it is present on either side.
• n+ layer 5a and n+ layer 5b are formed from a p+ layer semiconductor region containing a high concentration of acceptor impurities, in which holes are the majority carriers, if an n-type semiconductor is used for p layer 1 and p layer 4, and a p-type semiconductor is used for n layer 3, the memory of the present invention will operate with electrons as the write carriers.
• one or more of the above-mentioned memory cells are arranged two-dimensionally on the p-layer 1.
• the majority carriers in the n layer 3, n+ layer 5a, and n+ layer 5b are electrons, and for example, poly-Si containing a high concentration of donor impurities is used for the gate conductor layer 21 connected to the plate line PL and the gate conductor layer 22 connected to the word line WL (hereinafter, poly-Si containing a high concentration of donor impurities is referred to as "n+poly"), and a p-type semiconductor is used as the second semiconductor region 4. As shown in FIG.
• the MOSFET in this memory cell operates with the n+ layer 5a as the source, the n+ layer 5b as the drain, the gate insulating layer 13, the gate conductor layer 22 as the gate, and the p layer 4 as the substrate as its components.
• 0V is applied to the p-layer 1
• 0.5V is applied to the n-layer 3 connected to the control line CDC
• 0V is input to the n+ layer 5b connected to the source line SL
• 1.0V is input to the n+ layer 5a connected to the bit line BL
• -1V is applied to the gate conductor layer 21 connected to the plate line PL.
• the threshold of the MOSFET with the gate conductor layer 22 as the gate electrode before writing is set to 1.0V when the voltage of the plate line PL is -1V.
• a partial inversion layer 62 is formed directly under the gate insulating layer 13 below the gate conductor layer 22, and a pinch-off point 63 exists.
• the MOSFET having the gate conductor layer 22 operates in the saturation region.
• the electric field becomes maximum between the pinch-off point 63 and the n+ layer 5a in the MOSFET having the gate conductor layer 22, and impact ionization occurs in this region.
• This impact ionization causes electrons accelerated from the n+ layer 5b connected to the source line SL toward the n+ layer 5a connected to the bit line BL to collide with the Si lattice, and the kinetic energy creates electron-hole pairs.
• the created holes diffuse toward the area with the lower hole concentration due to the concentration gradient. As a result, a group of holes 64 accumulates in the p layer 4.
• the plate line PL is set to -1V, which prevents the depletion layer from spreading into the p-layer 4, helping to accumulate holes generated by impact ionization and to adjust the threshold voltage of the MOSFET in the memory cell through the substrate bias effect.
• n+poly is used for the gate conductor layer 21 to bias a negative voltage, but by using a material with a higher work function than n+poly as the material for the gate conductor layer 21, it is possible to achieve the same effect as applying a negative voltage without applying a voltage.
• the width of the p-layer 4 is made wider than the width of the second gate conductor layer 22 in a plan view to increase the amount of excess holes that can be accumulated.
• a gate-induced drain leakage (GIDL) current may be passed to generate a group of holes (see, for example, Non-Patent Document 7).
• FIG. 2(b) shows a group of holes 64 in the p-layer 4 immediately after writing when the plate line PL is -1V, the word line WL, source line SL, and bit line BL are biased to 0V, and the control line CDC is biased to 0.5V.
• the generated group of holes 64 move uniformly in the p-layer 4 by diffusion due to the difference in carrier concentration.
• the p-layer 4 is accumulated in a higher concentration near the first gate insulating layer 11.
• the threshold voltage of the MOSFET having the gate conductor layer 22 is lowered by the positive substrate bias effect due to the holes temporarily accumulated in the p-layer 4.
• the threshold voltage of the MOSFET having the gate conductor layer 22 connected to the word line WL is about 0.6V, which is lower than before writing. This write state is assigned to the logical memory data "1".
• the voltage application conditions can be combinations such as 1.0V (V-BL)/-1V (V-PL)/2.0V (V-WL), 1.0V (V-BL)/-0.5V (V-PL)/1.2V (V-WL), and 1.5V (V-BL)/-1V (V-PL)/2.0V (V-WL), with SL set to 0V.
• the voltage relationship between the bit line BL and source line SL may also be reversed.
• the threshold voltage drops during writing, and the pinch-off point 63 gradually shifts toward the n+ layer 5b, and the MOSFET may operate linearly.
• Figure 3(a) shows the state immediately after the holes 64 generated by impact ionization in the previous cycle are stored in the p-layer 4 before the erase operation.
• the source line SL, bit line BL, and word line WL are 0V
• the voltage of the control line CDC is 0.5V
• the voltage of the plate line PL is -1V.
• the source line SL, bit line BL, and word line WL are set to 0V, and the voltage of the control line CDC is set to 0.5V.
• the voltage of the plate line PL is set to, for example, 2V.
• the electrons lost due to recombination are replenished from the inversion layer 65 in contact with the p-layer 4 through the n-layer 3.
• the hole concentration of the p-layer 4 decreases over time, and the threshold voltage of the MOSFET becomes higher than when "1" was written.
• the threshold voltage of the MOSFET becomes 1.2V.
• the MOSFET having the gate conductor layer 22 to which this word line WL is connected hardly flows a current even when a voltage is applied, and the MOSFET is in an erased state. This state is the memory's logical storage data "0".
• the contact area between the p-layer 4 and gate insulating layer 13 is larger than the contact area between the gate conductor layer 22 and gate insulating layer 13.
• the dependence of the MOSFET threshold on the number of hole carriers in the p-layer 4 becomes larger compared to a planar MOSFET, and the operating margin of the memory is expanded.
• the vertical cross section of the p-layer 4 is concave, the effective distance between the n+ layer 5a and the n+ layer 5b is longer, and the leakage current of the MOSFET when the logical memory data is "0" can be reduced.
• the voltage application conditions can be combinations such as 0V (V-BL)/2V (W-PL)/-1V (V-WL), 0.4V (V-BL)/2V (V-PL)/0.5V (V-WL), or 1V (V-BL)/1.5V (V-PL)/0V (V-WL), with the source line SL at 0V and the control line CDC at 0.5V.
• the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL mentioned above are examples for performing a memory erase operation, and other operating conditions that allow a memory erase operation may also be used.
• control line CDC is set to 0.5V whether writing to or erasing memory, but the control line CDC can also be set to ground voltage, i.e. 0V.
• the bottom surfaces of the n+ layers 5a and 5b are separated from the top surface of the gate conductor layer 21. This prevents the n+ layers 5a and 5b from coming into direct contact with the inversion layer 65 formed between the p layer 4 and the gate insulating layer 11 when erasing the memory. This makes it difficult for current to flow from the n layer 3, which helps reduce power consumption when erasing.
• the memory can be erased even if a positive voltage is applied to the plate line PL during erasure, which has the advantage that information from multiple cells that share the gate conductor layer 22 can be erased at once.
• the contact area between the p layer 4 and the n layer 3 is depicted as being equal to the cross-sectional area of the p layer 4, but as long as the n layer 3 and the inversion layer are in partial contact at the time when the inversion layer 65 is formed during erasure, the contact area between the p layer 4 and the n layer 3 may be smaller than the cross-sectional area of the p layer 4.
• the memory cell of the present invention is formed in the area of a single MOSFET in a plan view, by sharing the source line and bit line with adjacent memory cells, a higher density memory cell array can be realized than conventional dynamic RAM.
• the MOSFET which is the access transistor of the memory according to the first embodiment of the present invention, can realize a higher density memory cell compared to a normal parallel plate (planar) type by surrounding a portion of the second gate conductor layer 22 with n+ layer 5a, n+ layer 5b, and p layer 4 which becomes the channel portion.
• the MOSFET which is the access transistor of the memory according to the first embodiment of the present invention, is formed by n+ layer 5a, n+ layer 5b, p layer 4, second gate insulating layer 13, and second gate conductor layer 22. Since the vertical cross section near the surface of p layer 4 is concave, the electric field lines from second gate conductor layer 22 to p layer 4, which is the channel portion of the MOSFET, are dispersed rather than concentrated. As a result, the backgate bias effect is increased, and the carrier concentration dependency of the threshold of the access transistor is increased compared to parallel plate (planar) type and FIN type MOSFETs, expanding the margin of memory operation.
• Feature 4 In the first embodiment of the present invention, as described in Feature 2, it is possible to arrange access transistors having a short gate length in a plan view, so that a high-density memory arrangement can be realized.
• the p-layer 4 which is one of the components of the MOSFET in the memory cell according to the first embodiment of the present invention, is connected to the n-layer 3 and the p-layer 1, and the threshold value of the MOSFET of the access transistor can be freely set by adjusting the voltage applied to the gate conductor layer 21. Furthermore, since the area under the MOSFET is not fully depleted, it is not greatly affected by the coupling of the gate electrode from the word line of the floating body, which is a drawback of DRAMs that do not have a capacitor. In other words, according to the present invention, it is possible to design a wide margin for the operating voltage as a memory.
• n+ layer 5a, n+ layer 5b, p layer 4, second gate insulating layer 13, and second gate conductor layer 22 can be formed in the same process as the peripheral CMOS, that is, the source, drain, substrate, gate oxide film, and gate electrode, and therefore it is possible to provide a high-density memory cell array and a structure compatible with the peripheral CMOS circuits.
• Second Embodiment 4A to 4N show a method for manufacturing a memory according to the second embodiment.
• (a) is a plan view
• (b) is a cross-sectional view taken along line XX' in (a)
• (c) is a cross-sectional view taken along line YY'.
• an n-layer 3, a p-layer 4, an insulating film 14, and a mask material layer 41 are formed on a p-layer 1, which is a p-type semiconductor substrate.
• the p-layer 4 and the n-layer 3 may be well layers, or may be formed using epitaxial technology with different impurity species and concentrations.
• the insulating layer 14 may be, for example, a silicon oxide film
• the mask material layer 41 may be, for example, a silicon nitride film.
• the mask material layer 41 in the area that will become the transistor portion of the memory cell is used as a mask to etch the insulating layer 14, the p-layer 4, and part of the n-layer 3 by RIE (Reactive Ion Etching). Note that in FIG. 4B, it is sufficient that the bottom of the etched groove is between the top and bottom of the n-layer 3.
• an insulating film 11 is selectively formed on the sidewalls and bottom of the trench formed above by oxidation.
• an oxide film may be formed overall using, for example, ALD (Atomic Layer Deposition) technology.
• the insulating film 11 is also formed around the mask material layer 41.
• the gate conductor layer 21 is formed by depositing n+poly-Si over the entire surface, for example, by CVD, and then etching back by selective RIE so that the upper surface of the gate conductor layer 21 is lower than the upper surface of the p-layer 4.
• n+poly film is used in this example, other metal films, such as a single layer film of W or a laminated film of TiN/W or silicide/poly, may also be used.
• an insulating layer 12 is formed on the entire surface, for example by a CVD method. After that, the insulating layer 12 is polished by a CMP (Chemical Mechanical Polishing) technique until the surface of the mask material layer 41 is exposed. This may be planarized by etch-back using an RIE technique with a selectivity between the mask material 41 and the insulating layer 12.
• CMP Chemical Mechanical Polishing
• the mask material layer 41 is selectively removed, and then the insulating layer 12 is etched so that the surface of the p-layer 4 is exposed.
• a method may be used in which the mask material layer 41 and part of the insulating layer 12 are planarized using CMP technology so that the surface of the p-layer 4 is exposed.
• an insulating layer 15 and a mask material 42 are formed on the entire surface, as shown in FIG. 4F.
• the mask material layer 42 is used as a mask to etch a portion of the insulating layer 15 and the p-layer 4 in the region that will become the gate electrode of the memory cell in the future by RIE.
• an insulating film 13 is selectively formed on the sidewalls and bottom of the trench formed above by oxidation.
• an oxide film may be formed overall by using, for example, ALD technology. In this case, the insulating film 13 is also formed around the mask material layer 42.
• an n+poly film is formed over the entire surface and then etched back, leaving the n+poly film in the groove, which forms the gate electrode 22. In this case, it is necessary to etch back the surface of the gate electrode 22 to a position lower than the surface of the insulating layer 12.
• n+poly film is used in this example, other metal films, such as a single layer film of W or a laminated film of TiN/W or silicide/poly, may also be used.
• This gate electrode 22 is also used as the gate electrode in all or part of the surrounding CMOS circuits.
• an insulating layer 15 is formed on the entire surface, for example by a CVD method. After that, the insulating layer 15 is polished by a CMP technique until the surface of the mask material layer 42 is exposed. This may be planarized by etch-back using an RIE technique that has a selectivity between the mask material 42 and the insulating layer 15.
• the insulating layer 15 and the mask material layer 42 are polished by CMP until the surface of the p-layer 4 is exposed. As a result, the insulating layer 15 remains on top of the gate electrode layer 13.
• n+ layer 5a and n+ layer 5b are formed in a self-aligned manner from the exposed surface of p-layer 4.
• This formation method can be the commonly known ion implantation, the introduction of impurities from the gas phase, or a heat treatment or laser annealing that activates the impurities as carriers.
• a W film 33 is formed over the entire surface, and then processed to form the desired wiring structure.
• adjacent n+ layers 5a or adjacent n+ layers 5b are connected to each other.
• a W film is used, but other materials that can make contact with the n+ layers 5a/5b, such as metal films, silicides, poly single-layer films, or laminated films, may also be used.
• a normal insulating layer may be formed over the entire surface, contact holes may be opened in the n+ layers 5a/5b, and each layer may be wired with a metal layer.
• an insulating layer 55 is formed over the entire surface, and then contact holes 34 are opened for each memory cell. After that, a wiring conductor layer 35 is formed.
• the wiring layer 33 cannot be seen from above, but is shown by a two-dot chain line in FIG. 4M (a) to make the positional relationship easier to understand.
• an insulating layer 56 is formed over the entire surface, and then contact holes 36 are opened in each memory cell. After that, a wiring conductor layer 37 is formed. As a result, the wiring conductor layer 35 is connected to the source line SL. Also, the wiring conductor layer 37 is connected to the bit line BL.
• FIG. 4N(a) In the plan view of FIG. 4N(a), only the second wiring conductor layer 37 and insulating film 56 are visible at the top, but to aid understanding, the main lower layers of FIG. 4N(a) are shown, including the n+ layer 5a/5b, gate electrode layer 22, metal layer 33, contact hole 34, and wiring conductor layer 35.
• groove shape is described using a rectangular vertical cross section in Figures 4A to 4N, it may be trapezoidal or circular.
• the n-layer 3 may be present in the area where memory cells will be located in the future. Therefore, although FIG. 4A shows the n-layer 3 formed over the entire surface of the p-layer 1, the n-layer 3 may be formed only in a selected area on the p-layer 1.
• the gate insulating layer 11 and the gate insulating film 13 can be made of any insulating film used in normal MOS processes, such as a SiO2 film, a SiON film, a HfSiON film, or a laminated film of SiO2/SiN.
• wiring conductor layer 35 and wiring conductor layer 37 separately to connect to the BL line has been shown, but it is also possible to form wiring conductor layers 35 and 37 and contact holes 34 and 36 in a single process using a damascene method or the like.
• This embodiment provides the following features: (Feature 1) According to the memory manufacturing method of the second embodiment of the present invention, since wafers used in normal MOS processes can be used, no new cost is added as materials. Also, since a special process such as selective epitaxial as shown in Patent Document 4 is not required, the method is compatible with normal generalized MOS processes and easy to introduce.
• the n+ layer 5a of the memory cell shown in Fig. 4N, the wiring conductor layers 35 and 37 connected to the bit line BL, and the contact holes 34 and 36 are shared between adjacent cells. Also, the wiring conductor layer 35 and the contact hole 34 connected to the source line SL are shared between adjacent cells. Therefore, the present invention can provide a fine memory cell.
• the contact between the wiring in the memory cell and the n+ layer 5a/5b is formed in a self-aligned manner as shown in Fig. 4L, so that the number of masks can be reduced. Furthermore, since the lateral length of this contact is determined without depending on the processing accuracy of lithography, contacts of minute dimensions can be formed, which contributes to miniaturization of the memory.
• the present invention makes it possible to provide a semiconductor memory device that is denser, faster, and has a higher operating margin than conventional devices.
• First semiconductor region 3 First impurity layer 4 Second semiconductor region 5a, 5b n+ layer 8 Third semiconductor region 11 First gate insulating layer 12 Insulating layer 13 Second gate insulating layer 15 Insulating layer 21 First gate conductor layer 22 Second gate conductor layer 33 Wiring conductor layer 34 Contact hole 35 Wiring conductor layer 36 Contact hole 37 Wiring conductor layer 41 Mask material 42 Mask material 55 Insulating film 56 Insulating film 62 Inversion layer 63 Pinch-off point 64 Hole group 65 Inversion layer 66 Electron group SL Source line PL Plate line WL Word line BL Bit line CDC Control line

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• 2023
  • 2023-05-30 JP JP2025523748A patent/JPWO2024247113A1/ja active Pending
  • 2023-05-30 WO PCT/JP2023/020110 patent/WO2024247113A1/ja not_active Ceased
• 2024
  • 2024-05-29 US US18/676,782 patent/US20240404583A1/en active Pending

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