JPWO2024247113A1 - - Google Patents

Info

Publication number
JPWO2024247113A1
JPWO2024247113A1 JP2025523748A JP2025523748A JPWO2024247113A1 JP WO2024247113 A1 JPWO2024247113 A1 JP WO2024247113A1 JP 2025523748 A JP2025523748 A JP 2025523748A JP 2025523748 A JP2025523748 A JP 2025523748A JP WO2024247113 A1 JPWO2024247113 A1 JP WO2024247113A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2025523748A
Other languages
Japanese (ja)
Other versions
JPWO2024247113A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2024247113A1 publication Critical patent/JPWO2024247113A1/ja
Publication of JPWO2024247113A5 publication Critical patent/JPWO2024247113A5/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/20DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435Cross-sectional shapes or dispositions of interconnections

Landscapes

  • Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
JP2025523748A 2023-05-30 2023-05-30 Pending JPWO2024247113A1 (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2023/020110 WO2024247113A1 (ja) 2023-05-30 2023-05-30 半導体素子を用いたメモリ装置

Publications (2)

Publication Number Publication Date
JPWO2024247113A1 true JPWO2024247113A1 (https=) 2024-12-05
JPWO2024247113A5 JPWO2024247113A5 (https=) 2026-02-19

Family

ID=93652606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2025523748A Pending JPWO2024247113A1 (https=) 2023-05-30 2023-05-30

Country Status (3)

Country Link
US (1) US20240404583A1 (https=)
JP (1) JPWO2024247113A1 (https=)
WO (1) WO2024247113A1 (https=)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3808763B2 (ja) * 2001-12-14 2006-08-16 株式会社東芝 半導体メモリ装置およびその製造方法
JP5078338B2 (ja) * 2006-12-12 2012-11-21 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7919800B2 (en) * 2007-02-26 2011-04-05 Micron Technology, Inc. Capacitor-less memory cells and cell arrays
JP2012074684A (ja) * 2010-09-03 2012-04-12 Elpida Memory Inc 半導体装置およびその製造方法
KR102529073B1 (ko) * 2015-04-29 2023-05-08 제노 세미컨덕터, 인크. 백바이어스를 이용한 드레인 전류가 향상된 트랜지스터 및 메모리 셀
KR102784170B1 (ko) * 2021-09-06 2025-03-19 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 반도체 소자를 사용한 메모리 장치

Also Published As

Publication number Publication date
WO2024247113A1 (ja) 2024-12-05
US20240404583A1 (en) 2024-12-05

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Legal Events

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