WO2024241514A1 - 電力変換装置 - Google Patents

電力変換装置 Download PDF

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Publication number
WO2024241514A1
WO2024241514A1 PCT/JP2023/019259 JP2023019259W WO2024241514A1 WO 2024241514 A1 WO2024241514 A1 WO 2024241514A1 JP 2023019259 W JP2023019259 W JP 2023019259W WO 2024241514 A1 WO2024241514 A1 WO 2024241514A1
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WO
WIPO (PCT)
Prior art keywords
voltage
output
phase inverter
output voltage
gradation level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/019259
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English (en)
French (fr)
Japanese (ja)
Inventor
章太 渡辺
浩行 吉野
聡士 小鹿
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to KR1020257037923A priority Critical patent/KR20250174667A/ko
Priority to JP2025521711A priority patent/JPWO2024241514A1/ja
Priority to CN202380098460.XA priority patent/CN121219951A/zh
Priority to PCT/JP2023/019259 priority patent/WO2024241514A1/ja
Priority to TW113115693A priority patent/TWI891338B/zh
Publication of WO2024241514A1 publication Critical patent/WO2024241514A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0083—Converters characterised by their input or output configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/49—Combination of the output voltage waveforms of a plurality of converters

Definitions

  • This application relates to a power conversion device.
  • a gradation-controlled power conversion device which is one type of power conversion device, can output a smooth AC waveform to a load without using a large-capacity output filter.
  • a gradation-controlled power conversion device is configured by connecting multiple single-phase inverters in series.
  • Patent Document 1 discloses a gradation-controlled power conversion device in which the absolute value of the minimum generated voltage in multiple single-phase inverters is set to 1, and the ratio of the absolute values of the output voltages in multiple single-phase inverters is configured to be a power of 2.
  • the power conversion device of Patent Document 1 gradation-controls the total voltage generated by each of the multiple single-phase inverters by combining the selection of whether or not to output.
  • a gradation control type inverter is driven by PWM (Pulse Width Modulation) control to supply power to a load.
  • PWM Pulse Width Modulation
  • a gradation control type inverter is originally characterized by reducing the number of switching times of a single-phase inverter with a high output voltage, thereby reducing the switching loss of the single-phase inverter with a high output voltage.
  • the period during which the single-phase inverter with a high output voltage performs PWM operation may be increased by performing PWM control.
  • the power conversion device of Patent Document 1 As the PWM operation period of the single-phase inverter with a high output voltage increases, the number of switching times of the single-phase inverter with a high output voltage increases, and the switching loss of the single-phase inverter increases. As a result, the power conversion device of Patent Document 1 has a problem in that the components and heat sink that make up the single-phase inverter become large, and the power conversion device itself becomes large.
  • the technology disclosed in this specification aims to realize a small, gradation-controlled power conversion device.
  • An example of a power conversion device disclosed in the present specification includes a power converter in which the AC sides of multiple single-phase inverters that convert DC power to AC power are connected in series, and which supplies a load with DC power or AC power of a total output voltage obtained by adding up the output voltages output by the multiple single-phase inverters, and a control unit that controls the power converter.
  • the single-phase inverter that outputs a minimum output voltage whose absolute value of the output voltage is greater than zero voltage and is the smallest is defined as the minimum single-phase inverter.
  • the absolute value of the total output voltage that can be discretely set by selectively combining the outputs of the multiple single-phase inverters is defined as a gradation level, and a predetermined gradation level at which the same total output voltage level is realized by multiple voltage combinations that are combinations of output voltages is defined as a special level, and the gradation levels that can be set include at least one special level.
  • the control unit controls the single-phase inverters to output a total output voltage of a set voltage value by selecting a combination of output voltages in the multiple single-phase inverters. When changing the gradation level to include a special level at either the front or rear, the control unit selects a voltage combination that does not change the output voltage of at least one single-phase inverter excluding the minimum single-phase inverter.
  • the power conversion device disclosed in this specification includes a special level that can achieve the same overall output voltage by combining the output voltages of multiple single-phase inverters in the gradation level, and when the control unit controls the power converter using the special level, it selects a voltage combination that does not change at least one output voltage, excluding the minimum output voltage whose absolute value is the smallest, so that a small-sized gradation-controlled power conversion device can be realized.
  • FIG. 1 is a diagram showing a configuration of a power conversion device according to a first embodiment
  • FIG. 2 is a diagram showing the configuration of the single-phase inverter of FIG. 1
  • FIG. 2 is a diagram showing a configuration of a gate driver shown in FIG. 1
  • 2 is a diagram showing output terminals and control signals in the control unit of FIG. 1
  • FIG. 2 is a diagram showing a configuration of a control unit in FIG. 1
  • FIG. 3 is a diagram illustrating an example of control of the single-phase inverter of FIG. 2
  • 2 is a diagram showing an example of grayscale levels and output voltages in the power conversion device of FIG. 1
  • 2 is a diagram illustrating an example of the operation of the power conversion device of FIG.
  • FIG. 11A and 11B are diagrams illustrating an example of grayscale levels and output voltages in a power conversion device of a comparative example.
  • FIG. 11 is a diagram illustrating an example of the operation of a power conversion device of a comparative example.
  • 10 is a diagram showing a third example of grayscale levels and output voltages in the power conversion device of FIG. 11A and 11B are diagrams illustrating an example of gray scale levels and output voltages in a power conversion device according to a second embodiment.
  • FIG. 11 is a diagram illustrating a first example of the operation of a power conversion device according to the second embodiment.
  • FIG. 11 is a diagram illustrating an example of the operation of a power conversion device of a comparative example.
  • FIG. 11 is a diagram showing a second example of the operation of the power conversion device according to the second embodiment.
  • 13A and 13B are diagrams illustrating an example of gray scale levels and output voltages in a power conversion device according to a third embodiment.
  • 13A and 13B are diagrams illustrating an example of gray scale levels and output voltages in a power conversion device according to a fourth embodiment.
  • FIG. 13 is a diagram illustrating an example of the operation of a power conversion device according to a fourth embodiment.
  • 11A and 11B are diagrams illustrating an example of grayscale levels and output voltages in a power conversion device of a comparative example.
  • FIG. 11 is a diagram illustrating an example of the operation of a power conversion device of a comparative example.
  • FIG. 13 is a diagram showing a first example of grayscale levels and output voltages in a power conversion device according to embodiment 5.
  • FIG. 13 is a diagram showing a first example of grayscale levels and output voltages in a power conversion device according to embodiment 5.
  • FIG. 13 is a diagram showing a second example of the grayscale levels and the output voltage in the power conversion device according to the fifth embodiment.
  • FIG. 13 is a diagram showing a second example of the grayscale levels and the output voltage in the power conversion device according to the fifth embodiment.
  • FIG. FIG. 13 is a diagram illustrating an example of the operation of a power conversion device according to a fifth embodiment.
  • 13 is a diagram showing a third example of the grayscale level and the output voltage in the power conversion device according to the fifth embodiment.
  • FIG. 13 is a diagram showing a configuration of a power conversion device according to a sixth embodiment.
  • FIG. 28 is a diagram showing the configuration of a control unit in FIG. 27 .
  • FIG. 28 is a diagram showing a configuration of a first example of the output detection unit in FIG. 27 .
  • FIG. 28 is a diagram showing a configuration of a second example of the output detection unit in FIG. 27 .
  • FIG. 2 is a diagram illustrating an example of a hardware configuration for implementing the functions of a control unit.
  • FIG. 1 is a diagram showing the configuration of a power conversion device according to a first embodiment.
  • FIG. 2 is a diagram showing the configuration of a single-phase inverter in FIG. 1
  • FIG. 3 is a diagram showing the configuration of a gate driver in FIG. 1.
  • FIG. 4 is a diagram showing an output terminal and a control signal in the control unit in FIG. 1
  • FIG. 5 is a diagram showing the configuration of the control unit in FIG. 1.
  • FIG. 6 is a diagram showing an example of control of the single-phase inverter in FIG. 2.
  • FIG. 7 is a diagram showing an example of a gradation level and an output voltage in the power conversion device in FIG. 1.
  • FIG. 8 is a diagram showing an example of an operation of the power conversion device in FIG. 1.
  • FIG. 1 is a diagram showing the configuration of a power conversion device according to a first embodiment.
  • FIG. 2 is a diagram showing the configuration of a single-phase inverter in FIG. 1
  • FIG. 3 is
  • the power conversion device 100 of the first embodiment is a gradation control type power conversion device that is provided with three or more single-phase inverters A or two single-phase inverters A connected in series and performs PWM operation.
  • 1 includes a power converter 50 in which n single-phase inverters A1 to An are connected in series, and a control unit 10 that controls the power converter 50.
  • the power converter 50 includes n single-phase inverters A1 to An and n gate drivers GD1 to GDn.
  • the power converter 50 has multiple single-phase inverters A1-An with their AC sides (output terminals N, P) connected in series to convert DC power to AC power, and supplies DC or AC power of a total output voltage Vsum, which is the sum of the output voltages V1-Vn output by the multiple single-phase inverters A1-An, to the load 20.
  • the control unit 10 determines the gradation level of the total output voltage Vsum by selecting a combination of the output voltages V1-Vn of the multiple single-phase inverters A1-An, and performs PWM control on the single-phase inverters so as to output a total output voltage Vsum of a preset set voltage value between adjacent gradation levels.
  • the gradation level is the absolute value of the total output voltage Vsum, which can be set discretely by selectively combining the outputs of the multiple inverters.
  • the single-phase inverters A1 to An are controlled based on control signals S1N to SnN and S1P to SnP output from the control unit 10 via the gate drivers GD1 to GDn.
  • the single-phase inverters A1 to An are connected to DC power supplies BT1 to BTn.
  • the DC power supplies BT1 to BTn output power supply voltages Vd1 to Vdn.
  • the single-phase inverters are generally designated by A, with A1 to An used to distinguish them.
  • the gate drivers are generally designated by GD, with GD1 to GDn used to distinguish them.
  • the control signals for one half-bridge inverter, described below, are generally designated by SN, with S1N to SnN used to distinguish them.
  • the control signals for the other half-bridge inverter, described below, are generally designated by SP, with S1P to SnP used to distinguish them.
  • the DC power supplies are generally designated by BT, with BT1 to BTn used to distinguish them.
  • FIG. 1 four single-phase inverters A1, A2, Am, An, four gate drivers GD1, GD2, GDm, GDn, and four DC power supplies BT1, BT2, BTm, BTn are specifically shown.
  • m and n are natural numbers equal to or greater than 3
  • m is a natural number smaller than n.
  • m is a natural number.
  • the absolute values of the respective output voltages are V1 to Vn, and are displayed with + or - to indicate the polarity of the voltage. Note that the absolute value of the voltage generated when the single-phase inverter outputs voltage is referred to as the absolute voltage value, where appropriate.
  • the control unit 10 controls each of the single-phase inverters A1 to An, and controls the power conversion device 100 to output the sum of the output voltages V1 to Vn of each of the single-phase inverters A1 to An as a total output voltage Vsum to the load 20.
  • the power conversion device 100 can output DC power or AC power of any predetermined magnitude.
  • the power conversion device 100 of the first embodiment is capable of handling a wide variety of loads 20, including resistive loads, capacitive loads, inductive loads, and combinations thereof.
  • the single-phase inverter A and gate driver GD will be explained using Figures 2 and 3.
  • the single-phase inverter A is a full-bridge inverter having four switching elements QNL, QNH, QPL, and QPH.
  • This full-bridge inverter is composed of one half-bridge inverter BN consisting of two switching elements QNL and QNH, and another half-bridge inverter BP consisting of two switching elements QPL and QPH.
  • the half-bridge inverter is connected to a DC power supply BT with a power supply voltage Vd, with the voltage being positive in the direction indicated by the arrow in Figure 2, that is, from the low-potential side wiring Ll to the high-potential side wiring Lh.
  • the symbol for the power supply voltage of the DC power supply is generally Vd, and Vd1 to Vdn are used when distinguishing between them.
  • a capacitor may be provided between the DC power supply BT and the single-phase inverter A.
  • Single-phase inverter A has a positive voltage in the direction shown by the arrow in Figure 2, that is, from output terminal N to output terminal P, and outputs an output voltage V with an absolute value of V.
  • the sign of the output voltage of single-phase inverter A is generally V, and V1 to Vn are used when distinguishing between them.
  • the output voltage V of single-phase inverter A is the same as the power supply voltage Vd of DC power supply BT.
  • a half-bridge inverter BN and a half-bridge inverter BP are connected in parallel between a high-potential side wiring Lh to which the positive side of the DC power supply BT is connected and a low-potential side wiring Ll to which the negative side of the DC power supply BT is connected.
  • the half-bridge inverter BN has a switching element QNH and a switching element QNL connected in series between the high-potential side wiring Lh and the low-potential side wiring Ll.
  • the half-bridge inverter BP has a switching element QPH and a switching element QPL connected in series between the high-potential side wiring Lh and the low-potential side wiring Ll.
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • the terminals of the switching elements QNL, QNH, QPL, and QPH are the drain terminal d, the source terminal s, and the gate terminal g.
  • the switching elements QNL, QNH, QPL, and QPH each include a transistor Tr and a diode Di.
  • the diode Di may be a separate element from the transistor Tr, or may be a parasitic diode.
  • the drive signal soNH output from the gate driver GD is input to the gate terminal g of the switching element QNH, and the drive signal soNL output from the gate driver GD is input to the gate terminal g of the switching element QNL.
  • the drain terminal d of the switching element QNH is connected to the high potential side wiring Lh
  • the source terminal s of the switching element QNH is connected to the drain terminal d of the switching element QNL
  • the source terminal s of the switching element QNL is connected to the low potential side wiring Ll.
  • the connection point where the source terminal s of the switching element QNH and the drain terminal d of the switching element QNL are connected is connected to the output terminal N.
  • a reference potential signal srNH is output from the source terminal s of the switching element QNH to the gate driver GD
  • a reference potential signal srNL is output from the source terminal s of the switching element QNL to the gate driver GD.
  • the drive signal soPH output from the gate driver GD is input to the gate terminal g of the switching element QPH, and the drive signal soPL output from the gate driver GD is input to the gate terminal g of the switching element QPL.
  • the drain terminal d of the switching element QPH is connected to the high potential side wiring Lh
  • the source terminal s of the switching element QPH is connected to the drain terminal d of the switching element QPL
  • the source terminal s of the switching element QPL is connected to the low potential side wiring Ll.
  • the connection point where the source terminal s of the switching element QPH and the drain terminal d of the switching element QPL are connected is connected to the output terminal P.
  • a reference potential signal srPH is output from the source terminal s of the switching element QPH to the gate driver GD
  • a reference potential signal srPL is output from the source terminal s of the switching element QNL to the gate driver GD.
  • the switching elements QNL, QNH, QPL, and QPH are MOSFETs, but this is not limited thereto, and they may be switching elements other than MOSFETs, such as IGBTs (Insulated Gate Bipolar Transistors) and thyristors.
  • the switching elements QNL, QNH, QPL, and QPH are each configured as a single component, but in order to ensure the withstand voltage and withstand current, each switching element QNL, QNH, QPL, and QPH may be configured with multiple switching elements connected in series or parallel, or may be configured with series and parallel connections, i.e., in a series-parallel state.
  • the gate driver GD is equipped with two dead time generating units DTN and DTP, four gate signal output units GONH, GONL, GOPH, and GOPL, and two inverters 61.
  • the control signal SN and the control signal SP are input to the gate driver GD from the input terminal DiN and the input terminal DiP, respectively, and after the dead time generating unit DTN and the dead time generating unit DTP generate the desired dead time that is predetermined, they are output to the single-phase inverter A as level-shifted drive signals soNH, soNL and drive signals soPH, soPL from the gate signal output units GONH, GONL and the gate signal output units GOPH, GOPL.
  • the two half-bridge inverters BN and BP are driven by the drive signals soNH, soNL, soPH, and soPL.
  • the circuit that generates the drive signals soNH and soNL that drive the half-bridge inverter BN will be described.
  • the control signal SN output from the control unit 10 is input from the input terminal DiN, and the control signal SN and an inverted signal obtained by inverting the control signal SN by an inverter 61 are input to the dead time generation unit DTN.
  • the dead time generation unit DTN outputs dead time signals sdtNH and sdtNL indicating a predetermined desired dead time from output terminals ToNH and ToNL, respectively.
  • the gate signal output unit GONH receives the reference potential signal srNH output from the source terminal s of the switching element QNH from the reference terminal DsNH, and receives the dead time signal sdtNH from the input terminal TiNH.
  • the gate signal output unit GONH outputs a drive signal soNH to which a predetermined desired dead time has been added based on the reference potential signal srNH and the dead time signal sdtNH from the output terminal DoNH to the gate terminal g of the switching element QNH.
  • the gate signal output unit GONL receives the reference potential signal srNL output from the source terminal s of the switching element QNL from the reference terminal DsNL and receives the dead time signal sdtNL from the input terminal TiNL.
  • the gate signal output unit GONL outputs a drive signal soNL to which a predetermined desired dead time has been added based on the reference potential signal srNL and the dead time signal sdtNL from the output terminal DoNL to the gate terminal g of the switching element QNL.
  • the circuit that generates the drive signals soPH, soPL that drive the half-bridge inverter BP will be described.
  • the control signal SP output from the control unit 10 is input from the input terminal DiP, and the control signal SP and an inverted signal obtained by inverting the control signal SP by an inverter 61 are input to the dead time generation unit DTP.
  • the dead time generation unit DTP outputs dead time signals sdtPH, sdtPL indicating a predetermined desired dead time from output terminals ToPH, ToPL, respectively.
  • the gate signal output unit GOPH receives the reference potential signal srPH output from the source terminal s of the switching element QPH from the reference terminal DsPH, and receives the dead time signal sdtPH from the input terminal TiPH.
  • the gate signal output unit GOPH outputs a drive signal soPH to which a predetermined desired dead time has been added based on the reference potential signal srPH and the dead time signal sdtPH from the output terminal DoPH to the gate terminal g of the switching element QPH.
  • the gate signal output unit GOPL receives the reference potential signal srPL output from the source terminal s of the switching element QPL from the reference terminal DsPL and receives the dead time signal sdtPL from the input terminal TiPL.
  • the gate signal output unit GOPL outputs a drive signal soPL to which a predetermined desired dead time has been added based on the reference potential signal srPL and the dead time signal sdtPL from the output terminal DoPL to the gate terminal g of the switching element QPL.
  • the four reference terminals DsNH, DsNL, DsPH, and DsPL constitute the reference terminal Dss of the gate driver GD.
  • the output terminals DoNH, DoNL, DoPH, and DoPL constitute the output terminal Doo of the gate driver GD.
  • the four reference potential signals srNH, srNL, srPH, and srPL constitute the reference potential signal sr.
  • the four drive signals soNH, soNL, soPH, and soPL constitute the drive signal so.
  • FIG 4 shows control signals S1N to SnN output from output terminals Co1N to ConN of the control unit 10, and control signals S1P to SnP output from output terminals Co1P to ConP of the control unit 10.
  • Control signals S1N, S1P are output from output terminals Co1N, Co1P, respectively.
  • Control signals S2N, S2P are output from output terminals Co2N, Co2P, respectively.
  • Control signals SmN, SmP are output from output terminals ComN, ComP, respectively.
  • Control signals SnN, SnP are output from output terminals ConN, ConP, respectively.
  • Figures 1 and 4 show eight output terminals Co1N, Co1P, Co2N, Co2P, ComN, ComP, ConN, and ConP, and eight control signals S1N, S1P, S2N, S2P, SmN, SmP, SnN, and SnP, which correspond to four single-phase inverters A1, A2, Am, and An.
  • m and n are natural numbers equal to or greater than 3
  • m is a natural number smaller than n.
  • the output terminal P of the uppermost single-phase inverter An among the multiple single-phase inverters A1 to An connected in series is connected to one terminal of the load (not shown) via an output power line 19, and the output terminal N of the lowermost single-phase inverter A1 among the multiple single-phase inverters A1 to An is connected to the other terminal of the load (not shown) via a grounded reference power line 18.
  • the reference power line 18 is at a reference ground potential (GND potential).
  • the output terminal P of the single-phase inverter A1 is connected to the output terminal N of the upper single-phase inverter A2.
  • the single-phase inverter Am where m is a natural number of 2 or more, has an output terminal N connected to the output terminal P of the adjacent lower single-phase inverter Ak, and an output terminal P connected to the output terminal N of the adjacent upper single-phase inverter Aka.
  • k is m-1
  • ka is m+1.
  • the drive signal so1 input to the single-phase inverter A1 is output from the output terminal Doo of the gate driver GD1 based on the control signals S1N, S1P output from the control unit 10 and the reference potential signal sr1 output from the single-phase inverter A1.
  • the reference potential signal sr1 is input to the reference terminal Dss of the gate driver GD1.
  • the drive signal so2 input to the single-phase inverter A2 is output from the output terminal Doo of the gate driver GD2 based on the control signals S2N, S2P output from the control unit 10 and the reference potential signal sr2 output from the single-phase inverter A2.
  • the reference potential signal sr2 is input to the reference terminal Dss of the gate driver GD2.
  • the drive signal som input to the single-phase inverter Am is output from the output terminal Doo of the gate driver GDm based on the control signals SmN, SmP output from the control unit 10 and the reference potential signal srm output from the single-phase inverter Am.
  • the reference potential signal srm is input to the reference terminal Dss of the gate driver GDm.
  • the drive signal son input to the single-phase inverter An is output from the output terminal Doo of the gate driver GDn based on the control signals SnN, SnP output from the control unit 10 and the reference potential signal srn output from the single-phase inverter An.
  • the reference potential signal srn is input to the reference terminal Dss of the gate driver GDn.
  • the symbol so is used collectively for the drive signals, and so1 to son are used when distinguishing between them.
  • the symbols sr are used collectively for the reference potential signals, and sr1 to srn are used when distinguishing between them
  • single-phase inverter Am is shown as a representative of single-phase inverters A1 to An.
  • Figure 6 shows an example of the on state STo and off state SToff of the four switching elements QNH, QNL, QPH, and QPL that make up single-phase inverter Am and the change in output voltage Vm of single-phase inverter Am in response to changes in control signals SmN and SmP.
  • Figure 6 shows an example of a state in which the aforementioned dead time is omitted, that is, an example in which switching elements QNH and QNL change simultaneously at times t3 and t4, and switching elements QPH and QPL change simultaneously at times t1 and t2.
  • the horizontal axis is time.
  • the vertical axis of control signals SmN and SmP is the voltage of the digital signal, and the vertical axis shows two states, high level (H level) and low level (L level).
  • the vertical axis of the switching elements QNH, QNL, QPH, and QPL represents the on/off state, and the two states shown are the on state SToN and the off state STOff.
  • the vertical axis of the output voltage Vm represents voltage, and the three states shown are the positive voltage +Vm, the negative voltage -Vm with the polarity reversed from this positive voltage, and zero voltage (0).
  • the control signals SmN and SmP are both at low level.
  • the high-side switching element QNH on the high-side wiring Lh of the half-bridge inverter BN i.e., the high-side switching element QNL on the low-side wiring Ll of the half-bridge inverter BN, i.e., the low-side switching element QNL
  • the high-side switching element QPH on the high-side wiring Lh of the half-bridge inverter BP i.e., the high-side switching element QPL on the low-side wiring Ll of the half-bridge inverter BP, i.e., the low-side switching element QPL, is in the on-state.
  • the control signal SmP changes to a high level
  • the control signal SmN becomes a low level
  • the control signal SmP becomes a high level.
  • the switching elements QNH and QNL of the half-bridge inverter BN are in the off state and on state, respectively
  • the switching elements QPH and QPL of the half-bridge inverter BP are in the on state and off state, respectively.
  • the output voltage Vm becomes a positive voltage (+Vm), that is, it is in a positive voltage output state.
  • control signal SmP changes to a low level, and the control signal SmN and the control signal SmP also become low levels. In this case, the state is the same as at time t0.
  • the control signal SmN changes to high level, and the control signal SmN becomes high level and the control signal SmP becomes low level.
  • the switching elements QNH and QNL of the half-bridge inverter BN become on and off states, respectively, and the switching elements QPH and QPL of the half-bridge inverter BP remain in off and on states, respectively.
  • the output voltage Vm becomes a negative voltage (-Vm), i.e., a negative voltage output state is entered.
  • control signal SmN changes to low level, and the control signal SmN and the control signal SmP become low level. In this case, the state is the same as at time t0.
  • the first power conversion device 100 of the first embodiment includes single-phase inverters A having at least three different output voltages, and is characterized in that the output voltage of each single-phase inverter A is set so that the same total output voltage Vsum can be output with a combination of multiple outputs at least one gradation level.
  • the gradation level is the absolute value of the total output voltage that can be set discretely by selectively combining the outputs of multiple inverters. In the case of PWM control, it may be as follows.
  • the gradation level is the absolute value of the total output voltage Vsum that can be set discretely when the output voltage V is constant in the control period Tc of the PWM control, that is, the level of the total output voltage Vsum.
  • a predetermined gradation level that can be set and that realizes the same level of the total output voltage Vsum by a plurality of voltage combinations that are combinations of the output voltage V is called a special level.
  • An example of the gradation levels, output voltages V1 to V3, and total output voltage Vsum in the first power conversion device 100 equipped with three single-phase inverters A is shown in FIG. 7.
  • the second power conversion device 100 of the first embodiment includes a single-phase inverter A having two different output voltages, and is characterized in that the output voltage of each single-phase inverter A is set so that the same total output voltage Vsum can be output with a combination of multiple outputs for at least one gradation level.
  • An example of the gradation levels, output voltages V1 to V3, and total output voltage Vsum in the second power conversion device 100 equipped with two single-phase inverters A is shown in FIG. 11.
  • the examples of gradation levels, output voltages V1 to V3, and total output voltage Vsum shown in FIG. 7 are gradation level setting examples for a power conversion device 100 having three single-phase inverters A1, A2, and A3.
  • the gradation level setting example shown in FIG. 7 can also be called gradation level setting data.
  • the examples of gradation levels, output voltages V1 to V3, and total output voltage Vsum shown in FIG. 7 are examples in which the ratio of the output voltages V1, V2, and V3 of the single-phase inverters A1, A2, and A3 is set to 1:3:8.
  • FIG. 11 are settings for a power conversion device 100 having two single-phase inverters A1 and A2.
  • the examples of gradation levels, output voltages V1, V2, and total output voltage Vsum shown in FIG. 11 are examples in which the ratio of the output voltages V1, V2 of the single-phase inverters A1 and A2 is set to 1:2.
  • the ratio of the output voltages V1, V2, and V3 of the single-phase inverters A1, A2, and A3 is set to 1:3:8.
  • Figure 7 shows the ratio of the gradation level and the total output voltage Vsum when the ratio of the output voltages V1 to V3 of the three single-phase inverters A1 to A3 is 1:3:8.
  • the ratio of the total output voltage Vsum is the ratio to the output voltage V1.
  • the state in which the three single-phase inverters A1 to A3 receive the output command of the voltage absolute values V1 to V3 is indicated by "1" or "-1", and the state in which they do not receive the output command is indicated by "0".
  • the output voltages V1, V2, and V3 set to "1” are positive voltages +V1, +V2, and +V3, respectively.
  • the output voltages V1, V2, and V3 set to "-1” are negative voltages -V1, -V2, and -V3, respectively.
  • the output voltages V1, V2, and V3 set to "0” are zero voltages, 0V (volts).
  • Each single-phase inverter A outputs a positive voltage when it receives an output instruction "1" during a period determined by the output polarity determination unit 33 described later as a positive voltage instruction, and outputs a negative voltage when it receives an output instruction "-1". Also, each single-phase inverter A outputs a negative voltage when it receives an output instruction "1” during a period determined by the output polarity determination unit 33 as a negative voltage instruction, and outputs a positive voltage when it receives an output instruction "-1". Also, regardless of the voltage instruction, when the output instruction is "0", the single-phase inverter A outputs zero voltage.
  • the total output voltage Vsum is output at gradation level 7 during a period in which the output voltage instruction is a positive voltage instruction, it is possible to output by setting the output voltage V3 to a positive voltage output, the output voltage V2 to a zero voltage output, and the output voltage V1 to a negative voltage output.
  • the voltage ratio of the absolute value of the output voltage V1 in the single-phase inverter A1 that outputs the minimum output voltage is 1.
  • the total output voltage Vsum for gradation level 7 is 7 x V1.
  • the ratio of the total output voltage Vsum is 0, 1 to 12, and the gradation levels are 0, 1 to 12.
  • the gradation level where the ratio of the total output voltage Vsum is 4 is the special level SL, and the gradation level for the first voltage combination in the special level SL is written as 4a, and the gradation level for the second voltage combination in the special level SL is written as 4b.
  • the gradation levels in the special level SL may be written by the numbers before the lowercase letters, rather than using lowercase letters such as "a" and "b" at the end to distinguish between voltage combinations.
  • the power conversion device 100 shown in FIG. 7 operates with a voltage combination of output voltages V1 to V3, and includes single-phase inverters A1 to A3 that output three different output voltages with a ratio of output voltages V1 to V3 of 1:3:8, and is configured to realize gradation level 4 with two voltage combinations.
  • gradation level 4 where the ratio of the total output voltage Vsum is 4, can be realized with a first voltage combination of V1: “1", V2: “1”, and V3: "0”, and a second voltage combination of V1: "-1", V2: “-1", and V3: "1".
  • the configuration having the gradation level i.e., the special level SL, which can be realized by the voltage combination of the output voltages V of the multiple single-phase inverters A, which is a feature of the power conversion device 100 of the first embodiment, satisfies the following setting conditions.
  • of the output voltage in the single-phase inverter A1 that outputs the minimum output voltage Vmin to the minimum output voltage Vmin is 1.
  • the single-phase inverter A1 that outputs the minimum output voltage Vmin, whose absolute value of the output voltage is greater than zero voltage and is the smallest, is defined as the minimum single-phase inverter.
  • m and i are natural numbers.
  • the first condition and the second condition are satisfied.
  • Second condition: At least one single-phase inverter satisfies formula (2). J ⁇ 2K+1...(1) J 2K+1-i...(2)
  • the voltage ratio of a single-phase inverter that outputs the minimum output voltage Vmin to the minimum output voltage Vmin is 1, the voltage ratio J and the sum of the voltage ratios K may be expressed with the minimum voltage ratio of a single-phase inverter that outputs the minimum output voltage Vmin being 1.
  • the power conversion device 100 of the first embodiment includes at least one single-phase inverter that satisfies formula (2), i.e., a target single-phase inverter, and it can also be said that the other single-phase inverters other than the target single-phase inverter satisfy formula (4).
  • the single-phase inverter A1 with output voltage V1 having a voltage ratio of 1 is the minimum single-phase inverter that outputs the minimum output voltage Vmin
  • the output voltage V2 with a voltage ratio of 3 is a single-phase inverter that satisfies equation (4)
  • the output voltage V3 with a voltage ratio of 8 is a single-phase inverter that satisfies equation (2), i.e., the target single-phase inverter.
  • FIG. 5 shows the configuration of the control unit 10 of the power conversion device 100.
  • the control unit 10 includes an output instruction unit 31, a compensation unit 32, an output polarity determination unit 33, an absolute value processing unit 34, an integer processing unit 35, a subtraction unit 36, a pulse modulation unit 37, an addition unit 38, and a control signal generation unit 39.
  • the output instruction unit 31 outputs an output instruction value Oref, for example a sine wave or a DC waveform.
  • the compensation unit 32 performs gain calculations on the output instruction value Oref and outputs a compensation signal Ocmp.
  • the output polarity determination unit 33 outputs an output polarity instruction signal Opol that determines whether the polarity of the total output voltage Vsum is positive or negative from the compensation signal Ocmp.
  • the absolute value processing unit 34 outputs an absolute value signal Oabs that converts the compensation signal Ocmp to an absolute value.
  • the integer processing unit 35 outputs an integer signal Oint that converts the absolute value signal Oabs to an integer value.
  • the subtraction unit 36 outputs a decimal value signal Odeci obtained by subtracting the integer value signal Oint from the absolute value signal Oabs.
  • the pulse modulation unit 37 performs pulse width modulation on the decimal value signal Odeci at a carrier frequency to generate a decimal part PWM signal dPMW, and outputs this decimal part PWM signal dPMW.
  • the addition unit 38 outputs an output voltage control signal Oct by adding the decimal part PWM signal dPMW to the integer value signal Oint.
  • the control signal generation unit 39 outputs n control signals S1N to SnN and n control signals S1P to SnP for performing switching control on the switching elements QNH, QNL, QPH, and QPL of each single-phase inverter A1 to An based on the output polarity instruction signal Opol and the output voltage control signal Oct.
  • the power conversion device 100 of the first embodiment generates control signals S1N-SnN and S1P-SnP that perform PWM control between adjacent gradation levels of the total output voltage Vsum based on the value of the compensation signal Ocmp that compensates for the output instruction value Oref, and realizes the total output voltage Vsum averaged to the value of the compensation signal Ocmp by controlling each single-phase inverter A1-An with the control signals S1N-SnN and S1P-SnP.
  • the power conversion device 100 of the first embodiment is set so that there is a predetermined special level SL at which the same level of the total output voltage Vsum is realized by the voltage combination of multiple output voltages V in the ratio setting of the output voltages V1-Vn of each single-phase inverter A1-An.
  • the power conversion device 100 of the first embodiment has a predetermined special level SL that realizes the same level of the total output voltage Vsum by a voltage combination of a plurality of output voltages V.
  • the power conversion device 100 of the first embodiment includes a special level SL that can realize the same total output voltage Vsum by a voltage combination of the output voltages V1 to Vn of the plurality of single-phase inverters A1 to An at the gradation level of the gradation control, and the control unit 10 selects a voltage combination of the output voltage V so as not to increase the number of switching times of the target single-phase inverter, which is a specific single-phase inverter, and controls each single-phase inverter A1 to An.
  • the control unit 10 selects a voltage combination of the output voltage V so as not to increase the number of switching times of the target single-phase inverter, which is a specific single-phase inverter, and controls each single-phase inverter A1 to An.
  • FIG. 8 shows a time series of gradation level changes selected based on the gradation level setting data shown in FIG. 7 so as to reduce the number of switching operations of a specific single-phase inverter, i.e., a target single-phase inverter.
  • the ratio of the output voltages V1 to V3 is 1:3:8, and the special level SL is set to gradation level 4.
  • the special level SL has gradation levels 4a and 4b, which have different voltage combinations.
  • gradation level setting data in which the ratio of the output voltages V1 to V3 is 1:3:9 and does not have the special level SL is shown in FIG. 10, and an example of the operation of a power conversion device of a comparative example based on the gradation level setting data of FIG. 9 is shown.
  • the gradation level setting data of the comparative example shown in FIG. 9 is an example in which all output voltages V1 to V3 satisfy formula (4).
  • the gradation level setting data of the comparative example in Figure 9 does not have a special level SL, so it has more gradation levels than the gradation level setting data in Figure 7, going up to gradation level 13.
  • FIG. 8 shows voltage waveforms 41a, 41b, 41c of output voltages V3, V2, V1, the order of one period of the control cycle Tc, i.e., the cycle ordinal number Nc, the waveform of the total output voltage Vsum, and the waveform of the compensation signal Ocmp.
  • FIG. 10 shows voltage waveforms 42a, 42b, 42c of output voltages V3, V2, V1, the cycle ordinal number Nc, the waveform of the total output voltage Vsum, and the waveform of the compensation signal Ocmp.
  • the cycle ordinal number Nc and the waveform of the compensation signal Ocmp are the same.
  • the horizontal axis is time.
  • the vertical axis of the total output voltage Vsum and the compensation signal Ocmp is the grayscale level
  • the vertical axis of the output voltages V3, V2, V1 is the digital voltage level.
  • FIGS. 8 and 10 show the operation waveforms when the compensation signal Ocmp monotonically increases from a voltage correction value corresponding to gradation level 3 to a voltage correction value corresponding to gradation level 5. Also, both Figs. 8 and 10 show the case where the output polarity instruction signal Opol is positive, i.e., a positive voltage instruction. Times t0 to t12 shown in Figs. 8 and 10 are the start and end times of the cycle ordinal number Nc or the time when the total output voltage Vsum changes. In Figs. 8 and 10, six cycles of the control cycle Tc with cycle ordinal numbers Nc from 1 to 6 are shown. Note that the example of the output voltage V3 shown in Figs.
  • the compensation signal Ocmp is at gradation level 3 at time t0, at gradation level 4 at time t6, and at gradation level 5 at time t12.
  • the gradation levels of the output voltages V3, V2, and V1 change from time t0 to t12 as follows. From time t0 to time t6, the output voltages V3, V2, and V1 are PWM controlled with voltages set at gradation level 3 and gradation level 4a, respectively. From time t6 to time t12, the output voltages V3, V2, and V1 are PWM controlled with voltages set at gradation level 4b and gradation level 5, respectively.
  • the gradation level is 4b, from time t9 to time t10, the gradation level is 5b, from time t10 to time t11, the gradation level is 4b, and from time t11 to time t12, the gradation level is 5.
  • the gradation level setting data in Figure 9 is used.
  • the voltage combination of gradation level 3 and the voltage combination of gradation level 4 are used, and when the compensation signal Ocmp is between gradation level 4 and gradation level 5, the voltage combination of gradation level 4 and the voltage combination of gradation level 5 are used.
  • the compensation signal Ocmp is at gradation level 3 at time t0, at gradation level 4 at time t6, and at gradation level 5 at time t12.
  • the changes in the gradation levels of the output voltages V3, V2, and V1 from time t0 to t12 are as follows: From time t0 to time t1, it is at gradation level 3, from time t1 to time t2, it is at gradation level 4, from time t2 to time t3, it is at gradation level 3, and from time t3 to time t4, it is at gradation level 4.
  • the period from time t8 to time t9 is gradation level 4, the period from time t9 to time t10 is gradation level 5, the period from time t10 to time t11 is gradation level 4, and the period from time t11 to time t12 is gradation level 5.
  • the power conversion device 100 of the first embodiment has gradation level setting data in which the ratio of the output voltages V1 to Vn of the single-phase inverters A1 to An is set so that there exists a gradation level, i.e., a special level SL, that can be realized by a voltage combination of a plurality of output voltages V, and by devising the selection of the voltage combination of the output voltages V1 to Vn used for PWM control, it is possible to reduce the number of switching operations of a specific single-phase inverter, i.e., a target single-phase inverter.
  • the gradation level setting data is provided, for example, in the control signal generating unit 39 of the control unit 10. In the example of FIG.
  • the target single-phase inverter is the single-phase inverter A3 that outputs the output voltage V3. Note that in FIG. 8, although the single-phase inverter A2 that outputs the output voltage V2 is not the target single-phase inverter in the gradation level setting data, the single-phase inverter A2 is an example in which the number of switching operations can be reduced.
  • the power conversion device 100 of the first embodiment can reduce the switching loss generated in the target single-phase inverter by reducing the number of switching operations of the target single-phase inverter, and since the generated loss can be reduced, the power conversion device 100 can be made highly efficient.
  • the power conversion device 100 of the first embodiment reduces heat generation in the power converter 50, so the options for the types of switching elements are increased, the heat sink can be made smaller, and the power conversion device 100 can be made smaller.
  • the power conversion device of Patent Document 1 has a problem that the components and heat sink that constitute the single-phase inverter are large, and the power conversion device is large, resulting in a high cost of the power conversion device.
  • the power conversion device 100 of the first embodiment can increase the options for the types of switching elements, so small switching elements and heat sinks can be installed, and the power conversion device 100 can be made smaller, resulting in a low-cost power conversion device 100.
  • a dead time is provided so as not to short-circuit the half-bridge inverters BN and BP of the single-phase inverter A.
  • the output voltage cannot be controlled, which causes the output waveform to become distorted.
  • the power conversion device 100 of the first embodiment reduces the number of times the target single-phase inverter is switched, so the dead time can be relatively short, which is also effective in preventing distortion of the output voltage.
  • the target single-phase inverter is particularly desirable to apply to single-phase inverters with large voltage ratios.
  • Single-phase inverters with large voltage ratios need to employ switching elements with high voltage resistance.
  • switching elements with high voltage resistance have lower characteristics such as switching speed compared to switching elements with low voltage resistance, so it is necessary to extend the dead time, resulting in large switching losses.
  • the target single-phase inverter that reduces the number of switching operations according to embodiment 1 is highly effective when applied to single-phase inverters with large voltage ratios.
  • the voltage combination of the gradation level 4a in the special level SL is switched to the voltage combination of the gradation level 4b at the timing when the compensation signal Ocmp becomes 4, but the timing of switching the gradation level is not limited to this and may be other timing. While the switching timing shown in FIG. 8 is dependent on the compensation signal, it may be dependent on the adjacent gradation level based on the change to the gradation level adjacent to the special level SL. Specifically, in the gradation level setting data of FIG. 7, the gradation levels other than the special level adjacent to the special level SL are gradation level 5 and gradation level 3. Until the voltage combination of gradation level 5 in FIG.
  • gradation level 4a continues to be used.
  • gradation level 5 may be used before gradation level 4b is used.
  • gradation level 4b may be continued until a voltage combination of gradation level 3 is required, and then gradation level 3 may be used before gradation level 4a begins to be used.
  • adjacent gradation level dependency is when the gradation level is switched with a delay from the timing of the arrival of the compensation signal, so it can also be said to be a switching timing with hysteresis.
  • the target single-phase inverter for reducing the number of switching times was the single-phase inverter A3 that outputs the output voltage V3.
  • this single-phase inverter A3 has a state change from "0" to "1”
  • FIG. 8 shows that the number of switching times of the single-phase inverter A3 can be reduced when the state changes from "0" to "1”.
  • FIG. 8 shows that the number of switching times is also reduced for the single-phase inverter A2 that outputs the output voltage V2, which is not the target single-phase inverter, but the number of switching times of V2 is reduced only when the state changes from "1" to "-1".
  • the output voltage V2 also has state changes from “0" to “1” and “-1” to “0” according to the gradation level setting data of FIG. 7, and the number of switching times for these changes is not reduced.
  • the output voltage V2 In order to reduce the number of switching times for the output voltage V2 of the single-phase inverter A2 in all state changes, the output voltage V2 must also be set to a voltage ratio that satisfies formula (2).
  • the power conversion device 100 of embodiment 1 can also reduce the number of switching times of the output voltage V2 for the single-phase inverter A2 that outputs the output voltage V2 that is not the target single-phase inverter, although for some changing states.
  • the power conversion device 100 of embodiment 1 has the special level SL in the gradation level setting data, and therefore an effect is obtained in that the number of switching times of the single-phase inverter that is not the target single-phase inverter can also be reduced compared to the comparative example.
  • the gradation level setting data shown in FIG. 11 is an example of gradation level setting data in a second power conversion device 100 equipped with two single-phase inverters A1 and A2.
  • the single-phase inverter A2 that outputs an output voltage V2 is the target single-phase inverter, and the voltage ratio of the output voltage V2 satisfies equation (2) with i being 1.
  • the single-phase inverter A1, which has an output voltage V1 with a voltage ratio of 1, is the minimum single-phase inverter that outputs a minimum output voltage Vmin.
  • the second power conversion device 100 can also reduce the number of switching times of the target single-phase inverter, and a small-sized gradation control type power conversion device can be realized.
  • the power conversion device 100 of the first embodiment includes a special level SL that can realize the same total output voltage Vsum by combining the output voltages V1 to Vn of the multiple single-phase inverters A1 to An at the gradation level of the gradation control, and when the control unit 10 executes PWM control of the power converter 50 using the special level SL, it selects one voltage combination at the special level SL in which at least one output voltage (e.g., output voltage Vn) does not change, excluding the minimum output voltage (output voltage V1) whose absolute value other than zero voltage is the smallest, so that a small-sized gradation-controlled power conversion device can be realized.
  • at least one output voltage e.g., output voltage Vn
  • FIG. 1 and 3 show an example in which the drive signals so1 to son of all the single-phase inverters A1 to An are generated by one gate driver GD1 to GD, respectively. That is, an example in which the two half-bridge inverters BN and BP of the single-phase inverter A are driven by one gate driver GD is shown, but this is not limited to this example.
  • the gate driver GD may have a different configuration, such as preparing two gate drivers capable of driving one half-bridge inverter, that is, configuring the first gate driver that drives the half-bridge inverter BN and the second gate driver that drives the half-bridge inverter BP as separate components. Also, in FIG.
  • the gate driver GD generates the drive signal so using the control signals SN and SP for the single-phase inverter A output from the control unit 10 and the control signals obtained by inverting the control signals SN and SP by the inverter 61, but this is not limited to this example.
  • a gate driver GD in which the control signals SN and SP are output from the control unit 10 together with the control signals SN and SP and the control signals obtained by logically inverting the control signals SN and SP and the inverter 61 is removed may be used.
  • the inverter 61 and the dead time generating units DTN and DTP may be removed from the gate driver GD, and the dead time generating units DTN and DTP may be provided in the control unit 10, with the control unit 10 outputting the dead time signals sdtNH, sdtNL, sdtPH, and sdtPL to the gate driver GD.
  • the control unit 10 outputs a control signal to which a dead time has been added to the gate driver GD.
  • the polarity of the output voltage V can be switched and output, but the single-phase inverter A is not limited to this.
  • the single-phase inverter A may be only one half-bridge inverter.
  • the switching element QNH on the high-side i.e., high-potential side wiring Lh side in the half-bridge inverter BN in FIG.
  • the drain terminal d and source terminal s of the switching element QNL on the low-side, i.e., low-potential side wiring Ll side may be shorted to be in a state, and the single-phase inverter A may be configured with only the half-bridge inverter BP.
  • the low-side switching element QNL may be removed.
  • the drain terminal d and source terminal s of the low-side switching element QPL may be shorted to form a single-phase inverter A using only the half-bridge inverter BN.
  • the low-side switching element QPL may also be removed.
  • control unit 10 is configured to have the output instruction unit 31 inside, but the output instruction unit 31 may be outside the control unit 10, and the control unit 10 may receive the output instruction value Oref from outside.
  • the power conversion device 100 of the first embodiment has been described on the assumption that the PWM operation is performed, but it can also be applied to control without PWM operation.
  • it can also be applied to a configuration in which the subtraction unit 36, the pulse modulation unit 37, and the addition unit 38 are removed from the control unit 10.
  • the gradation level is selected by the integer conversion signal Oint, which is the output of the integer conversion processing unit 35.
  • the compensation signal Ocmp fluctuates as shown in FIG.
  • the power conversion devices 100 of the second to sixth embodiments described later can also be applied to control without PWM operation.
  • the power conversion device 100 of the first embodiment includes a power converter 50 in which the AC sides (output terminals N, P) of the single-phase inverters A that convert DC power into AC power are connected in series, and which supplies DC or AC power of the total output voltage Vsum, which is the sum of the output voltages V output by the multiple single-phase inverters A, to the load 20, and a control unit 10 that controls the power converter 50.
  • a power converter 50 in which the AC sides (output terminals N, P) of the single-phase inverters A that convert DC power into AC power are connected in series, and which supplies DC or AC power of the total output voltage Vsum, which is the sum of the output voltages V output by the multiple single-phase inverters A, to the load 20, and a control unit 10 that controls the power converter 50.
  • Vsum DC or AC power of the total output voltage Vsum
  • the absolute value of the total output voltage Vsum which can be discretely set by selectively combining the outputs of the multiple single-phase inverters A, is defined as the gradation level, and the predetermined gradation level at which the same level of the total output voltage Vsum is realized by a plurality of voltage combinations, which are combinations of the output voltages V, is defined as the special level SL, and the gradation levels that can be set include at least one special level SL.
  • the control unit 10 controls the single-phase inverter A to output a total output voltage Vsum of a set voltage value by selecting a combination of output voltages V of the multiple single-phase inverters A.
  • the control unit 10 selects a voltage combination that does not change the output voltage V3 of at least one single-phase inverter A3 excluding the minimum single-phase inverter (single-phase inverter A1).
  • the power conversion device 100 of the first embodiment includes a special level SL that can realize the same total output voltage Vsum with a combination of output voltages V1, V2, and V3 of the multiple single-phase inverters A1, A2, and A3 in the gradation level, and when the control unit 10 controls the power converter 50 using the special level SL, a voltage combination that does not change at least one output voltage V3 excluding the minimum output voltage (output voltage V1) with the smallest absolute value is selected, so that a small-sized gradation control type power conversion device can be realized.
  • FIG. 12 is a diagram showing an example of gradation levels and output voltages in a power conversion device according to the second embodiment
  • FIG. 13 is a diagram showing a first example of the operation of the power conversion device according to the second embodiment
  • FIG. 14 is a diagram showing an example of the operation of a power conversion device of a comparative example
  • FIG. 15 is a diagram showing a second example of the operation of the power conversion device according to the second embodiment.
  • a condition having a gradation level that can be realized by a voltage combination of the output voltages V of a plurality of single-phase inverters A that is, a special level SL
  • a condition having a gradation level that can be realized by a voltage combination of the output voltages V of a plurality of single-phase inverters A that is, a special level SL
  • the value of i is not limited to 1.
  • the special level SL can be set to two or more.
  • the power conversion device 100 of the second embodiment is an example having gradation level setting data having two or more special levels SL.
  • the gradation level setting data is provided, for example, in the control signal generating unit 39 of the control unit 10. The parts different from the power conversion device 100 of the first embodiment will be mainly described.
  • FIG. 12 shows an example of gradation levels and output voltages V1 to V3 in the power conversion device 100 of embodiment 2, i.e., an example of gradation level setting data.
  • the ratio of the total output voltage Vsum is 0, 1 to 11, and the gradation levels are 0, 1 to 11.
  • the gradation level 3 in which the ratio of the total output voltage Vsum is 3 is the first special level SLa
  • the gradation level 4 in which the ratio of the total output voltage Vsum is 4 is the second special level SLb.
  • the gradation level for the first voltage combination in the first special level SLa is described as 3a
  • the gradation level for the second voltage combination in the first special level SLa is described as 3b
  • the gradation level for the first voltage combination in the second special level SLb is described as 4a
  • the gradation level for the second voltage combination in the second special level SLb is described as 4b.
  • the gradation level setting data shown in FIG. 12 is an example in which two special levels SL are set.
  • the special levels are generally designated SL, and SLa and SLb are used when distinguishing between them. Note that when there are three or more special levels SL and they are to be distinguished, a lowercase alphabet is added after "SL" and SLa, SLb, SLc, SLd, etc. are used.
  • Figure 13 shows a first example of the operation of the power conversion device 100 of the second embodiment, and is an example of an operating waveform in which a time series of gradation level changes is selected so as to reduce the number of switching times of a specific single-phase inverter, i.e., a target single-phase inverter, based on the gradation level setting data in which the ratio of output voltages V1 to V3 shown in Figure 12 is 1:3:7.
  • the target single-phase inverter is a single-phase inverter A3 that outputs an output voltage V3.
  • Figure 13 shows voltage waveforms 43a, 43b, 43c of the output voltages V3, V2, V1, the cycle ordinal number Nc, the waveform of the total output voltage Vsum, and the waveform of the compensation signal Ocmp.
  • the horizontal axis is time.
  • the vertical axis of the total output voltage Vsum and compensation signal Ocmp is the gradation level, and the vertical axis of the output voltages V3, V2, V1 is the digital voltage level.
  • the example of the output voltage V3 shown in Figure 13 is an example in which the output polarity instruction signal Opol is positive, i.e., a positive voltage instruction, and the output voltage V3 in the gradation level setting data is only "1" and "0", and a voltage level of "-1" is not output, so only "1” and "0” are shown.
  • the output polarity instruction signal Opol is negative, that is, when it indicates a negative voltage
  • the voltage levels of the voltage waveforms 43b and 43c of the output voltages V2 and V1 are inverted from positive to negative, and the voltage level of the voltage waveform 43a of the output voltage V3 changes between “0” and "-1.”
  • FIG. 13 the operation waveforms are shown when the compensation signal Ocmp monotonically increases from a voltage correction value corresponding to gradation level 2 to a voltage correction value corresponding to gradation level 5, and when gradation level switching is performed depending on adjacent gradation levels.
  • FIG. 13 also shows the case when the output polarity instruction signal Opol is positive, i.e., a positive voltage instruction.
  • Times t0 to t18 shown in FIG. 13 are the start and end times of the cycle ordinal number Nc, or the times when the overall output voltage Vsum changes.
  • nine cycles of the control cycle Tc are shown, with cycle ordinal numbers Nc ranging from 1 to 9.
  • the gradation levels other than the special levels adjacent to the special levels SLa and SLb are gradation level 2 and gradation level 5.
  • gradation levels 3a and 4a continue to be used until the voltage combination of gradation level 5 is required, that is, until the timing of time t13 in the period when the cycle ordinal number Nc is 7. Then, once gradation level 5 has been used, gradation levels 3b and 4b are used unless the voltage combination of gradation level 2 is used.
  • the compensation signal Ocmp is at gradation level 2 at time t0, at gradation level 3 at time t6, at gradation level 4 at time t12, and at gradation level 5 at time t18.
  • the gradation levels of the output voltages V3, V2, and V1 change from time t0 to t18 as follows. From time t0 to time t7, the output voltages V3, V2, and V1 are PWM-controlled with voltages set at gradation level 2 and gradation level 4a, respectively.
  • the output voltages V3, V2, and V1 are PWM-controlled with voltages set at gradation level 3a and gradation level 4a, respectively.
  • the output voltages V3, V2, and V1 are PWM-controlled with voltages set at gradation level 4b and gradation level 5, respectively.
  • the period from time t0 to time t1 is gradation level 2
  • the period from time t1 to time t2 is gradation level 3a
  • the period from time t2 to time t3 is gradation level 2
  • the period from time t3 to time t4 is gradation level 3a.
  • the period from time t4 to time t5 is gradation level 2
  • the period from time t5 to time t7 is gradation level 3a.
  • the period from time t7 to time t8 is gradation level 4a
  • the period from time t8 to time t9 is gradation level 3a
  • the period from time t9 to time t10 is gradation level 4a
  • the period from time t10 to time t11 is gradation level 3a.
  • the period from time t11 to time t13 is gradation level 4a
  • the period from time t13 to time t14 is gradation level 5.
  • the gradation level is 4b, from time t15 to time t16, the gradation level is 5, from time t16 to time t17, the gradation level is 4b, and from time t17 to time t18, the gradation level is 5.
  • the power conversion device 100 of the second embodiment like the power conversion device 100 of the first embodiment, has gradation level setting data in which the ratios of the output voltages V1 to Vn of the single-phase inverters A1 to An are set so that there exists a gradation level, i.e., a special level SL, that can be realized by a voltage combination of a plurality of output voltages V, and by devising the selection of the voltage combination of the output voltages V1 to Vn used for PWM control, it is possible to reduce the number of switching times of a specific single-phase inverter, i.e., a target single-phase inverter.
  • a gradation level i.e., a special level SL
  • the target single-phase inverter is a single-phase inverter A3 that outputs an output voltage V3.
  • the single-phase inverter A2 that outputs an output voltage V2 is not the target single-phase inverter in the gradation level setting data, the single-phase inverter A2 is an example in which the number of switching times can be reduced.
  • the power conversion device 100 of the second embodiment has two or more special levels and switches the gradation levels depending on the adjacent gradation levels, so that it has advantageous effects not described in the first embodiment.
  • special levels SL which are gradation levels that can be realized by voltage combinations of the output voltages V of the multiple single-phase inverters A
  • the number of gradation levels that the target single-phase inverter, which is a specific single-phase inverter, can output without switching can be increased compared to the case where this is not the case, and the period during which the target single-phase inverter does not switch can be increased.
  • This is advantageous when the output voltage control signal Oct changes suddenly, for example, when a large noise is applied to the output instruction value Oref output by the output instruction unit 31.
  • the operation when the compensation signal Ocmp changes suddenly will be described using Figures 14 and 15.
  • Figure 14 shows an example of operation when the ratio of output voltages V1 to V3 is 1:3:8, i.e., based on the gradation level setting data of Figure 7, and Figure 15 shows an example of operation when the ratio of output voltages V1 to V3 is 1:3:7, i.e., based on the gradation level setting data of Figure 12.
  • Figure 14 shows an example of operation of a comparative example for power conversion device 100 of embodiment 2
  • Figure 15 shows a second example of operation of power conversion device 100 of embodiment 2.
  • Figures 14 and 15 show operational waveforms when a drop of a magnitude equivalent to gradation level 1 occurs in compensation signal Ocmp during the period from gradation level 4 to gradation level 5 while compensation signal Ocmp is rising.
  • compensation signal Ocmp is at gradation level 3 at time t0, at gradation level 4 at time t6, and at gradation level 5 at time t12.
  • the compensation signal Ocmp is at gradation level 3 at time t6, at gradation level 4 at time t12, and at gradation level 5 at time t18. Therefore, the period from time t0 to time t12 in FIG. 14 is compared with the period from time t6 to time t18 in FIG. 15.
  • the operation during the period from time t7 to time t12 in FIG. 14 is as follows. From time t7 to time t8, it is gradation level 5, from time t8 to time t9, it is gradation level 3, from time t9 to time t11, it is gradation level 4a, and from time t11 to time t12, it is gradation level 5.
  • the operation during the period from time t7 to time t12 in FIG. 14 is the operation when gradation level switching is performed not depending on adjacent gradation levels but depending on compensation signals. Note that during the period from time t7 to time t12 in FIG.
  • the power conversion device 100 of the second embodiment like the power conversion device 100 of the first embodiment, has gradation level setting data with at least one gradation level, i.e., one special level SLa, SLb, that can be realized by a voltage combination of a plurality of output voltages V, and therefore has the same effect as the power conversion device 100 of the first embodiment. Furthermore, the power conversion device 100 of the second embodiment has gradation level setting data with two or more gradation levels, i.e., two or more special levels SLa, SLb, that can be realized by a voltage combination of a plurality of output voltages V, and therefore can reduce the number of switching operations of the target single-phase inverter even if the compensation signal Ocmp changes suddenly.
  • the power conversion device 100 of the second embodiment can increase the amount of fluctuation of the compensation signal Ocmp that can suppress the switching of the target single-phase inverter, and can suppress the occurrence of switching losses in the target single-phase inverter and the power converter 50.
  • the power conversion device 100 of the second embodiment by increasing the number of gradation levels that can be set by the voltage combinations of the output voltages V1 to Vn of the multiple single-phase inverters A1 to An, the absolute number of gradation levels that can be set is reduced. Therefore, it is desirable to check the degree of fluctuation in the compensation signal Ocmp and optimally design the number of gradation levels that can be set by the voltage combinations of the output voltages V1 to Vn of the single-phase inverters A1 to An.
  • FIG. 16 is a diagram showing an example of gradation levels and output voltages in a power conversion device according to a third embodiment.
  • the gradation level setting data in the first and second embodiments is an example that satisfies the first and second conditions.
  • the gradation level setting data satisfies the third or fourth condition shown below.
  • the parts different from the power conversion device 100 in the first and second embodiments will be mainly described.
  • the gradation level setting data in the first and second embodiments is most suitable for increasing the number of gradation levels per number of single-phase inverters A among the configurations that can output gradation levels for each gradation.
  • the power conversion device 100 of the third embodiment includes a single-phase inverter A that outputs at least three different output voltages V, and has at least one special level SL in the gradation level that can be realized by a voltage combination of the output voltages V of the multiple single-phase inverters A, i.e., the gradation level setting data.
  • the gradation level setting data may have at least one special level SL, and the ratio of the output voltages V1 to V3 may be 1:2:4, etc.
  • the third condition is satisfied when the minimum voltage ratio of the smallest single-phase inverter, which is a single-phase inverter that outputs the minimum output voltage Vmin, is 1, m is a natural number, the absolute value of the output voltage Vm of the mth single-phase inverter Am counted in ascending order of the absolute value of the output voltage excluding the smallest single-phase inverter is J, and the sum of the voltage ratios of the single-phase inverters whose voltage ratio is smaller than J is K.
  • single-phase inverter A1 whose output voltage V1 has a voltage ratio of 1, is the minimum single-phase inverter that outputs the minimum output voltage Vmin, output voltage V2, whose voltage ratio is 2, is the output voltage of single-phase inverter A2 that satisfies equation (5), and output voltage V3, whose voltage ratio is 4, is the output voltage of single-phase inverter A3 that satisfies equation (5).
  • the gradation level setting data of the third embodiment shown in FIG. 16 cannot distinguish between the target single-phase inverter and other single-phase inverters based on the difference in the formula, so each single-phase inverter is controlled to reduce the number of switching times of a target single-phase inverter by using a single-phase inverter other than the single-phase inverter that outputs the minimum output voltage Vmin as the target single-phase inverter.
  • the gradation level setting data shown in FIG. 16 is an example in which four special levels SLa, SLb, SLc, and SLd are set.
  • Special level SLa is set to gradation level 1, and has three voltage combinations.
  • the gradation level for the first voltage combination in special level SLa is described as 1a
  • the gradation level for the second voltage combination in special level SLa is described as 1b
  • the gradation level for the third voltage combination in special level SLa is described as 1c.
  • Special level SLb is set to gradation level 2, and has two voltage combinations.
  • the gradation level for the first voltage combination in special level SLb is described as 2a
  • the gradation level for the second voltage combination in special level SLb is described as 2b.
  • the special level SLc is set to gradation level 3, and has three voltage combinations.
  • the gradation level for the first voltage combination in the special level SLc is described as 3a
  • the gradation level for the second voltage combination in the special level SLc is described as 3b
  • the gradation level for the third voltage combination in the special level SLc is described as 3c.
  • the special level SLd is set to gradation level 5, and has two voltage combinations.
  • the gradation level for the first voltage combination in the special level SLd is described as 5a
  • the gradation level for the second voltage combination in the special level SLd is described as 5b.
  • a voltage combination at a special level may be selected with timing dependent on the adjacent gradation level as described in the second embodiment.
  • gradation levels 1a, 2a, and 3a may be used until the compensation signal Ocmp reaches gradation level 4, and once the compensation signal Ocmp reaches gradation level 4, gradation levels 1c, 2b, and 3b may be used, for example, until the compensation signal Ocmp reaches gradation level 0.
  • the minimum voltage ratio of the smallest single-phase inverter that outputs the minimum output voltage Vmin is 1, m is a natural number, the voltage ratio of the absolute value
  • the gradation level setting data of the third embodiment may satisfy not only the third condition but also the fourth condition. For example, even if the ratio of the output voltages V1 to V3 is 1:2:6, the gradation level setting data has at least one special level SL.
  • the gradation level setting data may satisfy the fourth condition when the minimum voltage ratio of the smallest single-phase inverter that outputs the minimum output voltage Vmin is 1, m and i are natural numbers, the voltage ratio of the absolute value
  • the other single-phase inverters that output an output voltage larger than the minimum output voltage Vmin include the single-phase inverter that satisfies the formula (5) and the single-phase inverter that satisfies the formula (2).
  • Single-phase inverter A1 whose output voltage V1 has a voltage ratio of 1, is the minimum single-phase inverter that outputs the minimum output voltage Vmin, output voltage V2, whose voltage ratio is 2, is the output voltage of single-phase inverter A2 that satisfies formula (5), and output voltage V3, whose voltage ratio is 6, is the output voltage of single-phase inverter A3 that satisfies formula (2) with i set to 1.
  • the gradation level setting data of the first and second embodiments has the advantage of being able to increase the number of gradation levels per number of single-phase inverters A the most among the configurations that can output gradation levels for each gradation level.
  • the gradation level setting data of the third embodiment has a smaller number of gradation levels per number of single-phase inverters A than the gradation level setting data of the first and second embodiments.
  • the power conversion device 100 of the third embodiment to which the gradation level setting data of the third embodiment is applied has a larger number of special levels SL than the gradation level setting data of the first and second embodiments, so that it can reduce the number of switching operations of the target single-phase inverter while appropriately responding to abrupt changes in the compensation signal Ocmp more than the power conversion device 100 of the first and second embodiments. That is, the power conversion device 100 of the third embodiment can increase the amount of fluctuation in the compensation signal Ocmp that can suppress the switching of the target single-phase inverter more than the power conversion device 100 of the first and second embodiments.
  • FIG. 11 An example of gradation level setting data in a power conversion device 100 having two single-phase inverters A1, A2 that satisfy formula (5) is shown in FIG. 11.
  • only one special level SL is set for gradation level 1.
  • the power conversion device 100 of embodiment 3 to which gradation level setting data from two single-phase inverters A1, A2 that satisfy formula (5) is applied achieves the same effect as the power conversion device 100 of embodiment 1.
  • FIG. 17 is a diagram showing an example of gradation levels and output voltages in a power conversion device according to the fourth embodiment
  • FIG. 18 is a diagram showing an example of the operation of the power conversion device according to the fourth embodiment
  • FIG. 19 is a diagram showing an example of gradation levels and output voltages in a power conversion device of a comparative example
  • FIG. 20 is a diagram showing an example of the operation of the power conversion device of the comparative example.
  • a plurality of single-phase inverters A of the power converter 50 can output three types of output voltages V, namely, a positive voltage, a negative voltage of the opposite polarity to the positive voltage, and a zero voltage. More specifically, even during a period determined by the output polarity determination unit 33 as a positive voltage instruction, a single-phase inverter that has received an output instruction of "-1" has output a negative voltage, and even during a period determined by the output polarity determination unit 33 as a positive voltage instruction, a single-phase inverter that has received an output instruction of "-1" has output a positive voltage.
  • the power conversion device 100 in the fourth embodiment is an example realized by a single-phase inverter A that outputs two types of output voltage V, i.e., output voltage V indicated as "1" and "0" in the gradation level setting data.
  • the power conversion device 100 in the fourth embodiment is an example in which the combination of output voltages in the multiple single-phase inverters A associated with the gradation levels is set in two states, output instruction and no output instruction, and the control unit 10 controls the multiple single-phase inverters A based on the output instruction and no output instruction states in the combination of output voltages in the multiple single-phase inverters A and the polarity state of the total output voltage Vsum.
  • the polarity state of the total output voltage Vsum is, for example, the positive voltage instruction state or negative voltage instruction state of the output polarity instruction signal Opol.
  • the control unit 10 controls the multiple single-phase inverters A as follows.
  • the control unit 10 controls the multiple single-phase inverters A to output two types of output voltages, a positive voltage and a zero voltage, when the total output voltage Vsum is set to a positive voltage, and controls the multiple single-phase inverters A to output two types of output voltages, a negative voltage and a zero voltage, when the total output voltage Vsum is set to a negative voltage.
  • the multiple single-phase inverters A of the power converter 50 can output three types of output voltages V, a positive voltage, a negative voltage of the opposite polarity to the positive voltage, and a zero voltage, and can output a negative total output voltage Vsum like the power conversion device 100 in the first embodiment, even if the output voltage V is set only to "1" and "0" in the gradation level setting data.
  • the power conversion device 100 in the fourth embodiment is provided with a single-phase inverter A that outputs at least three different output voltages V, even if the output voltage V is set only to "1" and "0" in the gradation level setting data, and as long as the gradation level setting data has a special level SL, the number of switching operations of the target single-phase inverter can be reduced like the power conversion device 100 in the first embodiment.
  • the following mainly describes the differences from the power conversion device 100 in embodiments 1 to 3.
  • the examples of gradation levels, output voltages V1 to V3, and total output voltage Vsum shown in FIG. 17 are gradation level setting examples, i.e., gradation level setting data, when the ratio of output voltages V1 to V3 is 1:2:3.
  • the gradation level setting data shown in FIG. 17 is an example set with only "1" and "0".
  • the gradation level setting data shown in FIG. 17 is configured with single-phase inverters A1 to A3 that output three different output voltages V1 to V3 with a voltage ratio of 1:2:3, and is configured as a special level SL where gradation level 3, where the ratio of the total output voltage Vsum is 3, can be achieved with two voltage combinations.
  • the gradation level for the first voltage combination at special level SL is described as 3a
  • the gradation level for the second voltage combination at special level SL is described as 3b.
  • the fifth and sixth conditions are satisfied when the minimum voltage ratio of the smallest single-phase inverter that outputs the minimum output voltage Vmin is 1, m is a natural number, the voltage ratio of the absolute value
  • the single-phase inverter that satisfies the sixth condition is the target single-phase inverter.
  • Fifth condition All single-phase inverters other than the minimum single-phase inverter satisfy formula (6).
  • the single-phase inverter A1 with output voltage V1 having a voltage ratio of 1 is the minimum single-phase inverter that outputs the minimum output voltage Vmin
  • the output voltage V2 with a voltage ratio of 2 is a single-phase inverter that satisfies equation (9)
  • the output voltage V3 with a voltage ratio of 4 is a single-phase inverter that satisfies equation (7), i.e., the target single-phase inverter.
  • FIG. 18 shows a time series of gradation level changes selected based on the gradation level setting data shown in FIG. 17 so as to reduce the number of switching operations of a specific single-phase inverter, i.e., a target single-phase inverter.
  • the ratio of the output voltages V1 to V3 is 1:2:3
  • the special level SL is set to gradation level 3.
  • the special level SL has gradation levels 3a and 3b with different voltage combinations.
  • gradation level setting data in which the ratio of the output voltages V1 to V3 is 1:2:4 and does not have the special level SL is shown in FIG.
  • FIG. 20 An example of the operation of a power conversion device of a comparative example based on the gradation level setting data of FIG. 19 is shown in FIG. 20.
  • the gradation level setting data of the comparative example shown in FIG. 19 is an example in which all output voltages V1 to V3 satisfy formula (9).
  • the gradation level setting data for the comparative example in Figure 19 does not have a special level SL, so it has more gradation levels than the gradation level setting data in Figure 17, going up to gradation level 7.
  • Figure 18 shows voltage waveforms 46a, 46b, 46c of the output voltages V3, V2, V1, the cycle ordinal number Nc, the waveform of the total output voltage Vsum, and the waveform of the compensation signal Ocmp.
  • Figure 20 shows voltage waveforms 47a, 47b, 47c of the output voltages V3, V2, V1, the cycle ordinal number Nc, the waveform of the total output voltage Vsum, and the waveform of the compensation signal Ocmp.
  • the waveforms of the cycle ordinal number Nc and the compensation signal Ocmp are the same in Figures 18 and 20.
  • the horizontal axis is time.
  • the vertical axis of the total output voltage Vsum and the compensation signal Ocmp is the grayscale level
  • the vertical axis of the output voltages V3, V2, V1 is the digital voltage level.
  • the output polarity instruction signal Opol is positive, i.e., a positive voltage instruction
  • the gradation level setting data in Figure 17 only has “1” and "0”, and does not output a voltage level of "-1", so only "1” and "0" are shown.
  • the output polarity instruction signal Opol is negative, i.e., a negative voltage instruction
  • the voltage levels of voltage waveforms 46a, 46b, and 46c and voltage waveforms 47a, 47b, and 47c of V3, V2, and V1 change between "0" and "-1".
  • FIGS. 18 and 20 show the operating waveforms when the compensation signal Ocmp monotonically rises from a voltage correction value corresponding to gradation level 2 to a voltage correction value corresponding to gradation level 4. Also, both FIG. 18 and FIG. 20 show the case when the output polarity instruction signal Opol is positive, i.e., a positive voltage instruction. Times t0 to t12 shown in FIG. 18 and FIG. 20 are the start and end times of the cycle ordinal number Nc or the times when the total output voltage Vsum changes. Six cycles of the control cycle Tc with cycle ordinal numbers Nc from 1 to 6 are shown in FIG. 18 and FIG. 20.
  • a voltage combination at a special level is selected with timing dependent on adjacent gray levels as explained in embodiment 2.
  • Gray level 3a is used until the compensation signal Ocmp reaches gray level 4
  • gray level 3b is used until the compensation signal Ocmp reaches gray level 2.
  • the output states of the output voltages V2 and V3 change multiple times during the period in which the compensation signal Ocmp rises from 3 to 4.
  • the output states of the output voltages V2 and V3 change only once at the timing when the gradation level becomes 4 (time t7), and it can be seen that the number of switching times has been reduced.
  • the compensation signal Ocmp is at gradation level 2 at time t0, at gradation level 3 at time t6, and at gradation level 4 at time t12.
  • the gradation levels of the output voltages V3, V2, and V1 change from time t0 to t12 as follows. From time t0 to time t7, the output voltages V3, V2, and V1 are PWM controlled with voltages set at gradation levels 2 and 3a, respectively. From time t7 to time t12, the output voltages V3, V2, and V1 are PWM controlled with voltages set at gradation levels 3b and 4, respectively.
  • the compensation signal Ocmp is at gradation level 2 at time t0, at gradation level 3 at time t6, and at gradation level 4 at time t12.
  • the changes in the gradation levels of the output voltages V3, V2, and V1 from time t0 to t12 are as follows: From time t0 to time t1, it is at gradation level 2, from time t1 to time t2, it is at gradation level 3, from time t2 to time t3, it is at gradation level 2, and from time t3 to time t4, it is at gradation level 3.
  • the period from time t9 to time t10 is gradation level 4, the period from time t10 to time t11 is gradation level 3, and the period from time t11 to time t12 is gradation level 4.
  • the power conversion device 100 of the fourth embodiment has gradation level setting data in which the ratio of the output voltages V1 to Vn of each single-phase inverter A1 to An is set so that there exists a gradation level, i.e., a special level SL, that can be realized by a voltage combination of a plurality of output voltages V, even when the output voltage V is set only to "1" and "0" in the gradation level setting data, and by devising the selection of the voltage combination of the output voltages V1 to Vn used for PWM control, the number of switching times of a specific single-phase inverter, i.e., a target single-phase inverter, can be reduced.
  • a gradation level i.e., a special level SL
  • the gradation level setting data is provided, for example, in the control signal generating unit 39 of the control unit 10.
  • the target single-phase inverter is the single-phase inverter A3 that outputs the output voltage V3.
  • the single-phase inverter A2 that outputs the output voltage V2 is not the target single-phase inverter in the gradation level setting data, but the single-phase inverter A2 is an example in which the number of switching times can be reduced.
  • the power conversion device 100 of embodiment 4 can reduce the switching loss generated in the target single-phase inverter by reducing the number of switching operations of the target single-phase inverter, and since the generated loss can be reduced, high efficiency of the power conversion device 100 can be realized. Furthermore, the power conversion device 100 of embodiment 4 reduces heat generation of the power converter 50, so the options for the types of switching elements are increased, the heat sink can be made smaller, and the power conversion device 100 can be made smaller.
  • the power conversion device 100 of embodiment 4 can be equipped with small switching elements and heat sinks by increasing the options for the types of switching elements, and the miniaturization of the power conversion device 100 can realize a low-cost power conversion device 100.
  • Embodiment 5 are diagrams showing a first example of the gradation level and the output voltage in the power conversion device according to the fifth embodiment
  • FIG. 23 and FIG. 24 are diagrams showing a second example of the gradation level and the output voltage in the power conversion device according to the fifth embodiment
  • FIG. 25 is a diagram showing an operation example of the power conversion device according to the fifth embodiment
  • FIG. 26 is a diagram showing a third example of the gradation level and the output voltage in the power conversion device according to the fifth embodiment.
  • FIG. 21 shows gradation levels 0 to 23, and FIG. 22 shows gradation levels 24 to 39 in continuation of FIG. 21.
  • FIG. 23 shows gradation levels 0 to 21, and FIG. 24 shows gradation levels 22 to 36 in continuation of FIG. 23.
  • the number of single-phase inverters is two or three have been specifically described. It has been described that the number of single-phase inverters may be four or more as long as the two condition sets or two independent conditions described in the first to fourth embodiments are satisfied.
  • the two sets of conditions are the first and second conditions (first set of conditions) described in embodiment 1, and the fifth and sixth conditions (second set of conditions) described in embodiment 4.
  • the two independent conditions are the third and fourth conditions described in embodiment 3.
  • embodiment 5 an example in which the number of single-phase inverters connected in series is four will be specifically described, and differences from the power conversion device 100 of embodiments 1 to 4 will be mainly described.
  • the examples of the gradation levels, output voltages V1 to V4, and total output voltage Vsum shown in Figures 21 and 22 are gradation level setting examples, i.e., gradation level setting data, when the number of single-phase inverters connected in series is four and the output voltages V1 to V4 are 1:3:9:26.
  • the gradation level setting data shown in Figures 21 and 22 is configured such that the gradation level 13, at which the ratio of the total output voltage Vsum is 13, is set to a special level SL that can be realized with two voltage combinations.
  • the gradation level for the first voltage combination at the special level SL is described as 13a
  • the gradation level for the second voltage combination at the special level SL is described as 13b.
  • the gradation level 13a is used until the compensation signal Ocmp reaches gradation level 14, and once the compensation signal Ocmp reaches gradation level 14, the gradation level 13b is used until the compensation signal Ocmp reaches gradation level 12, the number of switching times of the output voltages V2 to V4 can be reduced.
  • the voltage combination selected in this case is an example of selecting a voltage combination at a special level with timing dependent on adjacent grayscale levels.
  • the single-phase inverter A1 with the output voltage V1 having a voltage ratio of 1 is the minimum single-phase inverter that outputs the minimum output voltage Vmin
  • the output voltages V2 and V3 with voltage ratios of 3 and 9 are single-phase inverters that satisfy the formula (4)
  • the output voltage V4 with a voltage ratio of 26 is a single-phase inverter that satisfies the formula (2), i.e., the target single-phase inverter.
  • a single-phase inverter that reduces the number of switching times i.e., a target single-phase inverter, is not limited to a single-phase inverter with a maximum voltage.
  • Figures 23 and 24 show gradation level setting data when there are two target single-phase inverters.
  • the single-phase inverters A3 and A4 whose output voltage V3 ratio is 8 and whose output voltage V4 ratio is 24, are target single-phase inverters that satisfy formula (2), and the other single-phase inverters A1 and A2 are not target single-phase inverters, i.e., single-phase inverters that satisfy formula (4).
  • the voltage ratios of the single-phase inverters A1 and A2 are as described above.
  • the gradation level setting data shown in Figures 23 and 24 is configured such that gradation levels 4, 12, 20, and 28, at which the ratio of the total output voltage Vsum is 4, 12, 20, and 28, respectively, are set as special levels SL that can be realized with two voltage combinations.
  • the four special levels SL are special levels SLa, SLb, SLc, and SLd.
  • Gradation level 4, at which the ratio of the total output voltage Vsum is 4, is the first special level SLa
  • gradation level 12, at which the ratio of the total output voltage Vsum is 12 is the second special level SLb.
  • Gradation level 20, at which the ratio of the total output voltage Vsum is 20, is the third special level SLc
  • gradation level 28, at which the ratio of the total output voltage Vsum is 28, is the fourth special level SLd.
  • the gradation level for the first voltage combination in the special level SLa is described as 4a
  • the gradation level for the second voltage combination in the special level SLa is described as 4b
  • the gradation level for the first voltage combination in the special level SLb is described as 12a
  • the gradation level for the second voltage combination in the special level SLb is described as 12b.
  • the gradation level for the first voltage combination in the special level SLc is described as 20a, and the gradation level for the second voltage combination in the special level SLc is described as 20b.
  • the gradation level for the first voltage combination in the special level SLd is described as 28a, and the gradation level for the second voltage combination in the special level SLd is described as 28b.
  • Fig. 25 shows a gradation level change time series selected based on the gradation level setting data shown in Figs. 23 and 24 so as to reduce the number of switching times of the target single-phase inverters A3 and A4.
  • Fig. 25 shows an operating waveform in the case where the compensation signal Ocmp monotonically increases from a voltage correction value corresponding to gradation level 11 to a voltage correction value corresponding to gradation level 13 in the range of gradation levels including gradation level 12 where the output state of the output voltage V3 switches from "1" to "-1".
  • Fig. 25 also shows the case where the output polarity instruction signal Opol is positive, i.e., a positive voltage instruction.
  • FIG. 25 shows voltage waveforms 48a, 48b, 48c, 48d of the output voltages V4, V3, V2, V1, the cycle ordinal number Nc, the waveform of the total output voltage Vsum, and the waveform of the compensation signal Ocmp.
  • the horizontal axis is time.
  • the vertical axis of the total output voltage Vsum and the compensation signal Ocmp is the gradation level
  • the vertical axis of the output voltages V4, V3, V2, V1 is the digital voltage level. Note that the example of the output voltage V4 shown in FIG.
  • the output polarity instruction signal Opol is positive, i.e., a positive voltage instruction
  • the output voltage V4 in the gradation level setting data is only "1" and "0”
  • a voltage level of "-1" is not output, so only "1” and "0” are shown.
  • the output polarity instruction signal Opol is negative, that is, when it indicates a negative voltage
  • the voltage levels of the voltage waveforms 48b, 48c, and 48d of the output voltages V3, V2, and V1 are inverted from positive to negative, and the voltage level of the voltage waveform 48a of the output voltage V4 changes between “0” and "-1.”
  • FIG. 25 an example is shown in which a voltage combination at a special level is selected at a timing dependent on the adjacent gray level. Until the compensation signal Ocmp reaches gray level 13, gray level 12a is used, and once the compensation signal reaches gray level 13, gray level 12b is used until the compensation signal Ocmp reaches 11.
  • the output states of the output voltages V2, V3, and V4 are changed only once at the timing (time t7) when they reach gray level 13, and it can be confirmed that the number of switching times has been reduced.
  • gray level 13a in which the output state of the output voltage V3 is "1" is selected until time t7, and gray level 13b, in which the output state of the output voltage V3 is "-1”, is selected after time t7, so that the number of switching times of the target single-phase inverter A3 that outputs the output voltage V3 can be reduced.
  • Times t0 to t12 shown in FIG. 25 are the start and end times of the cycle ordinal number Nc or the times when the total output voltage Vsum changes.
  • FIG. 25 shows six control cycles Tc with cycle ordinal numbers Nc ranging from 1 to 6.
  • the compensation signal Ocmp is at gradation level 11 at time t0, at gradation level 12 at time t6, and at gradation level 13 at time t12.
  • the changes in the gradation levels of the output voltages V4, V3, V2, and V1 from time t0 to t12 are as follows. From time t0 to time t7, the output voltages V4, V3, V2, and V1 are PWM-controlled with voltages set at gradation level 11 and gradation level 12a, respectively.
  • the output voltages V4, V3, V2, and V1 are PWM-controlled with voltages set at gradation level 12b and gradation level 13, respectively.
  • the period from time t0 to time t1 is gradation level 11, the period from time t1 to time t2 is gradation level 12a, the period from time t2 to time t3 is gradation level 11, and the period from time t3 to time t4 is gradation level 12a.
  • the period from time t4 to time t5 is gradation level 11, and the period from time t5 to time t7 is gradation level 12a.
  • the period from time t7 to time t8 is gradation level 13, and the period from time t8 to time t9 is gradation level 12b.
  • the period from time t9 to time t10 is gradation level 13
  • the period from time t10 to time t11 is gradation level 12b
  • the period from time t11 to time t12 is gradation level 13.
  • the target single-phase inverter A3 that does not output the maximum voltage can reduce the number of switching operations of the target single-phase inverter A3 that outputs the output voltage V3, not only at the timing when the output state of the output voltage V3 switches from “1” to “-1", but also at the timing when the output state of the output voltage V3 switches from "0" to "1” and at the timing when the output state of the output voltage V3 switches from "-1" to "0", similar to the operation of FIG. 25.
  • the timing when the output state of the output voltage V3 switches from “0” to “1” is the timing when the output state of the output voltage V3 switches from gradation level 4a to gradation level 4b at the special level SLa, or the timing when the output state of the output voltage V3 switches from gradation level 28a to gradation level 28b at the special level SLd.
  • the timing when the output state of the output voltage V3 switches from “-1" to "0” is the timing when the output state of the output voltage V3 switches from gradation level 20a to gradation level 20b at the special level SLc.
  • the waveform of the compensation signal Ocmp shown in FIG. 25 does not select a voltage combination at a special level at the timing dependent on the adjacent gradation level targeted at the single-phase inverter A4.
  • the output state of the output voltage V4 switches between "0" and "1" only under one condition, that is, the voltage combination of the gradation level 12a and the voltage combination of the gradation level 12b at the special level SLb where the ratio of the total output voltage Vsum is 12. This one condition is shown in FIG. 25.
  • the single-phase inverter A4 which outputs an output voltage greater than that of the single-phase inverter A3 set as the target single-phase inverter, may be set as a single-phase inverter that is not the target single-phase inverter if the output state changes from "0" to "1" only once in the gradation level setting data.
  • the single-phase inverter A3 is the target single-phase inverter that satisfies formula (2) and the other single-phase inverters A1, A2, and A4 are not the target single-phase inverters, that is, they are single-phase inverters that satisfy formula (4), it is possible to reduce the number of switching times of the single-phase inverter A3 and the single-phase inverter A4.
  • An example of the gradation level setting data in this case is described below.
  • the output voltages V1 to V4 are 1:3:8:25.
  • the single-phase inverter A3, whose output voltage V3 ratio is 8 is the target single-phase inverter that satisfies formula (2), and the other single-phase inverters A1, A2, and A4 are not the target single-phase inverters, that is, they are single-phase inverters that satisfy formula (4).
  • the voltage ratios of the single-phase inverters A1, A2, and A3 are as described above.
  • the gradation level setting data for which the output voltages V1 to V4 are 1:3:8:25 is not shown, but the single-phase inverter A4, which outputs the maximum voltage, changes its output state from "0" to "1" only once.
  • the power conversion device 100 of the fifth embodiment can reduce the number of switching times of the target single-phase inverter even if a target single-phase inverter other than the single-phase inverter that outputs the maximum voltage is set. Furthermore, the power conversion device 100 of the fifth embodiment can also reduce the number of switching times of a single-phase inverter with a larger voltage ratio than the single-phase inverter set as the target single-phase inverter, by controlling the selection of a time series of change in the gradation level so as to reduce the number of switching times of the target single-phase inverter.
  • the maximum value of the gradation level in the gradation level setting data shown in Figures 21 and 22 is 39, and the maximum value of the gradation level in the gradation level setting data shown in Figures 23 and 24 is 36. From these comparisons, if the target single-phase inverter that reduces the number of switching times is set to a single-phase inverter with a small voltage ratio, since there is -i in formula (2), even if a voltage ratio that satisfies formula (4) is set to a single-phase inverter that outputs an output voltage larger than the output voltage of this target single-phase inverter, the number of gradation levels that can be set will be small, and the maximum value of the gradation level will also be small.
  • multiple target single-phase inverters that satisfy formula (2), such as a voltage ratio of output voltages V1 to V4 of 1:3:7:20, may be set.
  • single-phase inverter A4 which has a higher voltage ratio than target single-phase inverter A3, whose output voltage is not the maximum voltage, reduces the number of switching operations even if it is not the target single-phase inverter, and when multiple target single-phase inverters are set, the number of settable gradation levels decreases. Therefore, it is preferable to set only one target single-phase inverter among the multiple single-phase inverters of power converter 50.
  • the power conversion device 100 has been described in the case where the output voltages of all the single-phase inverters are different. However, if two single-phase inverters A or three or more single-phase inverters that output different output voltages are provided, and if multiple voltage combinations are set for at least one gradation level, that is, if a special level SL is set for at least one gradation level, the power conversion device 100 may be configured with single-phase inverters that have the same voltage ratio.
  • the gradation level 4 at which the ratio of the total output voltage Vsum is 4 and the gradation level 12 at which the ratio of the total output voltage Vsum is 12 are set to the special level SL.
  • the gradation level for the first voltage combination in the first special level SLa is described as 4a
  • the gradation level for the second voltage combination in the first special level SLa is described as 4b.
  • the gradation level for the first voltage combination in the second special level SLb is described as 12a
  • the gradation level for the second voltage combination in the second special level SLb is described as 12b.
  • the gradation level 12a is used until the compensation signal Ocmp reaches 13, and once the compensation signal Ocmp reaches 13, the gradation level 12b is used until the compensation signal Ocmp reaches 11, thereby reducing the number of switching times of the output voltages V2 to V4.
  • the gradation level 4a is used until the compensation signal Ocmp reaches 5, and once the compensation signal Ocmp reaches 5, the gradation level 4b is used until the compensation signal Ocmp reaches 3, thereby reducing the number of switching times of the output voltages V2 to V4.
  • FIG. 26 shows gradation level setting data when two single-phase inverters have the same voltage ratio.
  • the number of single-phase inverters with the same voltage ratio is not limited to the example in FIG. 26.
  • the number of single-phase inverters with the same voltage ratio may be three or more, such as an example where the output voltages V1 to V5 are 1:3:8:8:8, or the output voltages V1 to V6 are 1:3:3:14:14:14, or multiple voltage ratios may be provided that include single-phase inverters with the same voltage ratio. Note that it is preferable to provide single-phase inverters with the same voltage ratio at the location where the maximum voltage ratio is achieved, as this increases the number of gradation levels that can be set.
  • FIG. 27 is a diagram showing the configuration of a power conversion device according to the sixth embodiment
  • FIG. 28 is a diagram showing the configuration of the control unit in FIG. 27
  • FIG. 29 is a diagram showing the configuration of a first example of the output detection unit in FIG. 27,
  • FIG. 30 is a diagram showing the configuration of a second example of the output detection unit in FIG. 27.
  • the power conversion device 100 of the sixth embodiment is different from the power conversion device 100 of the first embodiment in that it includes an output detection unit 21 that detects the voltage output by the power converter 50 to the load 20, i.e., the total output voltage Vsum, and an AD converter (Analog to Digital Converter) 25 and a subtraction unit 26 are added to the control unit 10.
  • the parts different from the power conversion device 100 of the first embodiment will be mainly described.
  • the output detection unit 21 detects at least one of the voltage or current output to the load 20, and outputs a negative feedback signal.
  • the sign of the negative feedback signal is denoted as OFB (Output Feedback).
  • the output detection unit 21 outputs an analog negative feedback signal OFB to the input terminal Ci of the control unit 10.
  • the AD converter 25 converts the analog negative feedback signal OFB input from the input terminal Ci into a digital negative feedback signal OFBd.
  • the subtraction unit 26 installed inside the control unit 10 is configured with an analog circuit, the AD converter 25 may not be necessary.
  • FIG. 29 shows an example of a circuit diagram of the output detection unit 21 that detects the voltage output to the load 20.
  • the output detection unit 21 shown in FIG. 29 is installed between the single-phase inverters A1 to An and the load 20.
  • the output detection unit 21 has a differential circuit composed of an operational amplifier OP and multiple resistors R1 to R4.
  • the output detection unit 21 detects a differential voltage from the voltage applied to the load 20 and outputs an analog negative feedback signal OFB.
  • the differential voltage is the voltage between the output power line 19 and the reference power line 18, which is at ground potential (GND potential).
  • the potential of the output power line 19 is input to the positive terminal (+ terminal) of the operational amplifier OP via resistors R2 and R3.
  • resistors R2 and R3 are connected in series to the positive terminal of the operational amplifier OP and the reference power line 18 at ground potential, and the connection point between the resistors R2 and R3 is connected to the output power line 19.
  • the negative terminal (- terminal) of the operational amplifier OP is supplied with a ground potential via resistor R1, and the negative feedback signal OFB, which is the output of the operational amplifier OP, is supplied with a resistor R4.
  • FIG. 30 shows an example of a circuit diagram of the output detection unit 21 that detects the current output to the load 20.
  • the output detection unit 21 shown in FIG. 30 is installed between the single-phase inverters A1 to An and the load 20. Specifically, the voltage across the current detection resistor Rs that detects the current in the output power line 19 through which the current flows to the load 20 or in the reference power line 18 through which the current flows from the load 20 is input as a differential voltage to the operational amplifier OP.
  • FIG. 30 shows an example in which the current detection resistor Rs is placed on the reference power line 18.
  • the differential circuit shown in FIG. 30 is the same as the differential circuit shown in FIG. 29.
  • One end of the current detection resistor Rs is connected to the negative terminal of the operational amplifier OP via resistor R1, and the other end of the current detection resistor Rs is connected to the connection point of resistors R2 and R3 in series that are connected to the positive terminal of the operational amplifier OP.
  • the output detection unit 21 of the power conversion device 100 of the sixth embodiment includes at least one of the circuits shown in FIG. 29 and FIG. 30.
  • the output detection unit 21 detects both the voltage and current output to the load 20, it may include both of the circuits shown in FIG. 29 and FIG. 30.
  • the configuration of the output detection unit 21 shown in FIG. 29 and FIG. 30 is one example, and it may have a different configuration, such as a configuration using a transformer, as long as it is capable of detecting at least one of the voltage or current output to the load 20.
  • the signal detected by the output detection unit 21 is input to the control unit 10 as a negative feedback signal OFB, converted to a digital value by the AD converter 25, and output to the subtraction unit 26 as a negative feedback signal OFBd.
  • the subtraction unit 26 subtracts the negative feedback signal OFBd from the output instruction value Oref output by the output instruction unit 31, and outputs the result as a difference signal Osub.
  • the compensation unit 32 performs a compensation operation such as a proportional operation, an integral operation, or a differential operation on the difference signal Osub to make the deviation zero, and outputs the result as a compensation signal Ocmp.
  • the operations after the compensation unit 32 are the same as in FIG. 5.
  • the output command value Oref is an output voltage command value when the target output to the load 20 is voltage.
  • the output command value Oref is an output current command value.
  • the output command value Oref may be both an output voltage command value and an output current command value, or may be a power command value.
  • the power conversion device 100 of embodiment 6 can feedback control the value of the total output voltage Vsum, which is the output value of the power conversion device 100 of embodiment 1.
  • the feedback control configuration shown in embodiment 6 can also be applied to the power conversion devices 100 of embodiments 2 to 5.
  • the functions of the control unit 10 may be realized by a processor 98 and a memory 99 shown in FIG. 31.
  • FIG. 31 is a diagram showing an example of a hardware configuration that realizes the functions of the control unit.
  • each functional unit in the control unit 10 is realized by the processor 98 executing a program stored in the memory 99.
  • multiple processors 98 and multiple memories 99 may cooperate to execute each function.
  • the functional units of the control unit 10 shown in FIG. 5 are the output instruction unit 31, the compensation unit 32, the output polarity determination unit 33, the absolute value processing unit 34, the integer processing unit 35, the subtraction unit 36, the pulse modulation unit 37, the addition unit 38, and the control signal generation unit 39.
  • the functional units of the control unit 10 shown in FIG. 28 are the nine functional units of the control unit 10 shown in FIG. 5 and the subtraction unit 26.
  • 10 Control unit, 20...Load, 50...Power converter, 100...Power conversion device, A, A1, A2, Am, An...Single-phase inverter, N...Output terminal, P...Output terminal, SL, SLa, SLb, SLc, SLd...Special level, Tc...Control period, V, V1, V2, Vm, Vn...Output voltage, Vsum...Total output voltage

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JP2004328831A (ja) * 2003-04-22 2004-11-18 Mitsubishi Electric Corp 電圧変動補償装置
JP2005080414A (ja) * 2003-09-01 2005-03-24 Mitsubishi Electric Corp 電力変換装置及びそれを用いたパワーコンディショナ
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JP5154587B2 (ja) 2010-01-28 2013-02-27 三菱電機株式会社 電力変換装置
DE112010005608B4 (de) * 2010-05-28 2018-02-01 Mitsubishi Electric Corp. Leistungsumwandlungseinrichtung
JP6233216B2 (ja) * 2014-07-08 2017-11-22 住友電気工業株式会社 電力変換装置及び三相交流電源装置
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JP2004328831A (ja) * 2003-04-22 2004-11-18 Mitsubishi Electric Corp 電圧変動補償装置
JP2005080414A (ja) * 2003-09-01 2005-03-24 Mitsubishi Electric Corp 電力変換装置及びそれを用いたパワーコンディショナ
JP2007037355A (ja) * 2005-07-29 2007-02-08 Mitsubishi Electric Corp 電力変換装置
JP2008104253A (ja) * 2006-10-17 2008-05-01 Yaskawa Electric Corp 電力変換装置
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