WO2024219282A1 - 回路基板及び回路基板の製造方法 - Google Patents

回路基板及び回路基板の製造方法 Download PDF

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Publication number
WO2024219282A1
WO2024219282A1 PCT/JP2024/014333 JP2024014333W WO2024219282A1 WO 2024219282 A1 WO2024219282 A1 WO 2024219282A1 JP 2024014333 W JP2024014333 W JP 2024014333W WO 2024219282 A1 WO2024219282 A1 WO 2024219282A1
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Prior art keywords
layer
conductor layer
circuit board
conductor
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2024/014333
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English (en)
French (fr)
Japanese (ja)
Inventor
知大 古村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
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Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to CN202480026869.5A priority Critical patent/CN121040212A/zh
Priority to DE112024001376.7T priority patent/DE112024001376T5/de
Priority to JP2025515174A priority patent/JPWO2024219282A1/ja
Publication of WO2024219282A1 publication Critical patent/WO2024219282A1/ja
Priority to US19/343,260 priority patent/US20260032827A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0047—Drilling of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias

Definitions

  • the present invention relates to a circuit board and a method for manufacturing a circuit board.
  • Patent document 1 discloses a wiring board including an insulating layer and a conductor layer formed on one main surface of the insulating layer, the insulating layer having a hole with the conductor layer as a bottom and opening toward the other main surface of the insulating layer, the hole being provided with a first via portion connected to the conductor layer and a second via portion connected to the first via portion, the first via portion including a conductive member and not including a resin member, the first via portion having a protrusion at an end face of the first via portion on the second via portion side that protrudes toward the second via portion, a part of the second via portion extending between the protrusion of the first via portion and the insulating layer, and not in contact with the conductor layer connected to the first via portion.
  • Patent Document 1 describes a method of forming an interlayer connection conductor including a first via portion and a second via portion by plating a hole provided in an insulating layer with a conductor foil, and then forming a second via portion by filling the remaining portion of the hole where the first via portion was formed with a conductive paste.
  • Patent Document 1 describes a method of producing a laminated substrate (hereinafter also referred to as a multilayer circuit substrate) by sequentially stacking insulating layers including an insulating layer with a conductor foil in which a first via portion and a second via portion are formed, and then hot pressing (collectively pressing) the resulting laminate in the stacking direction.
  • the surface of conductor foil such as Cu foil is subjected to an anti-rust treatment.
  • an anti-rust layer By forming an anti-rust layer on the surface of the conductor foil, it is possible to prevent oxidation of the conductor foil and suppress the inhibition of adhesion with the insulating layer.
  • the reaction between the conductive paste and the conductor foil is inhibited by the anti-rust layer, which may reduce the reliability of the connection between the interlayer connection conductor including the first and second via portions and the conductor layer.
  • the present invention has been made to solve the above problems, and aims to provide a circuit board with excellent connection reliability between the interlayer connection conductor and the conductor layer. Furthermore, the present invention aims to provide a method for manufacturing the circuit board.
  • the circuit board of the present invention comprises an insulating layer having a first main surface and a second main surface opposed to each other in a thickness direction, a first conductor layer provided on the first main surface of the insulating layer, a second conductor layer provided on the second main surface of the insulating layer, an interlayer connection conductor provided to penetrate the insulating layer in the thickness direction and connected to the first conductor layer and the second conductor layer, and an anti-corrosion layer provided on the surface of the first conductor layer or the second conductor layer.
  • the interlayer connection conductor includes a first portion made of a single metal and a second portion containing at least a metal different from the first portion in the thickness direction.
  • the first portion is bonded to the second portion via a first intermediate layer containing a metal contained in the first portion and a metal contained in the second portion, and is bonded to the first conductor layer without the first intermediate layer.
  • the second portion is bonded to the second conductor layer via a second intermediate layer containing a metal contained in the second portion and a metal contained in the second conductor layer.
  • the anticorrosive layer is disposed at least at the interface between the first conductor layer and the insulating layer, and is not disposed between the second portion and the second conductor layer.
  • the method for manufacturing a circuit board of the present invention includes the steps of preparing a substrate having a conductor layer formed on one surface of an insulating layer and an anticorrosive layer provided on at least the surface of the conductor layer facing the insulating layer, forming a via hole in the substrate that penetrates the insulating layer and exposes a portion of the upper surface of the conductor layer, removing the anticorrosive layer provided on the exposed portion of the conductor layer, filling the via hole after the anticorrosive layer has been removed with a first material made of a single metal, and then filling it with a second material containing at least a metal different from the first material, and stacking a plurality of substrates including the substrate filled with the first material and the second material, and pressing them together by applying heat and pressure.
  • the present invention it is possible to provide a circuit board having excellent connection reliability between the interlayer connection conductor and the conductor layer. Furthermore, according to the present invention, it is possible to provide a method for manufacturing the circuit board.
  • FIG. 1 is a perspective view showing a schematic diagram of an example of a circuit board according to the present invention.
  • FIG. 2 is a cross-sectional view taken along line II-II of the circuit board shown in FIG.
  • FIG. 3 is a cross-sectional view illustrating an example of a circuit board according to the first embodiment of the present invention.
  • 4A to 4G are cross-sectional views that typically show an example of a method for manufacturing the circuit board 1A.
  • FIG. 5 is a cross-sectional view illustrating an example of a circuit board according to a second embodiment of the present invention.
  • FIG. 6 is a cross-sectional view showing an example of a circuit board according to a third embodiment of the present invention.
  • FIG. 1 is a perspective view showing a schematic diagram of an example of a circuit board according to the present invention.
  • FIG. 2 is a cross-sectional view taken along line II-II of the circuit board shown in FIG.
  • FIG. 3 is a cross-sectional view illustrating
  • FIG. 7 is a cross-sectional view illustrating an example of a circuit board according to a fourth embodiment of the present invention.
  • FIG. 8 is a cross-sectional view illustrating an example of a circuit board according to a fifth embodiment of the present invention.
  • FIG. 9 is a cross-sectional view illustrating another example of the circuit board according to the fifth embodiment of the present invention.
  • FIG. 10 is a cross-sectional view illustrating an example of a circuit board according to a sixth embodiment of the present invention.
  • FIG. 11 is a cross-sectional view illustrating another example of the circuit board according to the sixth embodiment of the present invention.
  • FIG. 12 is a cross-sectional view illustrating an example of a circuit board according to a seventh embodiment of the present invention.
  • FIG. 13 is a cross-sectional view illustrating an example of a circuit board according to an eighth embodiment of the present invention.
  • FIG. 14 is a cross-sectional view illustrating another example of the circuit board according to the eighth embodiment of the present invention.
  • FIG. 15 is a cross-sectional view illustrating an example of a circuit board according to a ninth embodiment of the present invention.
  • FIG. 16 is a cross-sectional view illustrating an example of a circuit board according to a tenth embodiment of the present invention.
  • FIG. 17 is a cross-sectional view illustrating another example of the circuit board according to the tenth embodiment of the present invention.
  • 18A, 18B, and 18C are cross-sectional views that typically show examples of a circuit board according to an eleventh embodiment of the present invention.
  • FIG. 19 is a cross-sectional view illustrating an example of a circuit board according to an eleventh embodiment of the present invention.
  • FIG. 20 is a cross-sectional view illustrating another example of the circuit board according to the eleventh embodiment of the present invention.
  • FIG. 21 is a cross-sectional view illustrating an example of a circuit board according to a twelfth embodiment of the present invention.
  • FIG. 22 is a cross-sectional view that illustrates an example of a circuit board on which electronic components are mounted.
  • FIG. 23 is a cross-sectional view illustrating an example of a circuit board having a bent portion.
  • circuit board and the method for producing the circuit board of the present invention will be described below.
  • present invention is not limited to the following configurations, and can be appropriately modified and applied within the scope of the present invention.
  • the present invention also includes a combination of two or more of the individual preferred configurations of the present invention described below.
  • terms indicating the relationship between elements are not expressions that only express a strict meaning, but are expressions that mean that they are substantially equivalent, for example, including differences of about a few percent.
  • “equivalent” is an expression that does not only mean that they are completely equivalent, but is an expression that means that they are substantially equivalent, for example, including differences of about a few percent.
  • FIG. 1 is a perspective view showing a schematic example of a circuit board of the present invention.
  • FIG. 2 is a cross-sectional view taken along line II-II of the circuit board shown in FIG. 1.
  • the circuit board 1 shown in FIG. 1 includes an insulating substrate 100 formed by laminating insulating layers (first insulating layer 110, second insulating layer 120, third insulating layer 130, fourth insulating layer 140), conductor layers (mounting electrode 150, ground wiring 160, signal line 170, wiring 180, wiring 185) provided on the surface or inside of the insulating substrate 100, an interlayer connection conductor 190, an interlayer connection conductor 195, an interlayer connection conductor 200, and a protective layer 210.
  • insulating substrate 100 formed by laminating insulating layers (first insulating layer 110, second insulating layer 120, third insulating layer 130, fourth insulating layer 140), conductor layers (mounting electrode 150, ground wiring 160, signal line 170, wiring 180, wiring 185) provided on the surface or inside of the insulating substrate 100, an interlayer connection conductor 190, an interlayer connection conductor 195, an interlayer connection conductor 200, and a protective layer 210.
  • the circuit board 1 is a multilayer circuit board having multiple insulating layers.
  • the circuit board 1 may be a rigid board or a flexible board.
  • the circuit board 1 may have a bent portion.
  • a mounting electrode 150, wiring 180, and a protective layer 210 are provided on one main surface (the bottom surface in FIG. 2) of the insulating substrate 100.
  • a ground wiring 160 is provided on the other main surface (the top surface in FIG. 2) of the insulating substrate 100.
  • a signal line 170 and wiring 185 are provided between the first insulating layer 110 and the second insulating layer 120, and between the second insulating layer 120 and the third insulating layer 130.
  • Interlayer connection conductors 190 and 200 are provided inside the first insulating layer 110 and the second insulating layer 120.
  • the interlayer connection conductors 190 connected to the signal line 170 overlap in the stacking direction (Z direction in FIG. 2). Therefore, the signal lines 170 are connected to each other by the interlayer connection conductors 190 provided inside the first insulating layer 110 and the interlayer connection conductors 190 provided inside the second insulating layer 120, forming a transmission line.
  • the signal line 170 is connected to the mounting electrode 150 by the interlayer connection conductors 190 provided inside the first insulating layer 110.
  • Interlayer connection conductors 195 are provided inside the third insulating layer 130 and the fourth insulating layer 140.
  • the ground wiring 160 is connected to the wiring 180 by an interlayer connection conductor 200 provided inside the first insulating layer 110, an interlayer connection conductor 200 provided inside the second insulating layer 120, an interlayer connection conductor 195 provided inside the third insulating layer 130, and an interlayer connection conductor 195 provided inside the fourth insulating layer 140.
  • Wiring 185 is provided between the interlayer connection conductor 200 provided inside the first insulating layer 110 and the interlayer connection conductor 200 provided inside the second insulating layer 120, and between the interlayer connection conductor 200 provided inside the second insulating layer 120 and the interlayer connection conductor 195 provided inside the third insulating layer 130.
  • wiring is provided between the interlayer connection conductor 195 provided inside the third insulating layer 130 and the interlayer connection conductor 195 provided inside the fourth insulating layer 140, but wiring may be provided. In addition, wiring may or may not be provided between the interlayer connection conductors 200 and between the interlayer connection conductors 195 and the interlayer connection conductors 200.
  • the protective layer 210 is, for example, a coverlay, a resist layer, or the like.
  • the protective layer 210 may be provided on both main surfaces of the insulating substrate 100, or on one of the main surfaces.
  • the circuit board 1 includes at least one interlayer connection conductor, which will be described in each of the embodiments shown below.
  • the circuit board 1 includes an interlayer connection conductor, which will be described in each of the embodiments shown below, as the interlayer connection conductor 190 that connects to the signal line 170.
  • FIG. 3 is a cross-sectional view showing a schematic example of a circuit board according to the first embodiment of the present invention.
  • the circuit board 1A comprises an insulating layer 10 having a first main surface 10a and a second main surface 10b that face each other in the thickness direction (the up-down direction in Figure 3), a first conductor layer 21 provided on the first main surface 10a of the insulating layer 10, a second conductor layer 22 provided on the second main surface 10b of the insulating layer 10, an interlayer connection conductor 30 that penetrates the insulating layer 10 in the thickness direction and is connected to the first conductor layer 21 and the second conductor layer 22, and an anti-corrosion layer 40 provided on the surface of the first conductor layer 21 or the second conductor layer 22.
  • the insulating layer 10 is, for example, a resin insulating layer whose main component is resin.
  • the loss during signal transmission can be reduced by forming the insulating layer 10 from a resin having a low dielectric constant.
  • the insulating layer 10 may be a ceramic insulating layer whose main component is ceramic.
  • the insulating layer 10 is made of ceramic with a high dielectric constant, allowing radiation or reception over a wide band.
  • the resin that constitutes the resin insulation layer may be a thermosetting resin or a thermoplastic resin, but is preferably a thermoplastic resin.
  • the resin insulation layer is made of a thermoplastic resin, multiple resin sheets on which conductor layers are formed can be stacked and collectively compressed (collectively pressed) by heat treatment.
  • Thermosetting resins include epoxy resins, phenolic resins, polyimide resins or modified resins thereof, and acrylic resins.
  • thermoplastic resins include liquid crystal polymers (LCPs), fluororesins, thermoplastic polyimide resins, polyether ether ketone resins (PEEK), polyphenylene sulfide resins (PPS), etc.
  • LCPs liquid crystal polymers
  • PEEK polyether ether ketone resins
  • PPS polyphenylene sulfide resins
  • the resin insulation layer is preferably made of liquid crystal polymer (LCP).
  • LCP liquid crystal polymer
  • Liquid crystal polymer has a lower water absorption rate than other thermoplastic resins. Therefore, when the resin insulation layer is made of liquid crystal polymer, the amount of moisture remaining in the resin insulation layer can be reduced.
  • the resin insulation layer may contain inorganic materials such as ceramic fillers.
  • Ceramic fillers include, for example, boron nitride, talc, and fused silica.
  • Examples of the ceramic that constitutes the ceramic insulating layer include low-temperature co-fired ceramic (LTCC) and high-temperature co-fired ceramic (HTCC).
  • LTCC low-temperature co-fired ceramic
  • HTCC high-temperature co-fired ceramic
  • each insulating layer 10 is preferably 10 ⁇ m or more and 100 ⁇ m or less.
  • the first conductor layer 21 and the second conductor layer 22 may each have a pattern shape patterned into wiring or the like, or may have a surface shape that spreads over one surface.
  • the shapes of the first conductor layer 21 and the second conductor layer 22 may be the same as each other or may be different.
  • the first conductor layer 21 and the second conductor layer 22 are each a metal layer containing at least one of the following metals, for example: copper, silver, aluminum, stainless steel, nickel, and gold.
  • the materials of the first conductor layer 21 and the second conductor layer 22 may be the same as or different from each other.
  • Both the first conductor layer 21 and the second conductor layer 22 are preferably made of a metal foil, and more preferably made of copper (Cu) foil.
  • the thickness (length in the stacking direction) of the first conductor layer 21 and the second conductor layer 22 is preferably 1 ⁇ m or more and 35 ⁇ m or less, and more preferably 6 ⁇ m or more and 18 ⁇ m or less.
  • the thicknesses of the first conductor layer 21 and the second conductor layer 22 may be the same as or different from each other.
  • the first conductor layer 21 and the second conductor layer 22 may or may not be parallel to each other.
  • One insulating layer 10 may be provided between the first conductor layer 21 and the second conductor layer 22, or two or more insulating layers 10 may be provided.
  • the configurations of the insulating layers 10 may be the same as each other or different.
  • the thicknesses of the insulating layers 10 may be the same as each other or different.
  • the interlayer connection conductor 30 is provided so as to penetrate the insulating layer 10 in the thickness direction, but not through the first conductor layer 21 and the second conductor layer 22, and to be connected to the first conductor layer 21 and the second conductor layer 22. Therefore, the interlayer connection conductor 30 penetrates the insulating layer 10 in the thickness direction by the number of layers provided between the first conductor layer 21 and the second conductor layer 22.
  • the shape of the interlayer connection conductor 30 is preferably circular.
  • circular shapes include not only perfect circles, but also ellipses, ovals, etc.
  • the interlayer connection conductor 30 includes a first portion 31 and a second portion 32 in the thickness direction.
  • the first part 31 is made of a single metal.
  • the first portion 31 is, for example, a plated via.
  • a plated via means a film grown by a liquid phase method or a vapor phase method.
  • the metal contained in the first portion 31 is preferably the same as the metal constituting the first conductor layer 21, e.g., Cu.
  • the second portion 32 contains at least a metal different from that of the first portion 31.
  • the second portion 32 is, for example, a paste via.
  • a paste via means a solidified paste.
  • the second portion 32 functions as a bonding material, thereby electrically connecting the first portion 31 and the second conductor layer 22.
  • examples of the metal contained in the second portion 32 include Cu, Sn, Ag, Ni, Cr, Pt, Mo, Ga, Ge, Sb, In, Pb, and alloys containing at least one of these metals.
  • the metal contained in the second portion 32 may be the same as or different from the metal contained in the first portion 31.
  • the metal contained in the second portion 32 is, for example, an alloy containing Cu and Sn.
  • the second portion 32 may be a plated via.
  • the first portion 31 is bonded to the second portion 32 via a first intermediate layer 51 that includes the metal contained in the first portion 31 and the metal contained in the second portion 32, and is bonded to the first conductor layer 21 without the first intermediate layer 51.
  • a first intermediate layer 51 containing Cu and Sn is formed on the end of the second portion 32 on the first portion 31 side.
  • the first intermediate layer 51 is made of a Cu-Sn alloy such as Cu 3 Sn or Cu 5 Sn.
  • the composition of the first intermediate layer 51 is different from the composition of the second portion 32.
  • the first portion 31 and the first conductor layer 21 are directly bonded together, without any dissimilar materials in between. Therefore, at the interface between the first portion 31 and the first conductor layer 21, there is a portion where no dissimilar materials exist, i.e., a portion where the first portion 31 and the first conductor layer 21 are in direct contact.
  • the second portion 32 is joined to the second conductor layer 22 via a second intermediate layer 52 that contains the metal contained in the second portion 32 and the metal contained in the second conductor layer 22.
  • a second intermediate layer 52 containing Cu and Sn is formed on the end of the second portion 32 on the second conductor layer 22 side.
  • the second intermediate layer 52 is made of a Cu-Sn alloy such as Cu 3 Sn or Cu 5 Sn.
  • the composition of the second intermediate layer 52 is different from the composition of the second portion 32.
  • the second intermediate layer 52 extends to the interface between the second conductor layer 22 and the insulating layer 10, but as described below, the second intermediate layer 52 does not have to extend to the interface between the second conductor layer 22 and the insulating layer 10.
  • the first intermediate layer 51 may be one layer or two or more layers.
  • the second intermediate layer 52 may be one layer or two or more layers.
  • the first intermediate layer 51 and the second intermediate layer 52 can be confirmed, for example, by observing a cross section of the insulating layer 10 cut in a direction parallel to the thickness direction using a scanning electron microscope (SEM).
  • SEM scanning electron microscope
  • compositions such as Cu5Sn , Cu3Sn , and Cu6Sn5 all contain Cu and Sn as metal species, but the content ratios of the metal species are different, so they can be said to have different compositions.
  • the anti-rust layer 40 is formed by applying an anti-rust treatment to the surface of the metal foil using a metal such as Zn, Ni, Cr, Mo, or Pt.
  • the anti-corrosive layer 40 is disposed at least at the interface between the first conductor layer 21 and the insulating layer 10, and is not disposed between the second portion 32 and the second conductor layer 22.
  • the circuit board 1A is produced by a batch press as described below, by disposing the rust-proof layer 40 at the interface between the first conductor layer 21 and the insulating layer 10, oxidation of the metal foil such as Cu foil that constitutes the first conductor layer 21 is prevented, and therefore a decrease in adhesion between the first conductor layer 21 and the insulating layer 10 can be suppressed.
  • the thermal load on the interface between the first conductor layer 21 and the insulating layer 10 is greater than that on the interface between the second conductor layer 22 and the insulating layer 10. Therefore, it is preferable that the anti-corrosion layer 40 is disposed at least on the interface between the first conductor layer 21 and the insulating layer 10.
  • an anti-rust layer 40 is disposed between the second portion 32 and the second conductor layer 22, the reaction between the material constituting the second portion 32 (e.g., conductive paste) and the material constituting the second conductor layer 22 (e.g., metal foil) is inhibited by the anti-rust layer 40, making it difficult to form the second intermediate layer 52. Therefore, by not disposing the anti-rust layer 40 between the second portion 32 and the second conductor layer 22, the second intermediate layer 52 is more easily formed, thereby improving the connection reliability between the interlayer connection conductor 30 and the second conductor layer 22.
  • the material constituting the second portion 32 e.g., conductive paste
  • the material constituting the second conductor layer 22 e.g., metal foil
  • the anti-rust layer 40 is not disposed at the interface between the second conductor layer 22 and the insulating layer 10. This makes it possible to prevent inhibition of the reaction between the material constituting the second portion 32 (e.g., conductive paste) and the material constituting the second conductor layer 22 (e.g., metal foil).
  • the anticorrosive layer 40 is not disposed between the first portion 31 and the first conductor layer 21.
  • the first portion 31 is joined to the first conductor layer 21 without the first intermediate layer 51. This increases the connection strength between the interlayer connection conductor 30 and the first conductor layer 21.
  • the second portion 32 may have a tapered shape in which the area of the end face on the first conductor layer 21 side is smaller than the area of the end face on the second conductor layer 22 side.
  • a weak second intermediate layer 52 may be formed at the end of the second portion 32 on the second conductor layer 22 side, but by increasing the area of the portion of the second portion 32 that is connected to the second conductor layer 22, the connection strength between the second portion 32 and the second conductor layer 22 can be increased.
  • the first portion 31 may have a tapered shape in which the area of the end face on the first conductor layer 21 side is smaller than the area of the end face on the second conductor layer 22 side.
  • the interlayer connection conductor 30 may have a tapered shape in which the area of the end face on the first conductor layer 21 side is smaller than the area of the end face on the second conductor layer 22 side.
  • the height t1 of the first portion 31 may be equal to the height t2 of the second portion 32 or may be lower than the height t2 of the second portion 32 ( t1 ⁇ t2 ), but is preferably higher than the height t2 of the second portion 32 ( t1 > t2 ).
  • the interlayer connection conductor 30 has a tapered shape, by making the height t1 of the first portion 31 higher than the height t2 of the second portion 32, the connection area between the first portion 31 and the second portion 32 is increased, and therefore the connection reliability of the interlayer connection conductor 30 can be improved.
  • the end face of the first portion 31 on the side of the second conductor layer 22 is flat, but as described below, it may protrude toward the second conductor layer 22 or may be recessed toward the first conductor layer 21.
  • the circuit board 1A is manufactured, for example, by the following method.
  • FIGS. 4A to 4G are cross-sectional views that show a schematic example of a method for manufacturing circuit board 1A.
  • Circuit board 1A may be manufactured in one-chip (individual piece) state, or may be manufactured by producing an aggregate board and then separating it into individual pieces.
  • An aggregate board in this case refers to a board that includes multiple circuit boards 1A.
  • a metal foil such as Cu foil is laminated onto one main surface of the insulating layer 10, and the metal foil is patterned by photolithography to form the conductor layer 20.
  • the insulating layer 10 is, for example, a resin sheet whose main component is a thermoplastic resin such as a liquid crystal polymer.
  • a via hole 70 is formed in the substrate 60, which penetrates the insulating layer 10 and exposes a portion of the upper surface of the conductor layer 20.
  • the via hole 70 preferably has a tapered shape.
  • a via hole 70 is formed in the insulating layer 10 using a laser or the like so that the top surface of the conductor layer 20 is exposed.
  • the anti-rust layer (not shown) provided on the surface of the conductor layer 20 opposite the insulating layer 10.
  • the anti-rust layers provided on the top and bottom surfaces of the conductor layer 20 may be removed simultaneously at the stage shown in Figure 4C, or the anti-rust layer provided on the bottom surface of the conductor layer 20 may be removed at a stage prior to Figure 4A.
  • the via hole 70 after the anticorrosive layer 40 has been removed is filled with a first material 71 made of a single metal.
  • the first material 71 is filled halfway into the via hole 70.
  • a plating metal such as Cu is filled into the via hole 70 as a first material 71.
  • the first material 71 forms the first portion 31 (see FIG. 4G).
  • the via hole 70 filled with the first material 71 is filled with a second material 72 containing at least a metal different from the first material 71.
  • the space in the via hole 70 is filled with the first material 71 and the second material 72.
  • a conductive paste containing a metal material such as Cu or Sn and a resin material is filled as the second material 72.
  • the second material 72 is solidified by a heating press described later, thereby forming the second portion 32 (see FIG. 4G).
  • the via hole 70 It is also possible to fill the via hole 70 with a plated metal such as Sn as the second material 72, but depending on the metal selected as the second material 72, there is a risk that the metal of the underlying first material 71 may remelt. Therefore, from the viewpoint of increasing the degree of freedom in selecting the first material 71 and the second material 72, it is preferable to fill the via hole 70 after the anti-corrosion layer 40 has been removed with a plated metal as the first material 71, and then fill it with a conductive paste as the second material 72.
  • a plated metal such as Sn
  • FIG. 4F a plurality of substrates including a substrate 60 filled with a first material 71 and a second material 72 are laminated.
  • FIG. 4F shows an example in which substrates 60 filled with a first material 71 and a second material 72 are laminated continuously, but there is no particular limitation as long as the substrates include substrates 60 filled with a first material 71 and a second material 72.
  • the circuit board 1A can be easily manufactured by pressing the insulating layer 10 all at once. This reduces the number of manufacturing steps for the circuit board 1A, and keeps manufacturing costs low.
  • FIG. 5 is a cross-sectional view showing a schematic example of a circuit board according to a second embodiment of the present invention.
  • the anti-rust layer 40 is disposed at the interface between the second conductor layer 22 and the insulating layer 10, to the extent that it does not come into contact with the second intermediate layer 52. This makes it possible to prevent inhibition of the reaction between the material constituting the second portion 32 (e.g., conductive paste) and the material constituting the second conductor layer 22 (e.g., metal foil).
  • FIG. 6 is a cross-sectional view showing a schematic example of a circuit board according to a third embodiment of the present invention.
  • the second intermediate layer 52 does not extend to the interface between the second conductor layer 22 and the insulating layer 10.
  • the anti-rust layer 40 is not disposed at the interface between the second conductor layer 22 and the insulating layer 10, but it may be disposed at the interface between the second conductor layer 22 and the insulating layer 10 to the extent that it does not contact the second intermediate layer 52.
  • FIG. 7 is a cross-sectional view showing a schematic example of a circuit board according to a fourth embodiment of the present invention.
  • the second portion 32 has a tapered shape in which the area of the end face on the first conductor layer 21 side is smaller than the area of the end face on the second conductor layer 22 side, and the tapered shape has a stepped inclination angle.
  • the area of the second portion 32 that is connected to the second conductor layer 22 can be made larger than in the circuit board 1A shown in FIG. 3. This makes it possible to further increase the connection strength between the second portion 32 and the second conductor layer 22.
  • the inclination angle of the tapered shape changes in two stages, but it may also change in three stages, or in four or more stages.
  • the first portion 31 may have a tapered shape in which the area of the end face on the first conductor layer 21 side is smaller than the area of the end face on the second conductor layer 22 side.
  • the tapered shape may have a stepwise varying inclination angle.
  • FIG. 8 is a cross-sectional view showing a schematic example of a circuit board according to a fifth embodiment of the present invention.
  • the end face of the first portion 31 on the second conductor layer 22 side protrudes toward the second conductor layer 22.
  • the end faces of the first portion 31 on the second conductor layer 22 side protrude symmetrically.
  • FIG. 9 is a cross-sectional view showing a schematic diagram of another example of a circuit board according to the fifth embodiment of the present invention.
  • the end face of the first portion 31 on the second conductor layer 22 side protrudes toward the second conductor layer 22, similar to FIG. 8.
  • the end face of the first portion 31 on the second conductor layer 22 side protrudes asymmetrically.
  • connection area between the first portion 31 and the second portion 32 becomes large, and the connection strength between the first portion 31 and the second portion 32 can be increased.
  • the height t1 of the first portion 31 may be equal to the height t2 of the second portion 32 or may be lower than the height t2 of the second portion 32 ( t1 ⁇ t2 ), but is preferably higher than the height t2 of the second portion 32 ( t1 > t2 ). Note that the height t1 of the first portion 31 is defined as the height of the highest portion, and the height t2 of the second portion 32 is defined as the height of the lowest portion.
  • FIG. 10 is a cross-sectional view showing a schematic example of a circuit board according to a sixth embodiment of the present invention.
  • the end face of the first portion 31 on the second conductor layer 22 side is recessed toward the first conductor layer 21.
  • the end face of the first portion 31 on the second conductor layer 22 side is recessed symmetrically.
  • the valley has one apex, but there may be two or more.
  • the size, depth, shape, etc. of the valley may be the same or different.
  • the end face of the first portion 31 on the second conductor layer 22 side may include a mixture of a portion that protrudes toward the second conductor layer 22 and a portion that is recessed toward the first conductor layer 21.
  • FIG. 12 is a cross-sectional view showing a schematic example of a circuit board according to the seventh embodiment of the present invention.
  • the end face of the first portion 31 on the first conductor layer 21 side protrudes toward the first conductor layer 21 side beyond the interface between the first conductor layer 21 and the insulating layer 10.
  • connection area between the first portion 31 and the first conductor layer 21 becomes larger, and the connection strength between the first portion 31 and the first conductor layer 21 can be increased.
  • the end face of the first portion 31 on the first conductor layer 21 side protrudes symmetrically, but it may also protrude asymmetrically.
  • the mountain has one vertex, but there may be two or more.
  • the size, height, shape, etc. of the mountain may be the same or different.
  • FIG. 13 is a cross-sectional view showing a schematic example of a circuit board according to an eighth embodiment of the present invention.
  • the first intermediate layer 51 may extend to the interface between the first portion 31 and the insulating layer 10.
  • the first intermediate layer 51 extends to the interface between the first portion 31 and the insulating layer 10, and also reaches the interface between the first conductor layer 21 and the insulating layer 10. This further increases the connection strength between the first portion 31 and the first conductor layer 21.
  • part of the end face of the first portion 31 on the second conductor layer 22 side is protruding toward the second conductor layer 22.
  • connection area between the first portion 31 and the second portion 32 becomes large, as in FIG. 8 or FIG. 9, and the connection strength between the first portion 31 and the second portion 32 can be increased.
  • a portion of the end face of the first portion 31 on the second conductor layer 22 side may have one protrusion, or two or more protrusions. If two or more protrusions are present, the size, height, shape, etc. of the protrusions may be the same or different.
  • the height of the protrusion is, for example, 1 ⁇ m or more and 20 ⁇ m or less. Note that the shape of the protrusion is not limited to the shape shown in FIG. 15.
  • the maximum diameter of the protrusion is, for example, 1 ⁇ m or more and 10 ⁇ m or less.
  • the maximum diameter of the protrusion refers to the diameter if the cross-sectional shape is circular, and refers to the maximum length passing through the center of the cross-section if the cross-sectional shape is other than circular.
  • FIG. 16 is a cross-sectional view showing a schematic example of a circuit board according to a tenth embodiment of the present invention.
  • connection area between the first portion 31 and the second portion 32 becomes large, as in FIG. 10 or FIG. 11, and therefore the connection strength between the first portion 31 and the second portion 32 can be increased.
  • a portion of the end face of the first portion 31 on the side of the second conductor layer 22 may have one recessed portion, or two or more recessed portions. If two or more recessed portions are present, the size, depth, shape, etc. of the recessed portions may be the same or different.
  • the maximum diameter of the recess is, for example, 1 ⁇ m or more and 10 ⁇ m or less.
  • the maximum diameter of the recess refers to the diameter if the cross-sectional shape is circular, and the maximum length passing through the center of the cross-section if the cross-sectional shape is other than circular.
  • a portion of the end face of the first portion 31 on the second conductor layer 22 side may include a mixture of protrusions and recesses.
  • FIG. 17 is a cross-sectional view showing a schematic diagram of another example of a circuit board according to the tenth embodiment of the present invention.
  • a part of the second portion 32 may be joined to the first conductor layer 21.
  • the first conductor layer 21 is joined to the second portion 32 via the first intermediate layer 51.
  • voids may exist inside the first portion 31.
  • the number, size, position, etc. of the voids are not particularly limited.
  • the voids may exist near the interface between the first portion 31 and the first conductor layer 21 as shown in FIG. 18A, near the interface between the insulating layer 10 and the first conductor layer 21 as shown in FIG. 18B, or near the first intermediate layer 51 as shown in FIG. 18C.
  • resin residues (carbides), copper foil oxides (copper oxide), etc. may be present.
  • the surface roughness of the first conductor layer 21 in contact with the insulating layer 10 is greater than the surface roughness of the second conductor layer 22 in contact with the insulating layer 10.
  • the adhesive area between the insulating layer 10 and the first conductor layer 21 is increased, and the adhesive strength between the two can be increased. Therefore, when electronic components or the like are mounted on the first conductor layer 21, they are less likely to be pulled off.
  • FIG. 20 is a cross-sectional view showing a schematic diagram of another example of a circuit board according to the 11th embodiment of the present invention.
  • the anti-corrosive layer 40 does not need to be disposed at the interface between the first conductor layer 21 and the insulating layer 10.
  • FIG. 21 is a cross-sectional view showing a schematic example of a circuit board according to a twelfth embodiment of the present invention.
  • the first portion 31 has a shape in which the area of the end face on the first conductor layer 21 side is equal to the area of the end face on the second conductor layer 22 side
  • the second portion 32 has a shape in which the area of the end face on the first conductor layer 21 side is equal to the area of the end face on the second conductor layer 22 side.
  • the interlayer connection conductor 30 has a tapered shape, as in the circuit board 1A shown in FIG. 3, strain stress tends to concentrate at the necking points of the interlayer connection conductor 30 (particularly the necking points between the interlayer connection conductor 30 and the first conductor layer 21).
  • the interlayer connection conductor 30 does not have a tapered shape, as in the circuit board 1T shown in FIG. 21, strain stress is prevented from concentrating at the necking points of the interlayer connection conductor 30. Therefore, the stress acting on the interlayer connection conductor 30 is distributed, improving connection reliability.
  • circuit board of the present invention is not limited to the above embodiment, and various applications and modifications can be made within the scope of the present invention with respect to the configuration of the circuit board, manufacturing conditions, etc.
  • the circuit board of the present invention can be used, for example, as follows:
  • the circuit board 3 has bent portions 3P1 and 3P2.
  • the number, shape, etc. of the bent portions are not particularly limited.
  • the insulating layer constituting the circuit board 3 is preferably a resin insulating layer whose main component is a thermoplastic resin such as a liquid crystal polymer.
  • the circuit board 3 can be produced by the batch pressing described above.
  • the circuit board of the present invention has the configuration described in the above embodiment, so even if it has a bent portion, it is expected to be able to suppress breakage due to bending stress.
  • ⁇ 4> The circuit board according to any one of ⁇ 1> to ⁇ 3>, wherein the second portion has a tapered shape in which an area of an end face on the first conductor layer side is smaller than an area of an end face on the second conductor layer side.
  • the interlayer connection conductor has a shape in which an area of an end face on the side of the first conductor layer is equal to an area of an end face on the side of the second conductor layer
  • the first portion has a shape in which an area of an end face on the first conductor layer side is equal to an area of an end face on the second conductor layer side
  • the circuit board according to any one of ⁇ 1> to ⁇ 3>, wherein the second portion has a shape in which an area of an end face on the side of the first conductor layer is equal to an area of an end face on the side of the second conductor layer.
  • ⁇ 7> The circuit board according to any one of ⁇ 1> to ⁇ 6>, wherein an end face of the first portion on the second conductor layer side protrudes toward the second conductor layer or is recessed toward the first conductor layer.
  • ⁇ 8> The circuit board according to any one of ⁇ 1> to ⁇ 7>, wherein an end face of the first portion on the first conductor layer side protrudes toward the first conductor layer side beyond an interface between the first conductor layer and the insulating layer.
  • ⁇ 9> The circuit board according to any one of ⁇ 1> to ⁇ 8>, wherein the first intermediate layer extends to an interface between the first portion and the insulating layer.
  • ⁇ 11> The circuit board according to any one of ⁇ 1> to ⁇ 10>, wherein a part of an end face of the first portion on the second conductor layer side has a part protruding toward the second conductor layer or a part recessed toward the first conductor layer.
  • ⁇ 12> The circuit board according to any one of ⁇ 1> to ⁇ 11>, wherein the surface roughness of the first conductor layer in contact with the insulating layer is greater than the surface roughness of the second conductor layer in contact with the insulating layer.
  • ⁇ 15> The circuit board according to any one of ⁇ 1> to ⁇ 14>, wherein the insulating layer is mainly composed of a resin.
  • ⁇ 16> The circuit board according to any one of ⁇ 1> to ⁇ 14>, wherein the insulating layer is mainly composed of ceramic.
  • the interlayer connection conductor has a shape in which an area of an end face on the side of the first conductor layer is equal to an area of an end face on the side of the second conductor layer
  • the first portion has a shape in which an area of an end face on the first conductor layer side is equal to an area of an end face on the second conductor layer side
  • ⁇ 35> The circuit board according to any one of ⁇ 31> to ⁇ 34>, wherein an end face of the first portion on the second conductor layer side protrudes toward the second conductor layer or is recessed toward the first conductor layer.
  • ⁇ 36> The circuit board according to any one of ⁇ 31> to ⁇ 35>, wherein an end face of the first portion on the first conductor layer side protrudes toward the first conductor layer side beyond an interface between the first conductor layer and the insulating layer.
  • ⁇ 37> The circuit board according to any one of ⁇ 31> to ⁇ 36>, wherein the first intermediate layer extends to an interface between the first portion and the insulating layer.
  • ⁇ 39> The circuit board according to any one of ⁇ 31> to ⁇ 38>, wherein a part of an end face of the first portion on the second conductor layer side has a part protruding toward the second conductor layer or a part recessed toward the first conductor layer.
  • ⁇ 40> The circuit board according to any one of ⁇ 31> to ⁇ 39>, wherein the second intermediate layer extends to an interface between the second conductor layer and the insulating layer.
  • ⁇ 41> The circuit board according to any one of ⁇ 31> to ⁇ 40>, wherein the insulating layer is mainly composed of a resin.
  • ⁇ 42> The circuit board according to any one of ⁇ 31> to ⁇ 40>, wherein the insulating layer is mainly composed of ceramic.
  • ⁇ 43> The circuit board according to any one of ⁇ 31> to ⁇ 42>, wherein the first conductor layer and the second conductor layer are both made of metal foil.
  • ⁇ 44> Further comprising an anticorrosive layer provided on a surface of the first conductor layer or the second conductor layer;
  • ⁇ 49> The method for manufacturing a circuit board according to ⁇ 48>, wherein the via hole is filled with a plating metal as the first material, and then filled with a conductive paste as the second material.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
PCT/JP2024/014333 2023-04-20 2024-04-09 回路基板及び回路基板の製造方法 Ceased WO2024219282A1 (ja)

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CN202480026869.5A CN121040212A (zh) 2023-04-20 2024-04-09 电路基板以及电路基板的制造方法
DE112024001376.7T DE112024001376T5 (de) 2023-04-20 2024-04-09 Schaltungsplatine und verfahren zum herstellen einer schaltungsplatte
JP2025515174A JPWO2024219282A1 (https=) 2023-04-20 2024-04-09
US19/343,260 US20260032827A1 (en) 2023-04-20 2025-09-29 Circuit board and method for producing circuit board

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1167900A (ja) * 1997-06-12 1999-03-09 Ngk Spark Plug Co Ltd 多層配線基板の製造方法
JP2001102696A (ja) * 1999-09-30 2001-04-13 Kyocera Corp 配線基板及びその製造方法
JP2004047836A (ja) * 2002-07-12 2004-02-12 Mitsui Chemicals Inc プリント配線板とその製造方法
JP2013157441A (ja) * 2012-01-30 2013-08-15 Shinko Electric Ind Co Ltd 配線基板及び配線基板の製造方法
WO2021246467A1 (ja) * 2020-06-03 2021-12-09 株式会社村田製作所 多層基板及びその製造方法
WO2022202322A1 (ja) * 2021-03-26 2022-09-29 株式会社村田製作所 配線基板、積層基板及び配線基板の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1167900A (ja) * 1997-06-12 1999-03-09 Ngk Spark Plug Co Ltd 多層配線基板の製造方法
JP2001102696A (ja) * 1999-09-30 2001-04-13 Kyocera Corp 配線基板及びその製造方法
JP2004047836A (ja) * 2002-07-12 2004-02-12 Mitsui Chemicals Inc プリント配線板とその製造方法
JP2013157441A (ja) * 2012-01-30 2013-08-15 Shinko Electric Ind Co Ltd 配線基板及び配線基板の製造方法
WO2021246467A1 (ja) * 2020-06-03 2021-12-09 株式会社村田製作所 多層基板及びその製造方法
WO2022202322A1 (ja) * 2021-03-26 2022-09-29 株式会社村田製作所 配線基板、積層基板及び配線基板の製造方法

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