WO2024214634A1 - 半導体装置及び電力変換装置 - Google Patents

半導体装置及び電力変換装置 Download PDF

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WO2024214634A1
WO2024214634A1 PCT/JP2024/013976 JP2024013976W WO2024214634A1 WO 2024214634 A1 WO2024214634 A1 WO 2024214634A1 JP 2024013976 W JP2024013976 W JP 2024013976W WO 2024214634 A1 WO2024214634 A1 WO 2024214634A1
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Prior art keywords
gate electrode
semiconductor device
insulating film
region
interlayer insulating
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French (fr)
Japanese (ja)
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慶治 別府
和成 中田
宗謙 池田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to CN202480021594.6A priority Critical patent/CN121003028A/zh
Priority to JP2025513929A priority patent/JPWO2024214634A1/ja
Publication of WO2024214634A1 publication Critical patent/WO2024214634A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 

Definitions

  • This disclosure relates to semiconductor devices and power conversion devices.
  • SiC silicon carbide
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • IGBTs Insulated Gate Bipolar Transistors
  • a SiC MOSFET with a breakdown voltage of 1 to 1.2 kV can have an on-resistance of 2 m ⁇ cm 2 or less, which is half or less of the resistance of a Si MOSFET and IGBT with the same breakdown voltage.
  • the on-resistance of a SiC semiconductor device can be significantly reduced compared to a Si semiconductor device is that the SiC semiconductor device has a high dielectric breakdown field, the breakdown voltage layer (i.e., the drift layer) for achieving the same breakdown voltage can be made thinner compared to a Si semiconductor device, and the impurity doping amount of the breakdown voltage layer can be increased.
  • the breakdown voltage layer i.e., the drift layer
  • a forward current i.e., a bipolar current
  • the recombination energy increases when the minority carriers injected by the current flow through the PN diode recombine with the majority carriers.
  • stacking faults which are planar defects, expand, starting from basal plane dislocations present in the SiC substrate.
  • the current decreases and the forward voltage increases, i.e., the forward voltage shifts, causing a reliability problem in that it reduces the reliability of the semiconductor device.
  • Patent Document 1 proposes providing a p+ type semiconductor region, which is a hole extraction region, so as to surround an active region in which a MOSFET is provided in a semiconductor substrate including an n - type SiC substrate and an epitaxial growth layer on the SiC substrate.
  • Patent Documents 2 and 3 also propose incorporating an SBD (Schottky Barrier Diode) as a unipolar diode in the same semiconductor chip as the MOSFET.
  • SBD Schottky Barrier Diode
  • the present disclosure has been made in consideration of the above problems, and aims to provide technology that can improve the reliability of semiconductor devices during operation.
  • the semiconductor device is a semiconductor device having an active region and a termination region defined therein, and includes a first interlayer insulating film provided in the termination region, and a gate electrode provided on the first interlayer insulating film, and when a first amount of heat generated on the reverse region side, which is located on the opposite side of the gate electrode from the active region, is greater than a second amount of heat generated on the active region side, a dimension of a first portion of the first interlayer insulating film on the reverse region side of the gate electrode is greater than a dimension of a second portion of the first interlayer insulating film on the active region side of the gate electrode, and when the second amount of heat generated is greater than the first amount of heat generated, a dimension of the second portion is greater than a dimension of the first portion.
  • the dimensions of the first portion are greater than the dimensions of the second portion
  • the dimensions of the second portion are greater than the dimensions of the first portion
  • 1 is a top view showing a configuration of a semiconductor device according to a first embodiment
  • 1 is a top view showing a configuration of a semiconductor device according to a first embodiment
  • 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a first embodiment
  • 2 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment.
  • 3A to 3C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.
  • 3A to 3C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.
  • 3A to 3C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.
  • 3A to 3C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.
  • 3A to 3C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.
  • 3A to 3C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.
  • 3A to 3C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.
  • 3A to 3C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.
  • 3A to 3C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.
  • 3A to 3C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.
  • 3A to 3C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.
  • 3A to 3C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.
  • 1A and 1B are a schematic cross-sectional view and an SEM photograph showing a configuration of a semiconductor device according to a first embodiment;
  • 11 is a diagram showing the results of trial calculation of thermal stress on a gate electrode in the semiconductor device according to the first embodiment;
  • 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a first modification of the first embodiment;
  • FIG. 11 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a fourth modification of the first embodiment.
  • FIG. 11 is a top view showing a configuration of a semiconductor device according to a second embodiment.
  • FIG. 11 is a top view showing a configuration of a semiconductor device according to a second embodiment.
  • 10 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment.
  • FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment.
  • FIG. 13 is a top view showing a configuration of a semiconductor device according to a fourth embodiment.
  • FIG. 13 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a fourth embodiment.
  • 13 is a flowchart showing a method for manufacturing a semiconductor device according to a fourth embodiment.
  • FIG. 13 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a first modification of the fourth embodiment. 13 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fifth embodiment is applied. FIG.
  • a certain part having a higher density than another part means, for example, that the average density of the certain part is higher than the average density of the other part.
  • a certain part having a lower density than another part means, for example, that the average density of the certain part is lower than the average density of the other part.
  • the semiconductor device according to the first embodiment is a power semiconductor device, made of an n-type SiC substrate, and a planar gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) incorporating an SBD (Schottky Barrier Diode).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • SBD Schottky Barrier Diode
  • the semiconductor device is not limited to this, and may be, for example, a trench gate type semiconductor device, an IGBT (Insulated Gate Bipolar Transistor), or an RC-IGBT (Reverse Conducting - IGBT).
  • FIG. 1 is a top view showing the configuration of a semiconductor device 1 according to the first embodiment.
  • a source electrode 3 located in the center and a gate wiring 2 surrounding the source electrode 3 are provided on the upper part of the semiconductor device 1.
  • a gate pad 4 is provided between the center and the end of the upper part of the semiconductor device 1, and is electrically connected to the gate wiring 2.
  • the gate wiring 2 and the gate pad 4 are separated and insulated from the source electrode 3.
  • the region where unit cells are periodically arranged is defined as an active region, and the region other than the active region is defined as a termination region.
  • FIG. 2 is an enlarged top view showing a portion between the active region and the termination region indicated by the dashed dotted line in FIG. 1.
  • the active region includes an SBD region 20 in which an SBD is provided, and a MOS region 22 in which a MOSFET is provided.
  • SBD regions 20 are periodically provided in a striped pattern
  • MOS regions 22 are periodically provided in a striped pattern
  • the SBD regions 20 and the MOS regions 22 are alternately provided one by one.
  • the second interlayer insulating film 5 is provided in a region other than the active region including the multiple SBD regions 20 and multiple MOS regions 22, i.e., the termination region.
  • the gate wiring 2 and source electrode 3 are provided on the second interlayer insulating film 5, and the second interlayer insulating film 5 has a gate contact hole 5a covered by the gate wiring 2 and a contact hole 5b covered by the source electrode 3.
  • an SBD is provided below the contact hole 5b in the termination region, similar to the SBD region 20 in the active region.
  • FIG. 3 is a schematic cross-sectional view showing the configuration of a portion taken along line a-a' in FIG. 2.
  • the second interlayer insulating film 5 is provided in the termination region, so FIG. 3 generally shows the configuration of the termination region.
  • Line a-a' in FIG. 2 crosses over contact hole 5b in the second interlayer insulating film 5, so in FIG. 3, the second interlayer insulating film 5 is shown in two locations on either side of contact hole 5b.
  • the semiconductor device 1 includes, in the termination region, an n-type SiC substrate 13, an n-type epitaxial growth layer 12, an n-type well region 11, a p-type well region 15, a p-type potential fixed layer 10, an n-type source region 16, a contact region 9, a first interlayer insulating film 7, a gate electrode 6, a second interlayer insulating film 5, a barrier metal layer 8, a source electrode 3, a gate wiring 2, and a drain electrode 14.
  • the epitaxial growth layer 12 is provided uniformly on the first main surface (top surface in FIG. 3) of the SiC substrate 13, and the n-type well region 11 is provided on the epitaxial growth layer 12.
  • the portion including the SiC substrate 13, the epitaxial growth layer 12, and the n-type well region 11 is a combination of the SiC substrate and the epitaxial growth layer, but it may be only the SiC substrate or only the epitaxial growth layer.
  • the p-type well region 15 is selectively provided on the upper part of the n-type well region 11.
  • the sides and bottom of the potential fixing layer 10 are provided so as to be covered by the p-type well region 15, and the sides and bottom of the source region 16 are provided so as to be covered by the p-type well region 15.
  • the first interlayer insulating film 7 is selectively provided on the potential fixing layer 10, the n-type well region 11, the p-type well region 15, and the source region 16 in the termination region.
  • the first interlayer insulating film 7 has contact holes 5b, just like the second interlayer insulating film 5, so in FIG. 3, the first interlayer insulating film 7 is shown in two places, just like the second interlayer insulating film 5.
  • the gate electrode 6 is provided on the first interlayer insulating film 7.
  • the region located on the opposite side of the active region with respect to the gate electrode 6 provided on the first interlayer insulating film 7 on the active region side will be referred to as the reverse region.
  • the gate electrode 6 is electrically connected to a gate electrode (not shown) provided in the MOS region 22 in FIG. 2, and is at the same potential as the gate electrode in the MOS region 22.
  • a voltage equal to or greater than the threshold voltage is applied to the gate electrode in the MOS region 22, the conductivity type of a portion of the p-type semiconductor layer sandwiched between the n-type semiconductor layers is inverted, and a channel is formed in that portion.
  • the configuration in FIG. 3 is not a MOS region 22, so the gate electrode 6 in FIG. 3 indirectly forms a channel in the p-type semiconductor layer in the MOS region, but does not directly form a channel in the p-type semiconductor layer in FIG. 3.
  • the second interlayer insulating film 5 is provided to cover the gate electrode 6 and the first interlayer insulating film 7.
  • the second interlayer insulating film 5 has a gate contact hole 5a that partially exposes the gate electrode 6 provided on the first interlayer insulating film 7 on the reverse region side, and a contact hole 5b that partially exposes the n-type well region 11 in the termination region.
  • the barrier metal layer 8 covers the potential fixing layer 10, the n-type well region 11, the p-type well region 15, the source region 16, the second interlayer insulating film 5, and the gate electrode 6 exposed from the gate contact hole 5a.
  • the barrier metal layer 8 covering the gate electrode 6 is separated and insulated from the barrier metal layer 8 covering the n-type well region 11, etc.
  • the contact region 9 is provided between the barrier metal layer 8 and one of the source region 16, the p-type well region 15, and the potential fixing layer 10 provided on the active region side of the first interlayer insulating film 7, and provides an ohmic connection between them.
  • the gate wiring 2 is electrically connected to the gate electrode 6 via a barrier metal layer 8 that covers the gate electrode 6 exposed from the gate contact hole 5a.
  • the source electrode 3 is electrically connected to the n-type well region 11 and the like via a barrier metal layer 8 that covers the n-type well region 11 and the like.
  • the drain electrode 14 is provided on a second main surface (the lower surface in FIG. 3) of the SiC substrate 13 that is opposite to the first main surface on which the epitaxial growth layer 12 is provided.
  • the SBD provided in the SBD region 20 of the active region and the SBD provided at the bottom of the contact hole 5b on the reverse region side generate heat during operation.
  • the first heat generation amount on the reverse region side is configured to be larger than the second heat generation amount on the active region side.
  • the dimension of the first part of the first interlayer insulating film 7 on the reverse region side of the gate electrode 6 is larger than the dimension of the second part of the first interlayer insulating film 7 on the active region side of the gate electrode 6.
  • the gate electrode 6 is biased toward the active region side with respect to the first interlayer insulating film 7 so that D1>0, D2>0, and D1-D2>0 are satisfied. This will be explained in detail later.
  • ⁇ Production Method> 4 is a flowchart showing a method for manufacturing a semiconductor device according to the first preferred embodiment of the present invention. Each of the steps from the semiconductor substrate preparation step S1 to the drain electrode formation step S13 will be described below.
  • an epitaxial growth layer 12 made of n-type SiC is formed by CVD (Chemical Vapor Deposition) on a first main surface of an n-type SiC substrate 13 having a polytype of 4H, as shown in Fig. 5.
  • the n-type impurity concentration of the epitaxial growth layer 12 is, for example, 1 x 1015 cm -3 to 1 x 1017 cm -3 .
  • the thickness of the epitaxial growth layer 12 is, for example, 5 ⁇ m to 50 ⁇ m.
  • impurities are ion-implanted into the upper part of the epitaxial growth layer 12 to form the n-type well region 11.
  • the impurity concentration of the n-type well region 11 is higher than the impurity concentration of the epitaxial growth layer 12.
  • an implantation mask is formed in a predetermined region of the n-type well region 11 using photoresist or the like, and then p-type impurities are ion-implanted to form the p-type well region 15.
  • the p-type impurities are, for example, B (boron) and Al (aluminum).
  • the implantation depth of the p-type well region 15 is shallower than the depth of the n-type well region 11.
  • the impurity concentration of the p-type well region 15 is, for example, 1 ⁇ 10 17 cm -3 to 1 ⁇ 10 19 cm -3 .
  • an implantation mask is formed in a predetermined region of the p-type well region 15 using photoresist or the like, and then n-type impurities are ion-implanted to form the source region 16.
  • the n-type impurities are, for example, phosphorus and nitrogen.
  • the implantation depth of the source region 16 is shallower than that of the p-type well region 15.
  • an implantation mask is formed in a predetermined region of the p-type well region 15 using photoresist or the like, and then p-type impurities are ion-implanted to form the potential fixing layer 10.
  • the impurity concentration of the potential fixing layer 10 is higher than that of the p-type well region 15.
  • the structure obtained in the step of FIG. 9 is annealed in a heat treatment device in an inert gas atmosphere such as Ar (argon) gas at a temperature of 1300 to 1900°C for 30 seconds to 1 hour. This annealing electrically activates the implanted p-type and n-type impurities.
  • the first interlayer insulating film formation process S6 a CVD method is used to form an insulating film that will become the first interlayer insulating film 7, and the insulating film is then patterned using photolithography and dry or wet etching techniques. As a result, as shown in FIG. 10, the first interlayer insulating film 7 is formed, which remains in predetermined regions on the potential fixing layer 10, the n-type well region 11, the p-type well region 15, and the source region 16.
  • the material for the first interlayer insulating film 7 is, for example, TEOS (Tetra EthOxy Silane).
  • a gate oxide film (not shown) is formed in the active region.
  • a conductive film is deposited on the first interlayer insulating film 7 by thermal oxidation or CVD, and then the conductive film is patterned by photolithography and dry or wet etching.
  • a gate electrode 6 is formed having a portion that is biased toward the active region side with respect to the first interlayer insulating film 7, as shown in Fig. 11.
  • the material of the conductive film that becomes the gate electrode 6 may be, for example, polycrystalline Si or poly-Si deposited by chemical vapor deposition or the like, or may be tungsten or tungsten silicide (WSi x ) when the semiconductor device 1 is to operate at a higher speed.
  • the second interlayer insulating film formation process S9 a CVD method is used to form an insulating film that will become the second interlayer insulating film 5, and the insulating film is then patterned using photolithography and dry or wet etching techniques.
  • the second interlayer insulating film 5 is formed, which covers the gate electrode 6 and the first interlayer insulating film 7 and has gate contact holes 5a and contact holes 5b.
  • the material of the second interlayer insulating film 5 is, for example, TEOS (tetra ethoxy silane) and BPSG (Boro-Phospho Silicate Glass).
  • the contact region 9 is a silicide layer formed, for example, by depositing a metal film mainly composed of Ni (nickel) in an opening of a photoresist or the like, and then performing a heat treatment at a temperature in the range of 600°C to 1100°C.
  • a barrier metal layer 8 made of titanium or a titanium compound such as titanium nitride (TiN) is formed. Then, a film of aluminum, an aluminum alloy made of aluminum and silicon, or nickel is formed to form the gate wiring 2 and the source electrode 3.
  • the second main surface of the SiC substrate 13 is machined using a grinding wheel to thin the SiC substrate 13.
  • a nickel film of, for example, about 600 nm is formed on the machined second main surface by appropriately using a sputtering method or the like to form the drain electrode 14.
  • a nickel film of, for example, about 600 nm is formed on the machined second main surface by appropriately using a sputtering method or the like to form the drain electrode 14.
  • a film containing a metal that has poor reactivity with the outside such as gold (Au) or silver (Ag)
  • the drain electrode 14 may be a laminated film consisting of a nickel film and a protective film.
  • thermal stress resulting from these is generated at the interface between each interlayer insulating film and the source electrode 3. This thermal stress causes deterioration of each interlayer insulating film, lowering the insulating performance of each interlayer insulating film and damaging the gate electrode 6 in the termination region, resulting in a problem of malfunction of the semiconductor device.
  • the dimension of the first portion of the first interlayer insulating film 7 on the reverse region side of the gate electrode 6 is greater than the dimension of the second portion of the first interlayer insulating film 7 on the active region side of the gate electrode 6.
  • the gate electrode 6 is biased toward the active region side with respect to the first interlayer insulating film 7 so that D1>0, D2>0, and D1-D2>0 are satisfied.
  • the SEM photograph in FIG. 17 shows a scanning electron microscope (SEM) image of a semiconductor device manufactured by the manufacturing method according to the first embodiment. In the semiconductor device in the SEM photograph, D1 is about 1 ⁇ m and D2 is about 0.5 ⁇ m.
  • FIG. 18 is a diagram showing the results of an estimate of the thermal stress on the gate electrode 6 in the semiconductor device according to the first embodiment.
  • the semiconductor device according to the first embodiment in which D1-D2>0, has a thermal stress on the gate electrode 6 that is reduced by approximately 30% compared to the semiconductor device (comparative example) in which D2-D1>0. Therefore, according to the semiconductor device according to the first embodiment, the thermal stress on the gate electrode 6 can be reduced and damage to the gate electrode 6 can be suppressed, thereby improving the reliability of the semiconductor device during operation.
  • wide band gap semiconductor devices that utilize the high breakdown field of wide band gap semiconductors to be made smaller and more efficient have a large increase in temperature during operation, so it is effective to increase the reliability of the semiconductor device as described above.
  • Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and diamond.
  • FIG. 19 is a schematic cross-sectional view showing the configuration of a semiconductor device according to the first modification of the first embodiment. D3 and D4 are shown in FIG. 19. D3 is the distance between the end of the first portion on the reverse region side and the end of the gate electrode 6 on the reverse region side in a plan view. D4 is the distance between the end of the second portion on the active region side and the end of the gate electrode 6 on the active region side in a plan view.
  • the gate electrode 6 may be biased toward the active region side with respect to the first interlayer insulating film 7 so that D3>0, D4>0, and D3-D4>0 are satisfied. Even with such a configuration, the reliability of the semiconductor device during operation can be improved, similarly to the first embodiment.
  • the heat generation amount and dimensions of the first embodiment and the first modification may be reversed from the heat generation amount and dimensions described above. That is, when the second heat generation amount on the active region side is larger than the first heat generation amount on the reverse region side, the dimension of the second portion of the first interlayer insulating film 7 on the active region side of the gate electrode 6 may be larger than the dimension of the first portion of the first interlayer insulating film 7 on the reverse region side of the gate electrode 6.
  • the gate electrode 6 may be biased toward the reverse region side with respect to the first interlayer insulating film 7 so that D1>0, D2>0, D2-D1>0, or D3>0, D4>0, D4-D3>0 are satisfied. Even with such a configuration, the reliability of the semiconductor device during operation can be improved, similarly to the first embodiment.
  • ⁇ Modification 3> In a power semiconductor device, a current usually flows through the BD region on the active region side and the SBD region on the reverse region side during reflux operation, and the semiconductor device itself heats up due to these resistance components. Therefore, when the resistance value of the SBD region on the reverse region side in the power semiconductor device is set to a first resistance value (R1) and the resistance value of the BD region on the active region side is set to a second resistance value (R2), D1 and D2, or D3 and D4 may be set according to the first resistance value (R1) and the second resistance value (R2).
  • the dimension of the first portion of the first interlayer insulating film 7 on the reverse region side of the gate electrode 6 may be larger than the dimension of the second portion of the first interlayer insulating film 7 on the active region side of the gate electrode 6.
  • the gate electrode 6 may be biased toward the active region side with respect to the first interlayer insulating film 7 so that D1>0, D2>0, D1-D2>0, or D3>0, D4>0, D3-D4>0 are satisfied.
  • the dimension of the second portion of the first interlayer insulating film 7 closer to the active region than the gate electrode 6 may be larger than the dimension of the first portion of the first interlayer insulating film 7 closer to the reverse region than the gate electrode 6.
  • the gate electrode 6 may be biased toward the reverse region side with respect to the first interlayer insulating film 7 so that D1>0, D2>0, D2-D1>0, or D3>0, D4>0, D4-D3>0 are satisfied. Even with such a configuration, the reliability of the semiconductor device during operation can be improved, as in the first embodiment.
  • ⁇ Modification 4> 20 is a schematic cross-sectional view showing a configuration of a semiconductor device according to Modification 4 of the first embodiment.
  • a protective film including a first protective film 17 covering the source electrode 3 and the gate line 2 and a second protective film 18 covering the first protective film 17 may be provided.
  • the material of the first protective film 17 is preferably an insulating material or a semi-insulating material, such as SOG (Spin On Glass).
  • the material of the second protective film 18 is preferably an insulating material or a semi-insulating material, such as a polyimide film.
  • the semiconductor device 1 is described in which an SBD is provided in the termination region, but if a configuration for passing a current during a return operation is provided in the termination region, an SBD does not have to be provided in the termination region.
  • a diode such as a PN diode may be provided in the termination region instead of an SBD.
  • the above-mentioned modified examples may also be applied to the second and subsequent embodiments.
  • ⁇ Embodiment 2> 21 is a top view showing the configuration of a semiconductor device 1 according to the second embodiment.
  • a source electrode 3 and a gate wiring 2 surrounding the source electrode 3 are provided on the upper part of the semiconductor device 1.
  • a gate pad 4 electrically connected to the gate wiring 2 is also provided on a part of the upper part of the semiconductor device 1. The gate wiring 2 and the gate pad 4 are separated from and insulated from the source electrode 3.
  • FIG. 22 is an enlarged top view of a portion between the active region and the termination region, indicated by the dashed dotted line in FIG. 21.
  • the active region includes not only a plurality of SBD regions 20 and a plurality of MOS regions 22, but also a plurality of BD (body diode) regions 23 periodically arranged in a stripe pattern.
  • a body diode is provided in the BD region 23.
  • the SBD regions 20 and the BD regions 23 are arranged alternately. This makes it possible to reduce the on-resistance in the active region.
  • the configuration of the portion along line a-a' is the same as the configuration of FIG. 3 described in the first embodiment, and an SBD is provided at the bottom of contact hole 5b in the termination region.
  • the gate electrode 6 is unevenly located with respect to the first interlayer insulating film 7, so that damage to the gate electrode 6 in the termination region can be suppressed, and the reliability of the semiconductor device during operation can be improved.
  • FIG. 23 is a flowchart showing a method for manufacturing a semiconductor device according to the second embodiment.
  • the method for manufacturing a semiconductor device according to the second embodiment is similar to the method in the flowchart of FIG. 4 showing the method for manufacturing a semiconductor device according to the first embodiment, except that the thinning step S12 of the SiC substrate is moved to after the semiconductor substrate preparation step S1.
  • the manufacturing method may be such that the n-type well region 11 formation step S2 and subsequent steps are performed after the SiC substrate 13 is thinned.
  • the semiconductor device according to the first embodiment may also be formed according to the process sequence shown in the flowchart of FIG. 23.
  • a source electrode 3 located at the center and a gate wiring 2 surrounding the source electrode 3 are provided in the upper part of the semiconductor device 1.
  • a gate pad 4 is provided between the center and the end of the upper part of the semiconductor device 1, and is electrically connected to the gate wiring 2.
  • the gate wiring 2 and the gate pad 4 are separated from the source electrode 3 and insulated from it.
  • the configuration between the active region and the termination region in the third embodiment is similar to that of the semiconductor device 1 in the first embodiment shown in the top view of FIG. 2, and the active region includes an SBD region 20 in which an SBD is provided, and a MOS region 22 in which a MOSFET is provided.
  • the SBD regions 20 are periodically arranged in a stripe pattern
  • the MOS regions 22 are periodically arranged in a stripe pattern
  • the SBD regions 20 and the MOS regions 22 are alternately arranged one by one.
  • FIG. 24 is a schematic cross-sectional view showing the configuration of a semiconductor device according to the third embodiment, and is a schematic cross-sectional view showing the configuration of a portion along line a-a' in FIG. 2.
  • the second interlayer insulating film 5 is provided in the termination region, so FIG. 24 generally shows the configuration of the termination region.
  • Line a-a' in FIG. 2 straddles contact hole 5b in second interlayer insulating film 5, so in FIG. 24, second interlayer insulating film 5 is shown in two places on either side of contact hole 5b.
  • the SBD provided in the SBD region 20 of the active region and the SBD provided under the contact hole 5b on the reverse region side generate heat during operation.
  • the first heat generation amount on the reverse region side is configured to be larger than the second heat generation amount on the active region side.
  • the first heat generation amount and the second heat generation amount may be calculated from the conduction loss value in the on-state of the semiconductor device when current is applied, or the switching loss value of the semiconductor device when switching between the on-state and the off-state.
  • the first heat generation amount and the second heat generation amount may be calculated from the temperature distribution inside the semiconductor device based on an image captured using an infrared camera.
  • the first heat generation amount and the second heat generation amount may be calculated by combining the first and second examples, and various measurement and analysis methods can be used to calculate the first and second heat generation amounts.
  • the thickness of the first interlayer insulating film 7 is defined as h
  • the distance between the end of the upper part of the first portion on the reverse region side and the end of the gate electrode 6 on the reverse region side is defined as D1
  • the distance between the end of the upper part of the second portion on the active region side and the end of the gate electrode 6 on the active region side is defined as D2
  • D1>0, D2>0, D1-D2>0, and h>min(D1,D2) hold.
  • min(D1,D2) is the smaller of D1 and D2.
  • min(D1,D2) D2.
  • the thickness h of the first interlayer insulating film 7 is larger than the smaller of the dimensions of the first portion and the second portion, so that the thermal stress applied to the gate electrode 6 can be shared not only by the gate electrode 6 but also by the first interlayer insulating film 7. This leads to a reduction in the thermal stress applied to the gate electrode 6, that is, to the suppression of damage to the gate electrode 6, so that the reliability of the semiconductor device during operation can be improved. Note that it is more preferable to make the thickness of the first interlayer insulating film 7 larger than the dimensions of both the first portion and the second portion, since this can reduce the thermal stress applied to the ends of both sides of the gate electrode 6 from the surroundings.
  • ⁇ Fourth embodiment> 25 is a top view showing a configuration of a semiconductor device according to the fourth embodiment.
  • a second gate wiring 32 is provided on the gate wiring 2
  • a second source electrode 33 is provided on the source electrode 3.
  • the second gate wiring 32 and the second source electrode 33 in Fig. 25 have substantially the same shapes as the gate wiring 2 and the source electrode 3 in Fig. 1.
  • the configuration between the active region and the termination region in this fourth embodiment is also similar to the configuration of the semiconductor device 1 in the first embodiment shown in the top view of FIG. 2, and the active region includes an SBD region 20 in which an SBD is provided, and a MOS region 22 in which a MOSFET is provided.
  • the multiple SBD regions 20 are periodically provided in a striped pattern
  • the multiple MOS regions 22 are periodically provided in a striped pattern
  • the SBD regions 20 and the MOS regions 22 are alternately provided one by one.
  • FIG. 26 is a schematic cross-sectional view showing the configuration of a semiconductor device according to the fourth embodiment, and is a schematic cross-sectional view showing the configuration of a portion along line a-a' in FIG. 2.
  • the second interlayer insulating film 5 is provided in the termination region, so FIG. 26 generally shows the configuration of the termination region.
  • Line a-a' in FIG. 2 straddles contact hole 5b in second interlayer insulating film 5, so in FIG. 26, second interlayer insulating film 5 is shown in two places on either side of contact hole 5b.
  • the SBD provided in the SBD region 20 in the active region and the SBD provided below the contact hole 5b on the reverse region side generate heat during operation.
  • the first amount of heat generated on the reverse region side is configured to be greater than the second amount of heat generated on the active region side.
  • the second gate wiring 32 is provided on the gate wiring 2
  • the second source electrode 33 which is the second electrode, is provided on the source electrode 3.
  • the thermal conductivity of the second source electrode 33 is higher than the thermal conductivity of the semiconductor layer on which the first interlayer insulating film 7 is provided.
  • the semiconductor layer here includes, for example, at least one of the SiC substrate 13, the epitaxial growth layer 12, the n-type well region 11, the p-type well region 15, the potential fixed layer 10, and the source region 16.
  • the distance between the end of the upper part of the first portion on the reverse region side and the end of the gate electrode 6 on the reverse region side is defined as D1
  • the distance between the end of the upper part of the second portion on the active region side and the end of the gate electrode 6 on the active region side is defined as D2
  • the width of the second interlayer insulating film 5 is defined as w
  • the thickness of the portion of the source electrode 3 above the gate electrode 6 is defined as ts1
  • the thickness of the portion of the second source electrode 33 above the gate electrode 6 is defined as ts2
  • Fig. 27 is a flowchart showing a method for manufacturing a semiconductor device according to the fourth preferred embodiment.
  • the manufacturing method shown in Fig. 27 is similar to the manufacturing method shown in Fig. 4, in which a second source electrode forming step S14 following the drain electrode forming step S13 is added. Therefore, the second source electrode forming step S14 will be mainly described below.
  • the second source electrode 33 is made of a material that has a higher thermal conductivity than the materials of the source electrode 3 and the semiconductor layer described above.
  • the source electrode 3 is made of either an aluminum alloy made of aluminum and silicon, or nickel, it is suitable to form a film of copper, silver, gold, or the like as the second source electrode 33.
  • the method for forming the second source electrode 33 may be a PVD method or a plating method.
  • a sputtering method is used as the PVD method, and for example, an electrolytic plating method or an electroless plating method is used as the plating method.
  • the surface of the source electrode 3 is cleaned to remove oxide films, organic matter, foreign matter, etc.
  • acid cleaning or plasma treatment for example, is used.
  • the material of the source electrode 3 is a metal whose main component is aluminum, such as aluminum, an aluminum-silicon alloy, or an aluminum-copper alloy, so it is difficult to perform electroless plating of copper in this state. For this reason, the source electrode 3 is immersed in a zincate bath to perform a zincate treatment that replaces the aluminum of the source electrode 3 with zinc, and the surface of the source electrode 3 is replaced with zinc. Then, for example, an electroless plating process is performed using a copper sulfate bath maintained at about 60 to 80°C, so that the second source electrode 33 can be easily formed. Note that while the formation of the second source electrode 33 has been described above, the formation of the second gate wiring 32 is similar.
  • the thickness ts2 of the portion of the second source electrode 33 above the gate electrode 6 is larger than the width w of the second interlayer insulating film 5
  • the width w of the second interlayer insulating film 5 is larger than the thickness ts1 of the portion of the source electrode 3 above the gate electrode 6, and the thermal conductivity of the second source electrode 33 is higher than the thermal conductivity of the semiconductor layer.
  • the heat generated in the semiconductor device due to current flow can be prevented from increasing in temperature by the heat capacity of the second source electrode 33, and the heat can be transferred to the outside via the second source electrode 33.
  • the difference in the linear expansion coefficient between the second source electrode 33 and the gate electrode 6 is smaller than the difference in the linear expansion coefficient between the source electrode 3 and the gate electrode 6, since the thermal stress on the gate electrode 6 can be further reduced.
  • the content of the fourth embodiment may also be applied to, for example, the second modification of the first embodiment.
  • ⁇ Modification 1> 28 is a schematic cross-sectional view showing a configuration of a semiconductor device according to Modification 1 of the fourth embodiment.
  • the gate wiring 2 and the source electrode 3 are omitted, and the second gate wiring 32 and the second source electrode 33 are directly connected to the barrier metal layer 8.
  • the source electrode formation step S11 in the flowchart of FIG. 27 can be omitted, and the second gate wiring 32 and the second source electrode 33 can be formed by a PVD method or a plating method, thereby simplifying the manufacturing process.
  • the thickness ts2 of the portion of the second source electrode 33 above the gate electrode 6 is greater than the width w of the second interlayer insulating film 5, and the thermal conductivity of the second source electrode 33 is higher than the thermal conductivity of the semiconductor layer.
  • the semiconductor device according to the first to fourth embodiments is applied to a power conversion device.
  • the present disclosure is not limited to a specific power conversion device, the following will describe the fifth embodiment in the case where the present disclosure is applied to a three-phase inverter.
  • FIG. 29 is a block diagram showing the configuration of a power conversion system to which a power conversion device 200 according to the third embodiment is applied.
  • the power conversion system shown in FIG. 29 is composed of a power source 100, a power conversion device 200, and a load 300.
  • the power source 100 is a DC power source and supplies DC power to the power conversion device 200.
  • the power source 100 can be composed of various things, for example, a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit or an AC/DC converter connected to an AC system.
  • the power source 100 may also be composed of a DC/DC converter that converts DC power output from a DC system into a predetermined power.
  • the power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300.
  • the power conversion device 200 converts the DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300.
  • the power conversion device 200 includes a main conversion circuit 201 that converts the DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs a control signal to the drive circuit 202 to control the drive circuit 202.
  • the load 300 is a three-phase motor that is driven by AC power supplied from the power conversion device 200.
  • the load 300 is not limited to a specific use, but is a motor mounted on various electrical devices, and is used, for example, as a motor for a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.
  • the power conversion device 200 will be described in detail below.
  • the main conversion circuit 201 includes switching elements and free wheel diodes (not shown). By switching the switching elements, the main conversion circuit 201 converts the DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300.
  • the main conversion circuit 201 according to the fifth embodiment is a two-level three-phase full bridge circuit that can be configured with six switching elements and six free wheel diodes connected in reverse parallel to each switching element.
  • the semiconductor device 1 according to any of the above-mentioned embodiments 1 to 4 and their modifications is applied as at least one of the switching elements and free wheel diodes of the main conversion circuit 201.
  • the six switching elements are connected in series with two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit.
  • the output terminals of each upper and lower arm i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.
  • the drive circuit 202 generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203 described below, it outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off.
  • the drive signal is a voltage signal (on signal) that is greater than the threshold voltage of the switching element
  • the drive signal is a voltage signal (off signal) that is less than the threshold voltage of the switching element.
  • the control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the control circuit 203 calculates the time so that the main conversion circuit 201 can be controlled by pulse width modulation (PWM) control, which modulates the on time of the switching element according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each point in time, and an off signal is output to the switching element that should be in the off state. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
  • PWM pulse width modulation
  • the manufacturing method of the power conversion device 200 has the following steps.
  • the semiconductor device 1 is manufactured by the manufacturing method described in the above-mentioned embodiment or its modified example.
  • a main conversion circuit 201 having the semiconductor device 1 is formed, and a drive circuit 202 and a control circuit 203 are formed. This results in the power conversion device 200.
  • the main conversion circuit 201 is formed, the drain electrode of the semiconductor device 1 is bonded onto the mounting substrate, and the source electrode of the semiconductor device 1 is bonded to the mounting substrate via a wire.
  • the semiconductor device 1 according to the first to fourth embodiments is used as the semiconductor device that constitutes the main conversion circuit 201, so that the reliability of the main conversion circuit 201 and the power conversion device during operation can be improved.
  • the power conversion device according to the fifth embodiment is a two-level power conversion device, but it may be a three-level or multi-level power conversion device, and the present disclosure may be applied to a single-phase inverter when supplying power to a single-phase load.
  • the present disclosure can also be applied to a DC/DC converter or AC/DC converter when supplying power to a DC load, etc.
  • the power conversion device to which this disclosure is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system, etc.
  • a semiconductor device having an active region and a termination region defined therein, a first interlayer insulating film provided in the termination region; a gate electrode provided on the first interlayer insulating film; when a first amount of heat generated on a reverse region side located on an opposite side of the active region with respect to the gate electrode is larger than a second amount of heat generated on the active region side, a dimension of a first portion of the first interlayer insulating film located on the reverse region side of the gate electrode is larger than a dimension of a second portion of the first interlayer insulating film located on the active region side of the gate electrode, When the second amount of heat generation is greater than the first amount of heat generation, a dimension of the second portion is greater than a dimension of the first portion.
  • a semiconductor device having an active region and a termination region defined therein, a first interlayer insulating film provided in the termination region; a gate electrode provided on the first interlayer insulating film;
  • a first resistance value of an SBD region on a reverse region side located on an opposite side of the active region with respect to the gate electrode is larger than a second resistance value of a BD region on the active region side
  • a dimension of a first portion of the first interlayer insulating film on the reverse region side of the gate electrode is larger than a dimension of a second portion of the first interlayer insulating film on the active region side of the gate electrode
  • the second resistance value is greater than the first resistance value
  • a dimension of the second portion is greater than a dimension of the first portion.
  • the active region comprises: A plurality of SBD regions periodically provided in a stripe shape; 7.
  • a width of the second interlayer insulating film is greater than a thickness of a portion of the first electrode above the gate electrode.
  • a main conversion circuit having the semiconductor device according to any one of claims 1 to 12, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; a control circuit configured to output a control signal to the drive circuit for controlling the drive circuit.

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018120879A (ja) * 2015-06-04 2018-08-02 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP2020096202A (ja) * 2017-02-24 2020-06-18 三菱電機株式会社 炭化珪素半導体装置および電力変換装置
JP2021028930A (ja) * 2019-08-09 2021-02-25 富士電機株式会社 半導体装置
JP2022073497A (ja) * 2020-11-02 2022-05-17 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP2022130063A (ja) * 2021-02-25 2022-09-06 株式会社東芝 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018120879A (ja) * 2015-06-04 2018-08-02 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP2020096202A (ja) * 2017-02-24 2020-06-18 三菱電機株式会社 炭化珪素半導体装置および電力変換装置
JP2021028930A (ja) * 2019-08-09 2021-02-25 富士電機株式会社 半導体装置
JP2022073497A (ja) * 2020-11-02 2022-05-17 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP2022130063A (ja) * 2021-02-25 2022-09-06 株式会社東芝 半導体装置

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