WO2024203480A1 - 面発光半導体レーザ素子の製造方法及び面発光半導体レーザ素子 - Google Patents

面発光半導体レーザ素子の製造方法及び面発光半導体レーザ素子 Download PDF

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WO2024203480A1
WO2024203480A1 PCT/JP2024/010328 JP2024010328W WO2024203480A1 WO 2024203480 A1 WO2024203480 A1 WO 2024203480A1 JP 2024010328 W JP2024010328 W JP 2024010328W WO 2024203480 A1 WO2024203480 A1 WO 2024203480A1
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layer
hole
buried
semiconductor laser
emitting semiconductor
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French (fr)
Japanese (ja)
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進 野田
朋朗 小泉
渓 江本
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Stanley Electric Co Ltd
Kyoto University NUC
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Stanley Electric Co Ltd
Kyoto University NUC
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Priority to DE112024001490.9T priority Critical patent/DE112024001490T5/de
Priority to CN202480016642.2A priority patent/CN120836125A/zh
Publication of WO2024203480A1 publication Critical patent/WO2024203480A1/ja
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    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/11—Comprising a photonic bandgap structure
    • H—ELECTRICITY
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    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0207—Substrates having a special shape
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    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04252—Electrodes, e.g. characterised by the structure characterised by the material
    • H01S5/04253—Electrodes, e.g. characterised by the structure characterised by the material having specific optical properties, e.g. transparent electrodes
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    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04254—Electrodes, e.g. characterised by the structure characterised by the shape
    • H—ELECTRICITY
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    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04256—Electrodes, e.g. characterised by the structure characterised by the configuration
    • H01S5/04257—Electrodes, e.g. characterised by the structure characterised by the configuration having positive and negative electrodes on the same side of the substrate
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    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/185—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL]
    • H—ELECTRICITY
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    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/2201—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure in a specific crystallographic orientation
    • H—ELECTRICITY
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    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H—ELECTRICITY
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    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/34333—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser
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    • H01S2301/00—Functional characteristics
    • H01S2301/17—Semiconductor lasers comprising special layers
    • H01S2301/176—Specific passivation layers on surfaces other than the emission facet
    • H—ELECTRICITY
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    • H01S2304/00—Special growth methods for semiconductor lasers
    • H01S2304/04—MOCVD or MOVPE
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2304/00—Special growth methods for semiconductor lasers
    • H01S2304/12—Pendeo epitaxial lateral overgrowth [ELOG], e.g. for growing GaN based blue laser diodes

Definitions

  • the present invention relates to a method for manufacturing a surface-emitting semiconductor laser element having a photonic crystal, and to the surface-emitting semiconductor laser element.
  • PCSELs photonic crystal surface-emitting lasers
  • PCs photonic crystals
  • Patent Document 1 proposes a method of embedding holes with a hexagonal column structure with ⁇ 10-10 ⁇ side faces in a group III nitride semiconductor layer using facet selective growth in order to enhance the diffraction effect in the hole layer in a photonic crystal laser and obtain a high resonance effect. It describes how this realizes a photonic crystal laser element equipped with a photonic crystal that has a large filling factor and a large optical confinement coefficient.
  • Patent Document 2 also proposes a method for embedding holes in a group III nitride semiconductor layer in a photonic crystal laser using mass transport. It describes how this results in a photonic crystal laser with a large coupling coefficient for light waves propagating through the photonic crystal layer.
  • Patent Document 2 also proposes a method of filling holes using mass transport, but when this method is used, the holes are filled with a cross-sectional shape that has the most thermally stable columnar structure, i.e., a regular hexagonal column structure. Therefore, it is difficult to introduce asymmetry into the cross-sectional shape of the holes, and high emission efficiency cannot be obtained. In other words, high-output operation is not possible.
  • the present invention aims to provide a surface-emitting semiconductor laser device that has a high-quality active layer, a low threshold value, and high efficiency, and a manufacturing method thereof, in which the air hole layer and the active layer are brought into close proximity to each other, thereby enhancing the resonance effect.
  • a method for manufacturing a surface emitting semiconductor laser device includes the steps of: forming a hole formation preparation layer on a substrate; forming holes arranged two-dimensionally at each of the lattice points in the hole formation preparation layer to form a hole formation layer; forming a first burying layer by performing facet growth to close the hole; growing a second burying layer that buries the first burying layer evenly to form a void layer having voids corresponding to the holes; annealing the second buried layer in a hydrogen atmosphere to flatten the second buried layer; Crystal growth of a semiconductor layer including an active layer is performed on the flat etched second buried layer.
  • a surface emitting semiconductor laser device comprises: A surface emitting semiconductor laser element manufactured by the above manufacturing method, The distance between the active layer and the hole layer is 200 nm or less.
  • FIG. 1 is a cross-sectional view showing a schematic example of a structure of a PCSEL element according to a first embodiment.
  • FIG. 1B is an enlarged cross-sectional view showing a schematic diagram of holes arranged in the hole layer shown in FIG. 1A.
  • FIG. 2 is a plan view showing a schematic top surface of a PCSEL element. 2 is a cross-sectional view that illustrates a cross section taken along a plane parallel to an n-side guide layer.
  • FIG. 1 is an SEM image of a cross section of a wafer when the etching time is (i) 5 minutes.
  • 13 is an SEM image of a cross section of a wafer when the etching time is (ii) 20 minutes.
  • FIG. 13 is an SEM image of a cross section of a wafer when the etching time is (iii) 50 minutes.
  • FIG. 2 is a diagram showing an AFM image of the surface of an active layer.
  • FIG. 13 is a diagram showing the measurement results of surface roughness when the etching time is (ii) 20 minutes.
  • FIG. 13 is a diagram showing the measurement results of surface roughness when the etching time is (iii) 50 minutes.
  • FIG. 13 is a diagram showing the measured surface roughness Ra of a 20 ⁇ m ⁇ 20 ⁇ m area versus the layer thickness of the buried layer.
  • a photonic crystal surface-emitting laser element is a surface-emitting semiconductor laser element that has a resonator layer in a direction parallel to the semiconductor light-emitting structure layers (n-side guide layer, light-emitting layer, p-side guide layer) that constitute the light-emitting element, and emits coherent light in a direction perpendicular to the resonator layer.
  • a PCSEL element in a PCSEL element, light waves propagating within a plane parallel to the air hole layer (photonic crystal layer) are diffracted by the diffraction effect of the photonic crystal to form a two-dimensional resonance mode, and are also diffracted in a direction perpendicular to the parallel plane.
  • the light extraction direction is perpendicular to the resonance direction (within the plane parallel to the air hole layer).
  • FIG. 1A is a cross-sectional view showing an example of the structure of a photonic crystal surface-emitting laser element (PCSEL element) 10 according to an embodiment of the present invention.
  • FIG. 1B is an enlarged cross-sectional view showing an air hole layer 14P and air holes 14K arranged in the air hole layer 14P in FIG. 1A.
  • PCSEL element photonic crystal surface-emitting laser element
  • FIG 2A is a plan view showing the top surface of the PCSEL device 10.
  • FIG 2B is a cross-sectional view showing the cross section of the hole layer 14P in a plane parallel to the n-side guide layer 14, and
  • FIG 2C is a plan view showing the bottom surface of the PCSEL device 10.
  • a semiconductor structure layer 11 is formed on a light-transmitting device substrate 12. The semiconductor layers are stacked perpendicularly to the central axis CX of the semiconductor structure layer 11.
  • the semiconductor structure layer 11 is made of a hexagonal nitride semiconductor.
  • the semiconductor structure layer 11 is made of, for example, a GaN-based semiconductor.
  • a semiconductor structure layer 11 consisting of multiple semiconductor layers is formed on an element substrate 12, in this order: an n-clad layer (first clad layer of a first conductivity type) 13, an n-side guide layer (first guide layer) 14 which is a guide layer provided on the n-side, a light distribution adjustment layer 23, an active layer (ACT) 15, a p-side guide layer (second guide layer) 16 which is a guide layer provided on the p-side, an electron barrier layer (EBL: Electron Blocking Layer) 17, a p-clad layer (second clad layer of a second conductivity type) 18, and a p-contact layer 19.
  • the first conductivity type is n-type and the second conductivity type, which is the opposite conductivity type to the first conductivity type, is p-type
  • the first conductivity type and the second conductivity type may also be p-type and n-type, respectively.
  • the element substrate 12 is a hexagonal GaN single crystal substrate that has a high transmittance for the light emitted from the active layer 15. More specifically, the element substrate 12 is a hexagonal GaN single crystal substrate whose main surface (crystal growth surface) is a +c plane, which is a ⁇ 0001 ⁇ plane in which Ga atoms are arranged on the outermost surface.
  • the back surface (light emission surface) is a -c plane, which is a (000-1) plane in which N atoms are arranged on the outermost surface.
  • the -c plane is suitable as a light emission surface because it is resistant to oxidation, etc.
  • the element substrate 12 is not limited to this, but is preferably a so-called just substrate, or, for example, a substrate whose main surface is offset by about 1° in the m-axis direction.
  • a substrate offset by about 0.3 to 0.7° in the m-axis direction can obtain mirror-finish growth under a wide range of growth conditions.
  • the back surface of the substrate opposite the main surface is the light emitting surface, which is the "-c" surface, which is the (000-1) surface on which N atoms are arranged at the top surface.
  • the -c surface is resistant to oxidation, etc., so it is suitable as a light extraction surface.
  • each semiconductor layer is explained below, but these are merely examples and can be modified as appropriate.
  • the n-cladding layer 13 is, for example, an n-Al 0.04 Ga 0.96 N layer with an Al composition of 4% and a thickness of 2 ⁇ m.
  • the aluminum (Al) composition ratio is set so that the refractive index is smaller than that of the layer adjacent to the active layer 15 side (i.e., the n-side guide layer 14).
  • the n-side guide layer 14 is composed of a lower guide layer 14A, an air-hole layer (or PC layer) 14P, which is a photonic crystal layer, and a buried layer 14B.
  • the air-hole layer 14P has a layer thickness d PC
  • the buried layer 14B has a layer thickness D.
  • the layer thickness d PC of the air-hole layer 14P is 40 to 180 nm.
  • the air hole layer 14P refers to a layer portion extending from the upper end to the lower end of the air hole 14K in the n-side guide layer 14 (see FIG. 1B). Therefore, the layer thickness d PC of the air hole layer 14P is equal to the height of the air hole.
  • the lower guide layer 14A is, for example, n-GaN with a layer thickness of 100 to 400 nm.
  • the void layer 14P is n-GaN with a layer thickness (or the height of the void 14K) of 40 to 180 nm.
  • the buried layer 14B is made of n-GaN or n-InGaN, or undoped GaN or undoped InGaN. Alternatively, it may be a layer in which these semiconductor layers are stacked.
  • the layer thickness D of the buried layer 14B is, for example, 30 to 150 nm.
  • the buried layer 14B is made of a first buried layer 14B1 and a second buried layer 14B2. In other words, the buried layer 14B is a stacked buried layer in which the second buried layer 14B2 is stacked on the first buried layer 14B1.
  • a light distribution adjustment layer 23 which is a hetero semiconductor layer (a heterogeneous semiconductor layer) that has a different crystal composition from the second buried layer 14B2 and forms a heterostructure with the second buried layer 14B2.
  • the light distribution adjustment layer 23 may be a semiconductor layer of the same conductivity type as the second buried layer 14B2, or at least one of them may be an i-layer (intrinsic semiconductor layer).
  • the light distribution adjustment layer 23 is provided between the buried layer 14B and the active layer 15, and has the function of adjusting the coupling efficiency between the light propagating in the hole layer 14P and the hole layer 14P acting as a resonator.
  • the light distribution adjustment layer 23 is an undoped In 0.03 Ga 0.97 N layer, and has a thickness of, for example, 50 nm.
  • the thickness of the light distribution adjustment layer 23 is selected according to the composition or refractive index of the light distribution adjustment layer 23 and the adjustment of the coupling efficiency.
  • the n-side semiconductor layer including the n-side guide layer 14 and the light distribution adjustment layer 23 is also referred to as the first semiconductor layer, but the light distribution adjustment layer 23 does not necessarily have to be provided.
  • the active layer 15, which is the light-emitting layer, is, for example, a multiple quantum well (MQW) layer having two quantum well layers.
  • the barrier layer and quantum well layer of the MQW are GaN (layer thickness 6.0 nm) and InGaN (layer thickness 4.0 nm), respectively.
  • the central emission wavelength of the active layer 15 is 440 nm.
  • the active layer 15 is disposed within 180 nm of the air hole layer 14P (i.e., within the period PK of the air holes 14K). In this case, a high resonance effect is obtained by the air hole layer 14P.
  • the p-side guide layer 16 is composed of a p-side guide layer (1) 16A which is an undoped In 0.02 Ga 0.98 N layer (layer thickness 70 nm) and a p-side guide layer (2) 16B which is an undoped GaN layer (layer thickness 180 nm).
  • the p-side guide layer 16 is an undoped layer in consideration of the light absorption by the dopant (Mg: magnesium, etc.), but it may be doped to obtain good electrical conductivity.
  • the In composition and layer thickness of the p-side guide layer (1) 16A can be appropriately selected to adjust the electric field distribution in the oscillation operation mode.
  • the electron barrier layer (EBL) 17 is a magnesium (Mg)-doped p-type Al 0.2 Ga 0.8 N layer having a thickness of, for example, 15 nm.
  • the p-cladding layer 18 is an Mg-doped p-Al 0.06 Ga 0.94 N layer, and has a thickness of, for example, 600 nm.
  • the Al composition of the p-cladding layer 18 is preferably selected so that the refractive index is smaller than that of the p-side guide layer 16.
  • the p-cladding layer 18 functions as a first p-cladding layer.
  • the p-contact layer 19 is a Mg-doped p-GaN layer, and has a thickness of, for example, 20 nm.
  • the carrier density of the p-contact layer 19 is set to a concentration that allows for ohmic junction with the transparent electrode 29, which is a transparent conductive layer provided on the surface of the p-contact layer.
  • p-type GaN p-type or undoped InGaN may be used.
  • a layer in which a GaN layer and an InGaN layer are stacked may be used.
  • the layer consisting of the p-side guide layer 16, the electron barrier layer 17, the p-cladding layer 18 and the p-contact layer 19 is also referred to as the second semiconductor layer.
  • n-side and p-side do not necessarily mean n-type and p-type.
  • the n-side guide layer means a guide layer provided on the n-side of the active layer, and may be an undoped layer (or i-layer).
  • the n-cladding layer 13 may be composed of multiple layers rather than a single layer, in which case not all layers need to be n-layers (n-doped layers) and may include undoped layers (i-layers). The same applies to the p-side guide layer 16 and p-cladding layer 18.
  • a p-electrode 20B (second electrode) is formed as a translucent electrode/Ag/Au layer in which a translucent electrode 29 (not shown), a silver (Ag) layer, and a gold (Au) layer are laminated in this order. That is, the p-electrode 20B functions as a light reflecting layer, and the interface between the translucent electrode 29 and the Ag layer of the p-electrode 20B is a reflecting surface SR.
  • the reflecting surface SR is provided in parallel with the hole layer 14P.
  • the p-electrode 20B has a circular shape with a diameter RA centered on the central axis CX of the void formation region 14R.
  • Pd, Al, Al alloys, etc. may also be used as the p-electrode 20B.
  • a pad electrode, etc. may also be provided on the p-electrode 20B.
  • the translucent electrode 29 is formed of a translucent conductor, for example, indium tin oxide (ITO). Note that the translucent electrode 29 is not limited to ITO, and other translucent conductors such as zinc tin oxide (ZTO), GZO (ZnO:Ga), and AZO (ZnO:Al) can be used.
  • ITO indium tin oxide
  • ZTO zinc tin oxide
  • GZO ZnO:Ga
  • AZO ZnO:Al
  • the side and upper surfaces of the semiconductor structure layer 11 and the side surfaces of the p-electrode 20B are covered with an insulating film 21 such as SiO 2.
  • the insulating film 21 is formed so as to run onto the p-electrode 20B and cover the edge of the upper surface of the p-electrode 20B.
  • the insulating film 21 also functions as a protective film, protecting the aluminum (Al)-containing crystal layer constituting the PCSEL element 10 from corrosive gases, etc. It also prevents short circuits caused by adhesions or solder creeping up during mounting, contributing to improved reliability and yield.
  • the material of the insulating film 21 is not limited to SiO2 , but may be ZrO2 , HfO2, TiO2 , Al2O3 , SiNx , etc.
  • a circular cathode electrode 20A (first electrode) is formed on the back surface of the element substrate 12 (see FIG. 2C).
  • an anti-reflective (AR) coating layer 27 is formed on the inside of the cathode electrode 20A.
  • the cathode electrode 20A is made of Ti/Au and is in ohmic contact with the element substrate 12.
  • the electrode material can be selected from Ti/Al, Ti/Rh, Ti/Al/Pt/Au, Ti/Pt/Au, etc.
  • the light emitted from the active layer 15 is diffracted by the air hole layer (PC layer) 14P.
  • the light is diffracted by the air hole layer 14P (diffraction surface WS), and the light emitted directly from the air hole layer 14P (direct diffracted light Ld: first diffracted light) and the light emitted by the diffraction of the air hole layer 14P and reflected by the reflection surface SR (reflected diffracted light Lr: second diffracted light) are emitted to the outside from the light emission region 20L (Fig. 2C) of the rear surface (emission surface) 12R of the element substrate 12.
  • the voids 14K are arranged periodically within, for example, a rectangular void-forming region 14R.
  • the anode region RA is formed so as to be contained within the void-forming region 14R.
  • the cathode electrode 20A is provided as a ring-shaped electrode on the outside of the p-electrode 20B so as not to overlap with the p-electrode 20B when viewed from a direction perpendicular to the void layer 14P.
  • the area inside the cathode electrode 20A is the light emission area 20L.
  • a bonding pad 20C is provided that is electrically connected to the cathode electrode 20A and connects a wire for power supply from an external source.
  • MOVPE Metalorganic Vapor Phase Epitaxy
  • FIG. 3 is a flowchart showing a manufacturing method of the PCSEL device 10. Below, with reference to Fig. 3, a detailed description will be given of the process of manufacturing the PCSEL device 10 by forming air holes in the air hole layer by performing filling growth in the recesses (holes), and then growing the active layer and the p-side guide layer.
  • FIG. 4 is a cross-sectional view that shows a schematic cross section of the n-side guide layer 14 in steps S0 to S3 of forming the buried layer 14B. Note that for ease of explanation and understanding, FIG. 4 illustrates the case where the hole layer 14P is a single-lattice photonic crystal layer, but a multiple-lattice photonic crystal layer can also be formed in the same manner.
  • Step S0 Formation of holes
  • an n-type Al 0.04 Ga 0.96 N layer with an Al composition of 4% was grown as the n-clad layer 13 on the element substrate 12.
  • a hole formation preparation layer 14E which is an n-type GaN layer was grown on the n-clad layer 13.
  • This hole formation preparation layer 14E is a preparation layer for forming the lower guide layer 14A and the hole layer 14P including the holes 14K.
  • the hole formation preparation layer 14E has a surface (upper surface) consisting of a flat (0001) plane.
  • the substrate was removed from the chamber of the MOVPE device, and fine recesses (holes) were formed on the surface of the growth layer. After obtaining a clean surface by washing, a silicon nitride film (SiN x ) was formed by plasma CVD. A resist for electron beam lithography was applied thereon, and the substrate was placed in an electron beam lithography device to perform patterning of a two-dimensional periodic structure.
  • SiN x silicon nitride film
  • FIG. 5 is a plan view showing the main opening K1 and sub-opening K2 of the resist, and the main hole 14H1 and sub-hole 14H2 after etching.
  • a pattern was performed in which pairs of openings, each consisting of an oval-shaped main opening K1 and a sub-opening K2 that is smaller than the main opening K1, were two-dimensionally arranged in the plane of the resist in a square lattice pattern with a period PK.
  • the openings are shown with hatching.
  • the main openings K1 have their centers of gravity CD1 arranged two-dimensionally on the lattice points of a square lattice with period PK in two mutually orthogonal directions (x direction and y direction).
  • the sub-openings K2 have their centers of gravity CD2 arranged two-dimensionally on the lattice points of a square lattice with period PK in the x direction and y direction.
  • the major axes of the main opening K1 and the sub-opening K2 are parallel to the ⁇ 11-20> crystal orientation, and the minor axes of the main opening K1 and the sub-opening K2 are parallel to the ⁇ 1-100> crystal orientation.
  • the center of gravity CD2 of the sub-opening K2 is spaced apart from the center of gravity CD1 of the main opening K1 by ⁇ x and ⁇ y.
  • ⁇ x ⁇ y.
  • the center of gravity CD2 of the sub-opening K2 is spaced apart from the center of gravity CD1 of the main opening K1 in the ⁇ 1-100> direction.
  • the SiN x film was selectively dry etched by an ICP-RIE (Inductive Coupled Plasma - Reactive Ion Etching) device.
  • ICP-RIE Inductive Coupled Plasma - Reactive Ion Etching
  • the resist was removed, and recesses (holes) were formed in the GaN surface using the patterned SiN x film as a hard mask.
  • the GaN was dry-etched in the depth direction using a chlorine-based gas and argon gas in an ICP-RIE apparatus, to form a main hole 14H1 and a sub-hole 14H2, which are oblong cylindrical recesses dug vertically in the GaN surface.
  • holes 14H the recesses dug in the surface portion of the hole formation preparation layer 14E (GaN) by the above etching are simply referred to as holes to distinguish them from the air holes in the vacancy layer 14P.
  • holes 14H the holes 14H.
  • the shape of the hole 14H is not limited to an elongated cylinder, but may be cylindrical, polygonal, etc.
  • holes 14H were formed in the hole formation preparation layer 14E, and a hole formation layer 14J was formed (FIG. 4, S0).
  • Step S1 Hole Closure - First Filling Growth
  • the substrate (FIG. 4, SO) in which the hole 14H was formed was cleaned, and then it was introduced again into the reactor of the MOVPE apparatus to perform recrystallization growth. Specifically, ammonia (NH 3 ) and trimethylgallium (TMG) were supplied to perform the first filling growth by facet growth, and the opening of the hole 14H was closed.
  • NH 3 ammonia
  • TMG trimethylgallium
  • the first embedding growth was performed at a first temperature (920°C) at which the shape of hole 14H was transformed by mass transport into a shape composed of thermally stable surfaces.
  • N atoms are attached to the top surface of the growth substrate, so that N-polar faces are selectively grown. Therefore, as shown in FIG. 4, a crystal whose surface is a ⁇ 1-101 ⁇ facet is selectively grown.
  • the hole 14H is blocked and filled (facet growth). This first filling growth by facet growth is performed, and a vacancy 14K is formed corresponding to the hole 14H.
  • the hole formation layer 14J GaN layer
  • the buried layer 14B is formed is indicated by a dashed line.
  • Step S2 Planarization Filling-Second Filling Growth
  • the hole 14H was closed by facet growth, and then the second filling layer 14B2 having a thickness D2 of 50 nm was grown.
  • the second filling layer 14B2 was grown by raising the substrate temperature (growth temperature) to 1050° C. (second filling temperature) and then supplying triethylgallium (TEG) and NH 3.
  • the second filling temperature was higher than the first filling temperature.
  • the second filling layer 14B2 can be grown so that its growth surface becomes the (0001) plane, the temperature relationship between the second filling temperature and the first filling temperature may be reversed.
  • a thermal effect causes mass transport, which causes a second buried growth (planarized buried growth) to form a second buried layer 14B2 with a (0001) surface.
  • the first buried growth and second buried growth form a buried layer 14B.
  • the layer from the top surface of the void layer 14P (the surface closer to the active layer 15) to the top surface 14JS of the hole-forming layer 14J (including a part of the hole-forming layer 14J) is referred to as the first buried layer 14B1
  • the layer from the top surface 14JS of the hole-forming layer 14J to the flat surface formed by the second buried growth is referred to as the second buried layer 14B2 (see FIG. 4, S3).
  • the entire semiconductor layer from the top surface of the void layer 14P to the top surface of the second buried layer 14B2 (including a portion of the hole-forming layer 14J) is referred to as the buried layer 14B.
  • the thickness of the first buried layer 14B1 is defined as D1
  • the “upper surface” of each semiconductor layer of the n-side guide layer (first guide layer) 14 refers to the surface on the side closer to the active layer 15 .
  • GaN is used for the second buried growth.
  • the second buried layer 14B2 also functions as a light distribution adjustment layer to adjust the coupling efficiency (light field) between the light and the hole layer 14P.
  • undoped GaN is used for the first buried growth and the second buried growth.
  • the first buried growth and the second buried growth are not limited to GaN, and n-GaN, n-InGaN, undoped GaN, undoped InGaN, or a combination of these semiconductors can also be used.
  • Step S3 Etching by H2 Annealing
  • H2 hydrogen
  • Fig. 5 shows the case where the second buried layer 14B2 was etched flat from its surface by a thickness TE.
  • the (0001) plane is a thermally stable plane, and the buried layer 14B can be etched and thinned while maintaining the flatness of the surface. Therefore, a high-quality active layer with high flatness can be grown on the buried layer 14B.
  • the annealing atmosphere may contain group III and group V materials.
  • the H 2 annealing of the III-nitride semiconductor is preferably carried out in the temperature range of 900-1100°C.
  • an inert gas such as N2 gas may be appropriately mixed into H2 as the atmospheric gas.
  • the etching rate can be controlled by controlling the partial pressure of the gas.
  • Step S4 Recrystallization Growth Next, on the substrate on which the etching of the buried layer 14B was performed, crystal growth was further performed on the layer above the light distribution adjustment layer 23 in the reactor.
  • the light distribution-adjusting layer 23 is grown on the second buried layer 14B2.
  • the light distribution-adjusting layer 23 is an undoped In 0.03 Ga 0.97 N layer, and is a semiconductor layer (heterogeneous semiconductor layer) having a different crystal composition from the buried layer 14B (GaN layer).
  • the active layer 15, the p-side guide layer (second guide layer) 16, the electron barrier layer (EBL) 17, the p-cladding layer 18, and the p-contact layer 19 were grown in sequence on the light distribution adjustment layer 23.
  • the PCSEL element 10 was fabricated.
  • the above-mentioned filling process formed a double lattice structure hole layer 14P in which holes 14K consisting of pairs of main holes 14K1 and sub-holes 14K2 are arranged two-dimensionally at each of the square lattice points.
  • the sub-holes 14K2 have a smaller hole diameter and height than the main holes 14K1.
  • the upper surface of the holes 14K in the hole layer 14P of the multiple lattice structure means the upper surface of the main holes 14K1 or the sub-holes 14K2 that is closer to the upper layer (active layer) (i.e., the hole has a shallower upper surface).
  • the holes 14K may be a single lattice structure in which holes of the same size are arranged two-dimensionally at each of the square lattice points, instead of the main holes 14K1 and sub-holes 14K2 having different sizes.
  • FIG. 6 is a schematic diagram showing a cross section of the formed vacancy layer 14P perpendicular to the central axis CX.
  • the inner surface of hole 14H changes shape to a (1-100) plane (i.e., an m-plane). That is, the shape changes from an oval cylindrical shape to an oval hexagonal prism-shaped hole 14K whose side surface is made up of an m-plane.
  • the formed primary void 14K1 had a long hexagonal prism shape with a long diameter of 72.5 nm and a short diameter of 43.5 nm, and a long diameter/short diameter ratio of 1.67.
  • the secondary void 14K2 had a long diameter of 44.6 nm and a short diameter of 38.3 nm, and a long diameter/short diameter ratio of 1.16, and had a long hexagonal prism shape closer to a regular hexagonal prism than the primary void 14K1.
  • the void filling rate is the ratio of the area occupied by each void per unit area in a two-dimensional regular array. Specifically, when the areas of the main voids 14K1 and the sub-voids 14K2 in the void layer 14P are S1 and S2, respectively, the void filling rates FF1 and FF2 of the main voids 14K1 and the sub-voids 14K2 are given by the following formulas.
  • FIGS. 7A to 7C are SEM images of the cross section of the wafer when the etching time is (i) 5 minutes, (ii) 20 minutes, and (iii) 50 minutes, respectively.
  • D is the thickness of the buried layer 14B after etching (i.e., the total thickness of the first buried layer 14B1 and the second buried layer 14B2 after etching)
  • DE is the layer thickness of the second buried layer 14B2 after etching.
  • the cross section of the hole formation layer 14J is observed with slight shading.
  • the semiconductor layers of the buried layer 14B, the active layer 15, and the light distribution adjustment layer 23 are indicated by their respective reference numerals.
  • Figure 8 shows an AFM image of the surface of the active layer 15.
  • the surface roughness increases with increasing etching time.
  • the etching time is 50 minutes or longer, i.e., when the DE is less than 2 nm, the surface roughness is large, and it is not possible to obtain an active layer with good crystal quality on such a surface.
  • the reason why the surface roughness occurs when the etching time by H2 annealing is long is because a large amount of Si is deposited on the surface of the hole formation layer 14J in which the holes 14H are formed. More specifically, the Si is deposited by the hard mask (SiN film, etc.) used when forming the holes 14H and siloxane in the atmosphere adhering to the surface of the hole formation layer 14J.
  • Si reacts with N on the semiconductor (GaN) surface to form SiN. Since SiN forms an inversion domain on the GaN surface, the polarity of the GaN layer is locally inverted, causing significant surface roughness during shape change due to mass transport. According to FIG. 8, it can be seen that the surface roughness caused by the inversion domain generated on the semiconductor (GaN) surface appears on the upper surface of the active layer 15 even after the active layer is formed.
  • Figures 9A and 9B show the results of measuring the surface roughness (surface height) along the M-M line (see Figure 8) in an area of 20 ⁇ m x 20 ⁇ m for etching times of (ii) 20 minutes and (iii) 50 minutes, respectively.
  • the etching time is (ii) 20 minutes, the surface condition of the active layer 15 is not rough enough to affect the threshold current.
  • the etching time is (iii) 50 minutes, the surface roughness of the active layer 15 is significant, making it difficult to grow an active layer of good quality.
  • Figure 10 shows the measured surface roughness Ra of a 20 ⁇ m x 20 ⁇ m area when the layer thickness DE of the second buried layer 14B2 after etching is changed.
  • the layer thickness at which the surface roughness Ra changes critically with respect to the layer thickness DE of the second buried layer 14B2 is indicated by an arrow.
  • the surface roughness Ra is less than 1.0 nm at most, whereas when the layer thickness DE is less than 2 nm, the surface roughness increases significantly, making it difficult to grow an active layer with good crystal quality.
  • the distance between the active layer 15 and the air hole layer 14P i.e., the distance between the upper surface of the air hole 14K in the air hole layer 14P and the active layer 15, is 200 nm or less. In terms of obtaining high coupling efficiency, it is even more preferable that the distance between the upper surface of the air hole 14K in the air hole layer 14P and the active layer 15 is 150 nm or less.
  • the distance between the upper surface of the void 14K and the active layer 15 refers to the distance between the upper surface of the void 14K and the first quantum well layer (i.e., the quantum well layer closest to the void layer 14P).
  • the present invention it is possible to increase the resonance effect by bringing the air hole layer and the active layer into close proximity, and it is possible to provide a manufacturing method for a photonic crystal surface-emitting laser element having a high-quality active layer, low threshold and high efficiency, and a photonic crystal surface-emitting laser element.
  • the present invention has been exemplified with a photonic crystal layer (hole layer) in which the holes have a hexagonal columnar shape, it can also be applied to cases in which the holes in the photonic crystal layer have an irregular columnar shape, such as a cylindrical, rectangular, polygonal, or teardrop shape.

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JP2009094210A (ja) * 2007-10-05 2009-04-30 Hitachi Ltd 半導体装置
JP2019114663A (ja) * 2017-12-22 2019-07-11 国立大学法人京都大学 面発光レーザ素子及び面発光レーザ素子の製造方法
JP2020038892A (ja) * 2018-09-03 2020-03-12 国立大学法人京都大学 面発光レーザ素子及び面発光レーザ素子の製造方法
WO2021186965A1 (ja) * 2020-03-16 2021-09-23 国立大学法人京都大学 面発光レーザ素子及び面発光レーザ素子の製造方法

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JP2009094210A (ja) * 2007-10-05 2009-04-30 Hitachi Ltd 半導体装置
JP2019114663A (ja) * 2017-12-22 2019-07-11 国立大学法人京都大学 面発光レーザ素子及び面発光レーザ素子の製造方法
JP2020038892A (ja) * 2018-09-03 2020-03-12 国立大学法人京都大学 面発光レーザ素子及び面発光レーザ素子の製造方法
WO2021186965A1 (ja) * 2020-03-16 2021-09-23 国立大学法人京都大学 面発光レーザ素子及び面発光レーザ素子の製造方法

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