WO2024194749A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024194749A1
WO2024194749A1 PCT/IB2024/052440 IB2024052440W WO2024194749A1 WO 2024194749 A1 WO2024194749 A1 WO 2024194749A1 IB 2024052440 W IB2024052440 W IB 2024052440W WO 2024194749 A1 WO2024194749 A1 WO 2024194749A1
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Prior art keywords
transistor
conductor
insulator
oxide
element layer
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
松嵜隆徳
岡本佑樹
國武寛司
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2025507887A priority Critical patent/JPWO2024194749A1/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • One aspect of the present invention relates to a semiconductor device, etc.
  • one aspect of the present invention is not limited to the above technical field.
  • the technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device (memory device), a driving method thereof, or a manufacturing method thereof.
  • the CPU Central Processing Unit
  • the CPU executes a series of processes by sequentially executing operations according to the programs (data) stored in memory.
  • the data required for the processes is also stored in memory. Therefore, the speed at which the CPU accesses memory or the power consumption greatly affects the CPU's computing power or power consumption.
  • a configuration that allows equal access to data in all memories is highly versatile, but it slows down the speed at which the CPU accesses memory, resulting in reduced computing power and increased power consumption. For this reason, a hierarchical memory configuration is common, in which, in order of proximity to the CPU, cache memory made up of SRAM etc., main storage device made up of DRAM etc., auxiliary storage device such as flash memory or hard disk etc. are arranged.
  • the main memory operates slower than the cache memory, but has a larger storage capacity (also called memory capacity).
  • the auxiliary memory operates even slower than the main memory, but has a larger storage capacity.
  • the CPU basically accesses the cache memory, but if the desired data is not stored in the cache memory, it accesses the main memory, copies the data to the cache memory, and then accesses the data again. Furthermore, if the desired data is not stored in the main memory, it accesses the auxiliary memory, copies the data to the main memory and cache memory, and then accesses the data again.
  • the cache memory in a hierarchical structure, i.e., arranging the primary cache memory (primary cache, L1 cache), secondary cache memory (secondary cache, L2 cache), tertiary cache memory (tertiary cache, L3 cache), etc. in order of proximity to the CPU.
  • primary cache memory primary cache, L1 cache
  • secondary cache memory secondary cache, L2 cache
  • tertiary cache memory tertiary cache, L3 cache
  • Patent Document 1 discloses a configuration in which a memory unit using a transistor including an oxide semiconductor in its semiconductor layer is applied to a register, a cache memory, or a main memory device.
  • a transistor including an oxide semiconductor in its semiconductor layer has a characteristic of having an extremely small off-state current. Therefore, by applying the transistor to a memory unit such as a register, a cache memory, or a main memory device, stored data can be retained for a long time.
  • problems of one embodiment of the present invention are not limited to the problems listed above.
  • the problems listed above do not preclude the existence of other problems.
  • the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and/or other problems.
  • One aspect of the present invention is a semiconductor device having a first element layer, a second element layer, and a third element layer, the second element layer being stacked on the first element layer, the third element layer being stacked on the second element layer, a first memory unit being provided in the second element layer, and a second memory unit being provided in the third element layer, the first element layer having a first sense amplifier circuit electrically connected to the first memory unit and a second sense amplifier circuit electrically connected to the second memory unit, the first sense amplifier circuit and the second sense amplifier circuit each having a first transistor having a first semiconductor layer having silicon in a channel formation region, the first memory unit and the second memory unit each having a second transistor having a second semiconductor layer having an oxide semiconductor in a channel formation region, and the third element layer in which the second memory unit is provided is a semiconductor device in which a plurality of element layers are stacked.
  • One aspect of the present invention is a semiconductor device having a first element layer, a second element layer, and a third element layer, the second element layer being stacked on the first element layer, the third element layer being stacked on the second element layer, a first memory unit being provided in the second element layer, and a second memory unit being provided in the third element layer, the first element layer having a first sense amplifier circuit electrically connected to the first memory unit and a second sense amplifier circuit electrically connected to the second memory unit, the first sense amplifier circuit and the second sense amplifier circuit each having a first transistor having a first semiconductor layer having silicon in a channel formation region, the first memory unit having a second transistor having a second semiconductor layer having an oxide semiconductor in a channel formation region, the second memory unit having a third transistor having a third semiconductor layer having an oxide semiconductor in a channel formation region, and the third element layer in which the second memory unit is provided is a semiconductor device in which a plurality of element layers are stacked.
  • the oxide semiconductor is preferably a semiconductor device having at least In.
  • the first memory unit is preferably a semiconductor device that has the functionality of a cache memory for the arithmetic unit.
  • the semiconductor device is preferably such that the second transistor is a vertical transistor.
  • the semiconductor device is preferably such that the second transistor has a first gate electrode and a second gate electrode, the first gate electrode is provided with a signal for controlling the on/off state of the second transistor, and the second gate electrode is provided with a potential for controlling the electrical characteristics of the second transistor.
  • the semiconductor device is preferably such that the second transistor is a planar transistor and the third transistor is a vertical transistor.
  • a semiconductor device is preferably provided with switching circuits between the first memory unit and the first sense amplifier circuit, and between the second memory unit and the second sense amplifier circuit.
  • One aspect of the present invention can provide a novel semiconductor device, etc.
  • one aspect of the present invention can provide a semiconductor device that is excellent in terms of improved computing power, reduced power consumption, improved operating speed, miniaturization, or improved memory capacity.
  • FIG. 1A and 1B are schematic diagrams illustrating a configuration example of a semiconductor device.
  • FIG. 2 is a schematic diagram illustrating an example of the configuration of a semiconductor device.
  • FIG. 3 is a schematic diagram illustrating a configuration example of a semiconductor device.
  • 4A and 4B are schematic diagrams illustrating a configuration example of a semiconductor device.
  • FIG. 5 is a schematic diagram illustrating a configuration example of a semiconductor device.
  • FIG. 6 is a diagram illustrating an example of the configuration of a semiconductor device.
  • 7A and 7B are schematic diagrams illustrating a configuration example of a semiconductor device.
  • 8A to 8H are schematic diagrams illustrating configuration examples of a semiconductor device.
  • FIG. 9 is a schematic diagram illustrating a configuration example of a semiconductor device.
  • FIG. 9 is a schematic diagram illustrating a configuration example of a semiconductor device.
  • FIG. 10 is a schematic diagram illustrating a configuration example of a semiconductor device.
  • FIG. 11 is a block diagram illustrating an example of the configuration of a semiconductor device.
  • FIG. 12 is a schematic diagram illustrating a configuration example of a semiconductor device.
  • FIG. 13 is a schematic diagram illustrating a configuration example of a semiconductor device.
  • 14A to 14D are circuit diagrams illustrating configuration examples of a semiconductor device.
  • FIG. 15 is a circuit diagram illustrating an example of the configuration of a semiconductor device.
  • FIG. 16 is a cross-sectional view illustrating an example of the configuration of a semiconductor device.
  • 17A to 17C are cross-sectional views illustrating examples of the configuration of a semiconductor device.
  • Fig. 18A is a diagram illustrating a configuration example of a semiconductor device, and Fig.
  • FIG. 18B is a diagram illustrating an equivalent circuit of the semiconductor device.
  • FIG. 19 is a diagram illustrating a configuration example of a semiconductor device.
  • Fig. 20A is a diagram illustrating a configuration example of a semiconductor device, and
  • Fig. 20B is a diagram illustrating an equivalent circuit of the semiconductor device.
  • FIG. 21 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device.
  • 22A to 22C are plan views showing configuration examples of transistors included in a semiconductor device, and
  • FIG. 22D is a cross-sectional view showing the configuration example of a transistor included in the semiconductor device.
  • FIG. 23A is a plan view showing a configuration example of a transistor included in a semiconductor device, and FIG.
  • FIG. 23B is a cross-sectional view showing the configuration example of a transistor included in the semiconductor device.
  • FIG. 24 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device.
  • 25A and 25B are diagrams illustrating an example of an electronic component.
  • 26A and 26B are diagrams for explaining an example of an electronic device, and
  • Fig. 26C to Fig. 26E are diagrams for explaining an example of a mainframe computer.
  • FIG. 27 is a diagram illustrating an example of space equipment.
  • FIG. 28 is a diagram illustrating an example of a storage system that can be applied to a data center.
  • FIG. 29A is a schematic top view of a memory device according to an embodiment, and FIGS. 29B and 29C are perspective views of the memory device.
  • FIG. 30A is a 3D image of a memory device according to an embodiment
  • FIGS. 30B to 30D are cross-sectional SEM images of the memory device.
  • FIG. 31 shows electrical characteristics of the vertical transistor according to the example.
  • 32A and 32B are diagrams for explaining the operating speed of a semiconductor device according to an embodiment.
  • the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state).
  • the off-state refers to a state in which the voltage Vgs between the gate and the source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).
  • metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a transistor is referred to as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
  • the semiconductor device is a device that utilizes semiconductor characteristics, and is a circuit including a semiconductor element (a transistor, a diode, a photodiode, or the like) or a device having the same circuit.
  • the semiconductor device described in this embodiment has a function as an arithmetic device having a memory portion using a transistor with extremely low off-state current.
  • FIGS. 1A and 1B are schematic diagrams of a semiconductor device 10 described in this embodiment.
  • FIG. 1B is also a schematic diagram of a semiconductor device 10 described in this embodiment.
  • the direction perpendicular or approximately perpendicular to the surface of the element layer 20 is defined as the Z-axis direction.
  • the Z-axis direction may be referred to as the direction perpendicular to the surface of the element layer 20 in the specification.
  • approximately perpendicular refers to a state in which the elements are arranged at an angle of 85 degrees or more and 95 degrees or less.
  • the X direction, Y direction, and Z direction may be defined to explain the arrangement of each element.
  • the X direction, Y direction, and Z direction are defined to explain the arrangement of each element constituting semiconductor device 10.
  • the X direction, Y direction, and Z direction are perpendicular or approximately perpendicular to each other.
  • the semiconductor device 10 shown in Figures 1A and 1B has an element layer 20, an element layer 30 provided on the element layer 20, and an n-layer element layer 40 (n is an integer of 2 or more) provided on the element layer 30.
  • the element layer is a layer in which semiconductor elements such as transistors or capacitors are provided.
  • the element layer 20 has sense amplifier circuits 21 and 22.
  • the element layer 20 has transistors (Si transistors) having silicon in a semiconductor layer having a channel formation region.
  • the element layer 20 is an element layer in which a semiconductor layer having a channel formation region is provided in a silicon substrate, or an element layer in which a silicon semiconductor layer having a channel formation region is bonded to a silicon substrate.
  • a silicon substrate refers to a substrate that uses silicon as a semiconductor material, for example, a substrate made of single crystal silicon. It is not limited to silicon, and materials containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. may also be used for the substrate.
  • the Si transistors in the element layer 20 are made of silicon with high crystallinity, such as single crystal silicon or polycrystalline silicon. By using silicon with high crystallinity, the element layer 20 can achieve high field effect mobility, enabling faster operation. Therefore, in addition to the sense amplifier circuits 21 and 22, the element layer 20 can be provided with an arithmetic unit, peripheral circuits, etc.
  • the calculation unit that can be provided in the element layer 20 has the function of performing general-purpose processing such as running an operating system, controlling data, performing various calculations, and executing programs, like a CPU (Central Processing Unit) or GPU (Graphics Processing Unit).
  • the element layer 20 in which the calculation unit is provided is provided with a memory unit such as a register for holding data used in the calculation unit.
  • a calculation unit when a calculation unit is provided in the element layer 20, it is effective to configure the memory in a hierarchical manner in order to improve the calculation capacity and reduce power consumption. In this case, it is effective to configure a primary cache memory (primary cache, L1 cache), secondary cache memory (secondary cache, L2 cache), and tertiary cache memory (tertiary cache, L3 cache) within or around the calculation unit.
  • primary cache memory primary cache, L1 cache
  • secondary cache memory secondary cache, L2 cache
  • tertiary cache memory tertiary cache, L3 cache
  • the sense amplifier circuit 21 provided in the element layer 20 is a circuit for writing or reading data from the memory cells 34 of the memory unit 33 provided in the element layer 30.
  • the sense amplifier circuit 22 provided in the element layer 20 is a circuit for writing or reading data from the memory cells 44 of the memory unit 43 provided in the element layer 40.
  • the sense amplifier circuits 21 and 22 are provided in the element layer 20, enabling high-speed data writing or reading operations.
  • the element layer 30 has a transistor having an oxide semiconductor (OS transistor) in a semiconductor layer having a channel formation region.
  • the element layer 30 having the OS transistor can be stacked on the element layer 20.
  • the element layer 30 is illustrated as being stacked on the element layer 20.
  • the element layer 40 has an OS transistor, similar to the element layer 30.
  • the element layer 40 having the OS transistor can be stacked on the element layer 30.
  • an n-layer element layer 40 is illustrated stacked on the element layer 30.
  • metal oxides used in OS transistors include indium oxide (In oxide), gallium oxide (Ga oxide), and zinc oxide (Zn oxide).
  • the metal oxide used in OS transistors can be In-Zn oxide.
  • the metal oxide preferably has two or three elements selected from indium, element M, and zinc.
  • element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.
  • an oxide containing indium (In), gallium (Ga), and zinc (Zn) also referred to as IGZO
  • it is preferable to use an oxide containing indium (In), aluminum (Al), and zinc (Zn) also referred to as IAZO).
  • an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) also referred to as IAGZO
  • an oxide containing indium (In), gallium (Ga), zinc (Zn), and tin (Sn) also referred to as IGZTO
  • the metal oxide is an In-Zn oxide
  • In-Zn oxide may also contain a trace amount of element M.
  • the metal oxide used in the OS transistor can be a metal oxide layer having two or more layers with different compositions.
  • a laminate structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO may be used.
  • the metal oxide used in the OS transistor is preferably crystalline.
  • crystalline oxide semiconductors include CAAC (c-axis-aligned crystalline)-OS and nc (nanocrystalline)-OS.
  • CAAC c-axis-aligned crystalline
  • nc nanocrystalline
  • the OS transistor is preferably a vertical transistor in which the source electrode and the drain electrode are located at different heights.
  • a current flows in the height direction (Z direction) in the channel formation region of the semiconductor layer.
  • the channel length direction has a height direction (vertical direction) component. Therefore, the above-mentioned vertical transistor can also be called a VFET (Vertical Field Effect Transistor), a vertical channel transistor, a vertical channel transistor, or a vertical transistor.
  • VFET Vertical Field Effect Transistor
  • Vertical transistors have a structure in which the source region, the channel formation region, and the drain region can at least partially overlap when viewed from above, so that the area they occupy (also called the footprint) can be made small.
  • the structure allows the channel length to be small and the channel width to be large, the on-resistance can be made small (the on-current can be made large).
  • vertical transistors can increase the memory density compared to horizontal transistors (also called planar structure or planar type) in which the source electrode and the drain electrode are located at the same height.
  • Vertical transistors have a smaller occupied area (also called footprint), so that the memory density can be increased in the upper element layer.
  • a configuration in which vertical transistors are applied to the OS transistors of the element layer 40 is particularly effective.
  • a hierarchical configuration can be formed on the element layer 20 in which the register and the cache memory composed of Si transistors are provided, with the memory density being different in ascending order of proximity to the element layer 20.
  • a hierarchical configuration can be formed with the memory density being different in ascending order of proximity to the element layer 20.
  • the element layer 30 has a memory section 33 in which a memory cell 34 having an OS transistor is provided.
  • the element layer 40 has a memory section 43 in which a memory cell 44 having an OS transistor is provided. Note that the element layer 40 is located at a greater distance from the element layer 20, from which data is read, than the element layer 30. Therefore, the element layer 40 may have an amplifier circuit for amplifying data read from the element layer 40, in addition to the memory section 43 in which the memory cell 44 is provided.
  • the circuit configuration of the memory cells 34 provided in the storage unit 33 may be different from the circuit configuration of the memory cells 44 provided in the storage unit 43. This configuration allows a hierarchical configuration on the element layer 20 with different operating speeds in ascending order of distance from the element layer 20. For example, a circuit configuration different from that of the memory cells 34 provided in the storage unit 33 can be applied to the memory cells 44 provided in the storage unit 43. Alternatively, the transistor configuration of the memory cells 34 provided in the storage unit 33 may be different from that of the memory cells 44 provided in the storage unit 43. For example, the transistors of the memory cells 34 provided in the storage unit 33 can have a backgate electrode, and the transistors of the memory cells 44 provided in the storage unit 43 can have no backgate electrode.
  • the memory cells 44 provided in the memory unit 43 can be stacked across multiple layers. In this case, the same circuit configuration can be used across multiple layers of the element layer 40. This configuration allows a manufacturing process using the same photomask to be used for multiple element layers. Therefore, the memory unit 43 can be manufactured using the same manufacturing process repeatedly in the vertical direction, which reduces manufacturing costs.
  • the memory units 43 of the element layers 40 fabricated on the element layer 30 can also be designed to have different wiring intervals or transistor sizes for each of the multiple element layers 40.
  • the specifications of the memory units 43 such as the operating speed, can be made different for each of the multiple element layers 40, so that memory units 43 with the same area can have different memory capacities and operating speeds.
  • the memory unit 33 shown in FIG. 1A and FIG. 1B is configured to input and output data between the sense amplifier circuit 21 of the element layer 20.
  • the memory unit 33 is arranged so as to overlap with the region in the element layer 20 where the sense amplifier circuit 21 is provided, thereby shortening the wiring connecting the circuits, and thus improving the operating speed compared to the memory unit 43.
  • the memory unit 43 shown in FIG. 1A and FIG. 1B is configured to input and output data between the sense amplifier circuit 22 of the element layer 20.
  • the memory unit 43 is provided by extending the wiring through the region in the element layer 20 where the sense amplifier circuit 21 is provided and the element layer 30, so the wiring connecting the circuits becomes long. Therefore, the memory unit 43 has a slower operating speed than the memory unit 33.
  • the element layer 40 can be provided by stacking element layers on the element layer 30, so that the memory density (storage capacity per unit area) can be improved. Therefore, the memory unit 33 provided in the element layer 30 and the memory unit 43 provided in the element layer 40 can be made into a hierarchical memory unit.
  • the memory unit 33 which has excellent operating speed, can be used as a cache memory, for example, a fourth-level cache memory (fourth-level cache, L4 cache).
  • the memory unit 33 functioning as a cache memory can fill the performance gap between the L1 cache to the L3 cache and the main storage device.
  • the memory unit 33 which can be used as a large-capacity cache memory, above the element layer 20 in which the L1 cache to the L3 cache are provided, the frequency of access to the external storage device (main memory or auxiliary storage device) for data due to cache misses can be reduced, thereby improving power efficiency.
  • the cache located at the lowest level can be called an LLC (Last Level cache).
  • the memory unit 33 has a fast operating speed and can hold data for a long period of time, so it can be used suitably for an LLC.
  • the memory unit 33 can also be applied to an FLC (Final Level cache).
  • the memory unit 43 which is excellent for improving memory density, can also be used as a main memory. Having a memory unit 43 that can be provided on the element layer 30 having a memory unit 33 that functions as a cache memory, it is possible to reduce delays on buses and the like, and to bridge the performance gap between the L4 cache and an external storage device. By configuring a memory unit 43 that can be used as a large-capacity main memory above the element layer 30 where the L4 cache is provided, it is possible to reduce the frequency of accesses to the external storage device (main memory or auxiliary storage device) for data due to cache misses, thereby improving computing power and power efficiency.
  • main memory or auxiliary storage device main memory or auxiliary storage device
  • OS transistors have an extremely low off-state current. Therefore, charge corresponding to data written to memory cells 34 and 44 can be held in the capacitor for a long time. In other words, data once written in memory cells 34 and 44 can be held for a long time. This reduces the frequency of data refresh and reduces the power consumption of the semiconductor device 10 of one embodiment of the present invention.
  • OS memory a memory unit having a memory cell with an OS transistor
  • the storage units 33, 43 which are provided with memory cells 34, 44 having OS transistors, can be DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
  • DOSRAM refers to RAM having 1T (transistor) 1C (capacitance) type memory cells.
  • DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from the outside.
  • DOSRAM is a memory that utilizes the low off-current of OS transistors. Since DOSRAM is a 1T1C type memory cell, a large storage capacity can be realized in the storage units 33, 43. Furthermore, by using OS transistors, the data retention period can be increased compared to DRAM having Si transistors.
  • the Si transistors in DRAM have a higher off-current than OS transistors. Therefore, in order to reduce the off-current of Si transistors, the channel length needs to be increased. In order to ensure a long channel length in a limited area, it is effective to make the channel length long in the depth direction of the substrate, but in this case, it becomes difficult to make the substrate thin. In addition, the capacitance value of the capacitor needs to be increased to hold the charge. Therefore, the height of the capacitor needs to be increased, as in a trench (deep groove) structure. Therefore, in DRAM memory cells that have Si transistors, the cell size increases in the Z direction.
  • the off-current of the OS transistor in the DOSRAM is extremely low. Therefore, it is not necessary to increase the channel length in order to reduce the off-current.
  • the thickness of each element layer of the element layer 30 can be made thinner than that of the DRAM.
  • the capacitance of the capacitor can be estimated to be small.
  • a parallel plate type capacitor can be used instead of a trench type (deep groove type).
  • a parallel plate type capacitor is easier to manufacture than a trench type capacitor. Therefore, the yield is high and the number of manufacturing steps can be reduced.
  • Such a DOSRAM configuration that allows the element layer to be thin, has a high yield, and allows the number of manufacturing steps to be reduced is particularly effective when applied to the memory portion 43 of the element layer 40 of one embodiment of the present invention.
  • the memory units 33, 43 provided with memory cells 34, 44 having OS transistors can be NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory).
  • NOSRAM has memory cells that are two-transistor type (2T) or three-transistor type (3T) gain cells. NOSRAM rewrites data by charging and discharging a capacitor, so in principle there is no limit to the number of times it can be rewritten and it is low energy. Furthermore, NOSRAM can improve the data operation speed compared to DOSRAM. Therefore, NOSRAM is a memory that can operate at high speed, has low power consumption, and has high rewrite resistance compared to DOSRAM.
  • NOSRAM By storing data in three or more values, NOSRAM can store a larger amount of data per memory cell than DOSRAM. NOSRAM can also read written data non-destructively, making it suitable for long-term data retention. On the other hand, DOSRAM reads written data destructively, making it suitable for use in memory hierarchies that are accessed frequently.
  • OS transistors have better electrical characteristics than Si transistors in high-temperature environments. Specifically, even at high temperatures of 125° C. or higher and 150° C. or lower, the ratio of on current to off current is large, enabling good switching operation. Furthermore, OS transistors operate well in the temperature range of -40° C. or higher and 190° C. or lower. In other words, OS transistors have excellent heat resistance. This is a good heat resistance compared to the heat resistance of phase change memory (PCM) (-40°C to 150°C), resistance random access memory (ReRAM) (-40°C to 125°C), and magnetoresistive random access memory (MRAM) (-40°C to 105°C).
  • PCM phase change memory
  • ReRAM resistance random access memory
  • MRAM magnetoresistive random access memory
  • the memory units 33, 43 in which the memory cells 34, 44 are provided are stacked in a direction perpendicular or approximately perpendicular to the surface of the element layer 20.
  • the element layers 30, 40 are stacked in a direction perpendicular or approximately perpendicular to the surface of the substrate on which the element layer 20 is provided.
  • FIG. 2 is a schematic diagram illustrating wiring for writing or reading data between sense amplifier circuits 21 and 22 having memory cells 34 provided in element layer 20, memory unit 33 having memory cells 34 provided in element layer 30, and memory unit 43 having memory cells 44 provided in element layer 40 in the block diagrams of FIGS. 1A and 1B.
  • Memory unit 33 which has a faster operating speed than memory unit 43, is electrically connected to sense amplifier circuit 21 via wiring BL1.
  • Memory unit 43 which has a better memory density than memory unit 33, is electrically connected to sense amplifier circuit 22 via wiring BL2.
  • Wiring BL1 and BL2 function as bit lines for writing and reading data.
  • the wiring BL1, BL2 can be arranged in the horizontal and vertical directions on the substrate surface on which the element layer 20 is provided.
  • the wiring BL1, BL2 extending from the memory cells 34, 44 of the element layers 30, 40 with wiring arranged in the vertical direction in addition to wiring arranged in the horizontal direction on the substrate surface, the length of the wiring between the memory cell 34 and the sense amplifier circuit 21 and the length of the wiring between the memory cell 44 and the sense amplifier circuit 22 can be made different. Therefore, the signal propagation distance between the memory cell and the sense amplifier circuit can be made different between the memory units 33 and 43, and in addition to reducing power consumption and signal delays by significantly reducing the resistance and parasitic capacitance of the bit lines, the operating speed of the memory cells 34 and 44 can be made different.
  • Figure 3 is a block diagram showing the memory unit 43 having memory cells 44, the memory unit 33 having memory cells 34, and the sense amplifier circuits 21 and 22 of the element layer 20, element layer 30, and element layer 40 described above, as well as the arithmetic unit 25, register 26, L1 cache 27, L2 cache 28, and L3 cache 29 provided in the element layer 20.
  • Figure 3 also shows data Data input and output between each block.
  • FIG. 4A shows a hierarchy of the register 26, L1 cache 27, L2 cache 28, L3 cache 29, memory unit 33, memory unit 44, and memory unit 50 of the auxiliary storage device, which are arranged in order of operating speed and storage capacity.
  • the higher the layer the faster the operating speed and the smaller the storage capacity
  • the lower the layer the slower the operating speed and the larger the storage capacity.
  • the register 26 is provided within the arithmetic unit 25 as shown in FIG. 3 (illustrated as CPU (register)).
  • the L1 cache 27, L2 cache 28, and L3 cache 29 are provided in locations close to the arithmetic unit 25 as shown in FIG. 3 (illustrated as SRAM (Cache)).
  • the register 26 has a high operating speed and a small storage capacity.
  • the L1 cache 27, L2 cache 28, and L3 cache 29 are provided near the register 26, and have a relationship in which the operating speed is slowest, the L1 cache 27 is the fastest, and the L2 cache 28 is the fastest, and the L3 cache 29 is the largest.
  • the memory unit 33 is provided in the element layer 30 close to the element layer 20 in which the L3 cache 29 is provided (illustrated as OS memory (Cache)).
  • the memory unit 43 is provided in the element layer 40 close to the element layer 30 in which the memory unit 33 is provided (illustrated as OS memory (Main Memory)).
  • the memory unit 50 of the auxiliary storage device is a memory unit provided outside the semiconductor device 10. Examples of the auxiliary storage device include a flash memory, a hard disk drive, and a solid state drive, which are storage class memories.
  • the higher the hierarchical level of the memory unit the higher the speed of operation required. Also, the lower the hierarchical level of the memory unit, the higher the capacity and density (or the smaller the area per bit) required.
  • memory unit 33 is closer to the computation unit than memory unit 43, and is required to operate at a higher speed.
  • memory unit 43 is not required to operate at a higher speed than memory unit 33, but is required to have a larger capacity than memory unit 33 and a smaller area per bit than memory unit 33.
  • the semiconductor device provides a storage unit 33 that functions as a cache memory between the main memory and the L3 cache 29, thereby reducing the physical distance between the main memory and the L3 cache 29.
  • the semiconductor device also provides a storage unit 43 that functions as a main memory on the storage unit 33 that functions as a cache memory, thereby reducing the physical distance between the storage unit 43 and the storage unit 33. This also makes it possible to reduce the gap in the delay time required to read and write data.
  • the semiconductor device can be configured such that memory units 33 and 43 with different operating speeds or memory capacities are stacked in the z direction (the direction perpendicular to the substrate on which the element layer 20 is provided (z direction)) as shown in FIG. 4B, and data (Data) can be input and output through the memory units in each layer. Since data (Data) can be input and output using wiring between the stacked element layers, the parasitic capacitance or resistance of the wiring can be reduced, and an increase in power consumption due to data input and output can be suppressed.
  • the semiconductor device may have a configuration in which a memory unit 33 functioning as a cache memory and a memory unit 43 functioning as a main memory are stacked on an element layer 20 in which an arithmetic unit, a cache memory, a sense amplifier circuit, and the like are provided.
  • the memory unit 33 and the memory unit 43 can make the signal propagation distance between the memory cell and the sense amplifier circuit different, and in addition to reducing power consumption and signal delay by significantly reducing the resistance and parasitic capacitance of the bit line, the operating speed of the memory cell 34 and the memory cell 44 can be made different.
  • the configuration of one embodiment of the present invention can fill the performance gap between the L1 cache to the L3 cache and the main memory, and can also fill the performance gap between the L4 cache and the external memory.
  • the configuration of one embodiment of the present invention can fill the performance gap between the L1 cache to the L3 cache and the main memory, and can also fill the performance gap between the L4 cache and the external memory.
  • the configuration with a memory unit 43 that can be used as a large-capacity main memory the frequency of access to the external memory device (main memory or auxiliary memory device) for data due to cache misses can be reduced, thereby improving power efficiency.
  • the semiconductor device 10 may have a main memory composed of Si transistors such as DRAM between the main memory (storage unit 43) and the auxiliary storage device (storage unit 50).
  • a memory unit 49 illustrated as Si memory (Main Memory)
  • Si memory Main Memory
  • a switching circuit may be provided between the wirings BL1, BL2 of the element layers 30, 40 and the sense amplifier circuit.
  • a configuration may be provided in which a switching circuit 24 is provided as shown in FIG. 6.
  • the switching circuit 24 has a function of switching between a conductive state and a non-conductive state between the wirings BL1, BL2 and the wiring GBL.
  • the wiring GBL is connected to the sense amplifier circuit 23.
  • the switching circuit 24 is a circuit that selects one of the multiple wirings BL1 and BL2 and brings it into electrical contact with the wiring GBL. Therefore, if the memory cells 34 and 44 can use the same sense amplifier circuit, the sense amplifier circuits 21 and 22 can be made into a common sense amplifier circuit 23. In addition, since the number of wirings BL1 and BL2 that are in electrical contact with the wiring GBL when writing or reading data can be reduced, the wiring resistance and wiring capacitance can be reduced.
  • the switching circuit 24 shown in FIG. 6 can be configured with multiple switches SW as shown in FIG. 7A. By switching the conductive state or non-conductive state of the switches SW, it is possible to select the wirings BL1 and BL2 that are in a conductive state with the wiring GBL.
  • the switches SW can be configured to include OS transistors. In this case, the switches SW can be configured to be provided in the element layer 30 and the element layer 40.
  • the multiple switches SW are configured to be provided in element layer 30 and element layer 40, but they may be provided in element layer 20.
  • the switching circuit 24 can be configured with a multiplexer SEL having a Si transistor.
  • an element layer having a cache memory made up of OS transistors is provided on an element layer having a cache memory made up of Si transistors, and the storage capacity of the cache memory can be increased.
  • the OS memory that functions as the main memory is configured to be placed directly above the element layer having the cache memory made up of OS transistors, a semiconductor device with a small area, high computing power, and low power consumption can be provided.
  • FIGS. 8A to 8H are circuit diagrams illustrating examples of the configuration of a memory cell having an OS transistor that can be applied to the above-mentioned memory cells 34 and 44.
  • DOSRAM or NOSRAM can be given as an example of the configuration of a memory cell having an OS transistor.
  • FIG. 8A shows an example of a 1T1C type DOSRAM memory cell applicable to memory cells 34 and 44.
  • Memory cell 34A shown in FIG. 8A is electrically connected to wiring WL, wiring BL, wiring CDL that functions as a capacitance line, and wiring BGL that functions as a wiring that supplies a backgate voltage.
  • Memory cell 34A has a transistor 37 and a capacitor 38. The backgate of transistor 37 is electrically connected to wiring BGL.
  • Transistor 37 is an OS transistor. OS transistors have an extremely low off-state current. Therefore, memory cell 34A can reduce the frequency of data refresh. Therefore, the power required to hold data can be reduced.
  • FIG. 8B shows another example of the configuration of a memory cell of a 1T1C type DOSRAM.
  • Memory cell 34B shown in FIG. 8B differs from memory cell 34A shown in FIG. 8A in that transistor 37 is an OS transistor that does not have a backgate.
  • FIG. 8C shows an example of a NOSRAM memory cell that is a two-transistor type (2T) gain cell that can be used for memory cells 34 and 44.
  • Memory cell 34C shown in FIG. 8C has transistors 37A and 37B and a capacitor 38. Note that the capacitor 38 in the NOSRAM memory cell can be omitted by using parasitic capacitance such as the gate capacitance of the transistor.
  • Transistor 37A is a write transistor
  • transistor 37B is a read transistor.
  • the back gates of transistors 37A and 37B are electrically connected to wiring BGL.
  • memory cell 34C Since the write transistor is an OS transistor, it is possible to continue to hold the charge corresponding to the data by turning off the write transistor. Therefore, memory cell 34C does not consume power to hold the data. Therefore, memory cell 34C can function as a low-power memory cell that can hold data for a long period of time.
  • Memory cell 34D shown in FIG. 8D is a 3T type gain cell and has transistors 37A, 37B, 37C, and a capacitor 38.
  • Transistors 37A, 37B, and 37C are a write transistor, a read transistor, and a select transistor, respectively.
  • the back gates of transistors 37A, 37B, and 37C are electrically connected to wiring BGL.
  • Memory cell 34D is electrically connected to wirings RWL, WWL, wirings RBL, WBL, wiring CDL, and power supply line PL2. For example, voltage GND (low-level power supply voltage) is input to wiring CDL and wiring PL2.
  • voltage GND low-level power supply voltage
  • FIG. 8E shows another example of the configuration of a 2T-type gain cell.
  • Memory cell 34E shown in FIG. 8E differs from memory cell 34C shown in FIG. 8C in that the read transistor is an OS transistor that does not have a backgate.
  • FIG. 8F shows another example of the configuration of a 3T-type gain cell.
  • Memory cell 34F shown in FIG. 8F differs from memory cell 34D shown in FIG. 8D in that it is configured with OS transistors without backgates as read transistors and selection transistors.
  • FIG. 8G shows another example of the configuration of a 2T-type gain cell.
  • Memory cell 34G shown in FIG. 8G differs from memory cell 34C shown in FIG. 8C in that transistors 37A and 37B are OS transistors without a backgate and that capacitor 38 is omitted.
  • FIG. 8H shows another example of the configuration of a 3T-type gain cell.
  • Memory cell 34H shown in FIG. 8H differs from memory cell 34D shown in FIG. 8D in that transistors 37A, 37B, and 37C are OS transistors without a backgate, and capacitor 38 is omitted.
  • memory cells 34 and 44 are DOSRAM or NOSRAM
  • a voltage that turns off the access transistor is applied to the wiring (wirings WL and WWL in FIGS. 8A to 8H) connected to the gate of the transistor, and other parts can be power-gated.
  • the supply of power supply voltage can be stopped with data stored in memory cells 34 and 44.
  • memory cells 34A to 34H described in Figures 8A to 8H are applied to memory cells 34 of element layer 30 and memory cells 44 of element layer 40 described in Figures 1A to 3, it is preferable to apply memory cells having different circuit configurations or different transistor structures between memory cells 34 and memory cells 44.
  • the memory cells 34 of the storage unit 33 functioning as a cache memory are DOSRAM memory cells having a back gate that is advantageous for controlling electrical characteristics such as the threshold voltage, and that the memory cells 44 of the storage unit 43 functioning as a main memory are DOSRAM memory cells without a back gate that is advantageous for increasing the density of storage capacity.
  • FIG. 9 is a diagram showing a configuration example of a semiconductor device 10M_1 in which memory cells with different transistor structures are applied to element layers 30, 40 in different layers.
  • memory unit 33 in element layer 30 provided on element layer 20 uses memory cell 34A, which is a DOSRAM memory cell described in FIG. 8A. That is, memory unit 33 in element layer 30 uses transistor 37 having a back gate that is advantageous for controlling electrical characteristics such as threshold voltage, as described in FIG. 8A.
  • This configuration makes it possible to provide a semiconductor device with excellent transistor characteristics in memory unit 33 that functions as a cache memory.
  • the memory unit 33 provided in the element layer 30 is a DOSRAM that uses the planar transistors described above.
  • DOSRAM that uses planar transistors can be easily structured to have a back gate compared to vertical transistors, making it possible to provide a semiconductor device with excellent transistor characteristics.
  • memory cell 34B which is a DOSRAM memory cell described in FIG. 8B, is applied to memory unit 43 of element layer 40 provided on element layer 30.
  • transistor 37 without a back gate which is advantageous for increasing the density of memory cells, described in FIG. 8B, is applied to memory unit 43 in element layer 40.
  • the memory unit 43 provided in the element layer 40 is configured as a DOSRAM using the VFET described above.
  • the memory unit 43 which corresponds to the main memory, can be configured as a DOSRAM using a VFET to further increase the density of memory cells.
  • FIG. 10 is a diagram showing an example of a configuration of a semiconductor device 10M_2 in which memory cells with different transistor structures are applied to element layers 30 and 40 in different layers, which is different from the configuration in FIG. 9.
  • a transistor 37 having a back gate that is advantageous for controlling electrical characteristics such as the threshold voltage, as described in FIG. 8A is applied in the memory unit 33 of the element layer 30 provided on the element layer 20 .
  • a semiconductor device with excellent transistor characteristics can be obtained in the memory unit 33 that functions as a cache memory.
  • the operating speed of the memory unit 33 can be improved and the memory unit 43 can be used as a cache memory.
  • the memory unit 43 provided above the memory unit 33 can have a larger hierarchical level (hatched hierarchical level in Figure 4A) when used as a main memory by increasing the density of memory cells.
  • a semiconductor device 10 can be formed in which the arithmetic unit, main memory, and cache memory are integrated, and a different hierarchy of memory units from the conventional one can be provided.
  • the configuration of semiconductor device 10, in which a calculation unit, main memory, and cache memory are integrated, makes it possible to reduce the size of connection wiring, etc., compared to a technique in which a memory unit and a calculation unit are bonded together using through electrodes such as TSVs. This makes it possible to increase the amount of data accessed between memory units such as the calculation unit, main memory, and cache memory. In other words, it becomes possible to improve the bandwidth (also called memory bandwidth) of the memory (memory unit). Bandwidth is the amount of data transferred per unit time. Furthermore, the configuration of semiconductor device 10 can improve either or both of the memory bandwidth and the access latency. Access latency is the time from access to the start of data exchange.
  • Embodiment 2 In this embodiment, a specific configuration example of each circuit included in the semiconductor device described in the above embodiment will be described. In this embodiment, a configuration example of a semiconductor device in which an element layer in which a memory unit having memory cells is provided is stacked over an element layer including a sense amplifier circuit will be described.
  • FIG 11 is a block diagram illustrating a configuration example of a semiconductor device 10D according to one embodiment of the present invention.
  • the semiconductor device 10D illustrated in FIG 11 includes an element layer 20, an element layer 30, and an element layer 40 stacked thereon.
  • FIG. 11 shows an example in which memory cells 34 in the memory unit 33 are arranged in a matrix of 1 row and n columns (n is an integer of 2 or more) and memory cells 44 in the memory unit 43 are arranged in a matrix of m rows and n columns (n is an integer of 2 or more) in the element layer 30 and element layer 40.
  • FIG. 11 shows, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL1 and BL2 extending in the column direction.
  • wirings WL are shown with ordinal numbers such as wiring WL[1].
  • Wirings BL1 and BL2 function as bit lines for writing and reading data.
  • Wiring WL functions as a word line for controlling the on/off (conductive or non-conductive) of an access transistor that functions as a switch.
  • Wiring PL functions as a constant potential line connected to a capacitor. Note that a separate wiring CL (not shown) can be provided as a wiring for transmitting the backgate potential.
  • Memory cells 34, 44 in element layers 30, 40, respectively, are connected to a sense amplifier circuit 66 (Sense Amplifier) via wirings BL1, BL2.
  • the sense amplifier circuit 66 is a circuit that can be applied to the sense amplifier circuit 21 or the sense amplifier circuit 22 described in the first embodiment above.
  • the wiring BL can be arranged in the horizontal and vertical directions on the substrate surface on which the element layer 20 is provided.
  • the length of the wiring between the element layer 30 and the sense amplifier circuit 66 can be made different from the length of the wiring between the element layer 40 and the sense amplifier circuit 66. This makes it possible to shorten the signal propagation distance between the memory cell and the sense amplifier, and to reduce power consumption and signal delay by significantly reducing the resistance and parasitic capacitance of the bit line, and to make the operating speed of the memory cell 34 different from that of the memory cell 44. As a result, the operating speed of the memory unit 33 can be improved, and the memory capacity of the memory unit 43 can be improved.
  • the element layer 20 has a PSW 71 (power switch), a PSW 72, and a peripheral circuit 52.
  • the peripheral circuit 52 has a drive circuit 61, a control circuit 73, and a voltage generation circuit 74.
  • Each circuit in the element layer 20 has a Si transistor.
  • the peripheral circuit 52 is illustrated as being provided in common to the memory cells 34 of the memory unit 33 and the memory cells 44 of the memory unit 43, but other configurations are also possible. For example, a configuration in which a peripheral circuit 52 is provided for the memory cells 34 of the memory unit 33, and another peripheral circuit is provided for the memory cells 44 of the memory unit 43 may be used.
  • the circuits, signals, and voltages can be selected or removed as needed. Alternatively, other circuits or signals may be added.
  • the signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside.
  • the signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are signals for power gating control. Signals PON1 and PON2 may be generated by control circuit 73.
  • the control circuit 73 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 10D. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 10D. Alternatively, the control circuit 73 generates a control signal for the drive circuit 61 so that this operation mode is executed.
  • the control circuit 73 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 10D.
  • the control circuit 73 generates a control signal for the drive circuit 61 so that this operation mode is executed.
  • the voltage generation circuit 74 has the function of generating a negative voltage.
  • the signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 74. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 74, and the voltage generation circuit 74 generates a negative voltage.
  • the drive circuit 61 is a circuit for writing and reading data to the memory cells 34 and 44.
  • the drive circuit 61 has a row decoder 62, a column decoder 64, a row driver 63, a column driver 65, an input circuit 67, an output circuit 68, and the sense amplifier circuit 66 described above.
  • the row decoder 62 and column decoder 64 have the function of decoding the signal ADDR.
  • the row decoder 62 is a circuit for specifying the row to be accessed
  • the column decoder 64 is a circuit for specifying the column to be accessed.
  • the row driver 63 has the function of selecting the wiring WL specified by the row decoder 62.
  • the column driver 65 has the function of writing data to the memory cells 34 and 44, the function of reading data from the memory cells 34 and 44, the function of retaining the read data, etc.
  • the input circuit 67 has a function of holding a signal WDA.
  • the data held by the input circuit 67 is output to the column driver 65.
  • the output data of the input circuit 67 is data (Din) to be written to the memory cells 34, 44.
  • the data (Dout) read from the memory cells 34, 44 by the column driver 65 is output to the output circuit 68.
  • the output circuit 68 has a function of holding Dout.
  • the output circuit 68 has a function of outputting Dout to the outside of the semiconductor device 10D.
  • the data output from the output circuit 68 is the signal RDA.
  • PSW71 has a function of controlling the supply of VDD to the peripheral circuit 52.
  • PSW72 has a function of controlling the supply of VHM to the row driver 63.
  • the high power supply voltage of the semiconductor device 10D is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD.
  • the on/off of PSW71 is controlled by signal PON1, and the on/off of PSW72 is controlled by signal PON2.
  • the number of power supply domains to which VDD is supplied in the peripheral circuit 52 is one, but it is also possible to have multiple power supply domains. In this case, a power switch can be provided for each power supply domain.
  • the element layer 40 provided in the first layer is shown as element layer 40[1]
  • the element layer 40 provided in the second layer is shown as element layer 40[2]
  • the element layer 40 provided in the fourth layer is shown as element layer 40[4].
  • wiring WL and wiring PL extending in the X direction
  • wiring BL1, BL2 and wiring BL1B, BL2B extending in the Y direction and Z direction (directions perpendicular to the substrate surface on which the drive circuit is provided).
  • Wiring BL1B and BL2B are inverted bit lines. Note that in order to make the drawing easier to understand, some of the wiring WL and wiring PL of each element layer 30 are omitted.
  • FIG. 13 shows a schematic diagram illustrating an example of the configuration of the sense amplifier circuits 21 and 22 connected to the wirings BL1 and BL2 and wirings BL1B and BL2B shown in FIG. 12, and the memory cells 34 and 44 included in the element layer 30 and element layers 40[1] to 40[4] connected to the wirings BL1 and BL2 and wirings BL1B and BL2BB.
  • FIG. 13 illustrates an example of the circuit configuration of memory cells 34, 44 connected to wirings BL1B, BL2BB.
  • memory cells 34, 44 have the same circuit configuration, they have a transistor 37 and a capacitor 38 as shown in FIG. 13.
  • the transistor 37, the capacitor 38, and each wiring (BL, WL, etc.) for example, wiring BL[1] and wiring WL[1] may be referred to as wiring BL and wiring WL, etc.
  • one of the source and drain of transistor 37 is connected to wiring BL.
  • the other of the source and drain of transistor 37 is connected to one electrode of capacitor 38.
  • the other electrode of capacitor 38 is connected to wiring PL.
  • the gate of transistor 37 is connected to wiring WL.
  • the wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitor 38. By connecting multiple wirings PL together as a single wiring, the number of wirings can be reduced.
  • the OS transistors are stacked and the wiring that functions as the bit line is arranged in a vertical direction to the substrate surface on which the element layer 20 is provided.
  • the transistors 37 and capacitors of the memory cells 34 and 44 are arranged in a line in a vertical direction to the substrate surface on which the element layer 20 is provided.
  • the signal propagation distance between the memory cell and the sense amplifier can be shortened, and the resistance and parasitic capacitance of the bit line are significantly reduced, thereby reducing power consumption and signal delay, and the operating speed of the memory cell 34 and the memory cell 44 can be made different.
  • the operating speed of the memory unit 33 can be improved and the memory capacity of the memory unit 43 can be improved.
  • FIG. 14A and 14B show circuit diagrams corresponding to the memory cells 34 and 44 described above, and diagrams for explaining circuit blocks corresponding to the circuit diagrams. As shown in Fig. 14A and 14B, the memory cells 34 and 44 may be shown as blocks in the drawings. Note that the wiring BL (corresponding to wirings BL1 and BL2) shown in Fig. 14A and 14B can be similarly expressed when replaced with wiring BLB (corresponding to wirings BL1B and BL2B).
  • FIGS. 14C and 14D show circuit diagrams of sense amplifier circuits 21 and 22 corresponding to the above-mentioned sense amplifier circuit 66, and diagrams explaining circuit blocks corresponding to the circuit diagrams.
  • the sense amplifier circuits 21 and 22 are illustrated with a switch circuit 82, a precharge circuit 83, a precharge circuit 84, and an amplifier circuit 85.
  • wiring SA_OUT and wiring SA_OUTB that output the read signal are also illustrated.
  • the switch circuit 82 has, for example, n-channel transistors 82_1 and 82_2.
  • the transistors 82_1 and 82_2 switch the conduction state between the wiring pair of the wiring SA_OUT and the wiring SA_OUTB and the wiring pair of the wiring BL and the wiring BLB in response to the signal CSEL.
  • the precharge circuit 83 is composed of n-channel transistors 83_1 to 83_3 as shown in FIG. 14C.
  • the precharge circuit 83 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE that corresponds to a potential VDD/2 in response to a signal EQ.
  • the precharge circuit 84 is composed of p-channel transistors 84_1 to 84_3 as shown in FIG. 14C.
  • the precharge circuit 84 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE that corresponds to a potential VDD/2 in response to a signal EQB.
  • the amplifier circuit 85 is composed of p-channel transistors 85_1 and 85_2 and n-channel transistors 85_3 and 85_4 connected to a wiring SAP or wiring SAN.
  • the wiring SAP or wiring SAN has a function of providing VDD or VSS.
  • the transistors 85_1 to 85_4 are transistors that form an inverter loop.
  • FIG. 14D shows a diagram for explaining the circuit blocks corresponding to the sense amplifier circuits 21 and 22 described in FIG. 14C etc. As shown in FIG. 14D, the sense amplifier circuits 21 and 22 may be represented as blocks in drawings etc.
  • FIG. 15 is a circuit diagram of the semiconductor device 10D of FIG. 12.
  • the circuit blocks described in FIG. 14A to FIG. 14D are used for illustration.
  • the memory unit 33 provided in the element layer 30 and the memory unit 43 provided in the element layer 40 have memory cells 34 and 44.
  • the memory cells 34 and 44 shown in FIG. 15 are connected to a pair of wirings BL1 and BL1B, or wirings BL2 and BL2B.
  • Memory cell 34 connected to wirings BL1 and BL1B, and memory cell 44 connected to wirings BL2 and BL2B are memory cells to and from which data is written or read.
  • the wiring BL1 and the wiring BL1B are connected to the sense amplifier circuit 21, and the wiring BL2 and the wiring BL2B are connected to the sense amplifier circuit 22.
  • the sense amplifier circuit 21 and the sense amplifier circuit 22 can read data in response to various signals described in FIG. 14C.
  • ⁇ DOSRAM Configuration Example 1> 16 shows a cross-sectional configuration example in the case where a DOSRAM circuit configuration is used.
  • an element layer 30 and element layers 40[1] to 40[3] are stacked on an element layer 20.
  • the transistor 550 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 that is part of the substrate 311, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b.
  • Transistor 550 may be either a p-channel type or an n-channel type.
  • Low resistance region 314a and low resistance region 314b contain, in addition to the semiconductor material applied to semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.
  • the conductor 316 that functions as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.
  • a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.
  • Transistor 550 may be formed using an SOI (Silicon on Insulator) substrate, etc.
  • transistor 550 shown in FIG. 16 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration or driving method.
  • a wiring layer having an interlayer film, wiring, plugs, etc. may be provided between the element layer 20 and the element layer 30, between the element layer 30 and the element layer 40, or between the kth element layer 40 and the k+1th element layer 40.
  • the kth element layer 40 may be indicated as element layer 40[k]
  • the k+1th element layer 40 may be indicated as element layer 40[k+1].
  • k is an integer between 1 and N.
  • the solutions of "k+ ⁇ " and "k- ⁇ ” are integers between 1 and N.
  • wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film.
  • Conductors 328 and the like are embedded in the insulators 320 and 322.
  • Conductors 330 and the like are embedded in the insulators 324 and 326.
  • Conductors 328 and 330 function as contact plugs or wiring.
  • Insulators 320, 322, 324, and 326 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.
  • silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen
  • aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.
  • the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath.
  • the top surface of the insulator 320 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.
  • CMP chemical mechanical polishing
  • the insulator 324 it is preferable to use a film having barrier properties that prevent hydrogen, impurities, and the like from diffusing from the substrate 311 or the transistor 550 to the region in which the transistor 500 in the element layer 30 and the element layers 40[1] to 40[3] is provided.
  • a film having barrier properties against hydrogen for example, silicon nitride formed by a CVD method can be used.
  • silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 550.
  • a film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.
  • the insulator 326 has a lower dielectric constant than the insulator 324.
  • the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulator 326 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less.
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • insulator 350, insulator 357, insulator 352, and insulator 354 are stacked in this order on the insulator 326 and the conductor 330.
  • Conductor 356 is formed on insulator 350, insulator 357, and insulator 352. Conductor 356 functions as a contact plug or wiring.
  • the materials for each plug and wiring can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, either in a single layer or in a laminated form. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferable. Alternatively, it is preferable to form the wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.
  • An insulator 514 of the element layer 30 is provided on the insulator 354.
  • a conductor 358 is embedded in the insulator 514 and the insulator 354.
  • the conductor 358 functions as a contact plug or a wiring.
  • the wiring BL and the transistor 550 are electrically connected via the conductor 358, the conductor 356, the conductor 330, and the like.
  • the insulator 350 is an insulator having a barrier property against hydrogen, similar to the insulator 324. It is also preferable that the conductor 356 includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.
  • a conductor having a barrier property against hydrogen for example, tantalum nitride or the like can be used.
  • tantalum nitride As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like can be used.
  • tantalum nitride and highly conductive tungsten it is possible to suppress the diffusion of hydrogen from the transistor 550 while maintaining the conductivity of the wiring.
  • the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.
  • the memory cell MC illustrated in FIG. 16 includes a transistor M1 and a capacitor C.
  • An OS transistor can be used as the transistor M1.
  • Figures 17A and 17B are schematic cross-sectional views of a transistor 500 that can be used as transistor M1.
  • the transistor 500 has a conductor 503 disposed so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, conductors 542a and 542b disposed apart from each other on the oxide 530b, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed therebetween overlapping the conductors 542a and 542b, an insulator 545 disposed on the bottom and side surfaces of the opening, and a conductor 560 disposed on the surface on which the insulator 545 is formed.
  • an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580.
  • the conductor 560 has a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a.
  • an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 545.
  • oxide 530a and oxide 530b may be collectively referred to as oxide 530.
  • the present invention is not limited to this.
  • a structure in which a single layer of oxide 530b is provided, or a stacked structure of three or more layers may be provided.
  • the conductor 560 is shown as having a two-layer stacked structure, but the present invention is not limited to this.
  • the conductor 560 may have a single-layer structure or a stacked structure of three or more layers.
  • the transistor 500 shown in FIG. 17A is only one example, and the present invention is not limited to this structure, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc.
  • the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode and drain electrode, respectively.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region between the conductors 542a and 542b.
  • the arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized and highly integrated.
  • the conductor 560 since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This makes it possible to improve the switching speed of the transistor 500 and provide it with high frequency characteristics.
  • the conductor 560 may function as a first gate (also referred to as a top gate) electrode.
  • the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode.
  • the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560.
  • the threshold voltage of the transistor 500 can be made higher than 0 V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V, compared to when a negative potential is not applied.
  • the conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered.
  • the transistor structure in which the electric field of the first gate electrode electrically surrounds the channel formation region is called a surrounded channel (S-channel) structure.
  • the S-channel structure disclosed in this specification has a structure different from the Fin type structure and the planar type structure.
  • the S-channel structure disclosed in this specification can also be considered as a type of Fin type structure.
  • the Fin type structure refers to a structure in which the gate electrode is arranged to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.).
  • the channel formation region can be electrically surrounded. Since the S-channel structure electrically surrounds the channel formation region, it can be said that the S-channel structure is substantially equivalent to a GAA (Gate All Around) structure or a LGAA (Lateral Gate All Around) structure.
  • GAA Gate All Around
  • LGAA Layer Advanced Gate All Around
  • the channel formation region formed at or near the interface between the oxide 530 and the gate insulator can be the entire bulk of the oxide 530. Therefore, it is possible to improve the current density flowing through the transistor, and it is expected that the on-current of the transistor or the field effect mobility of the transistor can be improved.
  • conductor 503 is formed such that conductor 503a is in contact with the inner walls of the openings of insulator 514 and insulator 516, and conductor 503b is formed further inward.
  • transistor 500 shows a structure in which conductor 503a and conductor 503b are stacked, the present invention is not limited to this.
  • conductor 503 may be provided as a single layer or a stacked structure of three or more layers.
  • the conductor 503a is made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, copper atoms, etc. (the impurities are less likely to permeate).
  • the conductor 503a is made of a conductive material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).
  • the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or oxygen mentioned above.
  • conductor 503a has the function of suppressing the diffusion of oxygen, which can prevent conductor 503b from being oxidized and causing a decrease in conductivity.
  • the conductor 503 when the conductor 503 also functions as wiring, it is preferable that the conductor 503b is made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that in this embodiment, the conductor 503 is illustrated as a laminate of the conductor 503a and the conductor 503b, but the conductor 503 may have a single layer structure.
  • Insulator 520, insulator 522, and insulator 524 function as a second gate insulating film.
  • the insulator 524 in contact with the oxide 530 is preferably an insulator containing more oxygen than the oxygen that satisfies the stoichiometric composition.
  • the oxygen is easily released from the film by heating.
  • oxygen released by heating may be referred to as "excess oxygen”. That is, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region").
  • the vacancies may function as donors and generate electrons that are carriers.
  • some of the hydrogen may bond to oxygen that is bonded to a metal atom and generate electrons that are carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics.
  • hydrogen in an oxide semiconductor is easily mobile due to stress such as heat or an electric field, and therefore, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.
  • oxide semiconductor with sufficiently reduced VOH it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also referred to as “dehydration” or “dehydrogenation treatment”) and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also referred to as “oxygenation treatment”).
  • impurities such as moisture and hydrogen
  • oxygen treatment also referred to as “oxygenation treatment”
  • an oxide material from which part of oxygen is released by heating is an oxide film from which the amount of oxygen released, calculated as oxygen atoms, is 1.0 ⁇ 10 18 atoms/cm 3 or more, preferably 1.0 ⁇ 10 19 atoms/cm 3 or more, more preferably 2.0 ⁇ 10 19 atoms/cm 3 or more, or 3.0 ⁇ 10 20 atoms/cm 3 or more, in TDS (Thermal Desorption Spectroscopy) analysis.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.
  • the insulator having the excess oxygen region and the oxide 530 may be brought into contact with each other and subjected to one or more of heat treatment, microwave treatment, and RF treatment.
  • heat treatment microwave treatment, and RF treatment.
  • water or hydrogen in the oxide 530 can be removed.
  • a reaction occurs in the oxide 530 in which the bond of VoH is broken, in other words, a reaction of " VOH ⁇ Vo+H" occurs, and dehydrogenation can be performed.
  • some of the generated hydrogen may be combined with oxygen to become H 2 O and removed from the oxide 530 or the insulator near the oxide 530.
  • some of the hydrogen may be gettered to the conductors 542a and 542b.
  • the microwave treatment is preferably performed using, for example, a device having a power source that generates high-density plasma or a device having a power source that applies RF to the substrate side.
  • high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530.
  • the pressure of the microwave treatment may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more.
  • oxygen and argon are used as gases to be introduced into the microwave treatment device, and the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is 50% or less, preferably 10% or more and 30% or less.
  • the heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher.
  • the heat treatment is preferably performed in an oxygen atmosphere. In this way, oxygen can be supplied to the oxide 530 to reduce oxygen vacancies (V O ).
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher in order to compensate for desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere.
  • heat treatment may be successively performed in a nitrogen gas or inert gas atmosphere.
  • oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo+O ⁇ null" can be promoted. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide 530, so that the hydrogen can be removed as H2O (dehydrated). This can prevent hydrogen remaining in the oxide 530 from recombining with the oxygen vacancies to form VOH .
  • the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).
  • oxygen e.g., oxygen atoms, oxygen molecules, etc.
  • the insulator 522 has a function of suppressing the diffusion of oxygen, impurities, etc., so that the oxygen contained in the oxide 530 does not diffuse toward the insulator 520, which is preferable.
  • the conductor 503 can be suppressed from reacting with the oxygen contained in the insulator 524, the oxide 530, etc.
  • the insulator 522 is preferably a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr)TiO 3 (BST).
  • a so-called high-k material such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr)TiO 3 (BST).
  • an insulator containing an oxide of one or both of aluminum and hafnium which are insulating materials that have the function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to permeate).
  • an insulator containing an oxide of one or both of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.
  • the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530, or the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above insulators.
  • the insulator 520 is thermally stable.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • by combining a high-k material insulator with silicon oxide or silicon oxynitride it is possible to obtain an insulator 520 having a layered structure that is thermally stable and has a high relative dielectric constant.
  • insulator 520, insulator 522, and insulator 524 are illustrated as the second gate insulating film having a three-layer stack structure, but the second gate insulating film may have a single layer, two layers, or a stack structure of four or more layers. In that case, it is not limited to a stack structure made of the same material, and may be a stack structure made of different materials.
  • the transistor 500 uses a metal oxide that functions as an oxide semiconductor for the oxide 530, which includes the channel formation region.
  • the metal oxide that functions as an oxide semiconductor may be formed by sputtering or ALD (Atomic Layer Deposition).
  • ALD Advanced Deposition
  • the metal oxide that functions as an oxide semiconductor will be described in detail in other embodiments.
  • a metal oxide that functions as a channel formation region in the oxide 530 with a band gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using a metal oxide with a large band gap, the off-state current of the transistor can be reduced.
  • oxide 530 By having oxide 530a below oxide 530b, oxide 530 can suppress the diffusion of impurities from components formed below oxide 530a to oxide 530b.
  • the oxide 530 has a structure of multiple oxide layers with different atomic ratios of each metal atom.
  • the atomic ratio of element M among the constituent elements is preferably greater than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b.
  • the atomic ratio of element M to In in the metal oxide used for the oxide 530a is greater than the atomic ratio of element M to In in the metal oxide used for the oxide 530b.
  • the atomic ratio of In to element M in the metal oxide used for the oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for the oxide 530a.
  • the energy of the conduction band minimum of the oxide 530a is higher than the energy of the conduction band minimum of the oxide 530b.
  • the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.
  • the energy level of the conduction band minimum changes smoothly.
  • the energy level of the conduction band minimum at the junction between oxide 530a and oxide 530b changes continuously or can be said to be a continuous junction.
  • oxide 530a is In-Ga-Zn oxide
  • oxide 530b is In-Ga-Zn oxide
  • the main carrier path is oxide 530b.
  • oxide 530a As described above, the defect state density at the interface between oxide 530a and oxide 530b can be reduced. As a result, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a large on-current.
  • Conductors 542a and 542b functioning as a source electrode and a drain electrode are provided on oxide 530b.
  • Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above-mentioned metal elements, or an alloy combining the above-mentioned metal elements.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, and are therefore preferable.
  • metal nitride films such as tantalum nitride are preferable because they have barrier properties against hydrogen or oxygen.
  • FIG. 17A shows conductor 542a and conductor 542b as a single layer structure, they may be laminated with two or more layers.
  • a tantalum nitride film and a tungsten film may be laminated.
  • a titanium film and an aluminum film may also be laminated.
  • a two-layer structure in which an aluminum film is laminated on a tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may be used.
  • Other examples include a three-layer structure in which a titanium film or titanium nitride film is laminated on top of an aluminum film or copper film, and a titanium film or titanium nitride film is further formed on top of that; and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on top of an aluminum film or copper film, and a molybdenum film or molybdenum nitride film is further formed on top of that.
  • a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.
  • regions 543a and 543b may be formed as low-resistance regions at and near the interface of oxide 530 with conductor 542a (conductor 542b).
  • region 543a functions as one of the source region and drain region
  • region 543b functions as the other of the source region and drain region.
  • a channel formation region is formed in the region sandwiched between regions 543a and 543b.
  • the oxygen concentration in the region 543a (region 543b) may be reduced.
  • a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.
  • the insulator 544 is provided to cover the conductors 542a and 542b, and suppresses oxidation of the conductors 542a and 542b.
  • the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.
  • insulator 544 a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used.
  • silicon nitride oxide or silicon nitride can also be used as the insulator 544.
  • an insulator containing an oxide of either or both of aluminum and hafnium such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).
  • hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in a later process.
  • the conductors 542a and 542b are made of a material that is resistant to oxidation, or a material whose conductivity does not decrease significantly even when it absorbs oxygen, the insulator 544 is not an essential component. It may be designed appropriately depending on the desired transistor characteristics.
  • insulator 544 can prevent impurities such as water and hydrogen contained in insulator 580 from diffusing into oxide 530b.
  • the presence of excess oxygen in insulator 580 can prevent conductors 542a and 542b from oxidizing.
  • the insulator 545 functions as a first gate insulating film. As with the insulator 524 described above, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen when heated.
  • silicon oxide with excess oxygen silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies can be used.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • insulator 545 By providing an insulator containing excess oxygen as insulator 545, oxygen can be effectively supplied from insulator 545 to the channel formation region of oxide 530b. As with insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in insulator 545 be reduced.
  • the film thickness of insulator 545 is preferably 1 nm or more and 20 nm or less.
  • a metal oxide may be provided between the insulator 545 and the conductor 560.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560.
  • the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed.
  • a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed.
  • oxidation of the conductor 560 due to excess oxygen can be suppressed.
  • a material that can be used for the insulator 544 may be used.
  • the insulator 545 may have a layered structure, similar to the second gate insulating film.
  • problems such as off-current may occur due to thinner gate insulating films. Therefore, by making the insulator that functions as the gate insulating film a layered structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • a layered structure that is thermally stable and has a high relative dielectric constant can be achieved.
  • the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in Figures 17A and 17B, but may have a single-layer structure or a stacked structure of three or more layers.
  • the conductor 560a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.), and copper atoms.
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.), and copper atoms.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one of oxygen atoms, oxygen molecules, etc.
  • the conductor 560a has a function of suppressing the diffusion of oxygen, so that the conductor 560b can be prevented from being oxidized by the oxygen contained in the insulator 545 and its conductivity can be reduced.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.
  • an oxide semiconductor that can be applied to the oxide 530 can be used as the conductor 560a.
  • the conductor 560b can be formed by a sputtering method to reduce the electrical resistance value of the conductor 560a to make it a conductor. This can be called an OC (Oxide Conductor) electrode.
  • the conductor 560b is made of a conductive material containing tungsten, copper, or aluminum as a main component. Moreover, since the conductor 560b also functions as wiring, it is preferable that a conductor with high conductivity is used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.
  • the insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544.
  • the insulator 580 preferably has an excess oxygen region.
  • the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, or resin.
  • silicon oxide and silicon oxynitride are preferred because they are thermally stable.
  • silicon oxide and silicon oxide with voids are preferred because they allow for easy formation of excess oxygen regions in a later process.
  • the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released when heated, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.
  • the opening of insulator 580 is formed so as to overlap the region between conductor 542a and conductor 542b. This allows conductor 560 to be formed so as to be embedded in the opening of insulator 580 and the region sandwiched between conductor 542a and conductor 542b.
  • the conductor 560 When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 560 does not decrease. If the thickness of the conductor 560 is increased in order to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, so that even if the conductor 560 has a shape with a high aspect ratio, it can be formed without the conductor 560 collapsing during the process.
  • the insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545.
  • an excess oxygen region can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen region into the oxide 530.
  • the insulator 574 may be a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc.
  • Aluminum oxide in particular, has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.
  • an insulator 581 that functions as an interlayer film on the insulator 574.
  • the concentration of impurities such as water or hydrogen in the insulator 581 is reduced.
  • conductors 540a and 540b are disposed in the openings formed in insulators 581, 574, 580, and 544. Conductors 540a and 540b are disposed opposite each other with conductor 560 in between.
  • Aluminum oxide in particular, has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • conductors 546 and 548 are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.
  • the conductor 546 and the conductor 548 function as plugs or wirings that connect to the transistor 500 or the transistor 550.
  • the conductor 546 and the conductor 548 can be formed using the same material as the conductor 328 and the conductor 330.
  • an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening.
  • an insulator with high barrier properties against hydrogen or water By wrapping the transistor 500 in the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside.
  • a plurality of transistors 500 may be wrapped together in an insulator with high barrier properties against hydrogen or water.
  • the insulator with high barrier properties against hydrogen or water for example, a material similar to the insulator 522 or the insulator 514 may be used.
  • the transistor that can be used in the present invention is not limited to the transistor 500 shown in Figures 17A and 17B.
  • a transistor 500 having the structure shown in Figure 17C may be used.
  • the transistor 500 shown in Figure 17C differs from the transistor shown in Figures 17A and 17B in that an insulator 555 is used and that the conductor 542a (conductor 542a1 and conductor 542a2) and the conductor 542b (conductor 542b1 and conductor 542b2) have a layered structure.
  • Conductor 542a has a layered structure of conductor 542a1 and conductor 542a2 on conductor 542a
  • conductor 542b has a layered structure of conductor 542b1 and conductor 542b2 on conductor 542b1.
  • Conductor 542a1 and conductor 542b1 in contact with oxide 530b are preferably conductors that are difficult to oxidize, such as metal nitrides. This can prevent conductor 542a and conductor 542b from being excessively oxidized by oxygen contained in oxide 530b.
  • Conductors 542a2 and conductor 542b2 are preferably conductors such as metal layers that are more conductive than conductor 542a1 and conductor 542b1.
  • conductor 542a and conductor 542b to function as highly conductive wiring or electrodes.
  • a semiconductor device can be provided in which conductors 542a and 542b, which function as wiring or electrodes, are provided in contact with the upper surface of oxide 530, which functions as an active layer.
  • a metal nitride for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum.
  • a nitride containing tantalum is particularly preferable.
  • ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.
  • conductor 542a2 and conductor 542b2 have higher conductivity than conductor 542a1 and conductor 542b1.
  • the film thickness of conductor 542a2 and conductor 542b2 is greater than the film thickness of conductor 542a1 and conductor 542b1.
  • Conductors 542a2 and conductor 542b2 may be conductors that can be used for conductor 560b.
  • tantalum nitride or titanium nitride can be used as the conductor 542a1 and the conductor 542b1, and tungsten can be used as the conductor 542a2 and the conductor 542b2.
  • the distance between conductor 542a1 and conductor 542b1 is smaller than the distance between conductor 542a2 and conductor 542b2.
  • the insulator 555 is preferably an insulator that is difficult to oxidize, such as a nitride.
  • the insulator 555 is formed in contact with the side surface of the conductor 542a2 and the side surface of the conductor 542b2, and has the function of protecting the conductor 542a2 and the conductor 542b2. Since the insulator 555 is exposed to an oxidizing atmosphere, it is preferable that the insulator 555 is an inorganic insulator that is difficult to oxidize.
  • the insulator 555 is in contact with the conductor 542a2 and the conductor 542b2, it is preferable that the insulator 555 is an inorganic insulator that is difficult to oxidize the conductors 542a2 and 542b2. Therefore, it is preferable that the insulator 555 is made of an insulating material that has a barrier property against oxygen. For example, silicon nitride can be used as the insulator 555.
  • 17C is formed by forming an opening in the insulator 580 and the insulator 544, forming an insulator 555 in contact with the sidewall of the opening, and then dividing the conductor 542a1 and the conductor 542b1 using a mask.
  • the opening overlaps with the region between the conductor 542a2 and the conductor 542b2.
  • parts of the conductor 542a1 and the conductor 542b1 are formed to protrude into the opening.
  • the insulator 555 contacts the top surface of the conductor 542a1, the top surface of the conductor 542b1, the side surface of the conductor 542a2, and the side surface of the conductor 542b2 within the opening.
  • the insulator 545 contacts the top surface of the oxide 530 in the region between the conductor 542a1 and the conductor 542b1.
  • the conductor 542a1 and the conductor 542b1 After separating the conductor 542a1 and the conductor 542b1, it is preferable to perform heat treatment in an atmosphere containing oxygen before forming the insulator 545. This allows oxygen to be supplied to the oxide 530a and the oxide 530b, thereby reducing oxygen deficiency. Furthermore, since the insulator 555 is formed in contact with the side surface of the conductor 542a2 and the side surface of the conductor 542b2, excessive oxidation of the conductor 542a2 and the conductor 542b2 can be prevented. As a result, the electrical characteristics and reliability of the transistor can be improved. In addition, the variation in the electrical characteristics of multiple transistors formed on the same substrate can be suppressed.
  • the insulator 524 may be formed in an island shape as shown in FIG. 17C.
  • the insulator 524 may be formed so that the side ends thereof roughly coincide with the oxide 530.
  • the insulator 522 may be in contact with the insulator 516 and the conductor 503.
  • the transistor 500 may be configured without the insulator 520 shown in FIG. 17A and FIG. 17B.
  • FIG. 18A shows an example of a cross-sectional structure of an element layer 40[k] that can be applied to the element layer 30 and element layers 40[1] to 40[3] shown in FIG. 16.
  • FIG. 18B shows an equivalent circuit diagram of FIG. 18A.
  • FIG. 18A shows an example in which two memory cells MC are electrically connected to one wiring BL.
  • transistor M1 is a modified version of transistor 500. Specifically, transistor M1 differs from transistor 500 in that conductor 542a and conductor 542b extend beyond the ends of metal oxide 531 (metal oxide 531a and metal oxide 531b).
  • the memory cell MC shown in FIG. 18A also has a conductor 156 that functions as one terminal of the capacitor C, an insulator 153 that functions as a dielectric, and a conductor 160 (conductor 160a and conductor 160b) that functions as the other terminal of the capacitor C.
  • Conductor 156 is electrically connected to a portion of conductor 542b.
  • Conductor 160 is also electrically connected to wiring PL (not shown in FIG. 18A).
  • Capacitor C is formed in an opening created by removing a portion of insulator 574, insulator 580, and insulator 554. Conductor 156, insulator 580, and insulator 554 are formed along the side of the opening, so it is preferable to form the film using the ALD method, CVD method, or the like.
  • conductor 156 and conductor 160 may be made of a conductor that can be used for conductor 505 or conductor 560.
  • titanium nitride formed using the ALD method may be used as conductor 156.
  • titanium nitride formed using the ALD method may be used as conductor 160a, and tungsten formed using the CVD method may be used as conductor 160b. Note that if the adhesion of tungsten to insulator 153 is sufficiently high, a single layer film of tungsten formed using the CVD method may be used as conductor 160.
  • an insulator made of a high dielectric constant (high-k) material (a material with a high relative dielectric constant).
  • high-k high dielectric constant
  • an oxide, an oxynitride, a nitriding oxide, or a nitride containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium can be used as the insulator made of a high dielectric constant material.
  • Silicon may also be contained in the oxide, the oxynitride, the nitriding oxide, or the nitride.
  • insulating layers made of the above materials can be stacked and used.
  • the insulator 153 may be a three-layer stacked structure of zirconium oxide, aluminum oxide, and zirconium oxide.
  • the three-layer stacked structure may be called ZrO xa ⁇ AlO xb ⁇ ZrO xc (ZAZ). Note that the above xa, xb, and xc are each an arbitrary unit.
  • the high dielectric constant material insulator may be aluminum oxide, hafnium oxide, zirconium oxide, oxide having aluminum and hafnium, oxynitride having aluminum and hafnium, oxide having silicon and hafnium, oxynitride having silicon and hafnium, oxide having silicon and zirconium, oxynitride having silicon and zirconium, oxide having hafnium and zirconium, oxynitride having hafnium and zirconium, etc.
  • the insulator 153 can be made thick enough to suppress the off current, and the capacitance of the capacitor C can be sufficiently ensured.
  • a laminated insulating layer made of the above materials it is preferable to use a laminated structure of a high dielectric constant material and a material having a higher dielectric strength than the high dielectric constant material.
  • an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 153.
  • an insulating film laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used.
  • an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used.
  • a material that can have ferroelectricity may be used as the insulator 153.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (where X is a real number greater than 0).
  • materials that can have ferroelectricity include a material in which an element J1 (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide.
  • the ratio of the number of atoms of hafnium atoms to the number of atoms of the element J1 can be set appropriately, and for example, the ratio of the number of atoms of hafnium atoms to the number of atoms of the element J1 may be set to 1:1 or close to 1:1.
  • materials that can have ferroelectricity include a material in which an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide.
  • the ratio of the number of zirconium atoms to the number of elements J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of elements J2 may be set to 1:1 or close to 1:1.
  • a piezoelectric ceramic having a perovskite structure such as lead titanate ( PbTiOx ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), barium titanate, etc. may be used.
  • a structure in which a Group 3 element (also called a Group IIIa element) in the periodic table is added to a metal oxide such as hafnium oxide, zirconium oxide, or HfZrOx (X is a real number greater than 0) may be used.
  • the Group 3 element in the periodic table is more preferably one or more selected from scandium, lanthanum, and yttrium, and even more preferably one or both of lanthanum and yttrium. In this specification and the like, the Group 3 element in the periodic table may be simply referred to as the Group 3 element.
  • Fig. 19 shows a cross-sectional configuration example when a circuit configuration of a NOSRAM memory cell is used.
  • Fig. 19 is also a modified example of Fig. 16.
  • Fig. 20A shows a cross-sectional structure example of an element layer 40[k].
  • Fig. 20B shows an equivalent circuit diagram of Fig. 20A.
  • the memory cell MC shown in Figures 19 and 20A has transistors M1, M2, and M3 on an insulator 514.
  • a conductor 515 is provided on the insulator 514.
  • the conductor 515 can be formed simultaneously with the conductor 505 using the same material and in the same process.
  • the transistors M2 and M3 shown in Figures 19 and 20A share one island-shaped metal oxide 531.
  • a part of the island-shaped metal oxide 531 functions as a channel formation region for the transistor M2, and another part functions as a channel formation region for the transistor M3.
  • the source of the transistor M2 and the drain of the transistor M3, or the drain of the transistor M2 and the source of the transistor M3, are also shared. Therefore, the area occupied by the transistors is smaller than when the transistors M2 and M3 are provided independently.
  • an insulator 287 is provided on an insulator 581, and a conductor 161 is embedded in the insulator 287.
  • an insulator 514 of the element layer 40[k+1] is provided on the insulator 287 and the conductor 161.
  • conductor 515 of element layer 40[k+1] functions as one terminal of capacitor C
  • insulator 514 of element layer 40[k+1] functions as a dielectric of capacitor C
  • conductor 161 functions as the other terminal of capacitor C.
  • the other of the source or drain of transistor M1 is electrically connected to conductor 161 via a contact plug
  • the gate of transistor M2 is electrically connected to conductor 161 via another contact plug.
  • ⁇ DOSRAM Configuration Example 2> 21 shows a cross-sectional example of an element layer including stacked OS transistors that can be applied to a semiconductor device or the like of one embodiment of the present invention, which is different from that in FIG. 16 to FIG. 20A and FIG. 20B , in a semiconductor device 10V shown in FIG. 21 , a capacitor C is provided below a transistor M1 in a memory cell MC included in the element layer 30 and the element layers 40[1] and 40[2] shown in FIG.
  • each of the element layer 30 and the multiple element layers 40 has multiple memory cells MC.
  • a transistor M1 and a capacitor C are illustrated.
  • the interlayer film between the element layer 20 and the element layer 30 is embedded with conductors 363a, 363b, and 363c.
  • the insulator 592 described below is embedded with conductor 365.
  • the insulator 593, 594, 553, and 595 described below are embedded with conductor 366.
  • the insulator 596, 583, 542b, 555, and 597 described below are embedded with conductor 367.
  • the conductors 363a, 363b, 363c, 365, 366, and 367 function as vias, contact plugs, or wiring.
  • FIG. 22A is a plan view showing an example of the configuration of a memory cell MC and its periphery included in each of the element layer 30 and the multiple element layers 40 of the semiconductor device 10V described above.
  • transistor 500A corresponds to transistor M1 in FIG. 21
  • capacitance 600A corresponds to capacitor C in FIG. 21.
  • FIG. 22D is a cross-sectional view of dashed dotted line A1-A2 shown in FIG. 22A.
  • some of the components of transistor M1, such as insulators are omitted.
  • some of the components, such as insulators are also omitted.
  • capacitance 600A has insulator 593, insulator 594, insulator 553, insulator 595, conductor 563, conductor 564, and conductor 542a.
  • the conductor 563 is embedded in the conductor 563.
  • the conductor 563 can be wiring PL extending in the Y direction.
  • insulators 593 and 594 are formed in this order on insulator 592 and conductor 563.
  • An opening is provided in the area of insulator 593 and insulator 594 that overlaps with conductor 563.
  • Conductor 564 is formed on the bottom surface (on conductor 563) and side surface of the opening. In FIG. 22D, conductor 564 is also formed on the top surface of insulator 594.
  • Insulator 553 is formed on insulator 594 and conductor 564.
  • Conductor 542a is formed so as to cover the area of insulator 553 that overlaps with conductor 564.
  • Insulator 595 is formed on conductor 542a and insulator 553.
  • the height of the top surface of insulator 595 and the height of the top surface of conductor 542a are approximately the same. For this reason, it is preferable that the insulator 595 and the conductor 542a are planarized by a planarization process using, for example, a chemical mechanical polishing (CMP) method.
  • CMP chemical mechanical polishing
  • the conductor 564 corresponds to, for example, one of a pair of terminals in the capacitance 600A.
  • the conductor 542a corresponds to, for example, the other of the pair of terminals in the capacitance 600A.
  • the insulator 553 functions as a dielectric sandwiched between a pair of terminals, for example, at a capacitance of 600A.
  • Transistor 500A is provided above conductor 542a and insulator 595 with a capacitance of 600A.
  • Transistor 500A is configured such that the direction of the channel length is not approximately parallel to substrate 311, but is aligned with the side of an opening provided in insulator 583, which will be described later.
  • the transistor 500A has a conductor 542a that functions as one of the source electrode or drain electrode, a conductor 542b that functions as the other of the source electrode or drain electrode, a metal oxide 533, an insulator 555, and a conductor 565 that functions as a gate electrode.
  • FIG. 22A shows an example in which the conductor 542b extends in a direction perpendicular to the conductor 542a and the conductor 565.
  • the conductor 542a also functions as the other of the pair of electrodes of the capacitance 600A.
  • the metal oxide 533 can be made of, for example, a material that can be used for the oxide 530 contained in the transistor 500 described above.
  • the direction in which the conductor 542b extends is the X direction.
  • the direction perpendicular to the X direction and parallel to the top surface of the conductor 563 for example, is the Y direction, and the direction perpendicular to the top surface of the conductor 563 is the Z direction.
  • the definitions of the X direction, Y direction, and Z direction may be similar in the subsequent drawings.
  • the X direction, Y direction, and Z direction may be perpendicular to each other.
  • the X direction may be referred to as the right side or left side
  • the Y direction may be referred to as the upper side or lower side.
  • the right side may be referred to as the X direction, the left side as the -X direction, the upper side as the Y direction, and the lower side as the -Y direction.
  • the conductor 542a functions as one of the source electrode or drain electrode of the transistor 500A.
  • the conductor 542b functions as the other of the source electrode or drain electrode of the transistor 500A.
  • the insulator 555 functions as the gate insulating layer of the transistor 500A.
  • the conductor 565 functions as the gate electrode of the transistor 500A.
  • the entire region of the metal oxide 533 that overlaps with the gate electrode via the gate insulating layer between the source electrode and drain electrode functions as a channel formation region.
  • the metal oxide 533 having a region that functions as a channel formation region is sometimes called a semiconductor layer.
  • the region of the metal oxide 533 that contacts the source electrode functions as a source region, and the region that contacts the drain electrode functions as a drain region.
  • An insulator 596 is provided on the insulator 595 and on the conductor 542a.
  • the insulator 596 can function as an interlayer insulating layer.
  • the interlayer insulating layer here can be a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen (e.g., hydrogen atoms and/or hydrogen molecules).
  • Insulator 583 (insulator 583a and insulator 583b) is provided on insulator 596, and conductor 542b is provided on insulator 583.
  • Insulator 583 can function as an interlayer insulating layer.
  • the interlayer insulating layer here can be an interlayer film for isolating the source electrode and gate electrode at 500A.
  • the insulator 583a is preferably made of, for example, an oxide or an oxynitride.
  • the insulator 583a is preferably made of a film that releases oxygen when heated.
  • the insulator 583a can be made of, for example, silicon oxide or silicon oxynitride.
  • the insulator 583a can supply oxygen to the metal oxide 533 by releasing oxygen.
  • the insulator 583a can supply oxygen to the metal oxide 533 by supplying oxygen from the insulator 583a to the metal oxide 533, particularly to the channel formation region of the metal oxide 533, thereby reducing oxygen vacancies in the metal oxide 533 and hydrogen that has entered the oxygen vacancies.
  • the transistor 500A can be a highly reliable transistor that exhibits good electrical characteristics.
  • the insulator 583b has a region with a higher nitrogen content than the insulator 583a.
  • silicon nitride or silicon nitride oxide can be suitably used for the insulator 583b.
  • the insulator 583b can be a blocking layer that suppresses oxygen from being released from the insulator 583a.
  • the insulator 583 may be a single layer.
  • the insulator 583 may be a barrier insulating film, typically silicon nitride, that suppresses the diffusion of impurities such as water and hydrogen (for example, one or both of hydrogen atoms and hydrogen molecules).
  • Insulator 596 and insulator 583 have an opening 601 that reaches conductor 542a.
  • Conductor 542b has an opening 603 that reaches opening 601. In other words, opening 603 has an area that overlaps with opening 601.
  • FIG. 22A conductor 542a, conductor 542b, metal oxide 533, conductor 565, opening 601, and opening 603 are shown as components of transistor 500A.
  • FIG. 22B shows a configuration example in which conductor 565 is omitted from the elements shown in FIG. 22A. That is, FIG. 22B shows conductor 542a, conductor 542b, metal oxide 533, opening 601, and opening 603.
  • FIG. 22C shows a configuration example in which metal oxide 533 is further omitted from the elements shown in FIG. 22B. That is, FIG. 22C shows conductor 542a, conductor 542b, opening 601, and opening 603.
  • conductor 542b has an opening 603 in the area where it overlaps with conductor 542a. As shown in FIG. 22C, conductor 542b can be configured to cover the entire outer periphery of opening 601 in plan view. Here, conductor 542b is preferably not provided inside opening 601. In other words, conductor 542b is preferably not in contact with the side of insulator 583 facing opening 601.
  • FIG. 22A to 22C show an example in which the shape of the openings 601 and 603 is circular in a plan view.
  • the processing accuracy when forming the openings 601 and 603 can be improved, and the openings 601 and 603 can be formed in fine sizes.
  • a circle is not limited to a perfect circle.
  • the planar shapes of the openings 601 and 603 may be elliptical, or may be a shape including a curve. Or, they may be polygonal.
  • the end of the conductor 542b on the opening 603 side coincides with or roughly coincides with the end of the insulator 583 on the opening 601 side. It can also be said that the planar shape of the opening 603 coincides with or roughly coincides with the planar shape of the opening 601.
  • the end of the conductor 542b on the opening 603 side refers to the bottom end of the conductor 542b on the opening 603 side.
  • the bottom surface of the conductor 542b refers to the surface on the insulator 583 side.
  • the end of the insulator 583 on the opening 601 side refers to the top end of the insulator 583 on the opening 601 side.
  • the top surface of the insulator 583 refers to the surface on the conductor 542b side.
  • the planar shape of the opening 603 refers to the planar shape of the bottom end of the conductor 542b on the opening 603 side.
  • the planar shape of the opening 601 refers to the planar shape of the top end of the insulator 583 on the opening 601 side.
  • ends that match or roughly match can also be said to mean that the ends are aligned or roughly aligned.
  • ends are aligned or roughly aligned, and when the planar shapes are aligned or roughly aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a planar view. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or partially using the same mask pattern.
  • the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, in which case it is also said that the ends are roughly aligned or the planar shapes are roughly aligned.
  • the opening 601 can be formed, for example, by using the resist mask used to form the opening 603. Specifically, first, an insulator 596 is formed on the conductor 542a and on the insulator 595, an insulator 583 is formed on the insulator 596, a conductive film that will become the conductor 542b on the insulator 583, and a resist mask is formed on the conductive film. Then, an opening 603 is formed in the conductive film using the resist mask, and then an opening 601 is formed in the insulator 596 and the insulator 583 using the resist mask, so that the edge of the opening 601 and the edge of the opening 603 can be aligned or approximately aligned. Such a configuration can simplify the process.
  • the metal oxide 533 is provided so as to cover the openings 601 and 603 and have a region located inside the openings 601 and 603.
  • the metal oxide 533 has a shape that follows the shapes of the upper surface and side surfaces of the conductor 542b, the side surfaces of the insulator 583, the side surfaces of the insulator 596, and the upper surface of the conductor 542a.
  • the metal oxide 533 has a region that contacts, for example, the upper surface and side surfaces of the conductor 542b, the side surfaces of the insulator 583, and the upper surface of the conductor 542a.
  • metal oxide 533 covers the end of conductor 542b on the opening 603 side.
  • FIG. 22D shows a configuration in which the end of metal oxide 533 is located on conductor 542b. It can also be said that the end of metal oxide 533 contacts the upper surface of conductor 542b.
  • the metal oxide 533 has a single-layer structure in FIG. 22D, one embodiment of the present invention is not limited to this.
  • the metal oxide 533 may have a stacked structure of two or more layers.
  • the insulator 555 which functions as a gate insulating layer of the transistor 500A, is provided so as to cover the openings 601 and 603 and have a region located inside the openings 601 and 603.
  • the insulator 555 is provided on the metal oxide 533, the conductor 542b, and the insulator 583.
  • the insulator 555 can have a region in contact with the top and side surfaces of the metal oxide 533, the top and side surfaces of the conductor 542b, the top surface of the insulator 583, and the top surface of the insulator 596.
  • the insulator 555 has a shape that follows the shapes of the top surface of the insulator 596, the top surface of the insulator 583, the top surface and side surfaces of the conductor 542b, and the top and side surfaces of the metal oxide 533.
  • the conductor 565 which functions as the gate electrode of the transistor 500A, is provided on the insulator 555 and can have a region in contact with the top surface of the insulator 555.
  • the conductor 565 has a region that overlaps with the metal oxide 533 via the insulator 555.
  • the conductor 565 has a shape that follows the shape of the top surface of the insulator 555.
  • conductor 565 in openings 601 and 603, conductor 565 has an area where it overlaps with metal oxide 533 via insulator 555.
  • conductor 565 has an area where it overlaps with conductor 542a and conductor 542b via insulator 555 and metal oxide 533.
  • Conductor 565 covers the entire metal oxide 533.
  • Transistor 500A is a so-called top-gate type transistor that has a gate electrode above metal oxide 533. Furthermore, since the bottom surface of metal oxide 533 has an area in contact with the source electrode and drain electrode, it can be said to be a TGBC (Top Gate Bottom Contact) type transistor.
  • TGBC Top Gate Bottom Contact
  • Transistor 500A is a transistor in which at least a portion of a semiconductor layer including a channel formation region is provided along a side surface of an insulating layer in an opening formed in the insulating layer. In this specification and the like, such a transistor may be referred to as a vertical transistor.
  • the source electrode and drain electrode are located at different heights, so current flows in the height direction (vertical direction) in the channel formation region of the semiconductor layer.
  • the channel length direction has a height (vertical) component. Therefore, the above-mentioned vertical transistor can also be called a VFET (Vertical Field Effect Transistor), a vertical channel transistor, or a vertical channel transistor.
  • VFET Vertical Field Effect Transistor
  • the source region, the channel formation region, and the drain region can be at least partially overlapped when viewed from above, so the area occupied (also called the footprint) can be made small.
  • the area occupied also called the footprint
  • the on-resistance can be made small (the on-current can be made large).
  • Figure 23A is an enlarged plan view showing an example of the configuration of transistor 500A shown in Figure 22A and its surroundings.
  • Figure 23B is an enlarged cross-sectional view showing an example of the configuration of transistor 500A shown in Figure 22D and its surroundings.
  • the region in contact with the conductor 542a functions as one of the source region and the drain region
  • the region in contact with the conductor 542b functions as the other of the source region and the drain region
  • the region between the source region and the drain region functions as a channel formation region
  • the channel length of transistor 500A is the distance between the source region and the drain region.
  • the channel length L500 of transistor 500A is indicated by a dashed double-headed arrow.
  • channel length L500 is the distance between the end of the region where metal oxide 533 and conductor 542a contact, and the end of the region where metal oxide 533 and conductor 542b contact.
  • the channel length L500 of the transistor 500A corresponds to the length of the side of the insulator 583 on the opening 601 side when viewed from the XZ plane.
  • the channel length L500 is determined by the film thickness T583 of the insulator 583, and is not affected by the performance of the exposure device used to fabricate the transistor. Therefore, the channel length L500 can be made smaller than the limit resolution of the exposure device, and a transistor of a fine size can be realized.
  • the channel length L500 is preferably 0.0010 ⁇ m or more, that is, 1 nm or more, and is preferably 0.010 ⁇ m or more and less than 3.0 ⁇ m, more preferably 0.050 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.10 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.15 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 3.0 ⁇ m, and even more preferably 0.20 ⁇ m or more and less than 2.5 ⁇ m.
  • the thickness is 0.20 ⁇ m or more and less than 2.0 ⁇ m, even more preferably, 0.20 ⁇ m or more and less than 1.5 ⁇ m, even more preferably, 0.30 ⁇ m or more and less than 1.5 ⁇ m, even more preferably, 0.30 ⁇ m or more and less than 1.2 ⁇ m, even more preferably, 0.40 ⁇ m or more and less than 1.2 ⁇ m, even more preferably, 0.40 ⁇ m or more and less than 1.0 ⁇ m, even more preferably, 0.50 ⁇ m or more and less than 1.0 ⁇ m.
  • the thickness T583 of the insulator 583 is indicated by a dashed line with a double-headed arrow.
  • the memory cell MC can be miniaturized. This allows the memory density to be increased, resulting in a semiconductor device with a large memory capacity.
  • the on-current of the transistor 500A can be increased, allowing the memory cell MC to be driven at high speed.
  • the channel length L500 can be controlled by adjusting the film thickness T583 of the insulator 596 and the insulator 583.
  • the film thickness T583 of the insulator 596 and the insulator 583 is preferably 0.0010 ⁇ m or more, i.e., 1 nm or more, and is preferably 0.010 ⁇ m or more and less than 3.0 ⁇ m, more preferably 0.050 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.10 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.15 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 3.0 ⁇ m, and even more preferably 0.20 ⁇ m or more and less than 2.
  • 0.20 ⁇ m or more and less than 2.0 ⁇ m is even more preferable
  • 0.20 ⁇ m or more and less than 1.5 ⁇ m is even more preferable
  • 0.30 ⁇ m or more and less than 1.5 ⁇ m is even more preferable
  • 0.30 ⁇ m or more and 1.2 ⁇ m or less is even more preferable
  • 0.40 ⁇ m or more and 1.2 ⁇ m or less is even more preferable
  • 0.40 ⁇ m or more and 1.0 ⁇ m or less is even more preferable
  • 0.50 ⁇ m or more and 1.0 ⁇ m or less is even more preferable.
  • FIG. 23B shows a configuration in which the shape of the side of insulator 596 and insulator 583 on the opening 601 side is straight in cross section, but this is not a limitation of one embodiment of the present invention.
  • the shape of the side of insulator 596 and insulator 583 on the opening 601 side may be curved, and the side may have both straight and curved regions.
  • the channel width of the transistor 500A is the width of the source region or the width of the drain region in a direction perpendicular to the channel length direction.
  • the channel width is the width of the region where the metal oxide 533 and the conductor 542a contact, or the width of the region where the metal oxide 533 and the conductor 542b contact, in a direction perpendicular to the channel length direction.
  • the channel width of the transistor 500A is described as the width of the region where the metal oxide 533 and the conductor 542b contact, in a direction perpendicular to the channel length direction.
  • the channel width W500 of the transistor 500A is indicated by a solid double-headed arrow.
  • the channel width W500 is the length of the bottom end of the conductor 542b on the opening 603 side in a plan view.
  • the channel width W500 is determined by the planar shape of the opening 603.
  • the width D500 of the opening 603 is indicated by a two-dot dashed line with a double arrow.
  • the width D500 indicates the short side of the smallest rectangle that circumscribes the opening 603 in a planar view.
  • the width D500 of the opening 603 is equal to or greater than the limit resolution of the exposure device.
  • the width D500 is, for example, preferably 0.20 ⁇ m or more and less than 5.0 ⁇ m, more preferably 0.20 ⁇ m or more and less than 4.5 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 4.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 3.5 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 2.5 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 2.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 1.5 ⁇ m, even more preferably 0.30 ⁇ m or more and less than 1.5 ⁇ m, even more preferably 0.30 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and
  • the width D500 corresponds to the diameter of the opening 603
  • the channel width W500 can be made equal to the length of the outer periphery of the opening 603 in a planar view, and can be calculated as "D500 x ⁇ ".
  • the size of the transistor 500A is small, by applying the transistor 500A to the element layer 30 and the multiple element layers 40, the memory density can be increased, and a semiconductor device having a memory section with a high memory capacity can be provided.
  • the operation of the transistor 500A is fast, by applying the transistor 500A to a semiconductor device, a semiconductor device with a high driving speed can be provided.
  • the electrical characteristics of the transistor 500A are stable, by applying the transistor 500A to a semiconductor device, a semiconductor device with high reliability can be provided.
  • the amount of off-current of the transistor 500A is small, by applying the transistor 500A to a semiconductor device, a semiconductor device with low power consumption can be provided.
  • the transistor 500A can also be used, for example, as a transistor in a circuit other than the memory cell MC. It can also be used in combination with another transistor configuration, such as the semiconductor device 10V_2 shown in FIG. 24, in which the element layer 30 having the transistor 500 described in FIG. 17 is combined. This configuration allows transistors with different transistor characteristics to be stacked, making it possible to arrange the circuit according to the switching characteristics.
  • Embodiment 4 electronic components, electronic devices, large scale computers, space equipment, and data centers (also referred to as data centers (DCs)) in which the semiconductor device described in the above embodiment can be used will be described.
  • the electronic components, electronic devices, large scale computers, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.
  • FIG. 25A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 709 is mounted.
  • the electronic component 709 shown in FIG. 25A has a semiconductor device 710 in a mold 711. In FIG. 25A, some parts are omitted in order to show the inside of the electronic component 709.
  • the electronic component 709 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714.
  • the electronic component 709 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716.
  • the memory layer 716 is configured by stacking a plurality of memory cell arrays.
  • the stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) and bonding technology such as Cu-Cu direct bonding.
  • TSV Through Silicon Via
  • bonding technology such as Cu-Cu direct bonding.
  • the memory as an on-chip memory, it is possible to reduce the size of the connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).
  • the multiple memory cell arrays in the memory layer 716 are formed using OS transistors and the multiple memory cell arrays are monolithically stacked.
  • OS transistors By configuring the multiple memory cell arrays as monolithic stacks, it is possible to improve either or both of the memory bandwidth and the memory access latency.
  • the bandwidth is the amount of data transferred per unit time
  • the access latency is the time from access to the start of data exchange.
  • Si transistors when Si transistors are used for the memory layer 716, it is difficult to configure the memory layer 716 as a monolithic stack compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in the monolithic stack configuration.
  • the semiconductor device 710 may also be referred to as a die.
  • a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into cubes.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.
  • the package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 may be, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer is sometimes called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode is provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrode.
  • a TSV can also be used as the through electrode.
  • the interposer that implements the HBM requires fine, high-density wiring. For this reason, it is preferable to use a silicon interposer for the interposer that implements the HBM.
  • silicon interposers Furthermore, in SiP and MCM using silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
  • a composite structure may be used that combines a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 25B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • FIG. 26A a perspective view of an electronic device 6500 is shown in FIG. 26A.
  • the electronic device 6500 shown in FIG. 26A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a semiconductor device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.
  • the electronic device 6600 shown in FIG. 26B is an information terminal that can be used as a notebook personal computer.
  • the electronic device 6600 has a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like.
  • the control device 6616 has, for example, one or more selected from a CPU, a GPU, and a semiconductor device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention for the above-mentioned control device 6509 and the control device 6616 is preferable because power consumption can be reduced.
  • Fig. 26C shows a perspective view of the large scale computer 5600.
  • the large scale computer 5600 shown in Fig. 26C has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • Computer 5620 can have the configuration shown in the perspective view of FIG. 26D, for example.
  • computer 5620 has motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • PC card 5621 is inserted into slot 5631.
  • PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.
  • PC card 5621 shown in FIG. 26E is an example of a processing board equipped with a CPU, a GPU, a semiconductor device, and the like.
  • PC card 5621 has board 5622.
  • Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629.
  • FIG. 26E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for those semiconductor devices, please refer to the explanation of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 described below.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5628 include a semiconductor device.
  • the electronic component 709 can be used as the semiconductor device 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment, such as equipment for processing and storing data.
  • the semiconductor device of one embodiment of the present invention can include an OS transistor.
  • the OS transistor has small fluctuations in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident.
  • the OS transistor can be preferably used in outer space.
  • FIG. 27 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • FIG. 27 shows a planet 6804 in outer space.
  • outer space refers to an altitude of 100 km or more, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the above-mentioned battery management system or battery control circuit is preferable because it has low power consumption and high reliability even in outer space.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the power required for the operation of the satellite 6800 is generated.
  • the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated.
  • the solar panel may be called a solar cell module.
  • Satellite 6800 can generate a signal.
  • the signal is transmitted via antenna 6803, and can be received, for example, by a receiver installed on the ground or by another satellite.
  • the position of the receiver that received the signal can be measured.
  • satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a semiconductor device.
  • a semiconductor device according to one embodiment of the present invention is preferably used for the control device 6807.
  • an OS transistor Compared to a Si transistor, an OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure. In other words, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor. For example, by configuring it to have a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground. Or, by configuring it to have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is given as an example of space equipment, but the invention is not limited thereto.
  • a semiconductor device according to one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the semiconductor device can be suitably used in a storage system applied to a data center or the like.
  • the data center is required to perform long-term data management, such as ensuring the immutability of data.
  • long-term data management such as ensuring the immutability of data.
  • a semiconductor device By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. This reduces adverse effects of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. This improves the reliability of the data center.
  • FIG. 28 shows a storage system applicable to a data center.
  • the storage system 7000 shown in FIG. 28 has multiple servers 7001sb as hosts 7001 (illustrated as Host Computer). It also has multiple semiconductor devices 7003md as storage 7003 (illustrated as Storage).
  • the host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).
  • SAN Storage Area Network
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • Storage 7003 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage.
  • cache memory is usually provided within the storage to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.
  • OS transistors as transistors for storing data in the above-mentioned cache memory and configuring it to hold a potential according to the data, it is possible to reduce the frequency of refreshing and lower power consumption.
  • configuring the memory cell array in a stacked structure it is possible to reduce the size.
  • the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.
  • CO 2 greenhouse gases
  • a transistor and a memory device according to one embodiment of the present invention were fabricated.
  • Figure 29A shows a schematic top view of the memory device
  • Figure 29B shows a schematic perspective view.
  • the memory device has a plurality of wirings WL and a plurality of wirings BL.
  • One memory cell MC is disposed at the intersection of the wirings WL and BL.
  • a vertical transistor (VFET) is stacked with a trench capacitor therebelow.
  • VFET vertical transistor
  • the area of the memory cells MC is 0.0144 ⁇ m 2.
  • a memory device in which the arrangement intervals of the memory cells MC are 260 nm both vertically and horizontally was fabricated.
  • FIG. 29C shows a perspective view with a part cut out from FIG. 29B.
  • the vertical transistor has an oxide semiconductor film (OS) in an opening (channel hole) provided in an interlayer insulating film.
  • a MIM (Metal Insulator Metal) capacitor is used as the trench capacitor.
  • a wiring PL is provided at the bottom of the trench capacitor.
  • Figure 30A is a 3D image created by performing continuous cross-sectional observation (slice & view) of the prototype memory device using a scanning electron microscope (SEM). The slice pitch is approximately 10 nm. Figure 30A shows an area of 4 ⁇ m x 5 ⁇ m. The area indicated by the dashed line is not shown.
  • Figure 30B is an enlarged view of region P in Figure 30A.
  • Figures 30C and 30D are cross-sectional views at heights Q and R in Figure 30B, respectively.
  • the fabricated vertical transistor uses an oxide semiconductor as the semiconductor in which the channel is formed, and the diameter of the channel hole is about 60 nm and the depth (channel length) is about 35 nm.
  • oxide semiconductor an In-Ga-Zn oxide film with a thickness of about 5 nm formed by the ALD method and an In-Ga-Zn oxide film with a thickness of about 2 nm formed by the sputtering method were used.
  • the upper electrode used an Si-containing In-Sn oxide film formed by the sputtering method
  • the lower electrode used a laminated film of a Ti nitride film, a W film, and an Si-containing In-Sn oxide film.
  • FIG. 31 The Id-Vg characteristics of the fabricated vertical transistor are shown in Figure 31.
  • the vertical axis is drain current (Id [A]) and the horizontal axis is gate voltage (Vg [V]).
  • Figure 31 shows two types of electrical characteristics when the drain voltage (Vd) is 0.1 V and 1.2 V. Nine measurements were taken for each case. As shown in Figure 31, it was confirmed that the fabricated vertical transistor has an extremely low off-current, a sufficiently large on/off ratio, and good electrical characteristics.
  • the operating speed of the write operation and the read operation of one embodiment of the present invention was estimated.
  • the estimation of the operating speed of the semiconductor device 10D of FIG. 11 described in the second embodiment above is described.
  • Figure 32A is a diagram explaining the read operation of the semiconductor device 10D.
  • Figure 32B is a diagram explaining the write operation of the semiconductor device 10D.
  • the input/output control circuit 91 has a function of controlling the reading of information to the semiconductor device 10D and the writing of information from the semiconductor device 10D.
  • the input/output control circuit 91 has a function of supplying the signals BW, CE, GW, CLK, WAKE, ADDR, PON1, and PON2 to the semiconductor device 10D.
  • data to be written to the semiconductor device 10D (signal WDA) is supplied from the input/output control circuit 91 to the semiconductor device 10D.
  • data read from the semiconductor device 10D (signal RDA) is supplied to the input/output control circuit 91.
  • the data read operation is executed in synchronization with a clock signal (signal CLK).
  • the input/output control circuit 91 supplies the row address of the memory cell from which data is to be read to the drive circuit 61.
  • the wiring WL specified by the row address is selected, and data of the memory cell connected to the wiring WL is supplied to the wiring BL connected to the sense amplifier circuit 66.
  • the third cycle (Cycle 3) of the signal CLK the data supplied to the wiring BL is amplified by the sense amplifier circuit 66 and supplied to the input/output control circuit 91.
  • the data write operation is also performed in synchronization with the clock signal (signal CLK).
  • the input/output control circuit 91 supplies the row address of the memory cell to which data is to be written to the drive circuit 61.
  • the wiring WL specified by the row address is selected, and the memory node of the memory cell connected to the wiring WL is connected to the sense amplifier circuit 66 via the wiring BL.
  • the input/output control circuit 91 supplies the signal WDA to the sense amplifier circuit 66.
  • the signal WDA amplified by the sense amplifier circuit 66 is supplied to the wiring BL.
  • the fourth cycle (Cycle 4) of the signal CLK the signal WDA is written to the memory cell.
  • the content described in one embodiment can be applied to, combined with, or replaced with another content described in that embodiment (or even a part of the content) and/or the content described in one or more other embodiments (or even a part of the content).
  • a figure (or a part of it) described in one embodiment can be combined with another part of that figure, with another figure (or a part of it) described in that embodiment, and/or with one or more figures (or a part of it) described in another embodiment to form even more figures.
  • the components in the block diagrams are classified by function and shown as independent blocks.
  • it is difficult to separate components by function and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits.
  • the blocks in the block diagrams are not limited to the components described in the specification and may be rephrased appropriately depending on the situation.
  • the terms "one of the source or drain” (or first electrode or first terminal) and “the other of the source or drain” (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.
  • electrode and “wiring” used in this specification and elsewhere do not limit the functionality of these components.
  • an “electrode” may be used as part of a “wiring”, and vice versa.
  • the terms “electrode” and “wiring” also include cases where multiple “electrodes” or “wirings” are formed as a single unit.
  • Voltage refers to the potential difference from a reference potential, and if the reference potential is a ground voltage (earth voltage), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.
  • film and “layer” may be interchangeable depending on the circumstances.
  • conductive layer may be changed to the term “conductive film.”
  • insulating film may be changed to the term “insulating layer.”
  • a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows.
  • a switch refers to a device that has the function of selecting and switching the path through which a current flows.
  • the channel length of a planar transistor refers to, for example, the distance between the source and drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is on) and the gate overlap in a top view of the transistor, or in the region where the channel is formed.
  • the channel width refers to, for example, the length of the area where the semiconductor (or the part of the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the part where the source and drain face each other in the area where the channel is formed.
  • a node can be referred to as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, wiring, etc. can be referred to as a node.
  • a and B are connected means that A and B are electrically connected.
  • a and B are electrically connected means a connection that allows transmission of an electrical signal between A and B when an object (referring to an element such as a switch, transistor element, or diode, or a circuit including said element and wiring) exists between A and B.
  • a and B being electrically connected includes the case where A and B are directly connected.
  • a and B being directly connected means a connection that allows transmission of an electrical signal between A and B via wiring (or electrodes) between A and B, without going through the object.
  • a direct connection means a connection that can be regarded as the same circuit diagram when expressed as an equivalent circuit.

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Citations (5)

* Cited by examiner, † Cited by third party
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JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
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