WO2024183041A1 - 扫描驱动电路及其控制方法、显示面板、显示装置 - Google Patents

扫描驱动电路及其控制方法、显示面板、显示装置 Download PDF

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Publication number
WO2024183041A1
WO2024183041A1 PCT/CN2023/080359 CN2023080359W WO2024183041A1 WO 2024183041 A1 WO2024183041 A1 WO 2024183041A1 CN 2023080359 W CN2023080359 W CN 2023080359W WO 2024183041 A1 WO2024183041 A1 WO 2024183041A1
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Prior art keywords
signal
terminal
node
clock signal
control
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PCT/CN2023/080359
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English (en)
French (fr)
Inventor
肖邦清
王本莲
郑海
胡明
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2023/080359 priority Critical patent/WO2024183041A1/zh
Publication of WO2024183041A1 publication Critical patent/WO2024183041A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a scan drive circuit and a control method thereof, a display panel, and a display device.
  • the scanning drive circuit is an important auxiliary circuit in the active matrix organic light-emitting diode (AMOLED) display.
  • the existing scanning drive circuit includes a plurality of cascaded shift registers. However, the brightness uniformity of the display device equipped with the scanning drive circuit is poor.
  • a scan drive circuit comprising a plurality of clock signal lines and a plurality of cascaded shift registers;
  • the shift register comprises an input subcircuit, a first control subcircuit, a second control subcircuit and an output subcircuit;
  • the input subcircuit is connected to a start signal terminal, a first node and a first signal terminal, and the input subcircuit is configured to write a signal from the start signal terminal into the first node under the control of a signal from the first signal terminal;
  • the first control subcircuit is connected to the first signal terminal, a second node and the first node, and the first control subcircuit is configured to write a signal from the first signal terminal into the second node under the control of a signal from the first node;
  • the second control subcircuit is connected to the first signal terminal, a second node and the first node, and the first control subcircuit is configured to write a signal from the first signal terminal into the second node under the control of a signal from the first node;
  • the plurality of clock signal lines are divided into a plurality of clock signal line groups, each of which The clock signal line group includes multiple clock signal lines; the multiple clock signal line groups include a first clock signal line group and a second clock signal line group, the third signal terminal in the two cascaded shift registers is connected to different clock signal lines in the first clock signal line group, and the second signal terminal in the two cascaded shift registers is connected to different clock signal lines in the second clock signal line group.
  • the first signal terminal in the two cascaded shift registers is connected to different clock signal lines in the second clock signal line group, and in the same shift register, the first signal terminal and the second signal terminal are connected to different clock signal lines in the second clock signal line group.
  • the clock signal line includes a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line
  • the multiple shift registers include a cascaded first shift register and a second shift register; in the first shift register, the first signal terminal is connected to the first clock signal line, the second signal terminal is connected to the second clock signal line, and the third signal terminal is connected to the fourth clock signal line; in the second shift register, the first signal terminal is connected to the second clock signal line, the second signal terminal is connected to the first clock signal line, and the third signal terminal is connected to the third clock signal line.
  • the plurality of shift registers include a plurality of the first shift registers and a plurality of the second shift registers, and the first shift registers and the second shift registers are arranged in an alternating manner.
  • the multiple shift registers also include a fifth shift register and a sixth shift register, and the first shift register, the second shift register, the fifth shift register, and the sixth shift register are cascaded in sequence; in the fifth shift register, the first signal terminal is connected to the third clock signal line, the second signal terminal is connected to the fourth clock signal line, and the third signal terminal is connected to the second clock signal line; in the sixth shift register, the first signal terminal is connected to the fourth clock signal line, the second signal terminal is connected to the third clock signal line, and the third signal terminal is connected to the first clock signal line.
  • the clock signal line further includes a fifth clock signal line and a sixth clock signal line
  • the plurality of shift registers further include a third shift register and a fourth shift register, the first shift register, the second shift register, the third shift register, and the fourth shift register are sequentially arranged and cascaded; in the third shift register, the first signal terminal is connected to the The fifth clock signal line is connected, the second signal terminal is connected to the sixth clock signal line, and the third signal terminal is connected to the fourth clock signal line; in the fourth shift register, the first signal terminal is connected to the sixth clock signal line, the second signal terminal is connected to the fifth clock signal line, and the third signal terminal is connected to the third clock signal line.
  • the second control subcircuit includes a sixth transistor and a seventh transistor; the sixth transistor has a gate connected to the second node, a first electrode connected to the second voltage terminal, and a second electrode connected to a third node; the seventh transistor has a gate connected to the third signal terminal, a first electrode connected to the third node, and a second electrode connected to the first node.
  • the output subcircuit includes a fourth transistor, a fifth transistor, a first capacitor and a second capacitor; the fourth transistor has a gate connected to the second node, a first electrode connected to the second voltage terminal, and a second electrode connected to the output terminal; the fifth transistor has a gate connected to the first node, a first electrode connected to the second signal terminal, and a second electrode connected to the output terminal; the first capacitor has one plate connected to the second voltage terminal and the other plate connected to the second node; the second capacitor has one plate connected to the output terminal and the other plate connected to the first node.
  • the input subcircuit includes a first transistor; the first transistor has a gate connected to the first signal terminal, a first electrode connected to the start signal terminal, and a second electrode connected to the first node.
  • the first control subcircuit includes a second transistor; the second transistor has a gate connected to the first node, a first electrode connected to the first signal terminal, and a second electrode connected to the second node.
  • the first control subcircuit is further connected to the first voltage terminal, and the first control subcircuit is further configured to write the signal of the first voltage terminal into the second node under the control of the signal of the first signal terminal.
  • the first control subcircuit includes a third transistor; the third transistor has a gate connected to the first signal terminal, a first electrode connected to the first voltage terminal, and a second electrode connected to the second node.
  • a display panel comprising the scanning driving circuit and a plurality of pixel driving circuits, wherein an output end of the scanning driving circuit is connected to the pixel driving circuit.
  • a display device comprising the display panel.
  • a control method of a scan driving circuit which is used to control the scan driving circuit, wherein the same frame period includes a first stage and a second stage, and the control method includes:
  • a first clock signal is provided to the first signal terminal, a second clock signal is provided to the second signal terminal, and a third clock signal is provided to the third signal terminal, so that:
  • the input subcircuit is turned on under the control of the signal at the first signal terminal, and writes the signal at the start signal terminal into the first node;
  • the first control subcircuit is turned on under the control of the signal of the first node, and writes the signal of the first signal terminal into the second node;
  • the second control subcircuit remains turned off under the control of the signal of the second node and the third signal terminal;
  • the output subcircuit is turned on under the control of the signal of the first node and the second node, and writes the signal of the second signal terminal and the second voltage terminal into the output terminal;
  • a first clock signal is provided to the first signal terminal
  • a second clock signal is provided to the second signal terminal
  • a third clock signal is provided to the third signal terminal, so that:
  • the input subcircuit remains turned off under the control of the first clock signal
  • the first control subcircuit is turned on under the control of the signal of the first node, and writes the signal of the first signal terminal into the second node;
  • the second control subcircuit remains turned off under the control of the signal at the third signal terminal and the second node;
  • the output subcircuit is turned on under the control of the signals of the second node and the first node, and writes the signal of the second signal terminal into the output terminal.
  • the effective level period of the second signal overlaps with the effective level period of the third signal, and the leading edge of the effective level in the second signal is earlier than the leading edge of the effective level in the third signal.
  • a duty cycle of the second signal is less than or equal to a duty cycle of the third signal.
  • FIG1 schematically shows a front view structure of a display device
  • FIG2 schematically shows a structural block diagram of a display panel
  • FIG3 schematically shows a circuit diagram of a pixel driving circuit
  • FIG4 is a circuit diagram of a shift register in the related art
  • FIG5 is a timing diagram of the operation of the shift register shown in FIG4 ;
  • FIG6 schematically shows a structural block diagram of a shift register
  • FIG7 schematically shows a block diagram of another structure of a shift register
  • FIG8 schematically shows a circuit diagram of a shift register
  • FIG9 schematically shows a working timing diagram of a shift register
  • FIG10 schematically shows another operation timing diagram of a shift register
  • FIG11 schematically shows a partial circuit diagram of a scan driving circuit
  • FIG12 is a partial layout diagram of the scan drive circuit shown in FIG11;
  • FIG13 schematically shows a timing diagram of a scan driving circuit
  • FIG14 schematically shows a potential waveform diagram of each node of the shift register after Vth is negatively biased
  • FIG15 schematically shows a potential waveform diagram of each node of the shift register after Vth is positively biased
  • FIG16 schematically shows a structural block diagram of another display panel
  • FIG17 schematically shows a circuit diagram of a scan driving circuit
  • FIG18 schematically shows a timing diagram of a scan driving circuit
  • FIG19 schematically shows a structural block diagram of yet another display panel
  • FIG20 schematically shows a partial circuit diagram of a scan driving circuit
  • FIG21 schematically shows a timing diagram of a scan driving circuit
  • FIG. 22 schematically shows a block diagram of the steps of a control method of a scan driving circuit.
  • the expressions “electrically connected” and “connected” and their derivatives may be used.
  • the term “point connection” may be used to indicate that two or more components are in direct physical or electrical contact with each other.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • FIG1 takes the display device 100 as a mobile phone as an example for illustration.
  • the display device 100 includes a display panel 110.
  • the display panel 110 may be a liquid crystal display panel (LCD); the display panel 110 may also be an electroluminescent display panel or a photoluminescent display panel.
  • the electroluminescent display panel may be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel.
  • the photoluminescent display device may be a quantum dot photoluminescent display panel.
  • the display panel 110 as an organic light-emitting diode (OLED) display panel as an example.
  • OLED organic light-emitting diode
  • the display panel 110 may be provided with a scanning drive circuit and a plurality of sub-pixels.
  • the sub-pixels include a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit.
  • the scanning drive circuit includes a plurality of clock signal lines and a plurality of cascaded shift registers, and the output end of the shift register is electrically connected to the pixel driving circuit.
  • a clock signal may be passed into each clock signal line to control the shift register to output a scanning signal step by step, and the pixel driving circuit drives the light-emitting device to emit light under the control of the scanning signal.
  • FIG2 schematically shows a block diagram of a structure of a display panel.
  • the display panel 110 can be divided into a display area 110a and a non-display area 110b connected to the display area 110a, a plurality of sub-pixels 111 are arranged in the display area 110a, and a scan drive circuit is arranged in the non-display area 110b.
  • a scan drive circuit is arranged in the non-display area 110b.
  • at least part of the structure of the scan drive circuit can also be arranged in the display area 110a.
  • FIG3 schematically shows a circuit diagram of a pixel driving circuit.
  • the pixel driving circuit includes a light emitting control terminal EM, a data writing control signal terminal Gate, and a reset control signal terminal Reset.
  • the pixel driving circuit can be configured to have a light emitting control terminal EM, a data writing control signal terminal Gate, and a reset control signal terminal Reset.
  • the light emitting device OLED is driven to emit light under the control of the signal of the reset control signal terminal Reset.
  • the output end of the shift register can be electrically connected to the data writing control signal end Gate and/or the reset control signal end Reset, or can be electrically connected to the light emitting control end EM.
  • the following is only an example of the output end of the shift register being electrically connected to the data writing control signal end Gate and/or the reset control signal end Reset.
  • a pixel driving circuit with a 7T1C structure is taken as an example.
  • the pixel driving circuit may also be a 4T1C, 6T1C, 6T2C, 7T2C, 8T2C or other structure.
  • the embodiment of the present disclosure does not limit the structure of the pixel driving circuit.
  • T represents a transistor
  • the number in front of T represents the number of transistors
  • C represents a capacitor
  • the number in front of C represents the number of capacitors.
  • Fig. 4 is a circuit diagram of a shift register in the related art
  • Fig. 5 is a working timing diagram of the shift register shown in Fig. 4.
  • the working process of the shift register in the related art includes: in stage L1, the first clock signal terminal CK is at a low level, the second clock signal terminal CB is at a high level, the transistor M1, the transistor M8 and the transistor M5 are turned on, and the signal output terminal OUT outputs a high level signal; in stage L2, the first clock signal terminal CK is at a high level, the second clock signal terminal CB is at a low level, the gate of the transistor M5 remains at a low level state, and the shift register outputs a low level signal through the transistor M5.
  • the luminous brightness of the light-emitting device OLED is more sensitive to the rising time/falling time (Tr/Tf) of the signal of the data writing control terminal Gate and the reset control terminal Reset.
  • the signal of the data writing control terminal Gate and the reset control terminal Reset is the shifted output of the signal of the second clock signal terminal CB.
  • the load (loading) of the signal line connected to the second clock signal terminal CB will directly affect the rising time/falling time (Tr/Tf) of the signal of the second clock signal terminal CB.
  • the load of the second clock signal terminal CB is large, so that the high and low level switching of the second clock signal terminal CB takes a long time (the signal output terminal OUT takes a long time to switch from a high level to a low level), that is, the falling edge time Tf is large, resulting in the difference between the rising edge time and the falling edge time of the data writing control terminal Gate and the reset control terminal Reset signal, causing poor display.
  • the falling edge of the signal outputted from the output end of the shift register is smaller, thereby improving the display defect.
  • Fig. 6 schematically shows a structural block diagram of a shift register.
  • the shift register includes an input subcircuit, a first control subcircuit, a second control subcircuit and an output subcircuit.
  • the input sub-circuit is connected to the start signal terminal ST, the first node N1 and the first signal terminal S1 , and is configured to write the signal of the start signal terminal ST into the first node N1 under the control of the signal of the first signal terminal S1 .
  • the input subcircuit when the signal received by the first signal terminal S1 is a low-level signal, the input subcircuit is turned on, and the signal of the start signal terminal ST is written into the first node N1.
  • the first node N1 when the signal of the start signal terminal ST is a low-level signal, the first node N1 is a low-level signal; when the signal of the start signal terminal ST is a high-level signal, the first node N1 is a high-level signal.
  • the first control subcircuit is connected to the first signal terminal S1, the first node N1, and the second node N2.
  • the first control subcircuit is configured to write the signal of the first signal terminal S1 into the second node N2 under the control of the signal of the first node N1.
  • the first control subcircuit when the signal of the first node N1 is a low level signal, the first control subcircuit is turned on, and the signal of the first signal terminal S1 is written into the second node N2.
  • the signal of the second node N2 when the signal of the first signal terminal S1 is a low level signal, the signal of the second node N2 is a low level signal; when the signal of the first signal terminal S1 is a high level signal, the signal of the second node N2 is a high level signal.
  • Fig. 7 schematically shows a structural block diagram of another shift register.
  • the first control subcircuit may also be connected to the first voltage terminal V1, and the first control subcircuit is further configured to write the signal of the first voltage terminal V1 into the second node N2 under the control of the signal of the first signal terminal S1.
  • the first control sub-circuit when the signal at the first signal terminal S1 is a low level signal, the first control sub-circuit writes the signal at the first voltage terminal V1 into the second node N2.
  • the first voltage terminal V1 is configured to provide a low level signal (eg, lower than or equal to the low level portion of the clock signal in the clock signal line).
  • the first voltage terminal V1 is connected to the Vgl line.
  • the second control subcircuit is connected to the first node N1, the second node N2, the second voltage terminal V2, and the third signal terminal S3.
  • the second control subcircuit is configured to write the signal of the second voltage terminal V2 into the first node N1 under the control of the signals of the second node N2 and the third signal terminal S3.
  • the second control subcircuit when the signals at the second node N2 and the third signal terminal S3 are both low level signals, the second control subcircuit is turned on and writes the signal at the second voltage terminal V2 into the first node N1.
  • the second voltage terminal V2 is configured to provide a DC high-level signal (eg, higher than or equal to the high-level portion of the clock signal in the clock signal line).
  • the second voltage terminal V2 is connected to the Vgh line.
  • the output sub-circuit is connected to the first node N1, the second node N2, the output terminal Gout, the second signal terminal S2, and the second voltage terminal V2.
  • the output sub-circuit is configured to output the second signal terminal S2 to the output terminal V2 under the control of the signal of the first node N1.
  • the signal of the second signal terminal S2 is written into the output terminal Gout, and is also configured to write the signal of the second voltage terminal V2 into the output terminal Gout under the control of the signal of the first node N1.
  • the second voltage terminal V2 is connected to the output terminal Gout, and the second signal terminal S2 is connected to the output terminal Gout; when the first node N1 is a low-level signal and the second node N2 is a high-level signal, the second voltage terminal V2 is disconnected from the output terminal Gout, and the second signal terminal S2 is connected to the output terminal Gout.
  • the shift register also includes a stabilizing subcircuit, which is connected to the first voltage terminal V1, the first node N1, and the fourth node N4.
  • the stabilizing subcircuit is configured to write the signal of the first node N1 into the fourth node N4, or to write the signal of the fourth node N4 into the first node N1 under the control of the signal of the first voltage terminal V1.
  • the output sub-circuit is connected to the first node N1 through the stabilizing sub-circuit.
  • the nodes in the embodiments of the present disclosure do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the junction points of related electrical connections in the circuit diagram.
  • the start signal terminal ST of the first shift register is connected to the start signal line STV, and the start signal terminals ST of the remaining shift registers are connected to the output terminal Gout of the previous shift register.
  • the same frame period includes the first phase and the second phase.
  • the input subcircuit writes the signal of the start signal terminal ST into the first node N1 under the control of the signal of the first signal terminal S1
  • the output subcircuit writes the signal of the second signal terminal S2 into the output terminal Gout under the control of the signal of the first node N1, so that the shift register outputs the signal of the second signal terminal S2 through the output terminal Gout.
  • the first control subcircuit writes the signal of the first signal terminal S1 into the second node N2 under the control of the signal of the first node N1
  • the output subcircuit writes the signal of the second voltage terminal V2 into the output terminal Gout under the control of the signal of the second node N2, so that the shift register outputs the signal of the second voltage terminal V2 through the output terminal Gout.
  • the second control subcircuit is not turned on under the control of the signal of the second node N2 and the third signal terminal S3, so that the first node N1 and the second node N2 remain disconnected.
  • the output sub-circuit writes the signal of the second signal terminal S2 into the output terminal Gout under the control of the signal of the first node N1, so that the shift register outputs the signal of the second signal terminal S2 through the output terminal Gout.
  • the first control subcircuit writes the signal of the first signal terminal S1 to the second node N2 under the control of the signal of the first node N1.
  • the second control subcircuit is not turned on under the control of the signal of the second node N2 and the third signal terminal S3, so that the first node N1 and the second node N2 remain disconnected.
  • the signal at the first signal terminal S1 is a low level signal
  • the signal at the second signal terminal S2 is a high level signal
  • the signal at the first signal terminal S1 is a high level signal
  • the signal at the second signal terminal S2 is a low level signal, so that the shift register outputs a high level signal in the first stage and a low level signal in the second stage.
  • the second signal terminal S2 and the third signal terminal S3 of the same shift register are connected to different clock signal lines. That is, in the same shift register, the clock signal line connected to the second signal terminal S2 is connected to the output subcircuit, but not to the second control subcircuit, which reduces the load of the clock signal line connected to the second signal terminal S2.
  • the time required for the signal of the second signal terminal S2 to switch to a high level is shorter (the time required for the output terminal Gout to switch from a high level to a low level is shorter), that is, the falling edge time Tf of the output signal of the shift register is shorter, which reduces the difference between the rising edge time and the falling edge time of the data write control terminal Gate and the reset control terminal Reset signal, and improves the display defect.
  • Fig. 8 schematically shows a circuit diagram of a shift register.
  • a shift register provided by an embodiment of the present disclosure is described in detail below.
  • the input subcircuit includes a first transistor T1.
  • the control electrode of the first transistor T1 is connected to the first signal terminal S1
  • the first electrode of the first transistor T1 is connected to the start signal terminal ST
  • the second electrode of the first transistor T1 is connected to the first node N1.
  • the first transistor T1 is configured to, in the first stage, write the signal of the start signal terminal ST to the first node N1 in response to the signal of the first signal terminal S1.
  • the first control subcircuit includes a second transistor T2.
  • the control electrode of the second transistor T2 is connected to the first node N1, the first electrode of the second transistor T2 is connected to the first signal terminal S1, and the second electrode of the second transistor T2 is connected to the second node N2.
  • the second transistor T2 is configured to write the signal of the first signal terminal S1 to the second node N2 in response to the signal of the first node N1 in the first stage and the second stage.
  • the first control subcircuit may further include a third transistor T3, wherein the control electrode of the third transistor T3 is connected to the first signal terminal S1, the first electrode of the third transistor T3 is connected to the first voltage terminal V1, and the second electrode of the third transistor T3 is connected to the second node N2.
  • the signal of the first voltage terminal V1 is written into the second node N2 in response to the signal of the first signal terminal S1.
  • the second control subcircuit includes a sixth transistor T6 and a seventh transistor T7.
  • the control electrode of the sixth transistor T6 is connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the second voltage terminal V2, and the second electrode of the sixth transistor T6 is connected to the third node N3.
  • the sixth transistor T6 is configured to write the signal of the second voltage terminal V2 to the third node N3 in response to the signal of the second node N2.
  • the control electrode of the seventh transistor T7 is connected to the third signal terminal S3, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the first node N1.
  • the seventh transistor T7 is configured to write the signal of the third node N3 into the first node N1 in response to the signal of the third signal terminal S3.
  • the output sub-circuit includes a fourth transistor T4, a fifth transistor T5, a first capacitor C1 and a second capacitor C2.
  • the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second voltage terminal V2, and the second electrode of the fourth transistor T4 is connected to the output terminal Gout.
  • the fourth transistor T4 is configured to write the signal of the second voltage terminal V2 to the output terminal Gout in response to the signal of the second node N2 in the first stage; the fourth transistor T4 is also configured to disconnect the second voltage terminal V2 and the output terminal Gout in response to the signal of the second node N2 in the second stage.
  • the control electrode of the fifth transistor T5 is connected to the first node N1, the first electrode of the fifth transistor T5 is connected to the second signal terminal S2, and the second electrode of the fifth transistor T5 is connected to the output terminal Gout.
  • the fifth transistor T5 is configured to write the signal of the second signal terminal S2 to the output terminal Gout in response to the signal of the first node N1.
  • One plate of the first capacitor C1 is connected to the second voltage terminal V2, and the other plate is connected to the second node N2.
  • the first capacitor C1 is configured to store the signal of the second node N2 so that the signal of the second node N2 does not suddenly change.
  • One plate of the second capacitor C2 is connected to the output terminal Gout, and the other plate is connected to the first node N1.
  • the second capacitor C2 is configured to store the signal of the first node N1 so that the signal of the first node N1 does not suddenly change.
  • the stabilization subcircuit includes an eighth transistor T8, a control electrode of the eighth transistor T8 is connected to the first voltage terminal V1, a first electrode of the eighth transistor T8 is connected to the first node N1, and a second electrode of the eighth transistor T8 is connected to the fourth node N4.
  • the eighth transistor T8 is configured to In response to the signal at the first voltage terminal V1, the signal at the first node N1 is written into the fourth node N4, or the signal at the fourth node N4 is written into the first node N1.
  • the control electrode of the fifth transistor T5 is connected to the fourth node N4, so that the control electrode of the fifth transistor T5 is connected to the first node N1 through the eighth transistor T8; the other plate of the second capacitor C2 is connected to the fourth node N4, so that the other plate of the second capacitor C2 is connected to the first node N1 through the eighth transistor T8.
  • the transistors used in the circuits provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors (such as oxide thin film transistors) or other switching devices with the same characteristics.
  • the embodiments of the present disclosure are described using thin film transistors as examples.
  • the control electrode of each transistor used in the shift register is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.
  • the transistors provided in the embodiments of the present disclosure are schematically described by taking a P-type transistor as an example.
  • the first signal terminal S1 of the first shift register is connected to the first clock signal line CK1
  • the second signal terminal S2 is connected to the second clock signal line CK2
  • the third signal terminal S3 is connected to the fourth clock signal line CK4
  • the start signal terminal ST is connected to the start signal line STV.
  • FIG9 schematically shows a working timing diagram of a shift register. The working process of the shift register is described in detail below by taking the first shift register as an example in combination with FIG8 and FIG9.
  • Phase 1 Both the first signal terminal S1 and the start signal terminal ST are low-level signals (valid level), and the second signal terminal S2 is high-level (invalid level).
  • the first transistor T1 is turned on under the control of the low-level signal of the first signal terminal S1, and the low-level signal of the start signal terminal ST is written into the first node N1 through the first transistor T1.
  • the eighth transistor T8 is turned on under the control of the low-level signal of the first voltage terminal V1, and the low-level signal written into the first node N1 continues to be written into the fourth node N4, thereby turning on the fifth transistor T5, and the high-level signal of the second signal terminal S2 is written into the output terminal Gout through the fifth transistor T5.
  • the second transistor T2 is turned on under the control of the low-level signal of the first node N1, and the low-level signal of the first signal terminal S1 is written into the second node N2 through the second transistor T2.
  • the third transistor T3 is turned on at the first node N1.
  • the fourth transistor T4 is turned on under the control of the low level signal of the voltage terminal V1, so that the low level signal of the first voltage terminal V1 is written into the second node N2, and the fourth transistor T4 is turned on under the control of the low level signal of the second node N2, so that the high level signal of the second voltage terminal V2 is written into the output terminal Gout through the fourth transistor T4.
  • the output terminal Gout of the shift register outputs a high level signal.
  • the second stage the first signal terminal S1 and the start signal terminal ST are both high-level signals (invalid level), and the second signal terminal S2 is a low-level signal (valid level).
  • the fourth node N4 can maintain the low-level signal of the first stage (under the action of the second capacitor C2), and the fifth transistor T5 remains turned on. After the signal at the second signal terminal S2 is switched from a high-level signal to a low-level signal, the low-level signal of the second signal terminal S2 is written to the output terminal Gout through the fifth transistor T5.
  • the first node N1 can maintain the low-level signal of the first stage (under the action of the second capacitor C2), so that the second transistor T2 is turned on, and the high-level signal of the first signal terminal S1 is written to the second node N2 through the second transistor T2, and the potential of the second node N2 is pulled up, so that the fourth transistor T4 and the sixth transistor T6 are turned off.
  • the shift register outputs a low-level signal through the output terminal Gout.
  • the third stage the first signal terminal S1 is a low-level signal (valid level), and the start signal terminal ST and the second signal terminal S2 are both high-level signals (invalid level).
  • the first transistor T1 is turned on under the control of the low-level signal of the first signal terminal S1, and the high-level signal of the start signal terminal ST is written into the first node N1 through the first transistor T1.
  • the eighth transistor T8 is turned on under the control of the low-level signal of the first voltage terminal V1, so that the high-level signal written into the first node N1 continues to be written into the fourth node N4, so that the fifth transistor T5 is turned off under the control of the high-level signal of the fourth node N4.
  • the second transistor T2 is turned off under the control of the high-level signal of the first node N1, and the third transistor T3 is turned on under the control of the low-level signal of the first signal terminal S1.
  • the low-level signal of the first voltage terminal V1 is written into the second node N2 through the third transistor T3, and the fourth transistor T4 is turned on under the control of the low-level signal of the second node N2, so that the high-level signal of the second voltage terminal V2 is written into the output terminal Gout through the fourth transistor T4.
  • the shift register outputs a high-level signal through the output terminal Gout.
  • the fourth stage the first signal terminal S1 and the start signal terminal ST are both high-level signals (invalid level), and the second signal terminal S2 is a low-level signal (valid level).
  • the first node N1 and the fourth node N4 maintain the high-level signal of the third stage (under the action of the second capacitor C2), and the second transistor T2 and the fifth transistor T5 remain in a closed state under the control of the high-level signal.
  • the second node N2 maintains the low-level signal of the third stage (under the action of the first capacitor C1), so that the fourth transistor T4 remains turned on under the control of the low-level signal of the second node N2, and the high-level signal of the second voltage terminal V2 passes through the fourth transistor T4 writes to the output terminal Gout.
  • the shift register outputs a high level signal through the output terminal Gout.
  • the fifth stage the first signal terminal S1 is a low-level signal (valid level), and the start signal terminal ST and the second signal terminal S2 are both high-level signals (invalid level).
  • the first transistor T1 is turned on under the control of the low-level signal of the first signal terminal S1, and the high-level signal of the start signal terminal ST is written into the first node N1 through the first transistor T1, and then written into the fourth node N4, and the fifth transistor T5 is turned off under the control of the high-level signal of the fourth node N4.
  • the third transistor T3 is turned on under the control of the low-level signal of the first signal terminal S1, and the low-level signal of the first voltage terminal V1 is written into the second node N2 through the third transistor T3, and the fourth transistor T4 is turned on under the control of the low-level signal of the second node N2, so that the high-level signal of the second voltage terminal V2 is written into the output terminal Gout through the fourth transistor T4.
  • the shift register outputs a high-level signal through the output terminal Gout.
  • the transistor M5 and the transistor M7 of the same shift register are connected to the second clock signal terminal CB, and the second clock signal terminal CB is connected to a clock signal line.
  • the transistor M7 is turned on, and a parasitic capacitor is formed between the gate of the transistor M7 and the active layer of the transistor M7.
  • the second signal terminal S2 and the third signal terminal S3 of the same shift register are connected to different clock signal lines. That is, in the same shift register, the fifth transistor T5 and the seventh transistor T7 are connected to different clock signal lines, which reduces the load of the clock signal line connected to the fifth transistor T5.
  • the time for switching the high-low level signal is shortened (the time required for the output terminal Gout to switch from a high level to a low level is shorter), that is, the falling edge time Tf of the shift register output signal is shorter, which reduces the difference between the rising edge time and the falling edge time of the data write control terminal Gate and the reset control terminal Reset signal, and improves the display defect.
  • the seventh transistor T7 in the shift register can be turned on or off by controlling the clock signal line connected to the third signal terminal S3.
  • FIG10 schematically shows another operation timing diagram of a shift register.
  • the first signal terminal S1 of the first shift register is connected to the first clock signal line CK1
  • the second signal terminal S2 is connected to the second clock signal line CK2
  • the third signal terminal S3 is connected to the fourth clock signal line CK4
  • the start signal terminal ST is connected to the start signal line STV.
  • the moment when the third signal terminal S3 switches from a high level signal to a low level signal is the first moment t1
  • the moment when the second signal terminal S2 switches from a high level signal to a low level signal is the second moment t2, and the first moment t1 is earlier than the second moment t2.
  • the signal of the second signal terminal S2 is switched to a low level signal, and the fourth node N4 and the first node N1 remain at a low level under the action of the second capacitor C2, so that the fifth transistor T5 and the second transistor T2 are turned on.
  • the signal of the third signal terminal S3 is still a high level signal
  • the seventh transistor T7 is not turned on
  • the charge stored in the second capacitor C2 will not be released to the third node N3 through the seventh transistor T7
  • the parasitic capacitance formed between the gate of the seventh transistor T7 and the active layer will not be charged, so that the first node N1 and the fourth node N4 maintain a low level signal, so that the fifth transistor T5 and the second transistor T2 are in a better turn-on state.
  • the multiple clock signal lines in the scan driving circuit can be divided into multiple clock signal line groups, each clock signal line group includes multiple clock signal lines, and a clock signal line can only belong to one clock signal line group.
  • the multiple clock signal line groups include a first clock signal line group and a second signal line group.
  • the clock signal lines connected to the third signal terminal S3 are divided into a first clock signal line group, and the clock signal lines among the plurality of clock signal lines except those in the first clock signal line group are divided into a second clock signal line group.
  • the clock signal lines in the first clock signal line group are connected to the third signal terminal S3 of the shift register, and at least part of the clock signal lines in the second clock signal line group are connected to the second signal terminal S2. That is to say, the clock signal line connected to the second signal terminal S2 is not connected to the third signal terminal S3, so that the load of the clock signal line connected to the second signal terminal S2 is reduced, and when a high-low level signal switching occurs in the clock signal line connected to the second signal terminal S2, the time of the high-low level signal switching is shortened (the time required for the output terminal Gout to switch from a high level to a low level is shorter), that is, the falling edge time Tf of the shift register output signal is shorter, and the difference between the rising edge time and the falling edge time of the data write control terminal Gate and the reset control terminal Reset signal is reduced, thereby improving display defects.
  • the second clock signal line group includes a first sub-clock signal line group and a second sub-clock signal line group.
  • the second sub-clock signal line group is connected to an effective level.
  • the clock signal line in the second sub-clock signal line group passes through an invalid level; when the clock signal line in the second sub-clock signal line group passes through a valid level, the clock signal line in the first sub-clock signal line group passes through an invalid level.
  • the clock signal line connected to the first signal terminal S1 belongs to one of the first sub-clock signal line group and the second sub-clock signal line group
  • the clock signal line connected to the second signal terminal S2 belongs to the other of the first sub-clock signal line group and the second sub-clock signal line group.
  • the third signal terminal S3 in the two cascaded shift registers is connected to different clock signal lines in the first clock signal line CK1 group, so that the third signal terminal S3 in one of the shift registers can pass a valid level, while the third signal terminal S3 in the other shift register can pass an invalid level.
  • the second signal terminal S2 in the two cascaded shift registers is connected to different clock signal lines in the second clock signal line group, so that the second signal terminal S2 in one of the shift registers can pass a valid level, while the second signal terminal S2 in the other shift register can pass an invalid level.
  • the first signal terminal S1 in the shift register may also be connected to the clock signal line in the second clock signal line group. That is, the first signal terminal S1 and the second signal terminal S2 are both connected to the clock signal line in the second clock signal line group, and the clock signal line in the first clock signal line group is not connected to the first signal terminal S1 and the second signal terminal S2.
  • the time when the high-low level switching occurs in the clock signal line in the first clock signal line group is late, the time when the high-low level switching of the signal at the first signal terminal S1 and/or the second signal terminal S2 occurs will not be delayed.
  • the first signal terminal S1 in the two cascaded shift registers is connected to different clock signal lines in the second clock signal line group, so that the first signal terminal S1 in one of the shift registers can pass a valid level, while the first signal terminal S1 in the other shift register can pass an invalid level.
  • the first signal terminal S1 and the second signal terminal S2 are connected to different clock signal lines in the second clock signal line group, so that in the same shift register, one of the first signal terminal S1 and the second signal terminal S2 can pass a valid level, while the other can pass an invalid level.
  • clock signal lines in the first clock signal group may also be connected to the first signal terminal S1 and the second signal terminal S2.
  • the clock signal line includes a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3 and a fourth clock signal line CK4.
  • the plurality of shift registers include a cascaded first shift register 112 and a second shift register 113.
  • the first shift register 112 and the second shift register 113 may be any two cascaded shift registers among the plurality of shift registers.
  • the output terminal Gout of the first shift register 112 may be connected to the start signal terminal ST of the second shift register 113, or
  • the output terminal Gout of the second shift register 113 is connected to the start signal terminal ST of the first shift register 112.
  • the following is a schematic description by taking the output terminal Gout of the first shift register 112 and the start signal terminal ST of the second shift register 113 as an example.
  • FIG. 11 schematically shows a partial circuit diagram of a scan drive circuit
  • FIG. 12 is a partial layout diagram of the scan drive circuit shown in FIG. 11.
  • the portion in the white dotted box in FIG. 12 is the first shift register 112.
  • the first signal terminal S1 is connected to the first clock signal line CK1
  • the second signal terminal S2 is connected to the second clock signal line CK2
  • the third signal terminal S3 is connected to the fourth clock signal line CK4.
  • the first signal terminal S1 is connected to the second clock signal line CK2
  • the second signal terminal S2 is connected to the first clock signal line CK1
  • the third signal terminal S3 is connected to the third clock signal line CK3.
  • Fig. 13 schematically shows a timing diagram of the scan driving circuit shown in Fig. 2, Fig. 11 and Fig. 12.
  • the first clock signal line CK1 when the first clock signal line CK1 is at an effective level, the second clock signal line CK2 is at an ineffective level; when the second clock signal line CK2 is at an effective level, the first clock signal line CK1 is at an ineffective level; when the third clock signal line CK3 is at an effective level, the fourth clock signal line CK4 is at an ineffective level; when the fourth clock signal line CK4 is at an effective level, the third clock signal line CK3 is at an ineffective level; when the third clock signal line CK3 is at an effective level, the first clock signal line CK1 is at an effective level; when the fourth clock signal line CK4 is at an effective level, the second clock signal line CK2 is at an effective level.
  • the multiple shift registers in the scan driving circuit include multiple first shift registers 112 and multiple second shift registers 113, and the first shift registers 112 and the second shift registers 113 are arranged in an alternating manner.
  • the alternating arrangement of the first shift registers 112 and the second shift registers 113 means that they are arranged and cascaded in the order of the first shift register 112, the second shift register 113, the first shift register 112, the second shift register 113, etc. That is, the output terminal Gout of the first shift register 112 is connected to the start signal terminal ST of the second shift register 113, and the output terminal Gout of the second shift register 113 is connected to the start signal terminal ST of another first shift register 112, and so on.
  • the second clock signal line CK2 and the first clock signal line CK1 are not connected to the seventh transistor T7, so that the load of the second clock signal line CK2 and the first clock signal line CK1 is reduced.
  • the high-low level signal switching occurs in the first clock signal line CK1 or the second clock signal line CK2
  • the switching time is shortened (the time required for the output terminal Gout to switch from a high level to a low level is shorter), that is, the falling edge time Tf of the shift register output signal is smaller, which reduces the difference in the rising edge time and falling edge time of the data write control terminal Gate and the reset control terminal Reset signal, thereby improving display defects.
  • Example 1 since the opening time of the seventh transistor T7 can be later than the opening time of the fifth transistor T5 through the third clock signal line CK3 and the fourth clock signal line CK4, the charge stored in the second capacitor C2 is prevented from being released through the seventh transistor T7, resulting in an increase in the potential of the fourth node N4, thereby affecting the output of the shift register.
  • FIG14 schematically shows the potential waveform of each node of the shift register after Vth is negatively biased
  • FIG15 schematically shows the potential waveform of each node of the shift register after Vth is positively biased
  • Ref represents the waveform in the related art
  • New represents the waveform of Example 1. It can be seen from FIG14 and FIG15 that regardless of Vth negative bias or positive bias, the waveform of each node of the shift register is closer to the ideal waveform.
  • the scanning driving circuit in the related art shown in FIG4 needs to be provided with at least four clock signal lines.
  • the scanning driving circuit in Example 1 can be provided with only four clock signal lines, namely, the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, and the fourth clock signal line CK4. Therefore, Example 1 can improve the output of the shift register without increasing the number of clock signal lines, thereby improving display defects.
  • the capacitance of the clock signal line connected to the first clock signal terminal CK is 73.13fF
  • the capacitance of the clock signal line connected to the second clock signal terminal CB is 73.13fF
  • the total capacitance of the clock signal line connected to the first clock signal terminal CK is 171.12pF
  • the total capacitance of the clock signal line connected to the second clock signal terminal CB is 171.12pF.
  • Example 1 the capacitance of the first clock signal line CK1 is 39.64fF, the capacitance of the second clock signal line CK2 is 39.64fF, the capacitance of the third clock signal line CK3 is 59.01fF, the capacitance of the fourth clock signal line CK4 is 59.01fF, the total capacitance of the first clock signal line CK1 is 92.76pF, the total capacitance of the second clock signal line CK2 is 92.76pF, the total capacitance of the third clock signal line CK3 is 138.09pF, and the total capacitance of the fourth clock signal line CK4 is 138.09pF.
  • FIG16 schematically shows a structural block diagram of another display panel
  • FIG17 schematically shows a circuit diagram of a scan drive circuit
  • FIG18 schematically shows a timing diagram of the scan drive circuit.
  • the clock signal line also includes a fifth clock signal line CK5 and a sixth clock signal line CK6.
  • the plurality of shift registers further include a third shift register 114 and a fourth shift register 115.
  • the first shift register 112, the second shift register 113, the third shift register 114, and the fourth shift register 115 are sequentially arranged and cascaded.
  • the first signal terminal S1 is connected to the fifth clock signal line CK5, the second signal terminal S2 is connected to the sixth clock signal line CK6, and the third signal terminal S3 is connected to the fourth clock signal line CK4.
  • the fourth shift register 115 the first signal terminal S1 is connected to the sixth clock signal line CK6, the second signal terminal S2 is connected to the fifth clock signal line CK5, and the third signal terminal S3 is connected to the third clock signal line CK3.
  • Example 2 a fifth clock signal line CK5 and a sixth clock signal line CK6 are added.
  • the fifth clock signal line CK5 is connected to the first signal terminal S1 of the third shift register 114 and the second signal terminal S2 of the fourth shift register 115, which reduces the load of the first clock signal line CK1 compared with Example 1;
  • the sixth clock signal line CK6 is chain-connected to the second signal terminal S2 of the third shift register 114 and the first signal terminal S1 of the fourth shift register 115, which reduces the load of the second clock signal line CK2 compared with Example 1.
  • the plurality of shift registers can be divided into a plurality of cascaded shift register units, wherein the shift register unit includes two cascaded shift registers.
  • the first signal terminal S1 of one shift register and the second signal terminal S2 of another shift register are connected to the same signal line.
  • FIG19 schematically shows a structural block diagram of another display panel
  • FIG20 schematically shows a partial circuit diagram of a scan drive circuit
  • FIG21 schematically shows a timing diagram of the scan drive circuit.
  • the plurality of shift registers further include a fifth shift register 116 and a sixth shift register 117, and the first shift register 112, the second shift register 113, the fifth shift register 116, and the sixth shift register 117 are arranged in sequence and cascaded.
  • the first signal terminal S1 is connected to the third clock signal line CK3
  • the second signal terminal S2 is connected to the fourth clock signal line CK4
  • the third signal terminal S3 is connected to the second clock signal line CK2.
  • the sixth shift register 117 the first signal terminal S1 is connected to the fourth clock signal line CK4, the second signal terminal S2 is connected to the third clock signal line CK3, and the third signal terminal S3 is connected to the first clock signal line CK1.
  • the scan driving circuit is only provided with four clock signal lines, which reduces the number of clock signal lines and makes the frame of the display panel 110 narrower.
  • FIG22 schematically shows a step block diagram of the control method for a scan drive circuit. As shown in FIG22 , the control method of the scan driving circuit includes the following steps.
  • Step S100 in the first stage, a first clock signal is provided to the first signal terminal, a second clock signal is provided to the second signal terminal, and a third clock signal is provided to the third signal terminal, so that: the input subcircuit is turned on under the signal control of the first signal terminal, and the signal of the start signal terminal is written into the first node; the first control subcircuit is turned on under the signal control of the first node, and the signal of the first signal terminal is written into the second node; the second control subcircuit remains turned off under the signal control of the second node and the third signal terminal; the output subcircuit is turned on under the signal control of the first node and the second node, and the signal of the second signal terminal and the second voltage terminal is written into the output terminal.
  • the signal at the first signal end is a first clock signal
  • the signal at the second signal end is a second clock signal
  • the signal at the third signal end is a third clock signal.
  • the clock signals may be different at different stages. For example, at the first stage, the first clock signal is a low level signal, and the second and third clock signals are high level signals; at the second stage, the first clock signal is a high level signal, and the second and third clock signals are low level signals.
  • the input subcircuit writes the low level signal of the start signal terminal ST to the first node N1 under the control of the low level signal of the first signal terminal S1
  • the output subcircuit writes the high level signal of the second signal terminal S2 to the output terminal Gout under the control of the low level signal of the first node N1, so that the shift register outputs the high level signal of the second signal terminal S2 through the output terminal Gout.
  • the first control subcircuit writes the low level signal of the first signal terminal S1 to the second node N2 under the control of the low level signal of the first node N1
  • the output subcircuit writes the high level signal of the second voltage terminal V2 to the output terminal Gout under the control of the low level signal of the second node N2, so that the shift register outputs the high level signal of the second voltage terminal V2 through the output terminal Gout.
  • the second control subcircuit is not turned on under the control of the signals of the second node N2 and the third signal terminal S3, so that the first node N1 and the second node N2 are not connected.
  • Step S200 in the second stage, a first clock signal is provided to the first signal terminal, a second clock signal is provided to the second signal terminal, and a third clock signal is provided to the third signal terminal, so that: the input subcircuit remains turned off under the control of the first clock signal; the first control subcircuit is turned on under the control of the signal of the first node, and the signal of the first signal terminal is written to the second node; the second control subcircuit remains turned off under the control of the signal of the third signal terminal and the second node; the output subcircuit is turned on under the control of the signals of the second node and the first node, and the signal of the second signal terminal is written to the output terminal.
  • the output sub-circuit writes the low level signal of the second signal terminal S2 into the output terminal Gout under the control of the low level signal of the first node N1, so that the shift register outputs The terminal Gout outputs the low level signal of the second signal terminal S2.
  • the first control subcircuit writes the high level signal of the first signal terminal S1 into the second node N2 under the control of the low level signal of the first node N1.
  • the second control subcircuit is not turned on under the control of the signal of the second node N2 and the third signal terminal S3, so that the first node N1 and the second node N2 are not connected.
  • the control method of the scan drive circuit provides signals to the first signal terminal S1, the second signal terminal S2 and the third signal terminal S3 of the same shift register respectively through different clock signal lines. That is, in the same shift register, the clock signal line connected to the second signal terminal S2 is connected to the output subcircuit, but not to the second control subcircuit, thereby reducing the load of the clock signal line connected to the second signal terminal S2.
  • the time required for the signal of the second signal terminal S2 to switch to a high level is shorter (the time required for the output terminal Gout to switch from a high level to a low level is shorter), that is, the falling edge time Tf of the output signal of the shift register is shorter, which reduces the difference between the rising edge time and the falling edge time of the data write control terminal Gate and the reset control terminal Reset signal, thereby improving the display defect.
  • the second control subcircuit includes a seventh transistor T7.
  • the control electrode of the seventh transistor T7 is connected to the third signal terminal S3, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the first node N1.
  • the seventh transistor T7 is configured to write the signal of the third node N3 to the first node N1 in response to the signal of the third signal terminal S3.
  • the output subcircuit includes a fifth transistor T5, an eighth transistor T8, and a second capacitor C2.
  • the control electrode of the fifth transistor T5 is connected to the fourth node N4, the first electrode of the fifth transistor T5 is connected to the second signal terminal S2, and the second electrode of the fifth transistor T5 is connected to the output terminal Gout.
  • the fifth transistor T5 is configured to write the signal of the second signal terminal S2 to the output terminal Gout in response to the signal of the fourth node N4.
  • the control electrode of the eighth transistor T8 is connected to the first voltage terminal V1
  • the first electrode of the eighth transistor T8 is connected to the first node N1
  • the second electrode of the eighth transistor T8 is connected to the fourth node N4.
  • the eighth transistor T8 is configured to write the signal of the first node N1 into the fourth node N4, or write the signal of the fourth node N4 into the first node N1 in response to the signal of the first voltage terminal V1.
  • One plate of the second capacitor C2 is connected to the output terminal Gout, and the other plate is connected to the fourth node N4.
  • the second capacitor C2 is configured to store the signal of the fourth node N4 so that the signal of the fourth node N4 does not suddenly change.
  • the effective level period of the second signal overlaps with the effective level period of the third signal, and the leading edge of the effective level in the second signal precedes the leading edge of the effective level in the third signal.
  • the time when the effective level signal is provided to the second signal terminal S2 is the first time t1
  • the time when the effective level signal is provided to the second signal terminal S2 is the first time t2.
  • the time when the third signal terminal S3 provides the effective level signal is the second time t2, and the first time t1 is earlier than the second time t2.
  • the signal of the second signal terminal S2 is switched to a low level signal, and the fourth node N4 and the first node N1 remain at a low level under the action of the second capacitor C2, so that the fifth transistor T5 and the second transistor T2 are turned on.
  • the signal of the third signal terminal S3 is still a high level signal
  • the seventh transistor T7 is not turned on
  • the charge stored in the second capacitor C2 will not be released to the third node N3 through the seventh transistor T7
  • the parasitic capacitance formed between the gate of the seventh transistor T7 and the active layer will not be charged, so that the first node N1 and the fourth node N4 maintain a low level signal, so that the fifth transistor T5 and the second transistor T2 are in a better turn-on state.
  • the duty cycle of the second signal may be less than or equal to the duty cycle of the third signal.
  • the trailing edge of the effective level in the second signal is synchronized with the trailing edge of the effective level in the third signal.
  • the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

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Abstract

本公开涉及显示技术领域，具体涉及一种扫描驱动电路及其控制方法、显示面板、显示装置。扫描驱动电路包括多条信号线以及多个依次级联的移位寄存器；移位寄存器包括输入子电路、第一控制子电路、第二控制子电路和输出子电路；输入子电路与起始信号端、第一节点、第一信号端连接；第一控制子电路与第一信号端、第一节点、第二节点连接；第二控制子电路与第一节点、第二节点、第二电压端、第三信号端连接；输出子电路与第一节点、第二节点、输出端、第二信号端、第二电压端连接；同一移位寄存器的第二信号端和第三信号端与不同的信号线连接。

Description

扫描驱动电路及其控制方法、显示面板、显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种扫描驱动电路及其控制方法、显示面板、显示装置。
背景技术
扫描驱动电路是有源矩阵有机发光二极体(Active Matrix Organic Light-Emitting Diode，AMOLED)显示中一种重要的辅助电路。现有的扫描驱动电路包括多个级联的移位寄存器。然而，设有该扫描驱动电路的显示装置的亮度均一性较差。
发明内容
本公开的实施例采用如下技术方案：
一方面，提供了一种扫描驱动电路，包括多条时钟信号线以及多个级联的移位寄存器；所述移位寄存器包括输入子电路、第一控制子电路、第二控制子电路和输出子电路；所述输入子电路与起始信号端、第一节点、第一信号端连接，所述输入子电路被配置为在所述第一信号端的信号控制下将所述起始信号端的信号写入所述第一节点；所述第一控制子电路与所述第一信号端、第二节点、所述第一节点连接，所述第一控制子电路被配置为在所述第一节点的信号控制下将所述第一信号端的信号写入所述第二节点；所述第二控制子电路与所述第一节点、所述第二节点、第二电压端、第三信号端连接，所述第二控制子电路被配置为在所述第二节点和所述第三信号端的信号控制下，将所述第二电压端的信号写入所述第一节点；所述输出子电路与所述第一节点、所述第二节点、输出端、第二信号端、所述第二电压端连接，所述输出子电路被配置为在所述第一节点的信号控制下将所述第二信号端的信号写入所述输出端，还被配置为在所述第一节点的信号控制下将所述第二电压端的信号写入所述输出端；同一所述移位寄存器的所述第二信号端和所述第三信号端与不同的所述时钟信号线连接。
在一些实施例中，所述多条时钟信号线划分为多个时钟信号线组，每个 所述时钟信号线组包括多条所述时钟信号线；所述多个时钟信号线组包括第一时钟信号线组和第二时钟信号线组，两个级联的所述移位寄存器中的所述第三信号端与所述第一时钟信号线组中的不同时钟信号线连接，两个级联的所述移位寄存器中的所述第二信号端与所述第二时钟信号线组中的不同时钟信号线连接。
在一些实施例中，两个级联的所述移位寄存器中的所述第一信号端与所述第二时钟信号线组中的不同时钟信号线连接，且同一所述移位寄存器中，所述第一信号端和所述第二信号端与所述第二时钟信号线组中的不同时钟信号线连接。
在一些实施例中，所述时钟信号线包括第一时钟信号线、第二时钟信号线、第三时钟信号线和第四时钟信号线，所述多个移位寄存器包括级联的第一移位寄存器和第二移位寄存器；所述第一移位寄存器中，所述第一信号端与所述第一时钟信号线连接，所述第二信号端与所述第二时钟信号线连接，所述第三信号端与所述第四时钟信号线连接；所述第二移位寄存器中，所述第一信号端与所述第二时钟信号线连接，所述第二信号端与所述第一时钟信号线连接，所述第三信号端与所述第三时钟信号线连接。
在一些实施例中，所述多个移位寄存器包括多个所述第一移位寄存器和多个所述第二移位寄存器，所述第一移位寄存器和所述第二移位寄存器交错排列。
在一些实施例中，多个移位寄存器还包括第五移位寄存器和第六移位寄存器，第一移位寄存器、第二移位寄存器、第五移位寄存器、第六移位寄存器依次级联；所述第五移位寄存器中，所述第一信号端与所述第三时钟信号线连接，所述第二信号端与所述第四时钟信号线连接，所述第三信号端与所述第二时钟信号线连接；所述第六移位寄存器中，所述第一信号端与所述第四时钟信号线连接，所述第二信号端与所述第三时钟信号线连接，所述第三信号端与所述第一时钟信号线连接。
在一些实施例中，所述时钟信号线还包括第五时钟信号线和第六时钟信号线，所述多个移位寄存器还包括第三移位寄存器和第四移位寄存器，所述第一移位寄存器、所述第二移位寄存器、所述第三移位寄存器、所述第四移位寄存器依次排布且级联；所述第三移位寄存器中，所述第一信号端与所述 第五时钟信号线连接，所述第二信号端与所述第六时钟信号线连接，所述第三信号端与所述第四时钟信号线连接；所述第四移位寄存器中，所述第一信号端与所述第六时钟信号线连接，所述第二信号端与所述第五时钟信号线连接，所述第三信号端与所述第三时钟信号线连接。
在一些实施例中，所述第二控制子电路包括第六晶体管和第七晶体管；所述第六晶体管，栅极与所述第二节点连接，第一极与所述第二电压端连接，第二极与第三节点连接；所述第七晶体管，栅极与所述第三信号端连接，第一极与所述第三节点连接，第二极与所述第一节点连接。
在一些实施例中，所述输出子电路包括第四晶体管、第五晶体管、第一电容和第二电容；所述第四晶体管，栅极与所述第二节点连接，第一极与所述第二电压端连接，第二极与所述输出端连接；所述第五晶体管，栅极与所述第一节点连接，第一极与所述第二信号端连接，第二极与所述输出端连接；所述第一电容，一个极板与所述第二电压端连接，另一极板与所述第二节点连接；所述第二电容，一个极板与所述输出端连接，另一极板与所述第一节点连接。
在一些实施例中，所述输入子电路包括第一晶体管；所述第一晶体管，栅极与所述第一信号端连接，第一极与所述起始信号端连接，第二极与所述第一节点连接。
在一些实施例中，所述第一控制子电路包括第二晶体管；所述第二晶体管，栅极与所述第一节点连接，第一极与所述第一信号端连接，第二极与所述第二节点连接。
在一些实施例中，所述第一控制子电路还与第一电压端连接，所述第一控制子电路还被配置为在所述第一信号端的信号控制下，将所述第一电压端的信号写入所述第二节点。
在一些实施例中，所述第一控制子电路包括第三晶体管；所述第三晶体管，栅极与所述第一信号端连接，第一极与所述第一电压端连接，第二极与所述第二节点连接。
另一方面，提供了一种显示面板，包括所述的扫描驱动电路和多个像素驱动电路，所述扫描驱动电路的输出端与所述像素驱动电路连接。
再一方面，提供了一种显示装置，包括所述的显示面板。
又一方面，提供了一种扫描驱动电路的控制方法，用于控制所述的扫描驱动电路，同一帧周期内包括第一阶段和第二阶段，所述控制方法包括：
在所述第一阶段，向第一信号端提供第一时钟信号，向第二信号端提供第二时钟信号，向第三信号端提供第三时钟信号，以使：
输入子电路在所述第一信号端的信号控制下导通，并将起始信号端的信号写入第一节点；
第一控制子电路在所述第一节点的信号控制下导通，将所述第一信号端的信号写入第二节点；
第二控制子电路在所述第二节点、所述第三信号端的信号控制下保持关断；
输出子电路在所述第一节点、所述第二节点的信号控制下导通，并将所述第二信号端、第二电压端的信号写入输出端；
在所述第二阶段，向所述第一信号端提供第一时钟信号，向所述第二信号端提供第二时钟信号，向所述第三信号端提供第三时钟信号，以使：
所述输入子电路在所述第一时钟信号的控制下保持关断；
所述第一控制子电路在所述第一节点的信号控制下导通，并将所述第一信号端的信号写入所述第二节点；
所述第二控制子电路在所述第三信号端、所述第二节点的信号控制下保持关断；
所述输出子电路在所述第二节点和所述第一节点的信号控制下导通，将所述第二信号端的信号写入所述输出端。
在一些实施例中，同一帧周期内，所述第二信号的有效电平时段与所述第三信号的有效电平时段有交叠，且所述第二信号中有效电平的前沿提前于所述第三信号中有效电平的前沿。
在一些实施例中，所述第二信号的占空比小于或等于所述第三信号的占空比。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示意性地示出了一种显示装置的正视结构；
图2示意性地示出了一种显示面板的结构框图；
图3示意性地示出了一种像素驱动电路的电路图；
图4为相关技术中移位寄存器的电路图；
图5为图4所示移位寄存器的工作时序图；
图6示意性地示出了一种移位寄存器的结构框图；
图7示意性地示出了另一种移位寄存器的结构框图；
图8示意性地示出了一种移位寄存器的电路图；
图9示意性地示出了一种移位寄存器的工作时序图；
图10示意性地示出了一种移位寄存器的另一个工作时序图；
图11示意性地示出了一种扫描驱动电路的部分电路图；
图12为图11所示扫描驱动电路的部分版图；
图13示意性地示出了扫描驱动电路的一种时序图；
图14示意性地示出了Vth负偏后移位寄存器各节点的电位波形图；
图15示意性地示出了Vth正偏后移位寄存器各节点的电位波形图；
图16示意性地示出了另一种显示面板的结构框图；
图17示意性地示出了一种扫描驱动电路的电路图；
图18示意性地示出了扫描驱动电路的时序图；
图19示意性地示出了又一种显示面板的结构框图；
图20示意性地示出了一种扫描驱动电路的部分电路图；
图21示意性地示出了扫描驱动电路的时序图；
图22示意性地示出了扫描驱动电路的控制方法的步骤框图。
具体实施例
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在描述一些实施例时，可能使用了“电连接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“点连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
图1示意性地示出了一种显示装置的正视结构。如图1所示，本公开的一些实施例提供一种显示装置100，该显示装置100可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机 监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。图1中以该显示装置100为手机为例进行示意。
该显示装置100包括显示面板110。该显示面板110可以为液晶显示面板(Liquid Crystal Display，简称LCD)；该显示面板110也可以为电致发光显示面板或光致发光显示面板。在该显示面板110为电致发光显示面板的情况下，电致发光显示面板可以为有机电致发光(Organic Light-Emitting Diode，简称OLED)显示面板或量子点电致发光(Quantum Dot Light Emitting Diode，简称QLED)显示面板。在该显示面板110为光致发光显示面板的情况下，光致发光显示装置可以为量子点光致发光显示面板。
本公开的一些实施例以显示面板110为有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示面板为例进行说明。
显示面板110可以设有扫描驱动电路和多个子像素。子像素包括像素驱动电路以及与像素驱动电路电连接的发光器件。扫描驱动电路包括多条时钟信号线以及多个级联的移位寄存器，移位寄存器的输出端与像素驱动电路电连接。显示面板110工作时，各时钟信号线内可以通入时钟信号，以控制移位寄存器逐级输出扫描信号，像素驱动电路在扫描信号的控制下驱动发光器件发光。
图2示意性地示出了一种显示面板的结构框图。示例性地，如图2所示，显示面板110可以划分为显示区110a以及与显示区110a连接的非显示区110b，多个子像素111设置在显示区110a内，扫描驱动电路设置在非显示区110b内。当然，实际应用过程中，为了降低显示面板110的边框尺寸，扫描驱动电路的至少部分结构也可以设置在显示区110a内。
示例性地，继续参考图2，多个子像素111阵列排布，形成多个子像素111行，每个移位寄存器的输出端与一个子像素111行内的像素驱动电路电连接。
图3示意性地示出了一种像素驱动电路的电路图。如图3所示，像素驱动电路包括发光控制端EM、数据写入控制信号端Gate以及复位控制信号端Reset。像素驱动电路可以在发光控制端EM、数据写入控制信号端Gate以及 复位控制信号端Reset的信号控制下驱动发光器件OLED发光。
移位寄存器的输出端可以与数据写入控制信号端Gate和/或复位控制信号端Reset电连接，也可以与发光控制端EM电连接。以下仅以移位寄存器的输出端与数据写入控制信号端Gate和/或复位控制信号端Reset电连接为例进行示意性说明。
其中，图3中以像素驱动电路为7T1C结构为例，实际应用时像素驱动电路还可以为4T1C、6T1C、6T2C、7T2C、8T2C等其他结构，本公开的实施例对像素驱动电路的结构不作限定。其中，T表示为晶体管管，位于T前面的数字表示为晶体管的数量，C表示为电容，位于C前面的数字表示为电容的数量。
图4为相关技术中移位寄存器的电路图，图5为图4所示移位寄存器的工作时序图。如图4和图5所示，相关技术中移位寄存器的工作过程包括：在阶段L1，第一时钟信号端CK为低电平，第二时钟信号端CB为高电平，晶体管M1、晶体管M8以及晶体管M5打开，信号输出端OUT输出高电平信号；在阶段L2，第一时钟信号端CK为高电平，第二时钟信号端CB为低电平，晶体管M5的栅极保持低电平状态，移位寄存器通过晶体管M5输出低电平信号。
由图3至图5可知，发光器件OLED的发光亮度对数据写入控制信端Gate以及复位控制端Reset的信号上升时间/下降时间(Tr/Tf)较为敏感。而数据写入控制端Gate及复位控制端Reset的信号是第二时钟信号端CB信号的移位输出，与第二时钟信号端CB连接的信号线的负载(loading)会直接影响第二时钟信号端CB信号的上升时间/下降时间(Tr/Tf)。由于第二时钟信号端CB同时与晶体管M5和晶体管M7连接，第二时钟信号端CB的负载较大，使得第二时钟信号端CB的高低电平切换需要较长时间(信号输出端OUT由高电平切换为低电平需要较长时间)，即下降沿时间Tf较大，导致数据写入控制端Gate和复位控制端Reset信号的上升沿时间和下降沿时间差异，引起显示不良。
鉴于此，本公开的一些实施例提供的扫描驱动电路中，移位寄存器的输出端输出的信号下降沿较小，改善了显示不良。
图6示意性地示出了一种移位寄存器的结构框图。如图6所示，移位寄存器包括输入子电路、第一控制子电路、第二控制子电路和输出子电路。
输入子电路与起始信号端ST、第一节点N1、第一信号端S1连接，输入子电路被配置为在第一信号端S1的信号控制下将起始信号端ST的信号写入第一节点N1。
示例性地，第一信号端S1接收的信号为低电平信号时，输入子电路导通，并将起始信号端ST的信号写入第一节点N1。例如，输入子电路导通后，起始信号端ST的信号为低电平信号时，第一节点N1为低电平信号；起始信号端ST的信号为高电平信号时，第一节点N1为高电平信号。
第一控制子电路与第一信号端S1、第一节点N1、第二节点N2连接，第一控制子电路被配置为在第一节点N1的信号控制下将第一信号端S1的信号写入第二节点N2。
示例性地，第一节点N1的信号为低电平信号时，第一控制子电路导通，并将第一信号端S1的信号写入第二节点N2。例如，第一控制子电路导通后，第一信号端S1的信号为低电平信号时，第二节点N2的信号为低电平信号；第一信号端S1的信号为高电平信号时，第二节点N2的信号为高电平信号。
图7示意性地示出了另一种移位寄存器的结构框图。可选地，如图7所示，第一控制子电路还可以与第一电压端V1连接，第一控制子电路还被配置为在第一信号端S1的信号控制下将第一电压端V1的信号写入第二节点N2。
示例性地，第一信号端S1的信号为低电平信号时，第一控制子电路将第一电压端V1的信号写入第二节点N2。
其中，第一电压端V1被配置为提供低电平信号(例如低于或等于时钟信号线中时钟信号的低电平部分)。例如，第一电压端V1与Vgl线连接。
第二控制子电路与第一节点N1、第二节点N2、第二电压端V2、第三信号端S3连接，第二控制子电路被配置为在第二节点N2和第三信号端S3的信号控制下，将第二电压端V2的信号写入第一节点N1。
示例性地，第二节点N2和第三信号端S3的信号同时为低电平信号时，第二控制子电路导通，并将第二电压端V2的信号写入第一节点N1。
其中，第二电压端V2被配置为提供直流高电平信号(例如高于或等于时钟信号线中时钟信号的高电平部分)。例如，第二电压端V2与Vgh线连接。
输出子电路与第一节点N1、第二节点N2、输出端Gout、第二信号端S2、第二电压端V2连接，输出子电路被配置为在第一节点N1的信号控制下将第 二信号端S2的信号写入输出端Gout，还被配置为在第一节点N1的信号控制下将第二电压端V2的信号写入输出端Gout。
示例性地，第一节点N1和第二节点N2同时为低电平信号时，第二电压端V2与输出端Gout连通，第二信号端S2与输出端Gout连通；第一节点N1为低电平信号，第二节点N2为高电平信号时，第二电压端V2与输出端Gout断开，第二信号端S2与输出端Gout连通。
可选地，移位寄存器还包括稳定子电路，稳定子电路与第一电压端V1、第一节点N1、第四节点N4连接，稳定子电路被配置为在第一电压端V1的信号控制下将第一节点N1的信号写入第四节点N4，或者将第四节点N4的信号写入第一节点N1。
当移位寄存器包括稳定子电路时，输出子电路通过稳定子电路与第一节点N1连接。
其中，本公开实施例中的节点(例如，第一节点N1、第二节点N2、第三节点N3、第四节点N4等)并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
示例性地，继续参考图2，多个移位寄存器级联后，第一个移位寄存器的起始信号端ST与起始信号线STV连接，其余的移位寄存器的起始信号端ST与上一个移位寄存器的输出端Gout连接。
同一帧周期包括第一阶段和第二阶段。
在第一阶段，输入子电路在第一信号端S1的信号控制下将起始信号端ST的信号写入第一节点N1，输出子电路在第一节点N1的信号控制下将第二信号端S2的信号写入输出端Gout，从而使移位寄存器通过输出端Gout输出第二信号端S2的信号。第一控制子电路在第一节点N1的信号控制下将第一信号端S1的信号写入第二节点N2，输出子电路在第二节点N2的信号控制下将第二电压端V2的信号写入输出端Gout，从而使移位寄存器通过输出端Gout输出第二电压端V2的信号。并且，第二控制子电路在第二节点N2和第三信号端S3的信号控制下不导通，使第一节点N1和第二节点N2保持断开。
在第二阶段，输出子电路在第一节点N1的信号控制下将第二信号端S2的信号写入输出端Gout，从而使移位寄存器通过输出端Gout输出第二信号端 S2的信号。第一控制子电路在第一节点N1的信号控制下将第一信号端S1的信号写入第二节点N2。并且，第二控制子电路在第二节点N2和第三信号端S3的信号控制下不导通，使第一节点N1和第二节点N2保持断开。
示例性地，在第一阶段，第一信号端S1的信号为低电平信号，第二信号端S2的信号为高电平信号；在第二阶段，第一信号端S1的信号为高电平信号，第二信号端S2的信号为低电平信号。使移位寄存器在第一阶段输出高电平信号，在第二阶段输出低电平信号。
其中，同一移位寄存器的第二信号端S2和第三信号端S3与不同的时钟信号线连接。即，同一移位寄存器中，与第二信号端S2连接的时钟信号线与输出子电路连接，而不与第二控制子电路连接，降低了与第二信号端S2连接的时钟信号线的负载。与第二信号端S2连接的时钟信号线的负载降低后，第二信号端S2的信号进行高电平切换所需要的时间更短(输出端Gout由高电平切换为低电平所需要的时间更短)，即移位寄存器输出信号的下降沿时间Tf较小，缩小了数据写入控制端Gate和复位控制端Reset信号的上升沿时间和下降沿时间差异，改善了显示不良。
图8示意性地示出了一种移位寄存器的电路图。下面结合图8对本公开实施例提供的一种移位寄存器进行详细说明。
在一些实施例中，输入子电路包括第一晶体管T1。第一晶体管T1的控制极与第一信号端S1连接，第一晶体管T1的第一极与起始信号端ST连接，第一晶体管T1的第二极与第一节点N1连接。第一晶体管T1被配置为，在第一阶段，响应于第一信号端S1的信号，将起始信号端ST的信号写入第一节点N1。
在一些实施例中，第一控制子电路包括第二晶体管T2。第二晶体管T2的控制极与第一节点N1连接，第二晶体管T2的第一极与第一信号端S1连接，第二晶体管T2的第二极与第二节点N2连接。第二晶体管T2被配置为，在第一阶段和第二阶段，响应于第一节点N1的信号，将第一信号端S1的信号写入第二节点N2。
第一控制子电路还可以包括第三晶体管T3，第三晶体管T3的控制极与第一信号端S1连接，第三晶体管T3的第一极与第一电压端V1连接，第三晶体管T3的第二极与第二节点N2连接。第三晶体管T3被配置为，在第一阶 段，响应于第一信号端S1的信号将第一电压端V1的信号写入第二节点N2。
在一些实施例中，第二控制子电路包括第六晶体管T6和第七晶体管T7。
第六晶体管T6的控制极与第二节点N2连接，第六晶体管T6的第一极与第二电压端V2连接，第六晶体管T6的第二极与第三节点N3连接。第六晶体管T6被配置为，响应于第二节点N2的信号将第二电压端V2的信号写入第三节点N3。
第七晶体管T7的控制极与第三信号端S3连接，第七晶体管T7的第一极与第三节点N3连接，第七晶体管T7的第二极与第一节点N1连接。第七晶体管T7被配置为，响应于第三信号端S3的信号将第三节点N3的信号写入第一节点N1。
在一些实施例中，输出子电路包括第四晶体管T4、第五晶体管T5、第一电容C1和第二电容C2。
第四晶体管T4的控制极与第二节点N2连接，第四晶体管T4的第一极与第二电压端V2连接，第四晶体管T4的第二极与输出端Gout连接。第四晶体管T4被配置为，在第一阶段，响应于第二节点N2的信号将第二电压端V2的信号写入输出端Gout；第四晶体管T4还被配置为，在第二阶段，响应于第二节点N2的信号使第二电压端V2和输出端Gout断开连接。
第五晶体管T5的控制极与第一节点N1连接，第五晶体管T5的第一极与第二信号端S2连接，第五晶体管T5的第二极与输出端Gout连接。第五晶体管T5被配置为，响应于第一节点N1的信号将第二信号端S2的信号写入输出端Gout。
第一电容C1的一个极板与第二电压端V2连接，另一极板与第二节点N2连接。第一电容C1被配置为储存第二节点N2的信号，使第二节点N2的信号不会发生突变。
第二电容C2的一个极板与输出端Gout连接，另一极板与第一节点N1连接。第二电容C2被配置为储存第一节点N1的信号，使第一节点N1的信号不会发生突变。
在一些实施例中，稳定子电路包括第八晶体管T8，第八晶体管T8的控制极与第一电压端V1连接，第八晶体管T8的第一极与第一节点N1连接，第八晶体管T8的第二极与第四节点N4连接。第八晶体管T8被配置为，响 应于第一电压端V1的信号，将第一节点N1的信号写入第四节点N4，或将第四节点N4的信号写入第一节点N1。
当移位寄存器包括稳定子电路时，第五晶体管T5的控制极与第四节点N4连接，以使第五晶体管T5的控制极通过第八晶体管T8与第一节点N1连接；第二电容C2的另一个极板与第四节点N4连接，以使第二电容C2的另一个极板通过第八晶体管T8与第一节点N1连接。
本公开的实施例提供的电路中所采用的晶体管可以为薄膜晶体管、场效应晶体管(例如氧化物薄膜晶体管)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在一些实施例中，移位寄存器所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
本公开的实施例提供的晶体管均以P型晶体管为例进行示意性说明。
示例性地，多个级联的移位寄存器中，第一个移位寄存器的第一信号端S1与第一时钟信号线CK1连接，第二信号端S2与第二时钟信号线CK2连接，第三信号端S3与第四时钟信号线CK4连接，起始信号端ST与起始信号线STV连接。图9示意性地示出了一种移位寄存器的工作时序图。下面结合图8和图9以第一个移位寄存器为例详细说明移位寄存器的工作过程。
第一阶段：第一信号端S1和起始信号端ST均为低电平信号(有效电平)，第二信号端S2为高电平(无效电平)。第一晶体管T1在第一信号端S1的低电平信号控制下导通，起始信号端ST的低电平信号通过第一晶体管T1写入第一节点N1，第八晶体管T8在第一电压端V1的低电平信号的控制下导通，第一节点N1写入的低电平信号继续写入第四节点N4，从而使得第五晶体管T5导通，第二信号端S2的高电平信号通过第五晶体管T5写入输出端Gout。并且，第二晶体管T2在第一节点N1的低电平信号控制下导通，第一信号端S1的低电平信号通过第二晶体管T2写入第二节点N2，第三晶体管T3在第一电 压端V1的低电平信号控制下导通，使第一电压端V1的低电平信号写入第二节点N2，第四晶体管T4在第二节点N2的低电平信号控制下导通，从而使第二电压端V2的高电平信号通过第四晶体管T4写入输出端Gout。此时，移位寄存器的输出端Gout输出高电平信号。
第二阶段：第一信号端S1和起始信号端ST均为高电平信号(无效电平)，第二信号端S2为低电平信号(有效电平)。第四节点N4可以保持第一阶段的低电平信号(在第二电容C2的作用下)，第五晶体管T5维持开启，在第二信号端S2的信号由高电平信号切换为低电平信号之后，第二信号端S2的低电平信号通过第五晶体管T5写入输出端Gout。并且，第一节点N1可以保持第一阶段的低电平信号(在第二电容C2的作用下)，使第二晶体管T2开启，第一信号端S1的高电平信号通过第二晶体管T2写入第二节点N2，将第二节点N2的电位拉高，使得第四晶体管T4和第六晶体管T6关闭。此时，移位寄存器通过输出端Gout输出低电平信号。
第三阶段：第一信号端S1为低电平信号(有效电平)，起始信号端ST和第二信号端S2均为高电平信号(无效电平)。第一晶体管T1在第一信号端S1的低电平信号控制下导通，起始信号端ST的高电平信号通过第一晶体管T1写入第一节点N1，第八晶体管T8在第一电压端V1低电平信号控制下导通，使写入第一节点N1的高电平信号继续写入第四节点N4，使第五晶体管T5在第四节点N4的高电平信号控制下关闭。并且，第二晶体管T2在第一节点N1的高电平信号控制下关闭，第三晶体管T3在第一信号端S1的低电平信号控制下导通，第一电压端V1的低电平信号通过第三晶体管T3写入第二节点N2，第四晶体管T4在第二节点N2的低电平信号控制下导通，使得第二电压端V2的高电平信号通过第四晶体管T4写入输出端Gout。此时，移位寄存器通过输出端Gout输出高电平信号。
第四阶段：第一信号端S1和起始信号端ST均为高电平信号(无效电平)，第二信号端S2为低电平信号(有效电平)。第一节点N1和第四节点N4保持着第三阶段的高电平信号(在第二电容C2的作用下)，第二晶体管T2和第五晶体管T5在高电平信号的控制下保持关闭状态。第二节点N2保持着第三阶段的低电平信号(在第一电容C1的作用下)，使第四晶体管T4在第二节点N2的低电平信号控制下保持导通，第二电压端V2的高电平信号通过第四晶体管 T4写入输出端Gout。此时，移位寄存器通过输出端Gout输出高电平信号。
第五阶段：第一信号端S1为低电平信号(有效电平)，起始信号端ST和第二信号端S2均为高电平信号(无效电平)。第一晶体管T1在第一信号端S1的低电平信号控制下导通，起始信号端ST的高电平信号通过第一晶体管T1写入第一节点N1，进而写入第四节点N4，第五晶体管T5在第四节点N4的高电平信号控制下关闭。并且，第三晶体管T3在第一信号端S1的低电平信号控制下导通，第一电压端V1的低电平信号通过第三晶体管T3写入第二节点N2，第四晶体管T4在第二节点N2的低电平信号控制下导通，使得第二电压端V2的高电平信号通过第四晶体管T4写入输出端Gout。此时，移位寄存器通过输出端Gout输出高电平信号。
相关技术的扫描驱动电路中，同一移位寄存器的晶体管M5和晶体管M7与第二时钟信号端CB连接，第二时钟信号端CB与一条时钟信号线连接。当第二时钟信号端CB为低电平信号时，晶体管M7导通，晶体管M7的栅极与晶体管M7的有源层之间形成寄生电容，与第二时钟信号端CB连接的时钟信号线中出现高低电平信号切换时，受寄生电容的影响，导致高低电平信号切换时间增大，即移位寄存器输出信号的下降沿时间Tf较大，使得数据写入控制端Gate和复位控制端Reset信号的上升沿时间和下降沿时间差异较大，容易出现显示不良。
本公开实施例中，同一移位寄存器的第二信号端S2和第三信号端S3与不同的时钟信号线连接。即，同一移位寄存器中，第五晶体管T5和第七晶体管T7与不同的时钟信号线连接，降低了与第五晶体管T5连接的时钟信号线的负载。与第五晶体管T5连接的时钟信号线中出现高低电平信号切换时，高低电平信号切换的时间缩小(输出端Gout由高电平切换为低电平所需要的时间更短)，即移位寄存器输出信号的下降沿时间Tf较小，缩小了数据写入控制端Gate和复位控制端Reset信号的上升沿时间和下降沿时间差异，改善了显示不良。
另外，由于同一移位寄存器中第二信号端S2和第三信号端S3与不同的时钟信号线连接，使得移位寄存器中的第七晶体管T7可以通过与第三信号端S3连接的时钟信号线控制第七晶体管T7开启或关闭时刻。
图10示意性地示出了一种移位寄存器的另一个工作时序图。示例性地， 如图10所示，第一个移位寄存器的第一信号端S1与第一时钟信号线CK1连接，第二信号端S2与第二时钟信号线CK2连接，第三信号端S3与第四时钟信号线CK4连接，起始信号端ST与起始信号线STV连接。第三信号端S3由高电平信号切换为低电平信号的时刻为第一时刻t1，第二信号端S2由高电平信号切换为低电平信号的时刻为第二时刻t2，第一时刻t1早于第二时刻t2。
第二阶段，在第一时刻t1至第二时刻t2范围内，第二信号端S2的信号切换为低电平信号，第四节点N4和第一节点N1在第二电容C2的作用下保持低电平，使得第五晶体管T5和第二晶体管T2导通。此时，第三信号端S3的信号仍然为高电平信号，第七晶体管T7不导通，第二电容C2储存的电荷不会经过第七晶体管T7释放到第三节点N3，也不会对第七晶体管T7的栅极与有源层之间形成的寄生电容充电，使第一节点N1和第四节点N4维持低电平信号，从而使第五晶体管T5和第二晶体管T2的开启状态较好。防止第二电容C2储存的电荷经过第七晶体管T7释放，导致的第四节点N4电位升高，从而影响移位寄存器的输出。
扫描驱动电路中的多条时钟信号线可以划分为多个时钟信号线组，每个时钟信号线组包括多条时钟信号线，且一条时钟信号线只能属于一个时钟信号线组。多个时钟信号线组包括第一时钟信号线组和第二信号线组。
示例性地，与第三信号端S3连接的时钟信号线划分为第一时钟信号线组，多条时钟信号线中除第一时钟信号线组中的时钟信号线划分为第二时钟信号线组。
第一时钟信号线组中的时钟信号线与移位寄存器的第三信号端S3连接，第二时钟信号线组中的至少部分时钟信号线与第二信号端S2连接。也就是说，与第二信号端S2连接的时钟信号线不与第三信号端S3连接，使得与第二信号端S2连接的时钟信号线的负载降低，与第二信号端S2连接的时钟信号线中出现高低电平信号切换时，高低电平信号切换的时间缩小(输出端Gout由高电平切换为低电平所需要的时间更短)，即移位寄存器输出信号的下降沿时间Tf较小，缩小了数据写入控制端Gate和复位控制端Reset信号的上升沿时间和下降沿时间差异，改善了显示不良。
示例性地，第二时钟信号线组包括第一子时钟信号线组和第二子时钟信号线组，第一子时钟信号线组中时钟信号线通入有效电平时，第二子时钟信 号线组中时钟信号线通入无效电平；第二子时钟信号线组中时钟信号线通入有效电平时，第一子时钟信号线组中时钟信号线通入无效电平。同一移位寄存器中，与第一信号端S1连接的时钟信号线属于第一子时钟信号线组和第二子时钟信号线组中的一个，与第二信号端S2连接的时钟信号线属于第一子时钟信号线组和第二子时钟信号线组中的另一个。
两个级联的移位寄存器中的第三信号端S3与第一时钟信号线CK1组中的不同时钟信号线连接，使得其中一个移位寄存器中的第三信号端S3可以通入有效电平，而另一个移位寄存器中的第三信号端S3可以通入无效电平。两个级联的移位寄存器中的第二信号端S2与第二时钟信号线组中的不同时钟信号线连接，使得其中一个移位寄存器中的第二信号端S2可以通入有效电平，而另一个移位寄存器中的第二信号端S2可以通入无效电平。
移位寄存器中的第一信号端S1也可以与第二时钟信号线组中的时钟信号线连接。即，第一信号端S1和第二信号端S2均与第二时钟信号线组中的时钟信号线连接，第一时钟信号线组中的时钟信号线不与第一信号端S1和第二信号端S2连接。当第一时钟信号线组中的时钟信号线中发生高低电平切换的时刻较晚时，不会使第一信号端S1和/或第二信号端S2的信号发生高低电平切换的时刻变晚。
两个级联的移位寄存器中的第一信号端S1与第二时钟信号线组中的不同时钟信号线连接，使得其中一个移位寄存器中的第一信号端S1可以通入有效电平，而另一个移位寄存器中的第一信号端S1可以通入无效电平。同一移位寄存器中，第一信号端S1和第二信号端S2与第二时钟信号线组中的不同时钟信号线连接，使得同一移位寄存器中，第一信号端S1和第二信号端S2中的一个可以通入有效电平，而另一个可以通入无效电平。
当然，第一时钟信号组中的时钟信号线也可以与第一信号端S1、第二信号端S2连接。
时钟信号线包括第一时钟信号线CK1、第二时钟信号线CK2、第三时钟信号线CK3和第四时钟信号线CK4。多个移位寄存器包括级联的第一移位寄存器112和第二移位寄存器113。第一移位寄存器112和第二移位寄存器113可以为多个移位寄存器中任意两个级联的移位寄存器。可以是第一移位寄存器112的输出端Gout与第二移位寄存器113的起始信号端ST连接，也可以 是第二移位寄存器113的输出端Gout与第一移位寄存器112的起始信号端ST连接。以下仅以第一移位寄存器112的输出端Gout与第二移位寄存器113的起始信号端ST连接为例进行示意性说明。
图11示意性地示出了一种扫描驱动电路的部分电路图，图12为图11所示扫描驱动电路的部分版图。图12中白色虚线框内的部分为第一移位寄存器112。如图2、图11和图12所示，第一移位寄存器112中，第一信号端S1与第一时钟信号线CK1连接，第二信号端S2与第二时钟信号线CK2连接，第三信号端S3与第四时钟信号线CK4连接。第二移位寄存器113中，第一信号端S1与第二时钟信号线CK2连接，第二信号端S2与第一时钟信号线CK1连接，第三信号端S3与第三时钟信号线CK3连接。
图13示意性地示出了图2、图11和图12所示扫描驱动电路的一种时序图。如图13所示，第一时钟信号线CK1通入有效电平时，第二时钟信号线CK2通入无效电平；第二时钟信号线CK2通入有效电平时，第一时钟信号线CK1通入无效电平；第三时钟信号线CK3通入有效电平时，第四时钟信号线CK4通入无效电平；第四时钟信号线CK4通入有效电平时，第三时钟信号线CK3通入无效电平；第三时钟信号线CK3通入有效电平时，第一时钟信号线CK1通入有效电平；第四时钟信号线CK4通入有效电平时，第二时钟信号线CK2通入有效电平。
示例一
继续参考图2，扫描驱动电路中的多个移位寄存器包括多个第一移位寄存器112和多个第二移位寄存器113，第一移位寄存器112和第二移位寄存器113交错排列。其中，第一移位寄存器112和第二移位寄存器113交错排列是指，按照第一移位寄存器112、第二移位寄存器113、第一移位寄存器112、第二移位寄存器113……的次序排列且级联。即，第一移位寄存器112的输出端Gout与第二移位寄存器113的起始信号端ST连接，第二移位寄存器113的输出端Gout与另一个第一移位寄存器112的起始信号端ST连接，依次类推。
第二时钟信号线CK2和第一时钟信号线CK1不与第七晶体管T7连接，使得第二时钟信号线CK2和第一时钟信号线CK1的负载降低，第一时钟信号线CK1或第二时钟信号线CK2中出现高低电平信号切换时，高低电平信号切 换的时间缩小(输出端Gout由高电平切换为低电平所需要的时间更短)，即移位寄存器输出信号的下降沿时间Tf较小，缩小了数据写入控制端Gate和复位控制端Reset信号的上升沿时间和下降沿时间差异，改善了显示不良。
另外，移位寄存器在信赖性测试后，晶体管的阈值电压Vth会发生偏移，此时移位寄存器的级传特性变差。示例一中，由于可以通过第三时钟信号线CK3和第四时钟信号线CK4使得第七晶体管T7的开启时间比第五晶体管T5的开启时间晚，防止第二电容C2储存的电荷经过第七晶体管T7释放，导致的第四节点N4电位升高，从而影响移位寄存器的输出。
图14示意性地示出了Vth负偏后移位寄存器各节点的电位波形图，图15示意性地示出了Vth正偏后移位寄存器各节点的电位波形图。其中“Ref”表示相关技术中的波形图，“New”表示示例一的波形图。由图14和图15可知，不管Vth负偏或正偏，移位寄存器各个节点的波形图都更接近于理想波形。
图4所示相关技术中的扫描驱动电路至少需要设置四条时钟信号线。如图2所示，示例一中扫描驱动电路可以仅设置第一时钟信号线CK1、第二时钟信号线CK2、第三时钟信号线CK3、第四时钟信号线CK4四条时钟信号线。因此，示例一可以在不增加时钟信号线数量的情况下，改善移位寄存器的输出，从而改善显示不良。
以扫描驱动电路包括2340个级联的移位寄存器为例。相关技术中的扫描驱动电路，与第一时钟信号端CK连接的时钟信号线的电容为73.13fF，与第二时钟信号端CB连接的时钟信号线的电容为73.13fF，与第一时钟信号端CK连接的时钟信号线的总电容为171.12pF，与第二时钟信号端CB连接的时钟信号线的总电容为171.12pF。示例一中，第一时钟信号线CK1的电容为39.64fF，第二时钟信号线CK2的电容为39.64fF，第三时钟信号线CK3的电容为59.01fF，第四时钟信号线CK4的电容为59.01fF，第一时钟信号线CK1的总电容为92.76pF，第二时钟信号线CK2的总电容为92.76pF，第三时钟信号线CK3的总电容为138.09pF，第四时钟信号线CK4的总电容为138.09pF。
示例二
图16示意性地示出了另一种显示面板的结构框图，图17示意性地示出了一种扫描驱动电路的电路图，图18示意性地示出了扫描驱动电路的时序图。如图16至图18所示，时钟信号线还包括第五时钟信号线CK5和第六时钟信 号线CK6，多个移位寄存器还包括第三移位寄存器114和第四移位寄存器115，第一移位寄存器112、第二移位寄存器113、第三移位寄存器114、第四移位寄存器115依次排布且级联。第三移位寄存器114中，第一信号端S1与第五时钟信号线CK5连接，第二信号端S2与第六时钟信号线CK6连接，第三信号端S3与第四时钟信号线CK4连接。第四移位寄存器115中，第一信号端S1与第六时钟信号线CK6连接，第二信号端S2与第五时钟信号线CK5连接，第三信号端S3与第三时钟信号线CK3连接。
示例二中增加了第五时钟信号线CK5和第六时钟信号线CK6，第五时钟信号线CK5与第三移位寄存器114的第一信号端S1以及第四移位寄存器115的第二信号端S2连接，与示例一相比降低了第一时钟信号线CK1的负载；第六时钟信号线CK6与第三移位寄存器114的第二信号端S2以及第四移位寄存器115的第一信号端S1链连接，与示例一相比降低了第二时钟信号线CK2的负载。
多个移位寄存器可以划分为多个级联的移位寄存单元，移位寄存单元包括两个级联的移位寄存器。同一移位寄存单元内，其中一个移位寄存器的第一信号端S1与另一个移位寄存器的第二信号端S2与同一信号线连接。
示例三
图19示意性地示出了又一种显示面板的结构框图，图20示意性地示出了一种扫描驱动电路的部分电路图；图21示意性地示出了扫描驱动电路的时序图。如图19至图21所示，多个移位寄存器还包括第五移位寄存器116和第六移位寄存器117，第一移位寄存器112、第二移位寄存器113、第五移位寄存器116、第六移位寄存器117依次排布且级联。第五移位寄存器116中，第一信号端S1与第三时钟信号线CK3连接，第二信号端S2与第四时钟信号线CK4连接，第三信号端S3与第二时钟信号线CK2连接。第六移位寄存器117中，第一信号端S1与第四时钟信号线CK4连接，第二信号端S2与第三时钟信号线CK3连接，第三信号端S3与第一时钟信号线CK1连接。
与示例二相比，扫描驱动电路只设置四条时钟信号线，减少了时钟信号线的数量，使得显示面板110的边框更窄。
本公开的一些实施例提供了一种扫描驱动电路的控制方法，用于控制上述的扫描驱动电路。图22示意性地示出了扫描驱动电路的控制方法的步骤框 图。如图22所示，扫描驱动电路的控制方法包括如下步骤。
步骤S100，在第一阶段，向第一信号端提供第一时钟信号，向第二信号端提供第二时钟信号，向第三信号端提供第三时钟信号，以使：输入子电路在第一信号端的信号控制下导通，并将起始信号端的信号写入第一节点；第一控制子电路在第一节点的信号控制下导通，将第一信号端的信号写入第二节点；第二控制子电路在第二节点、第三信号端的信号控制下保持关断；输出子电路在第一节点、第二节点的信号控制下导通，并将第二信号端、第二电压端的信号写入输出端。
其中，第一信号端的信号为第一时钟信号，第二信号端的信号为第二时钟信号，第三信号端的信号为第三时钟信号。在不同阶段，时钟信号可以不同。例如，在第一阶段，第一时钟信号为低电平信号，第二时钟信号、第三时钟信号为高电平信号；在第二阶段，第一时钟信号为高电平信号，第二时钟信号、第三时钟信号为低电平信号。
示例性地，在第一阶段，输入子电路在第一信号端S1的低电平信号控制下将起始信号端ST的低电平信号写入第一节点N1，输出子电路在第一节点N1的低电平信号控制下将第二信号端S2的高电平信号写入输出端Gout，从而使移位寄存器通过输出端Gout输出第二信号端S2的高电平信号。第一控制子电路在第一节点N1的低电平信号控制下将第一信号端S1的低电平信号写入第二节点N2，输出子电路在第二节点N2的低电平信号控制下将第二电压端V2的高电平信号写入输出端Gout，从而使移位寄存器通过输出端Gout输出第二电压端V2的高电平信号。并且，第二控制子电路在第二节点N2和第三信号端S3的信号控制下不导通，使第一节点N1和第二节点N2不连接。
步骤S200，在第二阶段，向第一信号端提供第一时钟信号，向第二信号端提供第二时钟信号，向第三信号端提供第三时钟信号，以使：输入子电路在第一时钟信号的控制下保持关断；第一控制子电路在第一节点的信号控制下导通，并将第一信号端的信号写入第二节点；第二控制子电路在第三信号端、第二节点的信号控制下保持关断；输出子电路在第二节点和第一节点的信号控制下导通，将第二信号端的信号写入输出端。
示例性地，在第二阶段，输出子电路在第一节点N1的低电平信号控制下将第二信号端S2的低电平信号写入输出端Gout，从而使移位寄存器通过输出 端Gout输出第二信号端S2的低电平信号。第一控制子电路在第一节点N1的低电平信号控制下将第一信号端S1的高电平信号写入第二节点N2。并且，第二控制子电路在第二节点N2和第三信号端S3的信号控制下不导通，使第一节点N1和第二节点N2不连接。
本公开实施例提供的扫描驱动电路的控制方法，通过不同的时钟信号线向同一移位寄存器的第一信号端S1、第二信号端S2和第三信号端S3分别提供信号。即，同一移位寄存器中，与第二信号端S2连接的时钟信号线与输出子电路连接，而不与第二控制子电路连接，降低了与第二信号端S2连接的时钟信号线的负载。与第二信号端S2连接的时钟信号线的负载降低后，第二信号端S2的信号进行高电平切换所需要的时间更短(输出端Gout由高电平切换为低电平所需要的时间更短)，即移位寄存器输出信号的下降沿时间Tf较小，缩小了数据写入控制端Gate和复位控制端Reset信号的上升沿时间和下降沿时间差异，改善了显示不良。
在一些实施例中，第二控制子电路包括第七晶体管T7。第七晶体管T7的控制极与第三信号端S3连接，第七晶体管T7的第一极与第三节点N3连接，第七晶体管T7的第二极与第一节点N1连接。第七晶体管T7被配置为，响应于第三信号端S3的信号将第三节点N3的信号写入第一节点N1。输出子电路包括第五晶体管T5、第八晶体管T8、第二电容C2。第五晶体管T5的控制极与第四节点N4连接，第五晶体管T5的第一极与第二信号端S2连接，第五晶体管T5的第二极与输出端Gout连接。第五晶体管T5被配置为，响应于第四节点N4的信号将第二信号端S2的信号写入输出端Gout。第八晶体管T8的控制极与第一电压端V1连接，第八晶体管T8的第一极与第一节点N1连接，第八晶体管T8的第二极与第四节点N4连接。第八晶体管T8被配置为，响应于第一电压端V1的信号，将第一节点N1的信号写入第四节点N4，或将第四节点N4的信号写入第一节点N1。第二电容C2的一个极板与输出端Gout连接，另一极板与第四节点N4连接。第二电容C2被配置为储存第四节点N4的信号，使第四节点N4的信号不会发生突变。
同一帧周期内，第二信号的有效电平时段与第三信号的有效电平时段有交叠，且第二信号中有效电平的前沿提前于第三信号中有效电平的前沿。
示例性地，向第二信号端S2提供有效电平信号的时刻为第一时刻t1，向 第三信号端S3提供有效电平信号的时刻为第二时刻t2，第一时刻t1比第二时刻t2早。
第二阶段，在第一时刻t1至第二时刻t2范围内，第二信号端S2的信号切换为低电平信号，第四节点N4和第一节点N1在第二电容C2的作用下保持低电平，使得第五晶体管T5和第二晶体管T2导通。此时，第三信号端S3的信号仍然为高电平信号，第七晶体管T7不导通，第二电容C2储存的电荷不会经过第七晶体管T7释放到第三节点N3，也不会对第七晶体管T7的栅极与有源层之间形成的寄生电容充电，使第一节点N1和第四节点N4维持低电平信号，从而使第五晶体管T5和第二晶体管T2的开启状态较好。防止第二电容C2储存的电荷经过第七晶体管T7释放，导致的第四节点N4电位升高，从而影响移位寄存器的输出。
第二信号的占空比可以小于或等于第三信号的占空比。示例性地，同一帧周期内，第二信号中有效电平的后沿与第三信号中有效电平的后沿同步。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本公开的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
最后应说明的是：以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (18)

  1. 一种扫描驱动电路，其中，包括多条时钟信号线以及多个级联的移位寄存器；所述移位寄存器包括输入子电路、第一控制子电路、第二控制子电路和输出子电路；
    所述输入子电路与起始信号端、第一节点、第一信号端连接，所述输入子电路被配置为在所述第一信号端的信号控制下将所述起始信号端的信号写入所述第一节点；
    所述第一控制子电路与所述第一信号端、第二节点、所述第一节点连接，所述第一控制子电路被配置为在所述第一节点的信号控制下将所述第一信号端的信号写入所述第二节点；
    所述第二控制子电路与所述第一节点、所述第二节点、第二电压端、第三信号端连接，所述第二控制子电路被配置为在所述第二节点和所述第三信号端的信号控制下，将所述第二电压端的信号写入所述第一节点；
    所述输出子电路与所述第一节点、所述第二节点、输出端、第二信号端、所述第二电压端连接，所述输出子电路被配置为在所述第一节点的信号控制下将所述第二信号端的信号写入所述输出端，还被配置为在所述第一节点的信号控制下将所述第二电压端的信号写入所述输出端；
    同一所述移位寄存器的所述第二信号端和所述第三信号端与不同的所述时钟信号线连接。
  2. 根据权利要求1所述的扫描驱动电路，其中，所述多条时钟信号线划分为多个时钟信号线组，每个所述时钟信号线组包括多条所述时钟信号线；
    所述多个时钟信号线组包括第一时钟信号线组和第二时钟信号线组，两个级联的所述移位寄存器中的所述第三信号端与所述第一时钟信号线组中的不同时钟信号线连接，两个级联的所述移位寄存器中的所述第二信号端与所述第二时钟信号线组中的不同时钟信号线连接。
  3. 根据权利要求2所述的扫描驱动电路，其中，两个级联的所述移位寄存器中的所述第一信号端与所述第二时钟信号线组中的不同时钟信号线连接，且同一所述移位寄存器中，所述第一信号端和所述第二信号端与所述第二时钟信号线组中的不同时钟信号线连接。
  4. 根据权利要求1所述的扫描驱动电路，其中，所述时钟信号线包括第一时钟信号线、第二时钟信号线、第三时钟信号线和第四时钟信号线，所述多个移位寄存器包括级联的第一移位寄存器和第二移位寄存器；
    所述第一移位寄存器中，所述第一信号端与所述第一时钟信号线连接，所述第二信号端与所述第二时钟信号线连接，所述第三信号端与所述第四时钟信号线连接；
    所述第二移位寄存器中，所述第一信号端与所述第二时钟信号线连接，所述第二信号端与所述第一时钟信号线连接，所述第三信号端与所述第三时钟信号线连接。
  5. 根据权利要求4所述的扫描驱动电路，其中，所述多个移位寄存器包括多个所述第一移位寄存器和多个所述第二移位寄存器，所述第一移位寄存器和所述第二移位寄存器交错排列。
  6. 根据权利要求4所述的扫描驱动电路，其中，多个移位寄存器还包括第五移位寄存器和第六移位寄存器，第一移位寄存器、第二移位寄存器、第五移位寄存器、第六移位寄存器依次级联；
    所述第五移位寄存器中，所述第一信号端与所述第三时钟信号线连接，所述第二信号端与所述第四时钟信号线连接，所述第三信号端与所述第二时钟信号线连接；
    所述第六移位寄存器中，所述第一信号端与所述第四时钟信号线连接，所述第二信号端与所述第三时钟信号线连接，所述第三信号端与所述第一时钟信号线连接。
  7. 根据权利要求4所述的扫描驱动电路，其中，所述时钟信号线还包括第五时钟信号线和第六时钟信号线，所述多个移位寄存器还包括第三移位寄存器和第四移位寄存器，所述第一移位寄存器、所述第二移位寄存器、所述第三移位寄存器、所述第四移位寄存器依次排布且级联；
    所述第三移位寄存器中，所述第一信号端与所述第五时钟信号线连接，所述第二信号端与所述第六时钟信号线连接，所述第三信号端与所述第四时钟信号线连接；
    所述第四移位寄存器中，所述第一信号端与所述第六时钟信号线连接，所述第二信号端与所述第五时钟信号线连接，所述第三信号端与所述第三时钟信号线连接。
  8. 根据权利要求1所述的扫描驱动电路，其中，所述第二控制子电路包括第六晶体管和第七晶体管；
    所述第六晶体管，栅极与所述第二节点连接，第一极与所述第二电压端连接，第二极与第三节点连接；
    所述第七晶体管，栅极与所述第三信号端连接，第一极与所述第三节点连接，第二极与所述第一节点连接。
  9. 根据权利要求1所述的扫描驱动电路，其中，所述输出子电路包括第四晶体管、第五晶体管、第一电容和第二电容；
    所述第四晶体管，栅极与所述第二节点连接，第一极与所述第二电压端连接，第二极与所述输出端连接；
    所述第五晶体管，栅极与所述第一节点连接，第一极与所述第二信号端连接，第二极与所述输出端连接；
    所述第一电容，一个极板与所述第二电压端连接，另一极板与所述第二节点连接；
    所述第二电容，一个极板与所述输出端连接，另一极板与所述第一节点连接。
  10. 根据权利要求1所述的扫描驱动电路，其中，所述输入子电路包括第一晶体管；
    所述第一晶体管，栅极与所述第一信号端连接，第一极与所述起始信号端连接，第二极与所述第一节点连接。
  11. 根据权利要求1所述的扫描驱动电路，其中，所述第一控制子电路包括第二晶体管；
    所述第二晶体管，栅极与所述第一节点连接，第一极与所述第一信号端连接，第二极与所述第二节点连接。
  12. 根据权利要求1所述的扫描驱动电路，其中，所述第一控制子电路还与第一电压端连接，所述第一控制子电路还被配置为在所述第一信号端的信号控制下，将所述第一电压端的信号写入所述第二节点。
  13. 根据权利要求12所述的扫描驱动电路，其中，所述第一控制子电路包括第三晶体管；
    所述第三晶体管，栅极与所述第一信号端连接，第一极与所述第一电压端连接，第二极与所述第二节点连接。
  14. 一种显示面板，其中，包括如权利要求1-13中任一项所述的扫描驱动电路和多个像素驱动电路，所述扫描驱动电路的输出端与所述像素驱动电路连接。
  15. 一种显示装置，其中，包括如权利要求14所述的显示面板。
  16. 一种扫描驱动电路的控制方法，用于控制如权利要求1-13中任一项 所述的扫描驱动电路，其中，同一帧周期内包括第一阶段和第二阶段，所述控制方法包括：
    在所述第一阶段，向第一信号端提供第一时钟信号，向第二信号端提供第二时钟信号，向第三信号端提供第三时钟信号，以使：
    输入子电路在所述第一信号端的信号控制下导通，并将起始信号端的信号写入第一节点；
    第一控制子电路在所述第一节点的信号控制下导通，将所述第一信号端的信号写入第二节点；
    第二控制子电路在所述第二节点、所述第三信号端的信号控制下保持关断；
    输出子电路在所述第一节点、所述第二节点的信号控制下导通，并将所述第二信号端、第二电压端的信号写入输出端；
    在所述第二阶段，向所述第一信号端提供第一时钟信号，向所述第二信号端提供第二时钟信号，向所述第三信号端提供第三时钟信号，以使：
    所述输入子电路在所述第一时钟信号的控制下保持关断；
    所述第一控制子电路在所述第一节点的信号控制下导通，并将所述第一信号端的信号写入所述第二节点；
    所述第二控制子电路在所述第三信号端、所述第二节点的信号控制下保持关断；
    所述输出子电路在所述第二节点和所述第一节点的信号控制下导通，将所述第二信号端的信号写入所述输出端。
  17. 根据权利要求16所述的扫描驱动电路的控制方法，其中，同一帧周期内，所述第二信号的有效电平时段与所述第三信号的有效电平时段有交叠，且所述第二信号中有效电平的前沿提前于所述第三信号中有效电平的前沿。
  18. 根据权利要求17所述的扫描驱动电路的控制方法，其中，所述第二信号的占空比小于或等于所述第三信号的占空比。
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