WO2024176583A1 - 電界効果トランジスタの製造方法 - Google Patents

電界効果トランジスタの製造方法 Download PDF

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WO2024176583A1
WO2024176583A1 PCT/JP2023/044980 JP2023044980W WO2024176583A1 WO 2024176583 A1 WO2024176583 A1 WO 2024176583A1 JP 2023044980 W JP2023044980 W JP 2023044980W WO 2024176583 A1 WO2024176583 A1 WO 2024176583A1
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type
trench
layer
lower layer
semiconductor substrate
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French (fr)
Japanese (ja)
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秀史 高谷
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Denso Corp
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Denso Corp
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Priority to CN202380091339.4A priority Critical patent/CN120604636A/zh
Priority to EP23924227.4A priority patent/EP4672305A1/en
Priority to JP2025502127A priority patent/JPWO2024176583A1/ja
Publication of WO2024176583A1 publication Critical patent/WO2024176583A1/ja
Priority to US19/307,467 priority patent/US20250380468A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/054—Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/058—Forming charge compensation regions, e.g. superjunctions by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • the technology disclosed in this specification relates to a method for manufacturing a field effect transistor.
  • JP2009-194065A discloses a trench-gate type field effect transistor.
  • This field effect transistor has multiple p-type deep layers that protrude downward from a body layer. Each p-type deep layer extends so as to intersect with the trench when the semiconductor substrate is viewed from above. The multiple p-type deep layers are arranged with gaps in their width direction. An n-type deep layer is provided within each gap. Each p-type deep layer and each n-type deep layer extends from the body layer to below the bottom surface of the trench. An n-type drift layer is arranged below the p-type deep layer and n-type deep layer. This structure can improve the breakdown voltage in the field effect transistor.
  • a p-layer (hereinafter referred to as the p-type trench lower layer) is provided at the bottom of the trench and extends along the trench, the feedback capacitance of the field effect transistor can be reduced and high-speed switching can be achieved.
  • This specification proposes a technology that effectively reduces the feedback capacitance of a field effect transistor by appropriately adjusting the p-type impurity concentration in the p-type trench lower layer during the manufacturing process of the field effect transistor.
  • the method for manufacturing a field effect transistor disclosed in this specification includes a semiconductor substrate preparation step, a body layer formation step, a trench formation step, a p-type trench lower layer formation step, and a gate electrode formation step.
  • a semiconductor substrate preparation step a semiconductor substrate having an n-type drift layer, a plurality of p-type deep layers, and a plurality of n-type deep layers is prepared.
  • the plurality of p-type deep layers and the plurality of n-type deep layers are arranged on the upper part of the n-type drift layer.
  • each of the p-type deep layers extends along a first direction and is arranged with a gap in a second direction perpendicular to the first direction.
  • Each of the n-type deep layers is arranged within the corresponding gap.
  • the semiconductor substrate is prepared in which the n-type impurity concentration of each of the n-type deep layers is higher than the n-type impurity concentration of the n-type drift layer.
  • a p-type body layer that contacts the plurality of p-type deep layers and the plurality of n-type deep layers from above is formed by ion-implanting p-type impurities into the semiconductor substrate.
  • a trench is formed on the upper surface of the semiconductor substrate.
  • the trench is formed so that when the semiconductor substrate is viewed from above, the trench intersects with the p-type deep layers, penetrates the body layer, and the lower end of the trench is located above the lower ends of the p-type deep layers.
  • a p-type trench lower layer connected to each of the p-type deep layers is formed below the trench by injecting p-type impurities into the bottom surface of the trench while the upper surface of the semiconductor substrate is covered with an ion implantation mask.
  • the gate electrode forming process a gate insulating film and a gate electrode are formed in the trench.
  • p-type impurities are injected at a higher concentration than in the body layer forming process.
  • the p-type trench lower layer may be formed in a position that contacts the bottom surface of the trench, or in a position away from the bottom surface of the trench (i.e., deeper than the bottom surface of the trench).
  • ion implantation into the body layer and ion implantation into the p-type trench lower layer are performed in separate processes, so the p-type impurity concentration in the p-type trench lower layer can be controlled independently from the p-type impurity concentration in the body layer.
  • the p-type impurity is implanted at a higher concentration than in the body layer formation process. Therefore, when a voltage is applied to a field effect transistor manufactured by this manufacturing method, the p-type trench lower layer is less likely to be depleted. Therefore, the feedback capacitance of the field effect transistor can be effectively reduced.
  • FIG. 2 is a cross-sectional perspective view of the MOSFET 10 (a view showing an xz cross section not including a p-type deep layer 36).
  • FIG. 2 is a cross-sectional perspective view of the MOSFET 10 with the source electrode 22 and the interlayer insulating film 20 omitted (a view showing an xz cross section not including the p-type deep layer 36).
  • An enlarged xy cross-section of MOSFET 10 including the p-type trench lower layer 35, the p-type deep layer 36, and the n-type deep layer 37, showing the arrangement of the p-type trench lower layer 35, the p-type deep layer 36, and the n-type deep layer 37 when the semiconductor substrate 12 is viewed from above.
  • FIG. 2 is a cross-sectional perspective view of the MOSFET 10 (a view showing an xz cross section including a p-type deep layer 36).
  • 4 is a cross-sectional view showing the distribution of non-depleted regions in a p-type trench lower layer 35.
  • 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10.
  • 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10.
  • 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10.
  • 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10.
  • 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10.
  • 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10.
  • 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10.
  • FIG. 11A to 11C are explanatory diagrams of a manufacturing method of a modified example.
  • FIG. 2 is a cross-sectional perspective view of a MOSFET according to a first modified example, the cross-sectional view corresponding to FIG. 1 .
  • FIG. 2 is a cross-sectional perspective view of a MOSFET according to a second modification, the cross-sectional view corresponding to FIG. 1 .
  • FIG. 11 is a cross-sectional perspective view of a MOSFET according to a third modified example, the cross-sectional view corresponding to FIG.
  • FIG. 11 is a sectional perspective view of a MOSFET according to a fourth modification, the view corresponding to FIG. FIG.
  • FIG. 13 is a cross-sectional perspective view of a MOSFET according to a fifth modified example, the cross-sectional view corresponding to FIG. FIG. 13 is a cross-sectional perspective view of a MOSFET according to a sixth modified example, the cross-sectional view corresponding to FIG. FIG. 13 is a sectional perspective view of a MOSFET according to a seventh modification, the view corresponding to FIG. FIG. 13 is a cross-sectional perspective view of a MOSFET according to an eighth modification, the cross-sectional view corresponding to FIG. FIG. 13 is a cross-sectional perspective view of a MOSFET according to a ninth modification, which corresponds to FIG. 6 .
  • the ion implantation depth in the p-type trench lower layer formation process may be shallower than the ion implantation depth in the body layer formation process.
  • Ion implantation may be performed multiple times while changing the ion implantation depth in the p-type trench lower layer formation process.
  • the above "ion implantation depth in the p-type trench lower layer formation process” refers to the deepest ion implantation depth in the p-type trench lower layer formation process.
  • Ion implantation may be performed multiple times while changing the ion implantation depth in the body layer formation process.
  • the above "ion implantation depth in the body layer formation process” refers to the deepest ion implantation depth in the body layer formation process.
  • This configuration allows the formation of a thin p-type trench lower layer, improving the breakdown voltage of the field effect transistor.
  • the p-type trench lower layer in the p-type trench lower layer forming step, may be formed so that the lower end of the p-type trench lower layer is located above the lower ends of each of the n-type deep layers.
  • the depletion layer is less likely to extend from the lower layer of the p-type trench to the drift layer when the field-effect transistor is in the on-state, so the on-resistance of the field-effect transistor can be reduced.
  • the p-type trench lower layer in the p-type trench lower layer forming step, may be formed so that the p-type trench lower layer is in contact with the bottom surface of the trench.
  • the total amount of p-type impurities in the p-type trench lower layer may be set so that a non-depleted region remains in a portion of the p-type trench lower layer that is in contact with the gate insulating film when a rated voltage is applied to the field effect transistor.
  • This configuration effectively reduces the feedback capacitance of the field effect transistor.
  • the p-type trench lower layer forming step may form the p-type trench lower layer having a first p-type trench lower layer and a second p-type trench lower layer.
  • the second p-type trench lower layer may have a higher p-type impurity concentration than the first p-type trench lower layer and may be located above or below the first p-type trench lower layer.
  • p-type impurities may be implanted into the bottom surface of the trench while the bottom surface and side surfaces of the trench are exposed.
  • This configuration allows the formation of a p-type trench lower layer having a width that is approximately equal to the width of the bottom surface of the trench. This configuration allows the electric field applied to the gate insulating film to be suppressed, and the on-resistance of the field-effect transistor to be reduced.
  • an etching mask may be formed on the upper surface of the semiconductor substrate, and the upper surface of the semiconductor substrate may be etched through the etching mask to form the trench.
  • the etching mask may be used as the ion implantation mask.
  • This configuration allows for efficient manufacturing of field effect transistors.
  • the semiconductor substrate preparation step may include preparing the semiconductor substrate having an n-type connection layer.
  • the n-type connection layer may be disposed below each of the p-type deep layers and connect the n-type deep layers to each other.
  • the n-type impurity concentration of the n-type connection layer may be higher than the n-type impurity concentration of the n-type drift layer.
  • the depletion layer is less likely to extend from the p-type deep layer to the drift layer when the field-effect transistor is in the on-state, reducing the on-resistance of the field-effect transistor.
  • the MOSFET 10 metal-oxide-semiconductor field effect transistor of the embodiment shown in Figures 1 and 2 has a semiconductor substrate 12.
  • the thickness direction of the semiconductor substrate 12 is referred to as the z-direction
  • one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction
  • the direction perpendicular to the x-direction and z-direction is referred to as the y-direction.
  • the semiconductor substrate 12 is made of silicon carbide (i.e., SiC).
  • the semiconductor substrate 12 may be made of other semiconductor materials such as silicon and gallium nitride.
  • a plurality of trenches 14 are provided in the upper surface 12a of the semiconductor substrate 12. As shown in Figure 2, the plurality of trenches 14 extend long along the y-direction on the upper surface 12a. The plurality of trenches 14 are arranged at intervals in the x-direction.
  • each trench 14 is covered with a gate insulating film 16.
  • a gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. As shown in FIG. 1, the upper surface of each gate electrode 18 is covered with an interlayer insulating film 20.
  • a source electrode 22 is provided on the upper part of the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 at a position where the interlayer insulating film 20 is not present.
  • a drain electrode 24 is disposed on the lower part of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire lower surface 12b of the semiconductor substrate 12.
  • the semiconductor substrate 12 has a plurality of source layers 30, a plurality of contact layers 32, a body layer 34, a plurality of p-type trench lower layers 35, a plurality of p-type deep layers 36, a plurality of n-type deep layers 37, an n-type connection layer 37x, a drift layer 38, and a drain layer 40.
  • Each source layer 30 is an n-type layer with a high n-type impurity concentration. Each source layer 30 is disposed in an area that partially includes the upper surface 12a of the semiconductor substrate 12. Each source layer 30 is in ohmic contact with the source electrode 22. Each source layer 30 is in contact with the gate insulating film 16 at the top of the side surface of the trench 14. Each source layer 30 faces the gate electrode 18 via the gate insulating film 16. Each source layer 30 extends long in the y direction along the side surface of the trench 14.
  • Each contact layer 32 is a p-type layer with a high p-type impurity concentration. Each contact layer 32 is disposed in an area that partially includes the upper surface 12a of the semiconductor substrate 12. Each contact layer 32 is disposed between two corresponding source layers 30. Each contact layer 32 is in ohmic contact with the source electrode 22. Each contact layer 32 extends long in the y direction.
  • the body layer 34 is a p-type layer having a lower p-type impurity concentration than the contact layer 32.
  • the body layer 34 is disposed below the multiple source layers 30 and the multiple contact layers 32.
  • the body layer 34 contacts the multiple source layers 30 and the multiple contact layers 32 from below.
  • the body layer 34 contacts the gate insulating film 16 on the side of the trench 14 located below the source layer 30.
  • the body layer 34 faces the gate electrode 18 via the gate insulating film 16.
  • Each p-type trench lower layer 35 is a p-type layer disposed under the corresponding trench 14.
  • the p-type impurity concentration of each p-type trench lower layer 35 is higher than the p-type impurity concentration of the body layer 34 and lower than the p-type impurity concentration of the contact layer 32.
  • Each p-type trench lower layer 35 contacts the gate insulating film 16 at the bottom surface of the corresponding trench 14.
  • the width (i.e., the dimension in the x direction) of each p-type trench lower layer 35 is approximately equal to the width (i.e., the dimension in the x direction) of the bottom surface of the trench 14 above it. As shown in FIG. 3, when the semiconductor substrate 12 is viewed from above, each p-type trench lower layer 35 extends long along the longitudinal direction of the corresponding trench 14 (the y direction in this example).
  • Each p-type deep layer 36 is a p-type layer protruding downward from the lower surface of the body layer 34.
  • the p-type impurity concentration of each p-type deep layer 36 is higher than the p-type impurity concentration of the body layer 34 and lower than the p-type impurity concentration of the contact layer 32.
  • each p-type deep layer 36 extends long in the x direction and is perpendicular to the longitudinal direction of the trench 14 (in this example, the y direction).
  • the multiple p-type deep layers 36 are arranged at intervals in the y direction.
  • the portion between the multiple p-type deep layers 36 is referred to as the interval portion 39 (see FIGS.
  • the p-type deep layer 36 has a shape that is long in the z direction in the yz cross section. That is, the dimension of the p-type deep layer 36 in the z direction (hereinafter referred to as the depth Dp) is larger than the dimension of the p-type deep layer 36 in the y direction (hereinafter referred to as the width Wp).
  • each p-type deep layer 36 extends from the lower surface of the body layer 34 to a depth below the bottom surface of each trench 14.
  • Each p-type deep layer 36 contacts the gate insulating film 16 on the side of the trench 14 located below the body layer 34.
  • each p-type deep layer 36 contacts the p-type trench lower layer 35 located below the trench 14.
  • Each n-type deep layer 37 is an n-type layer disposed in the corresponding gap 39. Each n-type deep layer 37 has a higher n-type impurity concentration than the drift layer 38. As shown in FIGS. 1 and 2, each n-type deep layer 37 is in contact with the lower surface of the body layer 34. Each n-type deep layer 37 is in contact with the side surfaces of the p-type deep layers 36 on both sides. Each n-type deep layer 37 extends from the lower surface of the body layer 34 to a position lower than the bottom surface of each trench 14 and the lower surface of each p-type deep layer 36. As shown in FIG. 5, the n-type deep layer 37 in the gap 39 has a shape that is long in the z direction in the yz cross section.
  • each n-type deep layer 37 in the z direction (hereinafter referred to as the depth Dn) is larger than the dimension of the n-type deep layer 37 in the gap 39 in the y direction (hereinafter referred to as the width Wn).
  • each n-type deep layer 37 contacts the gate insulating film 16 on the side of the trench 14 located below the body layer 34 within each gap 39.
  • each n-type deep layer 37 contacts the p-type trench lower layer 35 located below the trench 14.
  • an n-type connection layer 37x is disposed below each p-type deep layer 36.
  • the n-type connection layer 37x has a higher n-type impurity concentration than the drift layer 38.
  • the n-type connection layer 37x has approximately the same n-type impurity concentration as the n-type deep layer 37.
  • Each n-type connection layer 37x is in contact with the lower surface of the corresponding p-type deep layer 36.
  • Each n-type connection layer 37x connects two n-type deep layers 37 located on either side of the p-type deep layer 36.
  • the drift layer 38 is an n-type layer having a lower n-type impurity concentration than each n-type deep layer 37.
  • the drift layer 38 is disposed below the n-type deep layer 37 and the n-type connection layer 37x.
  • the drift layer 38 contacts the n-type deep layer 37 and the n-type connection layer 37x from below.
  • the drain layer 40 is an n-type layer having a higher n-type impurity concentration than the drift layer 38 and the n-type deep layer 37.
  • the drain layer 40 is in contact with the drift layer 38 from below.
  • the drain layer 40 is disposed in an area including the lower surface 12b of the semiconductor substrate 12.
  • the drain layer 40 is in ohmic contact with the drain electrode 24.
  • the MOSFET 10 is used with a higher potential applied to the drain electrode 24 than to the source electrode 22.
  • a potential equal to or greater than the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 near the gate insulating film 16.
  • the channel connects the source layer 30 and the n-type deep layer 37.
  • electrons flow from the source layer 30 through the channel, the n-type deep layer 37, and the drift layer 38 to the drain layer 40.
  • the MOSFET 10 is turned on.
  • the potential of each gate electrode 18 is reduced from a value equal to or greater than the gate threshold to a value less than the gate threshold, the channel disappears and the flow of electrons stops. In other words, the MOSFET 10 is turned off.
  • a channel When a channel is formed, electrons flow from the source layer 30 through the channel into the n-type deep layer 37. The electrons flow from the upper end to the lower end of the n-type deep layer 37 and into the drift layer 38. Therefore, a path through which the electrons flow (i.e., a current path) is formed in the n-type deep layer 37.
  • a depletion layer of a certain width extends from the p-type trench lower layer 35 and the p-type deep layer 36 to the n-type deep layer 37 due to the built-in potential.
  • the width of the depletion layer in the n-type deep layer 37 the narrower the current path in the n-type deep layer 37.
  • the n-type deep layer 37 has a higher n-type impurity concentration than the drift layer 38, the width of the depletion layer extending into the n-type deep layer 37 is narrow. Therefore, a wide current path is secured in the n-type deep layer 37. This reduces the on-resistance of the MOSFET.
  • the n-type impurity concentration of the drift layer 38 is low, a depletion layer easily spreads in the drift layer 38. If the p-type trench lower layer 35 and the p-type deep layer 36 were in direct contact with the drift layer 38, a relatively wide depletion layer would spread from the p-type trench lower layer 35 and the p-type deep layer 36 to the drift layer 38 when the MOSFET 10 is in the on state. In this case, the depletion layer narrows the current path in the drift layer 38, and the on-resistance of the MOSFET 10 increases.
  • the n-type deep layer 37 and the n-type connection layer 37x having a higher n-type impurity concentration than the drift layer 38 are provided below the p-type trench lower layer 35 and the p-type deep layer 36. That is, the p-type trench lower layer 35 and the p-type deep layer 36 are not in contact with the drift layer 38. Therefore, the depletion layer is less likely to spread to the drift layer 38 when the MOSFET 10 is in the on state. As a result, the on-resistance of the MOSFET 10 of this embodiment is further reduced.
  • each p-type deep layer 36 is electrically connected to the body layer 34 and has approximately the same potential as the body layer 34. Therefore, when the channel disappears, a reverse voltage is also applied to the pn junction at the interface between each p-type deep layer 36 and each n-type deep layer 37. Therefore, a depletion layer spreads from each p-type deep layer 36 to each n-type deep layer 37.
  • each p-type trench lower layer 35 is electrically connected to the body layer 34 via each p-type deep layer 36 and has approximately the same potential as the body layer 34. Therefore, when the channel disappears, a reverse voltage is also applied to the pn junction at the interface between each p-type trench lower layer 35 and each n-type deep layer 37. Therefore, the depletion layer also spreads from each p-type trench lower layer 35 to each n-type deep layer 37. In this way, each n-type deep layer 37 is quickly depleted by the depletion layer spreading from the body layer 34, each p-type trench lower layer 35, and each p-type deep layer 36.
  • each p-type trench lower layer 35 is provided below the corresponding trench 14, the periphery of the bottom surface of the trench 14 is depleted well. This significantly alleviates the electric field concentration near the bottom surface of the trench 14.
  • the width of the p-type trench lower layer 35 is almost equal to the width of the bottom surface of the trench 14, the electric field applied to the gate insulating film 16 covering the bottom surface of the trench 14 can be suitably alleviated.
  • the entire n-type deep layer 37 is depleted by the depletion layer spreading from the body layer 34, each p-type trench lower layer 35, and each p-type deep layer 36.
  • each n-type deep layer 37 has a higher n-type impurity concentration than the drift layer 38, the depletion layer is less likely to spread in each n-type deep layer 37 than in the drift layer 38.
  • each n-type deep layer 37 is sandwiched between the p-type deep layers 36, the entire n-type deep layer 37 is depleted.
  • the depletion layer spreads to the drift layer 38 through each n-type deep layer 37 and the n-type connection layer 37x. Since the n-type impurity concentration of the drift layer 38 is low, almost the entire drift layer 38 is depleted.
  • the depleted drift layer 38 and each n-type deep layer 37 hold the high voltage applied between the drain electrode 24 and the source electrode 22. Therefore, the MOSFET 10 has a high breakdown voltage.
  • the depletion layer extends from the n-type deep layer 37 to the p-type trench lower layer 35.
  • the p-type impurity concentration of the p-type trench lower layer 35 is higher than the p-type impurity concentration of the body layer 34. Therefore, the depletion layer does not easily spread in the p-type trench lower layer 35, and a non-depleted region remains in the p-type trench lower layer 35 when the MOSFET 10 is in the off state.
  • the total amount of p-type impurities in each p-type trench lower layer 35 is set so that a non-depleted region remains in each p-type trench lower layer 35 when a rated voltage is applied between the drain electrode 24 and the source electrode 22. Therefore, as shown in FIG. 7, a non-depleted region 60 remains in a part of each p-type trench lower layer 35 that contacts the gate insulating film 16 covering the bottom surface of the trench 14. In this way, when the MOSFET 10 is in the off state, the non-depleted region 60 remains at the bottom of the trench 14, so the electrostatic capacitance (i.e., feedback capacitance) between the gate electrode 18 and the drain electrode 24 is small. This allows the MOSFET 10 to switch at high speed.
  • electrostatic capacitance i.e., feedback capacitance
  • a pn diode (so-called body diode) is formed by a p-type anode layer consisting of the contact layer 32, the body layer 34, the p-type deep layer 36, and the p-type trench lower layer 35, and an n-type cathode layer consisting of the n-type deep layer 37, the n-type connection layer 37x, the drift layer 38, and the drain layer 40.
  • the potential of the source electrode 22 becomes higher than the potential of the drain electrode 24, the body diode is turned on.
  • an n-type deep layer 37 and an n-type connection layer 37x having a higher n-type impurity concentration than the drift layer 38 are provided below the p-type trench lower layer 35 and the p-type deep layer 36. That is, the p-type trench lower layer 35 and the p-type deep layer 36 are not in contact with the drift layer 38.
  • the n-type deep layer 37 and the n-type connection layer 37x suppress the inflow of holes from the p-type trench lower layer 35 and the p-type deep layer 36 to the drift layer 38. This suppresses the growth of crystal defects at the interface between the drift layer 38 and the drain layer 40.
  • MOSFET 10 is manufactured from a semiconductor substrate whose entire structure is made up of drain layer 40.
  • a semiconductor substrate preparation process First, a semiconductor substrate preparation process is performed. In the semiconductor substrate preparation process, first, as shown in FIG. 8, an n-type epitaxial layer 50 is formed on the drain layer 40 using an epitaxial growth technique. Next, as shown in FIG. 9, ions are implanted into the upper surface of the semiconductor substrate to form an n-type deep layer 37, an n-type connection layer 37x, and a p-type deep layer 36 inside the epitaxial layer 50.
  • the n-type deep layer 37, the n-type connection layer 37x, and the p-type deep layer 36 are formed by introducing n-type impurities and p-type impurities into a depth range R1 away from the upper surface of the semiconductor substrate 12.
  • n-type impurities are introduced planarly into the depth range R1.
  • the p-type deep layer 36 is formed by counter-doping a p-type impurity through a mask toward a part of the depth range R1.
  • the layers remaining as n-type in the depth range R1 become the n-type deep layer 37 and the n-type connection layer 37x.
  • the low-concentration n-type layer remaining below the depth range R1 becomes the drift layer 38.
  • a low-concentration n-type layer remains above the depth range R1.
  • a structure is formed in which a plurality of p-type deep layers 36 and a plurality of n-type deep layers 37 are arranged on the upper part of the drift layer 38.
  • the p-type deep layers 36 extend along the x direction and are arranged with gaps in the y direction.
  • the n-type deep layers 37 are arranged in each gap.
  • the n-type connection layers 37x are arranged below the p-type deep layers 36 and connect the n-type deep layers 37 to each other.
  • the n-type impurity concentrations of the n-type deep layers 37 and the n-type connection layers 37x are higher than the n-type impurity concentration of the drift layer 38.
  • the n-type deep layers 37, the n-type connection layers 37x, and the p-type deep layers 36 may be formed by sequentially introducing n-type impurities and p-type impurities through masks corresponding to the n-type deep layers 37, the n-type connection layers 37x, and the p-type deep layers 36, respectively.
  • the concentration of n-type impurities in the depth range R1 in advance when epitaxially growing the epitaxial layer 50 it is possible to omit the ion implantation for forming the n-type deep layer 37 and the n-type connection layer 37x.
  • a body layer forming process is performed.
  • a body layer 34 is formed in the surface layer of the semiconductor substrate 12 by ion-implanting p-type impurities into the upper surface of the semiconductor substrate.
  • the body layer 34 is formed so that the body layer 34 contacts the multiple p-type deep layers 36 and the multiple n-type deep layers 37 from above.
  • the body layer 34 is formed over the entire depth range above the p-type deep layers 36 and the n-type deep layers 37 by injecting p-type impurities multiple times while changing the ion implantation depth.
  • the depth D1 in FIG. 10 is the distance in the z direction from the upper surface of the semiconductor substrate to the lower end of the body layer 34.
  • the depth D1 is the deepest ion implantation depth in the body layer forming process.
  • a diffusion layer formation process is performed, in which an n-type impurity and a p-type impurity are introduced into the surface layer of the semiconductor substrate by ion implantation technology to form a source layer 30 and a contact layer 32, as shown in FIG.
  • a trench forming process is performed.
  • an etching mask 52 is formed on the upper surface of the semiconductor substrate (i.e., the upper surface of the epitaxial layer 50).
  • the etching mask 52 has an opening 52a.
  • the upper surface of the semiconductor substrate is dry etched through the etching mask 52. That is, the upper surface of the semiconductor substrate exposed in the opening 52a is dry etched. As a result, a plurality of trenches 14 are formed on the upper surface of the semiconductor substrate.
  • each trench 14 is formed so that the trench 14 intersects with the plurality of p-type deep layers 36 and the plurality of n-type deep layers 37. Also, here, each trench 14 is formed so that each trench 14 penetrates the source layer 30 and the body layer 34, and the lower end (i.e., the bottom surface) of each trench 14 is located within the depth range of the p-type deep layer 36 and the n-type deep layer 37. That is, the depth of the trench 14 is adjusted so that the bottom end of the trench 14 is located above the bottom ends of the n-type deep layer 37 and the p-type deep layer 36 .
  • a p-type trench lower layer forming step is performed.
  • a p-type trench lower layer 35 is formed using an ion implantation technique.
  • the etching mask 52 used in the trench forming step is used as an ion implantation mask as it is, and p-type impurities are ion-implanted into the semiconductor substrate from above.
  • ion implantation is performed in a state where the bottom and side surfaces of the trench 14 are exposed. The p-type impurities are implanted into the bottom surface of the trench 14.
  • the side surfaces of the trench 14 are approximately parallel to the ion implantation direction, almost no p-type impurities are implanted into the side surfaces of the trench 14. Since the upper surface of the semiconductor substrate is covered by the mask 52, no p-type impurities are implanted into the upper surface of the semiconductor substrate. Therefore, the p-type impurities can be selectively implanted into the bottom surface of the trench 14. As a result, the p-type trench lower layer 35 is formed in the lower part of the trench 14. Here, the p-type impurities are implanted multiple times while changing the ion implantation depth, thereby forming the p-type trench lower layer 35 having a predetermined thickness.
  • the p-type trench lower layer 35 is formed in a depth range overlapping with the p-type deep layer 36. Therefore, the p-type trench lower layer 35 is connected to each p-type deep layer 36.
  • the p-type trench lower layer 35 is formed so that the p-type trench lower layer 35 is exposed at the bottom surface of the trench 14. Since the bottom surface and side surface of the trench 14 are exposed, the p-type impurity is implanted into the entire bottom surface of the trench 14. Therefore, the p-type trench lower layer 35 having approximately the same width as the bottom surface of the trench 14 is formed.
  • the etching mask 52 is removed after the p-type trench lower layer forming process is performed.
  • ion implantation into the p-type trench lower layer 35 is performed in a separate process from ion implantation into the body layer 34, so that the p-type impurity concentration of the p-type trench lower layer 35 can be controlled independently from the p-type impurity concentration of the body layer 34.
  • the p-type impurity is implanted at a higher concentration than in the body layer forming process. Therefore, the p-type impurity concentration of the p-type trench lower layer 35 is higher than the p-type impurity concentration of the body layer 34.
  • the p-type impurity concentration of the p-type trench lower layer 35 is increased, the p-type trench lower layer 35 becomes less likely to be depleted when the MOSFET 10 is off. Therefore, the feedback capacitance of the MOSFET 10 can be reduced.
  • the total amount of p-type impurities implanted into each p-type trench lower layer 35 is adjusted so that a non-depleted region 60 remains in a portion of the p-type trench lower layer 35 that contacts the gate insulating film 16 when the rated voltage is applied to the MOSFET 10 as shown in FIG. 7. Therefore, the feedback capacitance of MOSFET 10 can be effectively reduced.
  • the depth D2 is the deepest ion implantation depth in the p-type trench lower layer formation process.
  • ion implantation into the p-type trench lower layer 35 is performed in a process separate from ion implantation into the body layer 34, so that the ion implantation depth D2 into the p-type trench lower layer 35 can be controlled independently from the ion implantation depth D1 into the body layer 34.
  • the ion implantation depth D2 is made shallower than the ion implantation depth D1.
  • the p-type trench lower layer 35 allows the p-type trench lower layer 35 to be formed so that the lower end of the p-type trench lower layer 35 is located above the lower end of the n-type deep layer 37.
  • the p-type trench lower layer 35 can be formed so that the lower end of the p-type trench lower layer 35 does not contact the drift layer 38. Therefore, as described above, in the on-state, the depletion layer is less likely to spread to the drift layer 38, and the on-resistance of the MOSFET 10 is reduced.
  • Gate electrode formation process 15 a gate electrode forming step is performed in which a gate insulating film 16 is formed to cover the inner surface of the trench 14. Furthermore, a gate electrode 18 is formed in the trench 14.
  • the interlayer insulating film 20, the source electrode 22, and the drain electrode 24 are formed. Through the above steps, the MOSFET 10 shown in FIG. 1 is completed.
  • the etching mask 52 is used as an ion implantation mask as is, so that the MOSFET 10 can be manufactured efficiently.
  • an ion implantation mask may be formed on the upper surface of the semiconductor substrate after removing the etching mask 52.
  • ion implantation was performed on the p-type trench lower layer 35 in a state where the bottom and side of the trench 14 were exposed (i.e., the semiconductor substrate was exposed on the bottom and side of the trench 14).
  • the p-type impurity can be implanted into the entire bottom of the trench 14, so that the p-type trench lower layer 35 having approximately the same width as the width of the bottom of the trench 14 can be formed.
  • the electric field applied to the gate insulating film 16 covering the bottom of the trench 14 can be efficiently alleviated.
  • the width of the p-type trench lower layer 35 does not become wider than necessary, so that a wide current path can be secured in the n-type deep layer 37, and the on-resistance of the MOSFET can be reduced.
  • ion implantation may be performed on the p-type trench lower layer 35 after forming a sacrificial oxide film 54 covering the bottom and side of the trench 14.
  • impurity soak to the side of the trench 14 can be suppressed.
  • the injection range of the p-type impurity at the bottom of the trench 14 is narrowed.
  • the thickness of the sacrificial oxide film 54 is thin, even with this configuration, it is possible to form a p-type trench lower layer 35 having a width close to the width of the bottom surface of the trench 14.
  • the p-type trench lower layer 35 is formed at a position away from the bottom surface of the trench 14 to the lower side. That is, in FIG. 17, the p-type trench lower layer 35 is not formed in the depth range R2a near the bottom surface of the trench 14, but is formed in the depth range R2b below it. In this way, even if the p-type trench lower layer 35 is disposed at a position away from the trench 14, the effect of reducing the feedback capacitance and mitigating the electric field can be obtained. Note that in the p-type trench lower layer formation process, the structure of FIG. 17 can be formed by injecting p-type impurities into the depth range R2b without injecting p-type impurities into the depth range R2a.
  • the p-type trench lower layer 35 has a first p-type trench lower layer 35a and a second p-type trench lower layer 35b.
  • the first p-type trench lower layer 35a is disposed within a depth range R2a near the bottom surface of the trench 14.
  • the second p-type trench lower layer 35b is disposed within a depth range R2b below the depth range R2a.
  • the second p-type trench lower layer 35b has a higher p-type impurity concentration than the first p-type trench lower layer 35a.
  • the second p-type trench lower layer 35b i.e., the layer with a high p-type impurity concentration
  • the first p-type trench lower layer 35a i.e., the layer with a low p-type impurity concentration
  • the p-type trench lower layer 35 reduces the feedback capacitance and reduces the electric field.
  • the second p-type trench lower layer 35b having a high p-type impurity concentration is disposed in a position in contact with the bottom surface of the trench 14 as in FIG. 19, the feedback capacitance is lower than that in FIG. 18.
  • the appropriate feedback capacitance varies depending on the application of the MOSFET 10.
  • the structure of FIG. 19 can be adopted, and when a low feedback capacitance is not required, the structure of FIG. 18 can be adopted.
  • the structure of FIG. 19 can be formed by injecting a high concentration of p-type impurities into the depth range R2a and a low concentration of p-type impurities into the depth range R2b in the p-type trench lower layer formation process.
  • the lower end of the p-type trench lower layer 35 is located at the same depth as the lower end of the n-type deep layer 37.
  • the lower end of the p-type trench lower layer 35 is located lower than the lower end of the n-type deep layer 37.
  • the p-type trench lower layer 35 is in contact with the drift layer 38. Even in these configurations, the p-type trench lower layer 35 provides the effects of reducing feedback capacitance and mitigating the electric field.
  • the lower end of the p-type deep layer 36 is located at the same depth as the lower end of the n-type deep layer 37.
  • the lower end of the p-type deep layer 36 is located lower than the lower end of the n-type deep layer 37.
  • the n-type deep layer 37 has a first n-type deep layer 37a and a second n-type deep layer 37b.
  • the first n-type deep layer 37a is disposed above the second n-type deep layer 37b.
  • the first n-type deep layer 37a has a higher n-type impurity concentration than the second n-type deep layer 37b.
  • the first n-type deep layer 37a is disposed above the lower end of the trench 14.
  • the p-type deep layer 36 has a first p-type deep layer 36a and a second p-type deep layer 36b.
  • the first p-type deep layer 36a is disposed above the second p-type deep layer 36b.
  • the first p-type deep layer 36a has a higher p-type impurity concentration than the second p-type deep layer 36b.
  • the first p-type deep layer 36a is disposed above the lower end of the trench 14.
  • (Configuration 1) A method for manufacturing a field effect transistor, comprising the steps of: a semiconductor substrate preparation step of preparing a semiconductor substrate having an n-type drift layer, a plurality of p-type deep layers, and a plurality of n-type deep layers, the plurality of p-type deep layers and the plurality of n-type deep layers being disposed on top of the n-type drift layer, the plurality of p-type deep layers extending along a first direction when the semiconductor substrate is viewed from above, the plurality of p-type deep layers being disposed at intervals in a second direction perpendicular to the first direction, the plurality of n-type deep layers being disposed within the corresponding intervals, and the plurality of n-type deep layers having an n-type impurity concentration higher than the n-type impurity concentration of the n-type drift layer; a body layer formation step of forming a p-type body layer in contact with
  • the p-type trench lower layer forming step the p-type trench lower layer is formed so as to be in contact with the bottom surface of the trench; a total amount of p-type impurities in the p-type trench lower layer is set so that a non-depleted region remains in a part of the p-type trench lower layer in contact with the gate insulating film when a rated voltage is applied to the field effect transistor.
  • the method for producing the present invention according to any one of claims 1 to 3.
  • the semiconductor substrate having an n-type connection layer is prepared, the n-type connection layer is disposed under each of the p-type deep layers and connects the n-type deep layers to each other; an n-type impurity concentration of the n-type connection layer is higher than an n-type impurity concentration of the n-type drift layer;
  • the method for producing the present invention according to any one of claims 1 to 7.

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009194065A (ja) 2008-02-13 2009-08-27 Denso Corp 炭化珪素半導体装置およびその製造方法
JP2017117951A (ja) * 2015-12-24 2017-06-29 トヨタ自動車株式会社 半導体装置の製造方法
JP2021027139A (ja) * 2019-08-02 2021-02-22 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機
JP2022099721A (ja) * 2020-12-23 2022-07-05 株式会社デンソー 炭化珪素半導体装置
JP2022140217A (ja) * 2021-03-11 2022-09-26 株式会社デンソー 電界効果トランジスタとその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009194065A (ja) 2008-02-13 2009-08-27 Denso Corp 炭化珪素半導体装置およびその製造方法
JP2017117951A (ja) * 2015-12-24 2017-06-29 トヨタ自動車株式会社 半導体装置の製造方法
JP2021027139A (ja) * 2019-08-02 2021-02-22 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機
JP2022099721A (ja) * 2020-12-23 2022-07-05 株式会社デンソー 炭化珪素半導体装置
JP2022140217A (ja) * 2021-03-11 2022-09-26 株式会社デンソー 電界効果トランジスタとその製造方法

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