WO2024174355A1 - 反熔丝结构及其制备方法、反熔丝阵列结构、存储器 - Google Patents

反熔丝结构及其制备方法、反熔丝阵列结构、存储器 Download PDF

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WO2024174355A1
WO2024174355A1 PCT/CN2023/086760 CN2023086760W WO2024174355A1 WO 2024174355 A1 WO2024174355 A1 WO 2024174355A1 CN 2023086760 W CN2023086760 W CN 2023086760W WO 2024174355 A1 WO2024174355 A1 WO 2024174355A1
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Prior art keywords
fuse
bit line
variable resistance
threshold
line structure
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French (fr)
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黄金荣
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular to an anti-fuse structure and a preparation method thereof, an anti-fuse array structure, and a memory.
  • DRAM dynamic random access memory
  • the traditional anti-fuse structure is relatively fixed in the semiconductor device and occupies a large area in the chip, which affects the high degree of integration of the semiconductor device.
  • the size of the traditional anti-fuse unit is negatively correlated with reliability.
  • the reliability of the anti-fuse structure drops sharply, resulting in a bottleneck in the miniaturization of the anti-fuse.
  • a new small-size anti-fuse structure is urgently needed to be developed.
  • an anti-fuse structure and a method for manufacturing the same, an anti-fuse array structure, and a memory are provided.
  • a semiconductor structure including: a bit line structure, a word line structure, and a variable resistance structure and a threshold gating structure located between the bit line structure and the word line structure, wherein the variable resistance structure is configured to change from a high resistance state to a low resistance state under a preset programming voltage; and the threshold gating structure is configured to be selected under a threshold voltage.
  • variable resistance structure is located between the bit line structure and the threshold gating structure, or the threshold gating structure is located between the bit line structure and the variable resistance structure.
  • variable resistance structure is a metal dielectric layer.
  • the material of the metal dielectric layer is one or more of hafnium oxide, zirconium oxide, thallium oxide and aluminum oxide.
  • the material of the threshold gate structure is one or more of titanium oxide, hafnium oxide, titanium hafnium oxide and tellurium tin germanium phase change material.
  • the anti-fuse structure is formed in a predetermined region of the memory structure; the predetermined region is selected from the surface of the first metal layer, the surface of the second metal layer, the surface of the top metal layer, and combinations thereof.
  • the anti-fuse structure is formed in a plane where the capacitor layer is located between the first metal layer and the second metal layer of the memory structure.
  • the thickness of the variable resistor structure ranges from The thickness of the threshold gating structure ranges from 1nm to 10nm; the thickness of the word line structure ranges from 20nm to 50nm; and the thickness of the bit line structure ranges from 20nm to 50nm.
  • an antifuse array structure which includes a first antifuse structure and a second antifuse structure, the first antifuse structure adopts the antifuse structure in any of the above-mentioned embodiments; the second antifuse structure adopts the antifuse structure in any of the above-mentioned embodiments; the first antifuse structure and the second antifuse structure share the same bit line structure, the variable resistance structure and threshold selection structure of the first antifuse structure are located on the opposite side of the shared bit line structure, and the variable resistance structure and threshold selection structure of the second antifuse structure are located on the other side of the shared bit line structure.
  • the bit line structure extends along a first direction, and multiple bit line structures are arranged in parallel and spaced apart along a second direction; the extension direction of the word line structure of the first anti-fuse structure is parallel to the second direction; the extension direction of the word line structure of the second anti-fuse structure is parallel to the second direction; the first direction and the second direction are perpendicular to each other.
  • a gate-on time of the threshold gate structure of the first anti-fuse structure and a gate-on time of the threshold gate structure of the second anti-fuse structure have a preset time difference.
  • variable resistance structure or the threshold gating structure of the two common bit line structures is located inside the bit line structure.
  • variable resistance structure or the threshold gating structure of the two common bit line structures is located inside the word line structure.
  • two first anti-fuse structures adjacent to each other along the second direction share the same word line structure; and/or two second anti-fuse structures adjacent to each other along the second direction share the same word line structure.
  • word line structures of two first anti-fuse structures adjacent to each other along the second direction are fabricated in the same process step.
  • word line structures of two second anti-fuse structures adjacent to each other along the second direction are fabricated in the same process step.
  • another aspect of the present disclosure provides a memory, which includes the semiconductor structure in any of the above embodiments, or the anti-fuse structure in any of the above embodiments.
  • the memory is a dynamic random access memory.
  • another aspect of the present disclosure provides a method for preparing an anti-fuse structure, the method comprising: providing a substrate; forming a bit line structure on the substrate; forming a variable resistance structure and a threshold selection structure on a side of the bit line structure away from the substrate; wherein the variable resistance structure is configured to change from a high resistance state to a low resistance state under a preset programming voltage; the threshold selection structure is configured to be selected under a threshold voltage; and forming a word line structure on the variable resistance structure and the threshold selection structure.
  • variable resistance structure is located between the bit line structure and the threshold selection structure, and forming the variable resistance structure and the threshold selection structure on the side of the bit line structure away from the substrate includes: forming the variable resistance structure on the surface of the bit line structure away from the substrate; forming the threshold selection structure on the surface of the variable resistance structure away from the bit line structure.
  • the threshold gating structure is located between the bit line structure and the variable resistance structure, and forming the variable resistance structure and the threshold gating structure on the side of the bit line structure away from the substrate includes: forming the threshold gating structure on the surface of the bit line structure away from the substrate; forming the variable resistance structure on the surface of the threshold gating structure away from the bit line structure.
  • FIG. 1a is a schematic diagram of a three-dimensional structure of an anti-fuse structure provided in an embodiment of the present disclosure
  • FIG1b is a schematic diagram of a three-dimensional structure of an anti-fuse structure provided in another embodiment of the present disclosure.
  • FIG1c is a schematic diagram of a three-dimensional structure of an anti-fuse structure provided in yet another embodiment of the present disclosure.
  • FIG. 1d is a schematic diagram of a three-dimensional structure of an anti-fuse structure provided in another embodiment of the present disclosure
  • FIG2 is a schematic diagram of a three-dimensional structure of an antifuse array structure provided in an embodiment of the present disclosure
  • FIG3 is a schematic flow diagram of a method for preparing an antifuse structure provided in an embodiment of the present disclosure
  • FIG4 is a schematic diagram of a cross-sectional structure obtained in the method for preparing an anti-fuse structure in the first embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a cross-sectional structure obtained in a method for preparing an anti-fuse structure in a second embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a cross-sectional structure obtained in a method for preparing an anti-fuse structure in a third embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a cross-sectional structure obtained in a method for preparing an anti-fuse structure in a fourth embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a cross-sectional structure obtained in a method for preparing an anti-fuse structure in a fifth embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of a cross-sectional structure obtained in a method for preparing an anti-fuse structure in a sixth embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a cross-sectional structure obtained in a method for preparing an anti-fuse structure in a seventh embodiment of the present disclosure
  • FIG11 is a schematic diagram of a cross-sectional structure obtained in a method for preparing an anti-fuse structure in an eighth embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a cross-sectional structure obtained in a method for preparing an anti-fuse structure in a ninth embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of a cross-sectional structure obtained in a method for preparing an anti-fuse structure in the tenth embodiment of the present disclosure.
  • the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.
  • Antifuses record the address information of failed cells, which is of great significance for improving product yield.
  • traditional antifuses occupy a large area on the product, which is not conducive to cost reduction.
  • Traditional antifuses mainly include Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the preparation position is relatively fixed and must be made on the active area. The position selectivity is poor and the area occupied is too large, which is not conducive to reducing the chip size. With the continuous miniaturization of the preparation process, the reliability of the antifuse structure has dropped sharply, resulting in a bottleneck in the miniaturization of antifuse.
  • traditional antifuse arrays cannot be stacked in the vertical direction.
  • the present disclosure provides an anti-fuse structure, an anti-fuse array structure, an anti-fuse structure preparation method, and a memory, which can reduce the planar area and volume of the anti-fuse structure and further reduce the size of the device integrating the anti-fuse structure.
  • the present disclosure provides an anti-fuse structure, which includes a bit line structure, a controllable resistance structure and a word line structure stacked in sequence, wherein the controllable resistance structure is configured to be enabled at a threshold voltage and to change from a high resistance state to a low resistance state at a preset programming voltage, and the controllable resistance structure includes a stacked variable resistance structure and a threshold selection structure.
  • the anti-fuse structure in the above-mentioned embodiment can utilize a controllable resistance structure with the performance of being in a high-resistance state in the initial state and changing from a high-resistance state to a low-resistance state under the drive of a preset programming voltage, and the anti-fuse structure can realize resistance value changes at a relatively low voltage, thereby realizing the writing and reading of the anti-fuse structure, thereby reducing the planar area and volume of the anti-fuse structure, and further reducing the volume of semiconductor devices with integrated anti-fuse structures.
  • the present disclosure provides an anti-fuse structure, the anti-fuse structure comprising a bit line junction
  • the invention relates to a bit line structure 10, a word line structure 40, and a variable resistance structure 20 and a threshold selection structure 30 located between the bit line structure 10 and the word line structure 40, wherein the variable resistance structure 20 is configured to change from a high resistance state to a low resistance state under a preset programming voltage; and the threshold selection structure 30 is configured to be selected under a threshold voltage.
  • the anti-fuse structure in the above embodiment can utilize the variable resistance structure 20 to have the performance of being in a high-resistance state in the initial state and changing from the high-resistance state to a low-resistance state under the drive of a preset programming voltage.
  • the anti-fuse structure can achieve resistance value changes at a lower voltage to achieve writing and reading of the anti-fuse structure. Therefore, the energy consumption of the anti-fuse structure can be further reduced while reducing the planar area and volume of the anti-fuse structure.
  • variable resistance structure 20 is located between the bit line structure 10 and the threshold gating structure 30 , or the threshold gating structure 30 is located between the bit line structure 10 and the variable resistance structure 20 .
  • the anti-fuse structure 100a may be a bit line structure 10, a variable resistance structure 20, a threshold gating structure 30 and a word line structure 40 stacked in sequence along the thickness direction of the bit line structure 10, such as the oz direction, and the anti-fuse structure 100a may form a conductive channel connected to the word line structure 40 by the bit line structure 10 through the variable resistance structure 20 and the threshold gating structure 30.
  • FIG. 1a please refer to FIG.
  • the anti-fuse structure 100b may be a bit line structure 10, a threshold gating structure 30, a variable resistance structure 20 and a word line structure 40 stacked in sequence along the oz direction, and the anti-fuse structure 100b may form a conductive channel connected to the word line structure 40 by the bit line structure 10 through the threshold gating structure 30 and the variable resistance structure 20.
  • the anti-fuse structure 100c may be a word line structure 40, a variable resistance structure 20, a threshold gating structure 30 and a bit line structure 10 stacked in sequence along the oz direction.
  • FIG. 1c the anti-fuse structure 100c may be a word line structure 40, a variable resistance structure 20, a threshold gating structure 30 and a bit line structure 10 stacked in sequence along the oz direction.
  • the anti-fuse structure 100d can be a word line structure 40, a threshold gating structure 30, a variable resistance structure 20 and a bit line structure 10 stacked in sequence along the oz direction.
  • the threshold gating structure 30 can be gated at a threshold voltage
  • the threshold gating structure 30 can be controlled to be turned on first, and then the variable resistance structure 20 can be controlled to change from a high resistance state to a low resistance state, so that the anti-fuse structure can achieve resistance value changes at a lower voltage, realize the writing and reading of the anti-fuse structure, and avoid signal crosstalk between the stacked anti-fuse structures; since no transistors are used, the anti-fuse structure in this embodiment can effectively reduce the product volume.
  • the variable resistor structure 20 is a metal dielectric layer, which breaks down under high voltage to form a conductive layer, thereby increasing the conductivity of the variable resistor structure 20 and reducing its on-resistance, so that the variable resistor structure can achieve resistance changes at a lower voltage and has low power consumption, thereby ensuring that the energy consumption per unit volume of the variable resistor structure is reduced without increasing the volume of the prepared product.
  • the material of the metal dielectric layer is one or more of hafnium oxide, zirconium oxide, thallium oxide and aluminum oxide, and these materials have variable resistance properties, and it is relatively easy to achieve resistance changes.
  • hafnium oxide has a high dielectric constant and good thermal stability
  • zirconium oxide has a high dielectric constant
  • thallium oxide has high cycle characteristics
  • aluminum oxide has high density and high barrier properties.
  • the material of the threshold selection structure 30 is one or more of titanium oxide, hafnium oxide, titanium hafnium oxide and tellurium tin germanium phase change material.
  • Titanium oxide has the characteristics of being stable and not easy to produce chemical reactions, and its own resistance value decreases with the increase of the ambient temperature; hafnium oxide has a high dielectric constant and good thermal stability; titanium hafnium oxide has a high dielectric constant in addition to the excellent properties of hafnium oxide; tellurium tin germanium phase change material has programmable characteristics. These materials have selection properties, so that the variable resistance structure 20 can be changed from a high resistance state to a low resistance state under a preset programming voltage, preventing crosstalk between stacked anti-fuse structures.
  • the material of the word line structure 40 is one or more of tungsten, copper, titanium, aluminum, thallium, hafnium, rubidium, indium tin oxide, conductive glass and indium gallium zinc oxide. These materials are conductive materials such as metals or metal oxides, which provide a programming voltage during programming and provide a lower reading voltage when reading the anti-fuse current.
  • Tungsten has strong covering ability and stable chemical properties, so that the formed word line structure 40 is uniform, dense and has a smooth surface, which is beneficial to improving the stability of the anti-fuse structure; copper has good heat release characteristics, thermal conductivity, low resistance and high mass production; titanium has low resistance, can reduce the volume of the formed word line structure 40, thereby improving the integration of the prepared product, and titanium will not produce defects when in contact with oxide semiconductors or silicon, and has high heat resistance; aluminum has good lattice matching and lattice coupling with various semiconductor materials, and has good sulfurization resistance and large adhesion; thallium has high plasticity and low melting point; hafnium has low work function, stable chemical properties and is not easy to react with water and common acids or alkalis; rubidium has excellent photoelectric properties, electrical conductivity and thermal conductivity; indium tin oxide has good chemical stability, thermal stability and graphic processing characteristics; conductive glass has good and stable optical and electrical properties; indium gallium zinc oxide has controllable doping and high adaptability.
  • the material of the bit line structure 10 is tungsten, copper, titanium, aluminum, thallium, hafnium, rubidium,
  • indium tin oxide, conductive glass and indium gallium zinc oxide, which are conductive materials such as metals or metal oxides, provide low voltage and form a voltage difference with the word line structure during the operation of the anti-fuse structure to provide a circuit channel.
  • Tungsten has strong covering ability and stable chemical properties, so that the formed word line structure 40 is uniform, dense and has a smooth surface, which is beneficial to improving the stability of the anti-fuse structure; copper has good heat release characteristics, thermal conductivity, low resistance and high mass production; titanium has low resistance, can reduce the volume of the formed word line structure 40, thereby improving the integration of the prepared product, and titanium will not produce defects when in contact with oxide semiconductors or silicon, and has high heat resistance; aluminum has good lattice matching and lattice coupling with various semiconductor materials, and has good sulfurization resistance and large adhesion; thallium has high plasticity and low melting point; hafnium has low work function, stable chemical properties and is not easy to react with water and common acids or alkalis; rubidium has excellent photoelectric properties, electrical conductivity and thermal conductivity; indium tin oxide has good chemical stability, thermal stability and graphic processing characteristics; conductive glass has good and stable optical and electrical properties; indium gallium zinc oxide has controllable doping and high adaptability.
  • the amplitude range of the preset programming voltage includes: 3.0V-4.0V, for example, the amplitude of the preset programming voltage can be 3.0V, 3.2V, 3.4V, 3.6V, 3.8V or 4.0V, etc.
  • the programming voltage of the anti-fuse structure of the present embodiment is related to the thickness of the variable resistance structure 20. Reducing the thickness of the variable resistance structure 20 can reduce the amplitude of its programming voltage.
  • the thickness of the variable resistance structure 20 of the present embodiment is greater than or equal to
  • the amplitude range of the preset read voltage is 0V-2.0V to gradually read the current change.
  • the preset read voltage can be 0V, 0.2V, 0.4V, 0.6V, 0.8V, 1.0V, 1.2V, 1.4V, 1.6V, 1.8V or 2.0V, etc.
  • the threshold selection structure 30 is selected under the 2V upper and lower voltage operation, so that the variable resistance structure 20 can be changed from a high resistance state to a low resistance state under the preset programming voltage, and crosstalk between the stacked anti-fuse structures is prevented.
  • the anti-fuse structure can realize resistance change at a relatively low voltage, which has a greater effect on reducing power consumption.
  • variable resistance structure 20 is configured to be in a high-resistance state in the initial state; under the drive of a preset programming voltage provided by the word line structure 40, it changes from the high-resistance state to a low-resistance state; and under the drive of a preset read voltage provided by the word line structure 40, if it is in the high-resistance state, a first value is read out, and if it is in the low-resistance state, a second value is read out.
  • a preset programming voltage is applied to the word line structure 40, and a 0V voltage is applied to the bit line structure 10 to form a voltage difference.
  • the threshold selection structure 30 is opened under the voltage difference, and the material of the variable resistance structure 20 is broken down under the voltage difference, and a conductive channel is formed inside, which changes from an initial high resistance state to a low resistance state, that is, the variable resistance structure 20 changes from an off state to an on state with a certain resistance value.
  • the first value can be "0" and the second value can be "1".
  • variable resistance structure 20 When the variable resistance structure 20 is read, a preset read voltage is applied to the word line structure 40, and a 0V voltage is applied to the bit line structure 10 to form a voltage difference.
  • the threshold selection structure 30 is opened under the voltage difference, and the current flowing through the variable resistance structure 20 is measured. At this time, the resistance value of the variable resistance structure 20 can be obtained by comparing the amplitude of the preset read voltage with the current flowing through the variable resistance structure 20.
  • variable resistor structure 20 If the variable resistor structure 20 is in a high resistance state, almost no current flows through the variable resistor structure 20, so the output low voltage is 0V, and the "0" state is read out; if the variable resistor structure 20 is in a low resistance state, current flows through the variable resistor structure 20, the output voltage is greater than 0V, and the "1" state is read out.
  • the first value can be "1” and the second value can be "0".
  • the anti-fuse structure is formed in a preset area of the storage structure; the preset area is selected from the surface of the first metal layer, the surface of the second metal layer, the surface of the top metal layer and a combination thereof.
  • the top metal layer can be the top metal layer in the manufacturing stage of the storage structure, and the top metal layer serves as the bottom structure of the anti-fuse structure.
  • the top metal layer serves as a bit line structure 10, on which a variable resistance structure 20, a threshold selection structure 30 and a word line structure 40 are sequentially stacked along the thickness direction, such as the oz direction.
  • the anti-fuse structure of this embodiment is not limited to being made on the active area, which greatly reduces the area of the active area, and the anti-fuse structure of this embodiment is formed in the preset area of the storage structure or in the idle area, which has high flexibility and can meet the preparation requirements of various application scenarios. It can also reduce the volume of the anti-fuse structure and improve the chip density and integration.
  • the anti-fuse structure is formed in the plane where the capacitor layer is located between the first metal layer and the second metal layer of the storage structure, and part or all of the anti-fuse structure is formed by utilizing the idle area near the capacitor layer of the storage structure, thereby reducing the complexity of the preparation of the anti-fuse structure, reducing the storage structure space occupied by the anti-fuse structure, further reducing the volume of the storage structure, and reducing manufacturing costs.
  • a target groove (not shown) is formed in the bit line structure 10; the variable resistance structure 20 or the threshold selection structure 30 connected to the bit line structure 10 is at least partially located in the target groove, so that the anti-fuse structure in this embodiment forms a buried bit line structure 10, thereby improving the integration of the anti-fuse structure.
  • the thickness range of the variable resistor structure 20 is For example: or
  • the thickness of the threshold gating structure 30 is in the range of 1 nm to 10 nm, for example, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm, etc.
  • the thickness of the word line structure 40 is in the range of 20 nm to 50 nm, for example, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc.
  • the thickness of the bit line structure 10 is in the range of 20 nm to 50 nm, for example, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc.
  • FIG. 2 provides an antifuse array structure 300, which includes an antifuse stack structure 200 arranged in an array.
  • the antifuse stack structure 200 includes a first antifuse structure 200a and a second antifuse structure 200b that share the same bit line structure 10; the first antifuse structure 200a adopts the antifuse structure of any of the above embodiments; the second antifuse structure 200b adopts the antifuse structure of any of the above embodiments.
  • variable resistance structure 12 of the first antifuse structure and the threshold selection structure 13 of the first antifuse structure are located on the opposite side of the shared bit line structure 10; the variable resistance structure 22 of the second antifuse structure and the threshold selection structure 23 of the second antifuse structure are located on the other opposite side of the shared bit line structure 10.
  • the anti-fuse array structure 300 in the above embodiment can utilize the variable resistance structure 12 of the first anti-fuse structure and the variable resistance structure 22 of the second anti-fuse structure, which have the performance of being in a high-resistance state in the initial state and changing from the high-resistance state to a low-resistance state under the drive of a preset programming voltage, so that the anti-fuse array structure 300 can achieve resistance change at a relatively low voltage, and realize the writing and reading of the anti-fuse array structure 300. Therefore, the energy consumption of the anti-fuse array structure 300 can be reduced while reducing the planar area and volume of the anti-fuse array structure 300.
  • the bit line structure 10 extends along a first direction, and a plurality of bit line structures 10 are arranged in parallel and spaced apart along a second direction; the word line structure 11 of the first anti-fuse structure extends in a direction parallel to the second direction; the word line structure 21 of the second anti-fuse structure extends in a direction parallel to the second direction; the first direction and the second direction are perpendicular to each other.
  • the first direction may be the ox direction
  • the second direction may be the oy direction.
  • the anti-fuse stack structure 200 of this embodiment uses a shared bit line structure 10, which can reduce the product volume, reduce the difficulty of preparation, and improve the reliability of the prepared product.
  • bit line structures 10 of two anti-fuse stack structures 200 adjacent to each other along a first direction can be prepared in the same process step.
  • the word line structures of two anti-fuse stack structures 200 adjacent to each other along a second direction can also be prepared in the same process step, so that the anti-fuse stack structures 200 adjacent to each other along the second direction, such as the oy direction, share the word line structure, and the anti-fuse stack structures 200 adjacent to each other along the first direction, such as the ox direction, share the bit line structure, thereby reducing the performance differences between different anti-fuse stack structures 200 and improving the performance and reliability of the anti-fuse array structure 300.
  • the gate timing of the threshold gate structure 13 of the first anti-fuse structure has a preset time difference with the gate timing of the threshold gate structure 23 of the second anti-fuse structure.
  • the anti-fuse array structure 300 of this embodiment ensures that the write or read operation will not be performed simultaneously during the write or read operation by means of the preset time difference, thereby avoiding operation conflicts.
  • each antifuse stack structure 200 includes a first antifuse structure 200a and a second antifuse structure 200b of a common bit line structure 10.
  • the threshold selection structure 13 of the first antifuse structure of the common bit line structure 10 and the threshold selection structure 23 of the second antifuse structure can be connected to the same node of the bit line structure 10.
  • the selection moment of the first antifuse structure 200a and the selection moment of the second antifuse structure 200b in the antifuse stack structure 200 have a preset time difference. During the writing or reading operation, it will be ensured that the writing or reading operation will not be performed at the same time, avoiding operation conflicts.
  • variable resistance structure 12 of the first anti-fuse structure of the shared bit line structure 10 can be partially or completely located inside the word line structure 11 of the first anti-fuse structure, and the variable resistance structure 22 of the second anti-fuse structure can be partially or completely located inside the word line structure 21 of the second anti-fuse structure; the threshold selection structure 13 of the first anti-fuse structure and the threshold selection structure 23 of the second anti-fuse structure can be partially or completely located inside the bit line structure 10, so that the anti-fuse array structure 300 of this embodiment forms an embedded anti-fuse structure to further reduce the volume of the anti-fuse array structure 300.
  • the present disclosure provides a memory including the antifuse structure and/or antifuse array structure described above.
  • the memory may be a dynamic random access memory, a static random access memory, a magnetoresistive random access memory, or the like.
  • the anti-fuse array including the anti-fuse structure of the common bit line structure is stacked in the vertical direction, and the volume of the anti-fuse array is effectively reduced while ensuring that the performance of the anti-fuse structure is not reduced; and because the anti-fuse structure has an initial state of high resistance and is driven by a preset programming voltage, The performance of changing from a high-resistance state to a low-resistance state under low voltage can realize resistance change at a lower voltage, realize writing and reading of the anti-fuse structure, and can reduce the planar area and volume of the anti-fuse structure, thereby reducing the volume of the memory.
  • the memory is a dynamic random access memory.
  • the anti-fuse structure is formed in the plane where the capacitor layer of the dynamic random access memory is located, and the vacant area near the capacitor layer of the dynamic random access memory is used to form part or all of the anti-fuse structure, thereby reducing the complexity of the preparation of the anti-fuse structure, reducing the space of the dynamic random access memory occupied by the anti-fuse structure, further reducing the volume of the dynamic random access memory, and reducing the manufacturing cost.
  • the embodiment of the present disclosure also provides a method for preparing the anti-fuse structure involved above.
  • the implementation scheme for solving the problem provided by the method is similar to the implementation scheme recorded in the above structure, so the specific definition in the embodiment of the preparation method of one or more anti-fuse structures provided below can refer to the definition of the anti-fuse structure above, and will not be repeated here.
  • the method includes:
  • Step S202 providing a substrate
  • Step S204 forming a bit line structure on the substrate
  • Step S206 forming a variable resistance structure and a threshold gating structure on a side of the bit line structure away from the substrate, wherein the variable resistance structure is configured to change from a high resistance state to a low resistance state at a preset programming voltage; and the threshold gating structure is configured to be gated at a threshold voltage;
  • Step S208 forming a word line structure on the variable resistance structure and the threshold gating structure.
  • the method for preparing the anti-fuse structure in the above embodiment forms a variable resistance structure and a threshold gating structure on the side of the bit line structure away from the substrate, and forms a word line structure on the variable resistance structure and the threshold gating structure, and configures the variable resistance structure to change from a high resistance state to a low resistance state at a preset programming voltage and the threshold gating structure to be gated at a threshold voltage, so that the anti-fuse structure can achieve resistance change at a lower voltage, write and read the anti-fuse structure, and avoid signal crosstalk between stacked anti-fuse structures.
  • the substrate in step S202 can be made of semiconductor material, insulating material, conductor material or any combination thereof.
  • the substrate can be a single-layer structure or a multi-layer structure.
  • the substrate can be a III/V semiconductor substrate or a II/VI semiconductor substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other.
  • Si silicon
  • SiGe silicon germanium
  • SiGeC silicon germanium carbon
  • SiC silicon carbide
  • GaAs gallium arsenide
  • InAs indium arsenide
  • InP indium phosphide
  • the substrate can be a layered substrate including Si/SiGe, Si/SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate should not limit the scope of protection of the present disclosure.
  • variable resistance structure and the threshold gating structure are included:
  • Step S2051 forming a first isolation layer 101 on the bit line structure 10;
  • Step S2052 forming a first patterned photoresist layer 102 on a surface of the first isolation layer 101 away from the bit line structure 10;
  • Step S2053 using the first patterned photoresist layer 102 as a mask to etch the first isolation layer 101 to obtain first trenches 103 arranged in parallel along the first direction.
  • a deposition process can be used to form a first isolation layer 101 on the bit line structure 10.
  • the first isolation layer 101 can be a single-layer structure or a multi-layer stacked structure, and its material can be silicon oxide.
  • a first photoresist material layer 1021 is coated on the surface of the first isolation layer 101 away from the bit line structure 10, and a series of steps such as exposure and development are performed to form a first patterned photoresist layer 102.
  • the first patterned photoresist layer 102 has an opening pattern that defines the position and shape of the first groove 103.
  • the photoresist can be a positive photoresist or a negative photoresist
  • the development method can be a positive development or a negative development.
  • an etching process can be used to etch the first isolation layer 101 using the first patterned photoresist layer 102 as a mask to obtain first grooves 103 arranged in parallel along the first direction.
  • the etching process can include but is not limited to a dry etching process and/or a wet etching process.
  • the dry etching process may include, but is not limited to, one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP), and high concentration plasma etching (HDP).
  • RIE reactive ion etching
  • ICP inductively coupled plasma etching
  • HDP high concentration plasma etching
  • variable resistance structure 20 is located between the bit line structure 10 and the threshold gating structure 30 , and the variable resistance structure 20 and the threshold gating structure 30 are formed on the side of the bit line structure 10 away from the substrate in step S206 , including:
  • Step S2061 forming a variable resistance structure 20 on a surface of the bit line structure 10 away from the substrate;
  • Step S2062 forming a threshold gating structure 30 on a surface of the variable resistor structure 20 away from the bit line structure 10 .
  • a deposition process can be used to deposit a variable resistance material layer 104 on the first groove 103.
  • the material of the variable resistance material layer 104 is one or more of hafnium oxide, zirconium oxide, thallium oxide and aluminum oxide.
  • the deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high density plasma deposition (High Density Plasma, HDP) process, a plasma enhanced deposition process and a spin-on dielectric layer (Spin-on Dielectric, SOD) process.
  • CVD chemical Vapor Deposition
  • ALD atomic layer deposition
  • HDP High Density Plasma
  • SOD spin-on dielectric layer
  • a deposition process may be used to deposit a threshold gating material layer 105 on the variable resistance material layer 104.
  • the material of the threshold gating material layer 105 is one or more of titanium oxide, hafnium oxide, titanium hafnium oxide, and tellurium tin germanium phase change material.
  • the deposition process may include, but is not limited to, one or more of CVD, ALD, HDP, and SOD processes.
  • step S2062 removes the remaining patterned photoresist layer, the variable resistance material layer 104 located on the patterned photoresist layer, and the threshold gating material layer 105.
  • the removal method may include ashing and wet cleaning.
  • an etching process can be used to etch the first isolation layer 101 on the threshold selection structure 30 to obtain a second groove 106 arranged in parallel along a first direction, such as the ox direction.
  • a deposition process can be used to deposit a word line material layer 107 on the threshold selection structure 30.
  • the material of the word line material layer 107 is one or more of tungsten, copper, titanium, aluminum, thallium, hafnium, rubidium, indium tin oxide, conductive glass and indium gallium zinc oxide.
  • a planarization process can be used to remove excess word line material layer 107, and a word line structure 40 is formed on the variable resistance structure 20 and the threshold selection structure 30.
  • the etching process may include but is not limited to a dry etching process and/or a wet etching process.
  • the dry etching process may include but is not limited to one or more of RIE, ICP and HDP.
  • the planarization process includes one or more of a mechanical polishing process, a grinding process, an etching process, a dry polishing process, etc.
  • the threshold gating structure is located between the bit line structure and the variable resistance structure, and the variable resistance structure and the threshold gating structure are formed on the side of the bit line structure away from the substrate, including: forming the threshold gating structure on the surface of the bit line structure away from the substrate; and forming the variable resistance structure on the surface of the threshold gating structure away from the bit line structure.
  • the anti-fuse structure of this embodiment is formed in the same manner as the above embodiment.
  • the disclosed embodiment also provides a method for implementing the anti-fuse stack structure involved above.
  • the solution to the problem provided by the method is similar to the solution described in the above structure, so the specific definition in the embodiment of the method for preparing one or more anti-fuse stack structures provided below can refer to the definition of the anti-fuse stack structure above, and will not be repeated here.
  • the preparation steps of the bit line structure, threshold selection structure, variable resistance structure and word line structure of the preparation method of the anti-fuse stack structure can be formed by the same preparation steps in the above-mentioned preparation method of the anti-fuse structure, but the bottom metal layer in the preparation method of the anti-fuse stack structure is the word line structure, which can be the first metal layer, the second metal layer, the middle metal layer, the top metal layer and their combination.
  • a method for preparing an anti-fuse stack structure includes: providing a substrate; forming a word line structure on the substrate; forming a first isolation layer on the word line structure; coating a first photoresist material layer on a surface of the first isolation layer away from the word line structure, and forming a first patterned photoresist layer through a series of steps such as exposure and development; etching the first isolation layer using the first patterned photoresist layer as a mask to obtain first grooves arranged in parallel along a first direction, such as the ox direction; depositing a threshold selection material layer on the first groove to form a threshold selection structure on a surface of the word line structure away from the substrate; depositing a variable resistance material layer on the threshold selection material layer to form a variable resistance structure on a surface of the threshold selection structure away from the word line structure; removing the remaining patterned photoresist layer, the threshold selection material layer and the variable resistance material layer located on the patterned photoresist layer; etching the first isolation layer on
  • the threshold gating structure is located between the bit line structure and the variable resistance structure, and the variable resistance structure and the threshold gating structure are formed on a side of the bit line structure away from the substrate, including: forming the threshold gating structure on a surface of the bit line structure away from the substrate; and forming the variable resistance structure on a surface of the threshold gating structure away from the bit line structure.

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Abstract

本公开涉及一种反熔丝结构及其制备方法、反熔丝阵列结构、存储器，反熔丝结构(100)包括位线结构(10)、字线结构(40)，以及位于位线结构(10)和字线结构(40)之间的可变电阻结构(20)和阈值选通结构(30)，可变电阻结构(20)被配置为在预设编程电压下从高阻态转变为低阻态；阈值选通结构(30)被配置为在阈值电压下选通。

Description

反熔丝结构及其制备方法、反熔丝阵列结构、存储器
相关申请的交叉引用
本公开要求于2023年02月23日日提交中国专利局、申请号为202310154914.2、发明名称为“反熔丝结构及其制备方法、反熔丝阵列结构、存储器”的中国专利的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种反熔丝结构及其制备方法、反熔丝阵列结构、存储器。
背景技术
随着半导体技术的发展，在动态随机存取存储器(Dynamic Random Access Memory，DRAM)中使用的熔丝，从以物理性切断的金属熔丝逐渐转变为使用脉冲电压的反熔丝。
传统的反熔丝结构在半导体器件中位置较为固定，且占据了芯片中较大面积，影响半导体器件的高度地集成化。传统反熔丝单元的尺寸与可靠性成负相关，随着制程工艺的微缩，反熔丝结构的可靠性急剧下降，导致反熔丝微缩遇到瓶颈，新型的小尺寸反熔丝结构亟待开发。
发明内容
根据本公开的各种实施例，提供一种反熔丝结构及其制备方法、反熔丝阵列结构、存储器。
根据本公开的各种实施例，一方面提供一种半导体结构，包括：位线结构、字线结构，以及位于位线结构和字线结构之间的可变电阻结构和阈值选通结构，其中，可变电阻结构被配置为在预设编程电压下从高阻态转变为低阻态；阈值选通结构被配置为在阈值电压下选通。
根据一些实施例，可变电阻结构位于位线结构及阈值选通结构之间，或阈值选通结构位于位线结构及可变电阻结构之间。
根据一些实施例，可变电阻结构为金属介质层。
根据一些实施例，金属介质层的材料为氧化铪、氧化锆、氧化铊与氧化铝中的一种或多种。
根据一些实施例，阈值选通结构的材料为氧化钛、氧化铪、氧化钛铪与碲锡锗相变材料中的一种或多种。
根据一些实施例，反熔丝结构形成于存储结构的预设区域内；预设区域选自第一金属层的表面、第二金属层的表面、顶层金属层的表面和其组合。
根据一些实施例，反熔丝结构形成于存储结构的第一金属层和第二金属层之间的电容层所在平面内。
根据一些实施例，可变电阻结构的厚度范围为阈值选通结构的厚度范围为1nm-10nm；字线结构的厚度范围为20nm-50nm；位线结构的厚度范围为20nm-50nm。
根据一些实施例，本公开的另一方面提供了一种反熔丝阵列结构，该反熔丝阵列结构包括第一反熔丝结构及第二反熔丝结构，第一反熔丝结构采用上述任一实施例中的反熔丝结构；第二反熔丝结构采用上述任一实施例中的反熔丝结构；第一反熔丝结构和第二反熔丝结构共用同一位线结构，第一反熔丝结构的可变电阻结构及阈值选通结构位于共用的位线结构的相对一侧，第二反熔丝结构的可变电阻结构及阈值选通结构位于共用的位线结构的相对另一侧。
根据一些实施例，位线结构沿第一方向延伸，多条位线结构沿第二方向平行间隔排布；第一反熔丝结构的字线结构的延伸方向平行于第二方向；第二反熔丝结构的字线结构的延伸方向平行于第二方向；第一方向、第二方向相互垂直。
根据一些实施例，第一反熔丝结构的阈值选通结构的选通时刻，与第二反熔丝结构的阈值选通结构的选通时刻具有预设时间差。
根据一些实施例，两个共用位线结构的可变电阻结构或阈值选通结构的至少部分位于位线结构的内部。
根据一些实施例，两个共用位线结构的可变电阻结构或阈值选通结构的至少部分位于字线结构的内部。
根据一些实施例，沿第二方向相邻的两个第一反熔丝结构共用同一字线结构；及/或，沿第二方向相邻的两个第二反熔丝结构共用同一字线结构。
根据一些实施例，沿第二方向相邻的两个第一反熔丝结构的字线结构在相同的工艺步骤中制备而成。
根据一些实施例，沿第二方向相邻的两个第二反熔丝结构的字线结构在相同的工艺步骤中制备而成。
根据一些实施例，本公开的再一方面提供了一种存储器，该存储器包括上述任一实施例中的半导体结构，或上述任一实施例中的反熔丝结构。
根据一些实施例，存储器为动态随机存取存储器。
根据一些实施例，本公开的又一方面提供了一种反熔丝结构制备方法，该方法包括：提供衬底；于衬底上形成位线结构；于位线结构远离衬底的一侧形成可变电阻结构和阈值选通结构；其中，可变电阻结构被配置为在预设编程电压下从高阻态转变为低阻态；阈值选通结构被配置为在阈值电压下选通；于可变电阻结构和阈值选通结构上形成字线结构。
根据一些实施例，可变电阻结构位于位线结构及阈值选通结构之间，于位线结构远离衬底的一侧形成可变电阻结构和阈值选通结构包括：于位线结构远离衬底的表面形成可变电阻结构；于可变电阻结构远离位线结构的表面形成阈值选通结构。
根据一些实施例，阈值选通结构位于位线结构及可变电阻结构之间，于位线结构远离衬底的一侧形成可变电阻结构和阈值选通结构包括：于位线结构远离衬底的表面形成阈值选通结构；于阈值选通结构远离位线结构的表面形成可变电阻结构。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开实施例的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a为本公开一实施例中提供的一种反熔丝结构的立体结构示意图；
图1b为本公开另一实施例中提供的一种反熔丝结构的立体结构示意图；
图1c为本公开再一实施例中提供的一种反熔丝结构的立体结构示意图；
图1d为本公开又一实施例中提供的一种反熔丝结构的立体结构示意图；
图2为本公开一实施例中提供的一种反熔丝阵列结构的立体结构示意图；
图3为本公开一实施例中提供的一种反熔丝结构的制备方法的流程示意图；
图4为本公开第一实施例中反熔丝结构的制备方法中所得截面结构示意图；
图5为本公开第二实施例中反熔丝结构的制备方法中所得截面结构示意图；
图6为本公开第三实施例中反熔丝结构的制备方法中所得截面结构示意图；
图7为本公开第四实施例中反熔丝结构的制备方法中所得截面结构示意图；
图8为本公开第五实施例中反熔丝结构的制备方法中所得截面结构示意图；
图9为本公开第六实施例中反熔丝结构的制备方法中所得截面结构示意图；
图10为本公开第七实施例中反熔丝结构的制备方法中所得截面结构示意图；
图11为本公开第八实施例中反熔丝结构的制备方法中所得截面结构示意图；
图12为本公开第九实施例中反熔丝结构的制备方法中所得截面结构示意图；
图13为本公开第十实施例中反熔丝结构的制备方法中所得截面结构示意图。
具体实施方式
为了便于理解本公开，下面将参阅相关附图对本公开进行更全面的描述。附图中给出了本公开的 首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本公开的基本构想，虽图示中仅显示与本公开中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
反熔丝记载了失效单元的地址信息，对于提升产品良率意义重大，但传统的反熔丝在产品上占用面积较大，不利于成本的降低。传统反熔丝主要包括金属-氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)器件，制备位置较为固定，必须做在有源区上，位置可选择性差,占用的面积过大，不利于芯片尺寸的缩减。随着制备工艺的不断微缩，反熔丝结构的可靠性急剧下降，导致反熔丝微缩遇到瓶颈。并且，传统的反熔丝阵列无法实现垂直方向的堆叠。
基于此，本公开提供一种反熔丝结构、反熔丝阵列结构及反熔丝结构制备方法、存储器，能够降低反熔丝结构的平面面积和体积，进一步降低集成反熔丝结构的器件的尺寸。
在一些实施例中，本公开提供了一种反熔丝结构，该反熔丝结构包括依次叠置的位线结构、可控电阻结构和字线结构，其中可控电阻结构被配置为在阈值电压下选通且在预设编程电压下从高阻态转变为低阻态，可控电阻结构包括层叠的可变电阻结构及阈值选通结构。
作为示例，上述实施例中的反熔丝结构，可以利用可控电阻结构具备初始态为高阻态且在预设编程电压驱动下由高阻态转变为低阻态的性能，且反熔丝结构在较低电压下可实现阻值变化，实现反熔丝结构的写入与读出，因此能够降低反熔丝结构的平面面积和体积，进一步降低集成反熔丝结构的半导体器件的体积。
在一些实施例中，请参考图1a-图1d，本公开提供了一种反熔丝结构，该反熔丝结构包括位线结 构10、字线结构40，以及位于位线结构10和字线结构40之间的可变电阻结构20和阈值选通结构30，其中可变电阻结构20被配置为在预设编程电压下从高阻态转变为低阻态；阈值选通结构30被配置为在阈值电压下选通。
作为示例，请继续参考图1a-图1d，上述实施例中的反熔丝结构，可以利用可变电阻结构20具备初始态为高阻态且在预设编程电压驱动下由高阻态转变为低阻态的性能，且反熔丝结构在较低电压下可实现阻值变化，实现反熔丝结构的写入与读出，因此能够在降低反熔丝结构的平面面积和体积的情况下，进一步降低反熔丝结构的能耗。
在一些实施例中，请继续参考图1a-图1d，可变电阻结构20位于位线结构10及阈值选通结构30之间，或阈值选通结构30位于位线结构10及可变电阻结构20之间。
在一些实施例中，请参考图1a，反熔丝结构100a可以为位线结构10、可变电阻结构20、阈值选通结构30和字线结构40沿位线结构10的厚度方向例如oz方向依次叠置，该反熔丝结构100a可以形成由位线结构10依次经由可变电阻结构20、阈值选通结构30连接至字线结构40的导电通道。在一些实施例中，请参考图1b，反熔丝结构100b可以为位线结构10、阈值选通结构30、可变电阻结构20和字线结构40沿oz方向依次叠置，该反熔丝结构100b可以形成由位线结构10依次经由阈值选通结构30、可变电阻结构20连接至字线结构40的导电通道。在一些实施例中，请参考图1c，反熔丝结构100c可以为字线结构40、可变电阻结构20、阈值选通结构30和位线结构10沿oz方向依次叠置。在一些实施例中，请参考图1d，反熔丝结构100d可以为字线结构40、阈值选通结构30、可变电阻结构20和位线结构10沿oz方向依次叠置。在本公开实施例中，由于可变电阻结构20能够在预设编程电压下从高阻态转变为低阻态，及阈值选通结构30能够在阈值电压下选通，可以先控制阈值选通结构30导通，再控制可变电阻结构20由高阻态变为低阻态，使得反熔丝结构在较低电压下可实现阻值变化，实现反熔丝结构的写入与读出，避免堆叠的反熔丝结构之间产生信号串扰；由于没有采用晶体管，本实施例中的反熔丝结构能够有效地缩减产品体积。多种不同的叠置方式可以满足多种不同应用场景的实际需求。在一些实施例中，请继续参考图1a-图1d，可变电阻结构20为金属介质层，在高压下击穿形成导电层，增加可变电阻结构20的导电性并降低其导通阻抗，使得可变电阻结构在较低电压下可实现阻值变化，且功耗低，以确保制备产品在体积不增加的情况下，降低可变电阻结构单位体积的能耗。
在一些实施例中，请继续参考图1a-图1d，金属介质层的材料为氧化铪、氧化锆、氧化铊与氧化铝中的一种或多种，这些材料具有阻值可变特性，比较容易实现阻值的变化。其中氧化铪具有高介电常数及良好的热稳定性；氧化锆高介电常数，氧化铊具有高循环特性，氧化铝具有高密度及高阻挡性。
在一些实施例中，请继续参考图1a-图1d，阈值选通结构30的材料为氧化钛、氧化铪、氧化钛铪与碲锡锗相变材料中的一种或多种。氧化钛具有性质稳定不易产生化学反应，及自身电阻值随着所在环境温度增加而减小的特质；氧化铪具有高介电常数及良好的热稳定性；氧化钛铪除了具有氧化铪的优良特性之外还具有高介电常数；碲锡锗相变材料具有可编程的特性。这些材料具有选通性能，使得可变电阻结构20能够在预设编程电压下从高阻态转变为低阻态，防止堆叠的反熔丝结构之间产生串扰现象。
在一些实施例中，请继续参考图1a-图1d，字线结构40的材料为钨、铜、钛、铝、铊、铪、铷、氧化铟锡、导电玻璃与氧化铟镓锌中的一种或多种，这些材料为金属或金属氧化物等具有导电性能的材料，在编程时提供编程电压，在读取反熔丝电流时提供较低的读取电压。钨具有较强的覆盖能力且化学性质稳定，使所形成字线结构40均匀致密且表面光滑，有利于提高反熔丝结构的稳定性；铜具有良好的放热特性、热导率、低电阻及高量产性；钛具有低电阻，能够减小所形成字线结构40的体积，从而可以提高制备产品的集成度，并且钛与氧化物半导体或硅接触不会产生缺陷，具有高耐热性；铝与各种半导体材料之间具有良好的晶格匹配度及晶格耦合度，且具有良好的耐硫化特性及较大的粘合力；铊具有较高的可塑性及低熔点；铪具有低功函数、化学性质稳定及不易与水和普通的酸或碱反应；铷具有优良的光电特性、导电性及导热性；氧化铟锡具有良好的化学稳定性、热稳定性和图形加工特性；导电玻璃具有良好且稳定的光学和电学性能；氧化铟镓锌具有可控掺杂性及高适应性。
在一些实施例中，请继续参考图1a-图1d，位线结构10的材料为钨、铜、钛、铝、铊、铪、铷、 氧化铟锡、导电玻璃与氧化铟镓锌中的一种或多种，这些材料为金属或金属氧化物等具有导电性能的材料，在反熔丝结构运作过程中提供低电压与字线结构形成压差，提供电路通道。钨具有较强的覆盖能力且化学性质稳定，使所形成字线结构40均匀致密且表面光滑，有利于提高反熔丝结构的稳定性；铜具有良好的放热特性、热导率、低电阻及高量产性；钛具有低电阻，能够减小所形成字线结构40的体积，从而可以提高制备产品的集成度，并且钛与氧化物半导体或硅接触不会产生缺陷，具有高耐热性；铝与各种半导体材料之间具有良好的晶格匹配度及晶格耦合度，且具有良好的耐硫化特性及较大的粘合力；铊具有较高的可塑性及低熔点；铪具有低功函数、化学性质稳定及不易与水和普通的酸或碱反应；铷具有优良的光电特性、导电性及导热性；氧化铟锡具有良好的化学稳定性、热稳定性和图形加工特性；导电玻璃具有良好且稳定的光学和电学性能；氧化铟镓锌具有可控掺杂性及高适应性。
作为示例，请继续参考图1a-图1d，预设编程电压的幅值范围包括：3.0V-4.0V，例如预设编程电压的幅值可以为3.0V、3.2V、3.4V、3.6V、3.8V或4.0V等等。本实施例的反熔丝结构的编程电压与可变电阻结构20厚度相关，减小可变电阻结构20的厚度，可以减小其编程电压的幅值，本实施例的可变电阻结构20厚度大于或等于
作为示例，请继续参考图1a-图1d，预设读取电压的幅值范围为0V-2.0V，以逐步读取电流变化。例如预设读取电压可以为0V、0.2V、0.4V、0.6V、0.8V、1.0V、1.2V、1.4V、1.6V、1.8V或2.0V等等。阈值选通结构30在2V上下电压操作下进行选通，从而实现可变电阻结构20能够在预设编程电压下从高阻态转变为低阻态，防止堆叠的反熔丝结构之间产生串扰现象。本实施例中反熔丝结构在较低电压下即可实现阻值变化，对降低功耗作用较大。
作为示例，请继续参考图1a-图1d，可变电阻结构20被配置为初始态为高阻态；在字线结构40提供的预设编程电压驱动下，从高阻态转变为低阻态；以及在字线结构40提供的预设读取电压驱动下，若为高阻态则读出第一数值及若为低阻态则读出第二数值。
作为示例，请继续参考图1a-图1d，在字线结构40上施加预设编程电压，位线结构10上施加0V电压，形成压差，阈值选通结构30在压差下打开，可变电阻结构20在压差下材料被击穿，内部形成导电通道，由初始高阻态转变为低阻态，即可变电阻结构20由关断状态变为具有一定阻值的导通状态。第一数值可以为“0”，第二数值可以为“1”。对可变电阻结构20进行读取操作时，向字线结构40施加预设读取电压，并向位线结构10上施加0V电压，形成压差，阈值选通结构30在压差下打开，测量流过可变电阻结构20的电流，此时用预设读取电压的幅值与流过可变电阻结构20的电流相比即可获取该可变电阻结构20的阻值。若可变电阻结构20为高阻态，则可变电阻结构20中几乎无电流流过，这样输出低电压为0V，将“0”状态读出；若可变电阻结构20为低阻态，则可变电阻结构20中有电流流过，输出电压大于0V，将“1”状态读出。根据读取参数的不同和读取电路的不同，第一数值可以为“1”，第二数值可以为“0”。
在一些实施例中，请继续参考图1a-图1d，反熔丝结构形成于存储结构的预设区域内；预设区域选自第一金属层的表面、第二金属层的表面、顶层金属层的表面和其组合。举例而言，顶层金属层可以为存储结构制造阶段的顶层金属层，顶层金属层作为反熔丝结构的底层结构，例如附图1a所示，顶层金属层作为位线结构10，在其上沿厚度方向例如oz方向依次叠置可变电阻结构20、阈值选通结构30及字线结构40。本实施例的反熔丝结构不限于做在有源区上，极大地降低了有源区的面积，并且本实施例中反熔丝结构形成于存储结构的预设区域内或形成于空闲区域，灵活性高，可以满足多种应用场景的制备需求，还可以减小反熔丝结构的体积，提高芯片密度与集成度。
在一些实施例中，反熔丝结构形成于存储结构的第一金属层和第二金属层之间的电容层所在平面内，利用存储结构的电容层附近空闲区域形成部分或全部反熔丝结构，降低反熔丝结构制备的复杂度，减小反熔丝结构所占存储结构空间，进一步降低存储结构的体积，并降低制造成本。
作为示例，请继续参考图1a-图1d，位线结构10内形成有目标沟槽(未图示)；连接位线结构10的可变电阻结构20或阈值选通结构30至少部分位于目标沟槽内，使得本实施例中的反熔丝结构形成埋入式位线结构10，提高反熔丝结构的集成度。
在一些实施例中，请继续参考图1a-图1d，可变电阻结构20的厚度范围为例如： 或等等。阈值选通结构30的厚度范围为1nm-10nm，例如：1nm、2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm或10nm等等。字线结构40的厚度范围为20nm-50nm，例如：20nm、25nm、30nm、35nm、40nm、45nm或50nm等等。位线结构10的厚度范围为20nm-50nm，例如：20nm、25nm、30nm、35nm、40nm、45nm或50nm等等。
在一些实施例中，请参考图2，提供了一种反熔丝阵列结构300，该反熔丝阵列结构300包括阵列排布的反熔丝堆叠结构200。反熔丝堆叠结构200包括共用同一位线结构10的第一反熔丝结构200a及第二反熔丝结构200b；第一反熔丝结构200a采用上述任一实施例的反熔丝结构；第二反熔丝结构200b采用上述任一实施例的反熔丝结构。第一反熔丝结构的可变电阻结构12及第一反熔丝结构的阈值选通结构13位于共用的位线结构10的相对一侧；第二反熔丝结构的可变电阻结构22及第二反熔丝结构的阈值选通结构23位于共用的位线结构10的相对另一侧。
作为示例，请继续参考图2，上述实施例中的反熔丝阵列结构300，可以利用第一反熔丝结构的可变电阻结构12及第二反熔丝结构的可变电阻结构22，具备的初始态为高阻态且在预设编程电压驱动下由高阻态转变为低阻态的性能，使得反熔丝阵列结构300在较低电压下可实现阻值变化，实现反熔丝阵列结构300的写入与读出，因此能够在降低反熔丝阵列结构300的平面面积和体积的前提下，降低反熔丝阵列结构300的能耗。
在一些实施例中，请参考图2，位线结构10沿第一方向延伸，多条位线结构10沿第二方向平行间隔排布；第一反熔丝结构的字线结构11的延伸方向平行于第二方向；第二反熔丝结构的字线结构21的延伸方向平行于第二方向；第一方向、第二方向相互垂直。第一方向可以为ox方向，第二方向可以为oy方向。本实施例的反熔丝堆叠结构200中采用共享位线结构10，可以减小产品体积、降低制备难度并提高制备产品的可靠性。
作为示例，请继续参考图2，可以设置沿第一方向例如ox方向相邻的两个反熔丝堆叠结构200的位线结构10在相同的工艺步骤中制备而成，还可以设置沿第二方向例如oy方向相邻的两个反熔丝堆叠结构200的字线结构在相同的工艺步骤中制备而成，使得沿第二方向例如oy方向相邻的反熔丝堆叠结构200共用字线结构，以及沿第一方向例如ox方向相邻的反熔丝堆叠结构200共用位线结构，从而能够减小不同反熔丝堆叠结构200的性能差异，提高反熔丝阵列结构300的性能与可靠性。
在一些实施例中，请继续参考图2，第一反熔丝结构的阈值选通结构13的选通时刻，与第二反熔丝结构的阈值选通结构23的选通时刻具有预设时间差。本实施例反熔丝阵列结构300通过预设时间差，在写入或读取操作过程中，将确保写入或读取操作不会同时进行，避免了操作冲突。
作为示例，请继续参考图2，多个反熔丝堆叠结构200阵列排布，每个反熔丝堆叠结构200包括共用位线结构10的第一反熔丝结构200a及第二反熔丝结构200b，该共用位线结构10的第一反熔丝结构的阈值选通结构13与第二反熔丝结构的阈值选通结构23可以连接至位线结构10的同一节点，反熔丝堆叠结构200中第一反熔丝结构200a的选通时刻与第二反熔丝结构200b的选通时刻具有预设时间差，在写入或读取操作过程中，将确保写入或读取操作不会同时进行，避免了操作冲突。
在一些实施例中，请继续参考图2，共用位线结构10的第一反熔丝结构的可变电阻结构12可以部分或全部位于第一反熔丝结构的字线结构11的内部，第二反熔丝结构的可变电阻结构22可以部分或全部位于第二反熔丝结构的字线结构21的内部；第一反熔丝结构的阈值选通结构13及第二反熔丝结构的阈值选通结构23的可以部分或全部位于位线结构10的内部，使得本实施例反熔丝阵列结构300形成埋入式反熔丝结构，以进一步减小反熔丝阵列结构300的体积。
在一些实施例中，本公开提供了一种存储器，该存储器包括上述的反熔丝结构和/或反熔丝阵列结构。存储器可以为动态随机存取存储器、静态随机存取存储器或磁阻随机存取存储器等存储器。
作为示例，存储器中由于集成本公开实施例中的反熔丝结构和/或反熔丝阵列结构，使得包括共用位线结构的反熔丝结构的反熔丝阵列实现垂直方向的堆叠，在确保反熔丝结构的性能不减小的情况下，有效地减小了反熔丝阵列的体积；并且，由于反熔丝结构具备初始态为高阻态且在预设编程电压驱动 下由高阻态转变为低阻态的性能，在较低电压下可实现阻值变化，实现反熔丝结构的写入与读出，能够降低反熔丝结构的平面面积与体积，进而降低存储器的体积。
在一些实施例中，存储器为动态随机存取存储器。反熔丝结构形成于动态随机存取存储器的电容层所在平面内，利用动态随机存取存储器的电容层附近空闲区域形成部分或全部反熔丝结构，降低反熔丝结构制备的复杂度，减小反熔丝结构所占动态随机存取存储器空间，进一步降低动态随机存取存储器的体积，并降低制造成本。
基于同样的发明构思，请参考图3，本公开实施例还提供了一种用于实现上述所涉及的反熔丝结构的制备方法。该方法所提供的解决问题的实现方案与上述结构中所记载的实现方案相似，故下面所提供的一个或多个反熔丝结构的制备方法实施例中的具体限定，可以参见上文中对于反熔丝结构的限定，在此不再赘述。该方法包括：
步骤S202：提供衬底；
步骤S204：于衬底上形成位线结构；
步骤S206：于位线结构远离衬底的一侧形成可变电阻结构和阈值选通结构，其中，可变电阻结构被配置为在预设编程电压下从高阻态转变为低阻态；阈值选通结构被配置为在阈值电压下选通；
步骤S208：于可变电阻结构和阈值选通结构上形成字线结构。上述实施例中的反熔丝结构的制备方法，通过于位线结构远离衬底的一侧形成可变电阻结构和阈值选通结构，及于可变电阻结构和阈值选通结构上形成字线结构，并将可变电阻结构被配置为在预设编程电压下从高阻态转变为低阻态及阈值选通结构被配置为在阈值电压下选通，使得反熔丝结构在较低电压下可实现阻值变化，进行反熔丝结构的写入与读出，避免堆叠的反熔丝结构之间产生信号串扰。
作为示例，请继续参考图3，步骤S202中的衬底可以采用半导体材料、绝缘材料、导体材料或者它们的任意组合构成。衬底可以为单层结构，也可以为多层结构。例如，衬底可以是诸如硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底或II/VI半导体衬底。或者，还例如，衬底可以是包括诸如Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗的层状衬底。因此衬底的类型不应限制本公开的保护范围。
作为示例，步骤S204中可以在衬底上形成位线结构，也可以将衬底上已有的导电材料层作为位线结构，省去制备位线结构的步骤，同时可以相对减少专门制备位线结构的占据体积。
作为示例，步骤S206中于位线结构远离衬底的一侧形成可变电阻结构和阈值选通结构之前，包括如下步骤：
步骤S2051：于位线结构10上形成第一隔离层101；
步骤S2052：于第一隔离层101远离位线结构10的表面形成第一图形化光刻胶层102；
步骤S2053：以第一图形化光刻胶层102为掩膜版刻蚀第一隔离层101，得到沿第一方向并列排布的第一沟槽103。
作为示例，请继续参考图4-图7，步骤S2051中可以采用沉积工艺于位线结构10上形成第一隔离层101，第一隔离层101可以是单层结构，也可以是多层堆叠结构，其材质可以是氧化硅。步骤S2052中在第一隔离层101远离位线结构10的表面涂覆第一光刻胶材料层1021，并经曝光、显影等一系列步骤，形成第一图形化光刻胶层102，第一图形化光刻胶层102具有限定第一沟槽103的位置及形状的开口图形，光刻胶可以是正光刻胶或负光刻胶，显影方式可以是正性显影或负性显影。步骤S2053中可以采用刻蚀工艺以第一图形化光刻胶层102为掩膜版刻蚀第一隔离层101，得到沿第一方向并列排布的第一沟槽103。刻蚀工艺可以包括但不限于干法刻蚀工艺及/或湿法刻蚀工艺。干法刻蚀工艺可以包括但不限于反应离子刻蚀(RIE)、感应耦合等离子体刻蚀(ICP)及高浓度等离子体刻蚀(HDP)等中一种或多种。
在一些实施例中，请参考图8-图10，可变电阻结构20位于位线结构10及阈值选通结构30之间，步骤S206中于位线结构10远离衬底的一侧形成可变电阻结构20和阈值选通结构30，包括：
步骤S2061：于位线结构10远离衬底的表面形成可变电阻结构20；
步骤S2062：于可变电阻结构20远离位线结构10的表面形成阈值选通结构30。
作为示例，请继续参考图8-图10，步骤S2061可以采用沉积工艺于第一沟槽103上沉积可变电阻材料层104。可变电阻材料层104的材料为氧化铪、氧化锆、氧化铊与氧化铝中的一种或多种。沉积工艺可以包括但不限于化学气相沉积工艺(Chemical Vapor Deposition，CVD)、原子层沉积工艺(Atomic Layer Deposition，ALD)、高密度等离子沉积(High Density Plasma，HDP)工艺、等离子体增强沉积工艺及旋涂介质层(Spin-on Dielectric，SOD)等工艺中的一种或多种。
作为示例，请继续参考图8-图10，步骤S2062可以采用沉积工艺于可变电阻材料层104上沉积阈值选通材料层105。阈值选通材料层105的材料为氧化钛、氧化铪、氧化钛铪与碲锡锗相变材料中的一种或多种。沉积工艺可以包括但不限于CVD、ALD、HDP及SOD等工艺中的一种或多种。
作为示例，请继续参考图8-图10，步骤S2062在形成阈值选通材料层105之后，去除剩余的图形化光刻胶层、位于图形化光刻胶层之上的可变电阻材料层104，以及阈值选通材料层105。对于去除图形化光刻胶层，去除方法可以包括灰化去胶及湿法清洗。
作为示例，请继续参考图11-图13，步骤S208中可以采用刻蚀工艺于阈值选通结构30之上刻蚀第一隔离层101，得到沿第一方向例如ox方向并列排布的第二沟槽106。步骤S208中可以采用沉积工艺于阈值选通结构30上沉积字线材料层107。字线材料层107的材料为钨、铜、钛、铝、铊、铪、铷、氧化铟锡、导电玻璃与氧化铟镓锌中的一种或多种。步骤S208中可以采用平坦化工艺去除多余的字线材料层107，于可变电阻结构20和阈值选通结构30上形成字线结构40。刻蚀工艺可以包括但不限于干法刻蚀工艺及/或湿法刻蚀工艺。干法刻蚀工艺可以包括但不限于RIE、ICP及HDP等中一种或多种。平坦化工艺包括机械抛光工艺、研磨工艺、刻蚀工艺、干式抛光工艺等中一种或多种。在一些实施例中，阈值选通结构位于位线结构及可变电阻结构之间，于位线结构远离衬底的一侧形成可变电阻结构和阈值选通结构，包括：于位线结构远离衬底的表面形成阈值选通结构；及于阈值选通结构远离位线结构的表面形成可变电阻结构。本实施例的反熔丝结构形成方式与上述实施例相同。
基于同样的发明构思，本公开实施例还提供了一种用于实现上述所涉及的反熔丝堆叠结构的制备方法。该方法所提供的解决问题的实现方案与上述结构中所记载的实现方案相似，故下面所提供的一个或多个反熔丝堆叠结构的制备方法实施例中的具体限定，可以参见上文中对于反熔丝堆叠结构的限定，在此不再赘述。
作为示例，反熔丝堆叠结构的制备方法的位线结构、阈值选通结构、可变电阻结构及字线结构的制备步骤可以采用上述反熔丝结构的制备方法中相同的制备步骤形成，但反熔丝堆叠结构的制备方法中最底层的金属层为字线结构、该层可以为第一金属层、第二金属层、中间金属层、顶层金属层和其组合。
作为示例，反熔丝堆叠结构的制备方法包括：提供衬底；于衬底上形成字线结构；于字线结构上形成第一隔离层；在第一隔离层远离字线结构的表面涂覆第一光刻胶材料层，并经曝光、显影等一系列步骤，形成第一图形化光刻胶层；以第一图形化光刻胶层为掩膜版刻蚀第一隔离层，得到沿第一方向例如ox方向并列排布的第一沟槽；于第一沟槽上沉积阈值选通材料层，于字线结构远离衬底的表面形成阈值选通结构；于阈值选通材料层上沉积可变电阻材料层，于阈值选通结构远离字线结构的表面形成可变电阻结构；去除剩余的图形化光刻胶层、位于图形化光刻胶层之上的阈值选通材料层及可变电阻材料层；于可变电阻结构之上刻蚀第一隔离层，得到沿第一方向例如ox方向并列排布的第二沟槽；于可变电阻结构上沉积位线材料层；去除多余位线材料层，于阈值选通结构和可变电阻结构上形成位线结构；于位线结构上形成第二隔离层；在第二隔离层远离位线结构的表面涂覆第二光刻胶材料层，并经曝光、显影等一系列步骤，形成第二图形化光刻胶层；以第二图形化光刻胶层为掩膜版刻蚀第二隔离层，得到沿第一方向并列排布的第三沟槽；于第三沟槽上沉积可变电阻材料层，于位线结构远离衬底的表面形成可变电阻结构；于可变电阻材料层上沉积阈值选通材料层，于可变电阻结构远离位线结构的表面形成阈值选通结构；去除剩余的图形化光刻胶层、位于图形化光刻胶层之上的可变电阻材料层及阈值选通材料层；于阈值选通结构之上刻蚀第二隔离层，得到沿第一方向例如ox方向并列排布的第四沟槽；于阈值选通结构上沉积字线材料层；去除多余字线材料层，于可变电阻结构和阈值选通 结构上形成字线结构。在一些实施例中，阈值选通结构位于位线结构及可变电阻结构之间，于位线结构远离衬底的一侧形成可变电阻结构和阈值选通结构，包括：于位线结构远离衬底的表面形成阈值选通结构；及于阈值选通结构远离位线结构的表面形成可变电阻结构。
应该理解的是，虽然图3的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，虽然图3中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对公开专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。

Claims (20)

  1. 一种反熔丝结构(100)，包括位线结构(10)、字线结构(40)，以及位于所述位线结构(10)和字线结构(40)之间的可变电阻结构(20)和阈值选通结构(30)，
    所述可变电阻结构(20)被配置为在预设编程电压下从高阻态转变为低阻态；
    所述阈值选通结构(30)被配置为在阈值电压下选通。
  2. 根据权利要求1所述的反熔丝结构(100)，其中，所述可变电阻结构(20)位于所述位线结构(10)及所述阈值选通结构(30)之间，或所述阈值选通结构(30)位于所述位线结构(10)及所述可变电阻结构(20)之间。
  3. 根据权利要求1或2所述的反熔丝结构(100)，其中，所述可变电阻结构(20)为金属介质层。
  4. 根据权利要求3所述的反熔丝结构(100)，其中，所述金属介质层的材料为氧化铪、氧化锆、氧化铊与氧化铝中的一种或多种。
  5. 根据权利要求1-4中任一项所述的反熔丝结构(100)，其中，所述阈值选通结构(30)的材料为氧化钛、氧化铪、氧化钛铪与碲锡锗相变材料中的一种或多种。
  6. 根据权利要求1-5中任一项所述的反熔丝结构(100)，其中，所述反熔丝结构(100)形成于存储结构的预设区域内；所述预设区域选自第一金属层的表面、第二金属层的表面、顶层金属层的表面和其组合。
  7. 根据权利要求1-6中任一项所述的反熔丝结构(100)，其中，所述反熔丝结构(100)形成于存储结构的第一金属层和第二金属层之间的电容层平面。
  8. 根据权利要求1-7中任一项所述的反熔丝结构，其中，包括如下特征中的至少一种：
    所述可变电阻结构(20)的厚度范围为
    所述阈值选通结构(30)的厚度范围为1nm-10nm；
    所述字线结构(40)的厚度范围为20nm-50nm；
    所述位线结构(10)的厚度范围为20nm-50nm。
  9. 一种反熔丝阵列结构，包括：
    第一反熔丝结构(200a)，采用权利要求1-8中任一项所述的反熔丝结构(100)；以及
    第二反熔丝结构(200b)，采用权利要求1-8中任一项所述的反熔丝结构(100)；
    所述第一反熔丝结构(200a)和所述第二反熔丝结构(200b)共用同一位线结构(10)，所述第一反熔丝结构(200a)的可变电阻结构(20)及阈值选通结构(30)位于共用的位线结构(10)的相对一侧，所述第二反熔丝结构(200b)的可变电阻结构(20)及阈值选通结构(30)位于共用的位线结构(10)的相对另一侧。
  10. 根据权利要求9所述的反熔丝阵列结构，其中，所述位线结构(10)沿第一方向延伸，多条所述位线结构(10)沿第二方向平行间隔排布；
    所述第一反熔丝结构(200a)的字线结构(40)的延伸方向平行于所述第二方向；
    所述第二反熔丝结构(200b)的字线结构(40)的延伸方向平行于所述第二方向；
    所述第一方向、所述第二方向相互垂直。
  11. 根据权利要求9或10所述的反熔丝阵列结构，其中，所述第一反熔丝结构(200a)的阈值选通结构(30)的选通时刻，与所述第二反熔丝结构(200b)的阈值选通结构(30)的选通时刻具有预设时间差。
  12. 根据权利要求9-11中任一项所述的反熔丝阵列结构，其中，两个共用所述位线结构(10)的所述可变电阻结构(20)或阈值选通结构(30)的至少部分位于所述位线结构(10)的内部。
  13. 根据权利要求9-12中任一项所述的反熔丝阵列结构，其中，两个共用所述位线结构(10)的所述可变电阻结构(20)或阈值选通结构(30)的至少部分位于所述字线结构(40)的内部。
  14. 根据权利要求10所述的反熔丝阵列结构，其中，沿所述第二方向相邻的两个所述第一反熔丝结构(200a)共用同一字线结构(40)；及/或
    沿所述第二方向相邻的两个所述第二反熔丝结构(200b)共用同一字线结构(40)。
  15. 根据权利要求10所述的反熔丝阵列结构，其中，沿所述第二方向相邻的两个所述第一反熔丝结构(200a)的字线结构(40)在相同的工艺步骤中制备而成；及/或
    沿所述第二方向相邻的两个所述第二反熔丝结构(200b)的字线结构(40)在相同的工艺步骤中制备而成。
  16. 一种存储器，包括权利要求1-8中任一项所述的反熔丝结构，或
    权利要求9-15中任一项所述的反熔丝阵列结构。
  17. 根据权利要求16所述的存储器，其中，所述存储器为动态随机存取存储器。
  18. 一种反熔丝结构的制备方法，包括：
    提供衬底；
    于所述衬底上形成位线结构(10)；
    于所述位线结构(10)远离所述衬底的一侧形成可变电阻结构(20)和阈值选通结构(30)；其中，所述可变电阻结构(20)被配置为在预设编程电压下从高阻态转变为低阻态；所述阈值选通结构(30)被配置为在阈值电压下选通；
    于所述可变电阻结构(20)和阈值选通结构(30)上形成字线结构(40)。
  19. 根据权利要求18所述的制备方法，其中，所述可变电阻结构(20)位于所述位线结构(10)及所述阈值选通结构(30)之间，所述于所述位线结构(10)远离所述衬底的一侧形成可变电阻结构(20)和阈值选通结构(30)，包括：
    于所述位线结构(10)远离所述衬底的表面形成所述可变电阻结构(20)；
    于所述可变电阻结构(20)远离所述位线结构(10)的表面形成所述阈值选通结构(30)。
  20. 根据权利要求19所述的制备方法，其中，所述阈值选通结构(30)位于所述位线结构(10)及所述可变电阻结构(20)之间，所述于所述位线结构(10)远离所述衬底的一侧形成可变电阻结构(20)和阈值选通结构(30)，包括：
    于所述位线结构(10)远离所述衬底的表面形成所述阈值选通结构(30)；
    于所述阈值选通结构(30)远离所述位线结构(10)的表面形成所述可变电阻结构(20)。
PCT/CN2023/086760 2023-02-23 2023-04-07 反熔丝结构及其制备方法、反熔丝阵列结构、存储器 Ceased WO2024174355A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140321194A1 (en) * 2013-04-25 2014-10-30 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and control method thereof
CN107545921A (zh) * 2016-06-27 2018-01-05 爱思开海力士有限公司 阻变存储器件及其感测方法
CN115863306A (zh) * 2023-02-23 2023-03-28 长鑫存储技术有限公司 反熔丝结构及其制备方法、反熔丝阵列结构、存储器

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WO2023011561A1 (zh) * 2021-08-06 2023-02-09 南方科技大学 存储器

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140321194A1 (en) * 2013-04-25 2014-10-30 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and control method thereof
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CN115863306A (zh) * 2023-02-23 2023-03-28 长鑫存储技术有限公司 反熔丝结构及其制备方法、反熔丝阵列结构、存储器

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