WO2024159685A1 - 3d堆叠的半导体器件及其制造方法、电子设备 - Google Patents

3d堆叠的半导体器件及其制造方法、电子设备 Download PDF

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Publication number
WO2024159685A1
WO2024159685A1 PCT/CN2023/099226 CN2023099226W WO2024159685A1 WO 2024159685 A1 WO2024159685 A1 WO 2024159685A1 CN 2023099226 W CN2023099226 W CN 2023099226W WO 2024159685 A1 WO2024159685 A1 WO 2024159685A1
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Prior art keywords
layer
layers
semiconductor device
electrode
insulating layer
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PCT/CN2023/099226
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English (en)
French (fr)
Inventor
艾学正
王祥升
王桂磊
戴瑾
赵超
桂文华
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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Priority to US18/692,912 priority Critical patent/US20250048615A1/en
Publication of WO2024159685A1 publication Critical patent/WO2024159685A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Definitions

  • the embodiments of the present disclosure relate to but are not limited to the field of semiconductor technology, and in particular to a 3D stacked semiconductor device and a manufacturing method thereof, and an electronic device.
  • DRAM dynamic random access memory
  • 3D DRAM three-dimensional (3D) DRAM is an important development direction.
  • the parasitic transistors generated by the device design and process of 3D DRAM affect the normal writing and reading of data when DRAM is working.
  • the present disclosure provides a 3D stacked semiconductor device, including:
  • Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate;
  • a word line passing through the transistors of different layers
  • the transistor comprises a semiconductor layer surrounding the sidewall of the word line, and a gate insulating layer arranged between the sidewall of the word line and the semiconductor layer;
  • the plurality of semiconductor layers of the plurality of transistors are arranged at intervals in the direction in which the word lines extend;
  • Each of the protection layers surrounds and covers the outer side wall of the semiconductor layer of the corresponding transistor, and two adjacent protection layers are disconnected.
  • the stacked plurality of transistors further comprises:
  • Insulating layers and conductive layers are alternately distributed from bottom to top along a direction perpendicular to the substrate;
  • the gate insulating layer is exposed between two adjacent semiconductor layers, the insulating layer is filled between two adjacent semiconductor layers and the insulating layer is in contact with the exposed gate insulating layer;
  • the conductive layer includes a first electrode and a second electrode independent of each other, one of the first electrode and the second electrode is the source of the transistor, and the other is the drain of the transistor.
  • the diameter of the through hole corresponding to the first area of the conductive layer is equal to the diameter of the through hole corresponding to the second area of the insulating layer;
  • the conductive layer only exposes the side wall in the through hole, and the insulating layer only exposes the side wall in the through hole;
  • the semiconductor layer is distributed on the side wall of the conductive layer.
  • the plurality of protection layers extend in a direction perpendicular to the substrate and are disconnected at upper and lower surfaces of the insulating layer.
  • the protection layer contacts the corresponding semiconductor layer of the transistor, and the protection layer covers a region of a sidewall of the semiconductor layer that is not in contact with the conductive layer.
  • the protection layer is further distributed on a sidewall of the conductive layer and contacts the sidewall of the conductive layer.
  • the protection layer and the insulating layer are made of different materials.
  • the plurality of transistors further include a fifth insulating layer covering an outer sidewall of the protection layer.
  • An embodiment of the present disclosure provides an electronic device, comprising the 3D stacked semiconductor device described in any of the above embodiments.
  • the present disclosure provides a method for manufacturing a 3D stacked semiconductor device, wherein the 3D stacked semiconductor device comprises: a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate; a word line running through the transistors in the different layers; and a plurality of protection layers respectively corresponding to the plurality of transistors.
  • the method for manufacturing the 3D stacked semiconductor device comprises:
  • the sacrificial layer is removed, and a semiconductor film and a gate insulating film are sequentially deposited on the sidewall of the through hole, and a gate electrode film filling the through hole is deposited to form a semiconductor layer, a gate insulating layer and a word line of the transistor in multiple layers, wherein the semiconductor layer is in contact with the first electrode, the second electrode and the protective layer; and the gate electrodes of the transistors in different layers are part of the word line;
  • the semiconductor layer in a region of the through hole corresponding to the first insulating layer is removed by etching.
  • the method before etching the conductive layer, further includes: etching from the top to the bottom of the stacked structure along a direction perpendicular to the substrate to expose the sidewalls of the conductive layer and the sidewalls of the first insulating layer;
  • the forming of a plurality of protection layers respectively corresponding to the plurality of transistors comprises:
  • a protective layer film is deposited on the side walls of the conductive layer, the side walls of the sacrificial layer and the side walls of the first insulating layer, and the protective layer film is etched from top to bottom in a direction perpendicular to the substrate to remove the protective layer film located on the side walls of the first insulating layer, thereby forming the protective layer covering the side walls of the conductive layer and the side walls of the sacrificial layer.
  • the method further comprises:
  • the third insulating layer and the first insulating layer are etched to expose a sidewall of the protection layer and a sidewall of the semiconductor layer in a region of the through hole corresponding to the first insulating layer.
  • FIG1A is a schematic cross-sectional view of a 3D stacked semiconductor device provided by an exemplary embodiment along a C1 direction parallel to a substrate;
  • FIG. 1B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG. 1A along a C2 direction perpendicular to the substrate;
  • FIG1C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG1A along a C3 direction perpendicular to the substrate;
  • 2A is a three-dimensional schematic diagram of a 3D stacked semiconductor device after forming a stacked structure of a conductive film and an insulating film according to an exemplary embodiment
  • FIG2B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG2A along direction C1;
  • FIG2C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG2A along direction C2;
  • FIG2D is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG2A along direction C3;
  • FIG3A is a perspective schematic diagram of a 3D stacked semiconductor device after a conductive layer is formed, provided by an exemplary embodiment
  • FIG3B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG3A along direction C1;
  • FIG3C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG3A along direction C2′;
  • FIG3D is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG3A along direction C3;
  • FIG. 4A is a three-dimensional schematic diagram of a 3D stacked semiconductor device after forming a capacitor according to an exemplary embodiment
  • FIG4B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG4A along direction C1;
  • FIG4C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG4A along direction C2′;
  • 4D is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG. 4A along direction C3;
  • FIG5A is a perspective schematic diagram of a 3D stacked semiconductor device after a sacrificial layer is formed according to an exemplary embodiment
  • FIG5B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG5A along direction C1;
  • 5C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG. 5A along direction C2;
  • 5D is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG. 5A along direction C3;
  • FIG6A is a three-dimensional schematic diagram of a 3D stacked semiconductor device provided by an exemplary embodiment after etching an insulating film between preset electrode patterns;
  • FIG6B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG6A along direction C1;
  • FIG6C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG6A along direction C2;
  • 6D is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG. 6A along direction C3;
  • FIG. 7A is a perspective schematic diagram of a 3D stacked semiconductor device after forming a first electrode and a second electrode according to an exemplary embodiment
  • FIG7B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG7A along direction C1;
  • FIG. 7C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG. 7A along direction C2;
  • FIG. 7D is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG. 7A along direction C3;
  • FIG8A is a perspective schematic diagram of a 3D stacked semiconductor device after a protective layer is formed according to an exemplary embodiment
  • FIG8B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG8A along direction C1;
  • FIG8C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG8A along direction C2;
  • FIG8D is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG8A along direction C3;
  • FIG9A is a perspective schematic diagram of a 3D stacked semiconductor device after removing a sacrificial layer provided by an exemplary embodiment
  • FIG9B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG9A along direction C1;
  • FIG. 9C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG. 9A along direction C2;
  • 9D is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG. 9A along direction C3;
  • FIG10A is a perspective schematic diagram of a 3D stacked semiconductor device after forming a semiconductor layer and a gate electrode according to an exemplary embodiment
  • FIG10B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG10A along direction C1;
  • FIG10C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG10A along direction C2;
  • 10D is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG. 10A along direction C3;
  • FIG. 11A is a perspective schematic diagram of a 3D stacked semiconductor device after exposing semiconductor layers between layers provided by an exemplary embodiment
  • FIG11B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG11A along direction C1;
  • FIG11C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG11A along direction C2;
  • FIG11D is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG11A along direction C3;
  • FIG12A is a perspective schematic diagram of a 3D stacked semiconductor device after etching a semiconductor layer between layers provided by an exemplary embodiment
  • FIG12B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG12A along direction C1;
  • FIG12C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG12A along direction C2;
  • FIG. 12D is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG. 12A along direction C3;
  • FIG13A is a perspective schematic diagram of a 3D stacked semiconductor device after a fourth insulating layer is formed according to an exemplary embodiment
  • FIG13B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG13A along direction C1;
  • FIG13C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG13A along direction C2;
  • FIG13D is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG13A along direction C3;
  • FIG14 is a schematic diagram of a preset electrode pattern provided by another exemplary embodiment.
  • FIG. 15 is a flow chart of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • a channel region refers to a region where current mainly flows.
  • parallel means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°.
  • perpendicular means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.
  • the "A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process.
  • the orthographic projection of B is within the range of the orthographic projection of A means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • a and B are an integrated structure
  • a film layer patterned to form a connection is an integrated structure.
  • a and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.
  • the semiconductor layers between different memory cell layers are removed by etching, so that parasitic transistors (parasitic MOS for short) between adjacent transistors between adjacent layers can be eliminated.
  • FIG1A is a schematic cross-sectional view of a 3D stacked semiconductor device provided by an exemplary embodiment along a C1 direction parallel to a substrate
  • FIG1B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG1A along a C2 direction perpendicular to the substrate
  • FIG1C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG1A along a C3 direction perpendicular to the substrate.
  • the C2 direction is perpendicular to the C3 direction, as shown in FIG1A, FIG1B and FIG1C, the 3D stacked semiconductor device provided in this embodiment may include:
  • a plurality of transistors are distributed in different layers and stacked along a direction perpendicular to the substrate 1;
  • a word line 40 which runs through the transistor structures of different layers, and the word line 40 may extend in a direction perpendicular to the substrate 1;
  • a plurality of protection layers 82 respectively corresponding to the plurality of transistors
  • the transistor may include a semiconductor layer 23 surrounding the sidewall of the word line 40, and a gate insulating layer 24 disposed between the sidewall of the word line 40 and the semiconductor layer 23;
  • the plurality of semiconductor layers 23 of the plurality of transistors are arranged at intervals in the direction in which the word line 40 extends, that is, the plurality of semiconductor layers 23 are distributed in different regions of the sidewall of the word line 40;
  • Each of the protective layers 82 surrounds and covers the outer sidewall of the semiconductor layer 23 of the corresponding transistor, and two adjacent protective layers 82 are disconnected, that is, the protective layers 82 corresponding to the multiple transistors are arranged at intervals.
  • the outer sidewall of the semiconductor layer 23 is the sidewall of the semiconductor layer 23 away from the gate electrode 26.
  • the semiconductor layers of transistors in different layers are arranged at intervals, which can eliminate parasitic transistors.
  • a protective layer when manufacturing the 3D stacked semiconductor device, it is possible to avoid exposing the semiconductor layer of the transistor and damaging the semiconductor layer, thereby improving the reliability and stability of the device channel material.
  • the transistor may further include a gate electrode 26 .
  • the gate electrode 26 may extend in a direction perpendicular to the substrate 1 .
  • the gate electrode 26 of each transistor is a part of the word line 40 .
  • the transistor may further include a first electrode 51 and a second electrode 52, and the channel between the first electrode 51 and the second electrode 52 may be a horizontal channel.
  • a horizontal channel is a channel in which the carrier transmission direction is in a plane parallel to the substrate, but the carrier transmission direction is not limited to one direction. In practical applications, the carrier transmission direction extends in one direction as a whole, but locally, it is related to the shape of the semiconductor layer. In other words, a horizontal channel does not mean that the carrier transmission direction is in a horizontal direction. It must extend in one direction in the plane, and may extend in different directions. For example, when the semiconductor layer is annular, the source contact area and the drain contact area on the annular semiconductor layer are part of the ring.
  • the carriers extend from the source contact area to the drain contact area in one direction as a whole, and may not be in a different direction locally.
  • the carrier transmission direction in the plane parallel to the substrate is also a macroscopic concept, and is not limited to being absolutely parallel to the substrate.
  • the present application protects the channel between the first electrode and the second electrode as a channel that is not perpendicular to the substrate.
  • the gate electrode 26 may extend only in a direction perpendicular to the substrate 1.
  • the gate electrode 26 includes a side surface and end surfaces at the upper and lower ends, and the side surface is perpendicular to the substrate as a whole, or in other words, the partial area of the side wall corresponding to the semiconductor layer 23 that controls the gate electrode 26, and the film layer of this area is perpendicular to the substrate 1.
  • the area where there may be local bending is also included in the above-mentioned situation of the present application.
  • the two opposite main surfaces have a larger surface area than the end faces.
  • the semiconductor layer 23 extends along the side wall of the gate electrode 26, the film thickness direction of the semiconductor layer 23 is parallel to the direction of the substrate 1, the length of the film layer extending up and down the side wall of the gate electrode 26 is the height of the film layer, and the length surrounding the gate electrode 26 is the width of the film layer.
  • the semiconductor layer 23 extends on the sidewall of the gate electrode 26 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate 1. In some embodiments, the semiconductor layer 23 may only extend in a direction perpendicular to the substrate 1. In other embodiments, the semiconductor layer 23 extends along the sidewall of the gate electrode 26 or the word line 40, and the shape of the semiconductor layer 23 is adapted to the shape of the sidewall of the word line 40 or the gate electrode 26.
  • the surrounding can be understood as partially or completely surrounding the gate electrode 26 or the word line 40.
  • the surrounding can be completely surrounded as a whole, and the cross-section of the semiconductor layer 23 after the surrounding can be a closed ring, and the ring shape is adapted to the outer contour of the cross-section of the gate electrode 26.
  • the cross-section of the gate electrode 26 is, for example, a square structure. The interception direction of the cross-section is intercepted along a direction parallel to the substrate 1.
  • the surrounding can be partially surrounded, and the cross-section after the surrounding is not closed, but presents a ring shape.
  • the cross-section of the semiconductor layer 23 is a ring with an opening.
  • the material composition of different regions of the word line 40 extending in a direction perpendicular to the substrate 1 is the same, which can be understood as being formed using the same film manufacturing process.
  • the same material composition can be understood as the same main elements tested in the material, for example, they are all made of conductive materials such as metal or ITO, but the atomic number ratio of different regions is not limited.
  • transistors in different layers may share a ring-shaped gate insulating layer 24 extending in a direction perpendicular to the substrate, that is, the gate insulating layers 24 of the multiple transistors are connected to form an integrated structure.
  • the first electrode 51 and the second electrode 52 of the same transistor may be located in the same conductive film layer. It can be understood that the first electrode 51 and the second electrode 52 are located in the same metal film layer, formed by patterning a conductive film layer, and the conductive film layer is approximately parallel to the upper surface of the substrate 1.
  • the first electrode 51 and the second electrode 52 may be arranged in the same layer. That is, the first electrode 51 and the second electrode 52 may be formed simultaneously by the same patterning process, but the embodiments of the present disclosure are not limited thereto, and the first electrode 51 and the second electrode 52 may be manufactured separately by different patterning processes.
  • the gate insulating layer 24 located between the gate electrode 26 and the semiconductor layer 23 is exposed between the semiconductor layers 23 that are spaced apart.
  • the stacked plurality of transistors may further include:
  • Insulating layers 16 and conductive layers 12 are alternately distributed in sequence from bottom to top along a direction perpendicular to the substrate 1 (i.e., from close to the substrate 1 to far away from the substrate 1);
  • the gate insulating layer 24 is exposed between two adjacent semiconductor layers 23 , and the insulating layer 16 is filled between two adjacent semiconductor layers 23 , and the insulating layer 16 is in contact with the exposed gate insulating layer 24 ;
  • the conductive layer 12 includes a first electrode 51 and a second electrode 52 that are independent of each other, one of the first electrode 51 and the second electrode 52 is the source of the transistor, and the other is the drain of the transistor, and each of the semiconductor layers 23 is in contact with the source and drain of the conductive layer 12 of the corresponding layer.
  • the diameter of the through hole K1 corresponding to the first area of the conductive layer 12 may be equal to the diameter of the through hole K2 corresponding to the second area of the insulating layer 16; that is, the size and shape of the cross section of the through hole K1 at different positions along the direction parallel to the substrate 1 may be the same, and the through hole K1 may be manufactured by one etching;
  • the conductive layer 12 only exposes the side wall in the through hole K1, and the insulating layer 16 only exposes the side wall in the through hole K1;
  • the semiconductor layer 23 is distributed on the sidewall of the conductive layer 12. In this embodiment, the semiconductor layer 23 does not extend to the upper and lower surfaces of the conductive layer 12, wherein the upper surface of the conductive layer 12 is the surface away from the substrate 1, and the lower surface of the conductive layer 12 is the surface close to the substrate 1.
  • the plurality of protective layers 82 may extend in a direction perpendicular to the substrate 1 and be disconnected at the upper and lower surfaces of the insulating layer 16.
  • the insulating layer 16 may include a lower surface located on a side facing the substrate 1 and a lower surface located on a side away from the substrate 1.
  • the protective layer 82 is disconnected at the upper and lower surfaces of the insulating layer 16, that is, the protective layer 82 is disconnected when it extends to the upper surface of the insulating layer 16 and is disconnected when it extends to the lower surface of the insulating layer 16. That is, the protective layer 82 is only distributed in the film layer where the conductive layer 12 is located.
  • the protection layer 82 is disconnected at the upper and lower surfaces of the insulating layer 16, which can facilitate the removal of the semiconductor layers between the layers.
  • the protective layer 82 contacts the semiconductor layer 23 of the corresponding transistor, and the protective layer 82 covers the area of the sidewall of the semiconductor layer 23 that is not in contact with the conductive layer 12.
  • the sidewall of the semiconductor layer 23 may include four side surfaces, one side surface contacts the first electrode 51, one side surface contacts the second electrode 52, and the remaining two side surfaces contact the protective layer 82 and are protected by the protective layer 82.
  • the protective layer 82 may also be distributed on the sidewalls of the conductive layer 12 and contact the sidewalls of the conductive layer 12. As shown in FIG1A , the protective layer 82 contacts the sidewalls of the first electrode 51 and the sidewalls of the second electrode 52. The protective layer 82 may protect the first electrode 51 and the second electrode 52 to avoid damage to the first electrode 51 and the second electrode 52 during the manufacturing process.
  • the protective layer 82 is made of a different material than the insulating layer 16.
  • an insulating film layer of the same material as the insulating layer 16 is usually filled between the conductive layers.
  • the protective layer 82 is made of a different material than the insulating layer 16, which facilitates the separate etching of the protective layer 82 and the insulating film layer during the manufacturing process of the 3D stacked semiconductor device.
  • the gate insulating layers 24 of the plurality of transistors may be connected to form an integrated structure.
  • the embodiments of the present disclosure are not limited thereto.
  • the gate insulating layers 24 of transistors in different layers may be spaced apart in a direction perpendicular to the substrate 1.
  • the plurality of gate insulating layers 24 of the plurality of transistors may be disconnected at the sidewalls of the insulating layer 16.
  • the stacked transistors further include a fifth insulating layer 17 covering the outer sidewall of the protective layer 82. As shown in FIG1B, the sidewall of the protective layer 82 away from the semiconductor layer 23 is the outer sidewall, and the outer sidewall of the protective layer 82 is covered with the fifth insulating layer 17.
  • the scheme provided by this embodiment can form a multi-layer stacked first electrode and a second electrode by relative stacking of a conductive layer and an insulating layer and then by a mask, so that the process is simple.
  • the structure of the 3D stacked semiconductor device can be made more compact.
  • the projections of the multiple protection layers 82 corresponding to the multiple transistors in the direction perpendicular to the substrate 1 overlap.
  • multiple protection layers 82 can be formed through a single manufacturing process during the process, thereby simplifying the process.
  • the structure of the 3D stacked semiconductor device can be made more compact.
  • the above-mentioned 3D stacked semiconductor device can form a 1T1C storage structure with a capacitor, or form a 2T0C storage structure with other transistors, and so on.
  • an embodiment of the present disclosure provides a 3D memory, comprising: the above-mentioned 3D stacked semiconductor device, and also comprising: a data storage element.
  • the data storage element is, for example, a capacitor, that is, a 1T1C storage structure is formed.
  • the capacitor may include a first plate 41 and a second plate 42, and the first plate 41 is connected to the first electrode 51.
  • the first plate 41 and the first electrode 51 can be connected as an integrated structure.
  • the second plates 42 of the capacitors in the same column of different layers can be connected as an integrated structure. As shown in FIG. 1C, the second plates 42 of the capacitors in the first column of different layers are connected as an integrated structure.
  • the second plates 42 of the capacitors in the second column of different layers are connected as an integrated structure, that is, the capacitors in the same column of different layers share the same plate as the second plate 42.
  • the capacitor may also include a second insulating layer 13 disposed between the first plate 41 and the second plate 42.
  • the second insulating layer 13 serves as a medium between the first plate 41 and the second plate 42.
  • the second insulating layer 13 of the capacitors in the same column of different layers can be connected as an integrated structure. As shown in FIG1C , the second insulating layer 13 of the capacitors in the first column of different layers is connected as an integrated structure. The second insulating layer 13 of the capacitors in the second column of different layers is connected as an integrated structure, that is, the capacitors in the same column of different layers share the same insulating layer as the medium between the plates.
  • a transistor and a data storage element constitute a memory cell.
  • the memory cells in the same layer form an array distributed along a first direction X and a second direction Y, respectively, and each layer of the memory cells further includes: a bit line 30, and the bit line 30 is connected to the second electrode 52 of the transistor in the same layer and the same column.
  • FIG1A shows that each layer includes three rows and two columns of memory cells, but the embodiments of the present disclosure are not limited thereto, and each layer may include memory cells of other numbers of rows and columns, for example, may include only one memory cell.
  • the first direction X may be parallel to the substrate
  • the second direction Y may be parallel to the substrate
  • the first direction X and the second direction Y intersect.
  • the first direction X and the second direction Y may be perpendicular.
  • the second electrodes 52 of the transistors of the memory cells in two adjacent columns are connected to form a bit line 30.
  • the second electrodes 52 of the transistors in two adjacent columns of the same layer and the bit line 30 may be connected to form an integrated structure.
  • the bit line 30 may extend along the second direction Y.
  • the first electrode 51 may extend along a first direction X.
  • a through hole penetrating the stacked structure is etched, a sacrificial layer is deposited in the through hole as a virtual word line, a protective layer is formed to protect the area of the virtual word line corresponding to the channel area, and then the sacrificial layer is removed to form a word line and a semiconductor layer in the through hole.
  • the channel area of the transistor in the semiconductor layer is protected by the protective layer, and then the channel of the parasitic transistor is exposed and removed, thereby achieving the effect of removing the parasitic transistor.
  • the technical solution of this embodiment is further explained below through the manufacturing process of the 3D stacked semiconductor device of this embodiment.
  • the "patterning process” mentioned in this embodiment includes depositing a film layer, coating a photoresist, Mask exposure, development, etching, stripping of photoresist and other processes are mature manufacturing processes in the relevant technology.
  • Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., and etching can adopt known methods, which are not specifically limited here.
  • thin film refers to a layer of thin film made by a deposition or coating process of a certain material on a substrate.
  • the "thin film” does not require a composition process or a photolithography process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” still requires a composition process or a photolithography process during the entire production process, it is called a “thin film” before the composition process and a “layer” after the composition process.
  • the "layer” after the composition process or the photolithography process contains at least one "pattern".
  • the manufacturing process of a 3D stacked semiconductor device may include:
  • FIG2A is a three-dimensional schematic diagram of a 3D stacked semiconductor device
  • FIG2B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in FIG2A along the C1 direction
  • FIG2C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in FIG2A along the C2 direction
  • FIG2D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in FIG2A along the C3 direction.
  • the C1 direction is parallel to the substrate 1
  • the C2 direction is perpendicular to the substrate 1
  • the C3 direction is perpendicular to the substrate 1
  • the C2 direction is perpendicular to the C3 direction.
  • the substrate 1 may be a semiconductor substrate, such as a silicon substrate.
  • the first insulating film 9 may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K ⁇ 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.
  • the first conductive film 11 may include but is not limited to a multi-layer structure of titanium nitride (TiN)/tungsten (W).
  • the stacked structure shown in FIG2A includes 5 layers of first insulating films 9 and 4 layers of first conductive films 11, which is only an example. In other embodiments, the stacked structure may include more or fewer layers of first insulating films 9 and first conductive films 11 that are alternately arranged.
  • the stacked structure shown in FIG2A also includes a hard mask disposed on the top, which is used in a subsequent patterning process and will be removed after patterning.
  • Fig. 3A is a three-dimensional schematic diagram of a 3D stacked semiconductor device
  • Fig. 3B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Fig. 3A along the C1 direction
  • Fig. 3C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Fig. 3A along the C2' direction
  • Fig. 3D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Fig. 3A along the C3 direction.
  • the C2' direction is parallel to the C2 direction.
  • the step of patterning the stacked structure to form a stacked structure including a conductive layer 12 and a first insulating layer 10 may include:
  • the stacked structure is etched by dry etching, and the conductive layer 12 is formed by patterning, and then the etched area is filled with a first insulating film to isolate different devices; the conductive layer 12 includes a preset conductive layer.
  • the preset electrode pattern includes a bit line to be formed and a first electrode and a second electrode of the transistor; as shown in FIG3B.
  • the preset electrode pattern shown in FIG3B is only an example, and the preset electrode pattern can be other shapes, such as the preset electrode pattern can be the shape shown in FIG14, which is not limited in the embodiment of the present disclosure.
  • the first insulating film is etched (which may include anisotropic etching and isotropic etching) to remove the first insulating film located in the capacitor area 100 to form a first insulating layer 10. At this time, the end surface and part of the side wall of the conductive layer 12 located in the capacitor area 100 are exposed, and the exposed area can be used as the first plate 41 of the capacitor.
  • the top layer of the device in FIG. 3A is a hard mask, which will be etched away in subsequent processes.
  • the forming of the second insulating layer 13 and the second electrode plate 42 may include: depositing a second insulating film and a conductor material in the capacitor region 100 in sequence to form the second insulating layer 13 and the second electrode plate 42, respectively, wherein the second insulating layer 13 covers the exposed area of the conductive layer 12, as shown in Figures 4A, 4B, 4C, and 4D, wherein Figure 4A is a three-dimensional schematic diagram of a 3D stacked semiconductor device, Figure 4B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 4A along the C1 direction, Figure 4C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 4A along the C2' direction, and Figure 4D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 4A along the C3 direction.
  • the second insulating layer 13 serves as a medium between the capacitor plates, and the second plate 42 serves as an electrode of the capacitor.
  • the second insulating film and the conductor material can be deposited by atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the second insulating film may be a High-K dielectric material, that is, a dielectric material with a dielectric constant K ⁇ 3.9.
  • the High-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide (Al 2 O 3 ), and hafnium oxide.
  • the conductor material includes but is not limited to at least one of the following: polysilicon, tungsten, and titanium nitride.
  • the forming of the sacrificial layer 81 may include: etching the stacked structure by dry etching to form a plurality of through holes K1 penetrating the plurality of stacked structures, wherein the side walls of the through holes K1 expose each of the conductive layers 12; the through holes K1 may include an area corresponding to the conductive layer 12 and an area corresponding to the first insulating layer 10, that is, the area formed by the through hole K1 penetrating the conductive layer 12 is the area of the conductive layer 12 corresponding to the through hole K1, and the area formed by the through hole K1 penetrating the first insulating layer 10 is the area of the first insulating layer 10 corresponding to the through hole K1.
  • Figures 5A, 5B, 5C, and 5D wherein Figure 5A is a three-dimensional schematic diagram of a 3D stacked semiconductor device, Figure 5B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 5A along the C1 direction, Figure 5C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 5A along the C2 direction, and Figure 5D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 5A along the C3 direction.
  • Figure 5A is a three-dimensional schematic diagram of a 3D stacked semiconductor device
  • Figure 5B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 5A along the C1 direction
  • Figure 5C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 5A along the C2 direction
  • Figure 5D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 5A along the C3 direction.
  • the orthographic projection of the through hole K1 on a plane parallel to the substrate 1 may be a square or the like.
  • an orthographic projection of the through hole K1 on a plane parallel to the substrate 1 is located within an orthographic projection of the conductive layer 12 when the through hole K1 is not formed.
  • the material of the insulating layer film is different from the material of the first insulating layer 10 , and the insulating layer film is, for example, silicon nitride (SiN).
  • the etching of the first insulating film filled between the preset electrode patterns may include: etching the first insulating film filled between the preset electrode patterns from the top to the bottom of the stacked structure along a direction perpendicular to the substrate 1 to expose the sidewalls of the conductive layer 12 and the first insulating layer 10 outside the capacitor region 100, as shown in Figures 6A, 6B, 6C, and 6D, wherein Figure 6A is a three-dimensional schematic diagram of a 3D stacked semiconductor device, Figure 6B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 6A along the C1 direction, Figure 6C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 6A along the C2 direction, and Figure 6D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 6A along the C3 direction.
  • the pattern of the first insulating layer 10 outside the capacitor region 100 is consistent with the pattern of the conductive layer 12 outside the capacitor region
  • Figures 7A, 7B, 7C, and 7D wherein Figure 7A is a three-dimensional schematic diagram of a 3D stacked semiconductor device, Figure 7B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 7A along the C1 direction, Figure 7C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 7A along the C2 direction, and Figure 7D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 7A along the C3 direction.
  • Figure 7A is a three-dimensional schematic diagram of a 3D stacked semiconductor device
  • Figure 7B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 7A along the C1 direction
  • Figure 7C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 7A along the C2 direction
  • Figure 7D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 7A along the C3 direction.
  • One of the first electrode 51 and the second electrode 52 serves as a source electrode of the transistor, and the other serves as a drain electrode of the transistor.
  • the first insulating layer 10 is not etched, that is, the pattern of the first insulating layer 10 remains unchanged, which is consistent with the pattern of the conductive layer 12 when step 6) is not performed, that is, consistent with the pattern of the conductive layer 12 shown in FIG. 6B .
  • the forming of the protection layer 82 may include: forming a protective layer 82 on the sidewalls of the conductive layer 12, the sidewalls of the sacrificial layer 81 (ie, the sidewalls of the sacrificial layer 81 exposed in step 6), and the sidewalls of the first insulating layer 10; A protective layer film is deposited on the wall, and the protective layer film is anisotropically etched, for example, the protective layer film is etched from top to bottom in a direction perpendicular to the substrate 1 to remove the protective layer film located on the side wall of the first insulating layer 10, to form the side wall of the conductive layer 12, the protective layer 82 on the side wall of the sacrificial layer 81, the protective layer 82 fills the area where the conductive layer 12 is etched in step 7), that is, the pattern formed by the protective layer 82 and the conductive layer 12 is consistent with the pattern of the conductive layer 12 that has not been etched, that is, consistent with the pattern of the conductive layer 12
  • the protective layer 82 may cover the sidewall of the conductive layer 12, and a plurality of protective layers 82 extend in a direction perpendicular to the substrate 1, and a plurality of protective layers 82 are arranged at intervals in a direction perpendicular to the substrate 1, and are disconnected at the sidewall of the first insulating layer 10.
  • the protective layer 82 contacts the sidewall of the sacrificial layer 81.
  • the protective layer 82 may include a first portion and a second portion, wherein the first portion is arranged on a first side of the sacrificial layer 81, and the second portion is arranged on a second side of the sacrificial layer 81, and the first side and the second side may be opposite sides.
  • the protective layer 82 may protect the semiconductor layer as the channel region of the transistor when the semiconductor layer of the parasitic transistor is subsequently etched.
  • a protective layer film can be deposited on the side walls of the conductive layer 12 and the sacrificial layer 81 and then etched to form the protective layer 82; or, a protective layer film can be deposited on the substrate 1 to fill the blank areas etched in the stacked structure, and then the protective layer film can be etched to form the protective layer 82.
  • the material of the protective layer film is different from that of the first insulating layer 10 , so that the protective layer 82 and the first insulating layer 10 can be etched independently.
  • the protective layer film may be made of the same material as the sacrificial layer film, but is not limited thereto.
  • the protective layer film may include but is not limited to SiN.
  • the removing of the sacrificial layer 81 may include:
  • the sacrificial layer 81 in the through hole K1 is removed by anisotropic etching, for example, etching is performed from the top to the bottom of the through hole K1 in a direction perpendicular to the substrate to remove the sacrificial layer 81, as shown in Figures 9A, 9B, 9C, and 9D, wherein Figure 9A is a three-dimensional schematic diagram of a 3D stacked semiconductor device, Figure 9B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 9A along the C1 direction, Figure 9C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 9A along the C2 direction, and Figure 9D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 9A along the C3 direction.
  • the forming of the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 may include: depositing a semiconductor film and a gate insulating film on the side wall of the through hole K1 in sequence, and depositing a gate electrode film filling the through hole K1, to sequentially form the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26; as shown in Figures 10A, 10B, 10C and 10D, wherein Figure 10A is a stereoscopic schematic diagram of a 3D stacked semiconductor device, Figure 10B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 10A along the C1 direction, Figure 10C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 10A along the C2 direction, and Figure 10D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 10A along the C3 direction.
  • the semiconductor film includes but is not limited to at least one of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO ), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnIn
  • the gate insulating film may be a High-K dielectric material, such as a dielectric material with a dielectric constant K ⁇ 3.9.
  • it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO 2 ) and other high-K materials.
  • the gate electrode material may be one or more of the following different types of materials.
  • metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing the metals mentioned above; it can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as tin-doped indium oxide ITO, indium-doped zinc oxide IZO, indium oxide InO, aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.
  • metals such as tungsten, aluminum, titanium,
  • FIGS. 11A, 11B, 11C, and 11D wherein FIG. 11A is a three-dimensional schematic diagram of a 3D stacked semiconductor device, FIG. 11B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in FIG. 11A along the C1 direction, and FIG. 11C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in FIG. 11A along the C2 direction.
  • 11D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in FIG11A along the C3 direction.
  • the semiconductor layer 23 in the region of the through hole K1 corresponding to the conductive layer 12 is not exposed, and the sidewall of the semiconductor layer 23 in the region is partially covered by the conductive layer 12 and partially covered by the protective layer 82, thereby avoiding damage in subsequent steps.
  • the etching of the first insulating layer 10 and the third insulating layer 14 may include: removing the third insulating layer 14 by dry etching, and removing the first insulating layer 10 covering the sidewall of the semiconductor layer 23 by wet etching.
  • Figure 12A is a three-dimensional schematic diagram of a 3D stacked semiconductor device
  • Figure 12B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 12A along the C1 direction
  • Figure 12C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 12A along the C2 direction
  • Figure 12D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 12A along the C3 direction.
  • the parasitic transistor can be removed and the device performance can be improved. It can be seen that the semiconductor layer 23 is etched into multiple segments arranged at intervals, and each segment serves as a semiconductor layer of a transistor.
  • the formation of the fourth insulating layer 15 may include: filling a fourth insulating film on the substrate formed with the aforementioned pattern and grinding it flat to form the fourth insulating layer 15, as shown in Figures 13A, 13B, 13C, and 13D, wherein Figure 13A is a three-dimensional schematic diagram of a 3D stacked semiconductor device, Figure 13B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 13A along the C1 direction, Figure 13C is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 13A along the C2 direction, and Figure 13D is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 13A along the C3 direction.
  • the fourth insulating layer 15 may include two parts, one part is an insulating layer 16 located between adjacent conductive layers 12, and the other part fills the area between the electrodes of the conductive layer 12, i.e., the fifth insulating layer 17.
  • the solution provided in this embodiment forms a sacrificial layer as a virtual word line after forming a through hole, removes the conductive layer in the channel area around the virtual word line, forms a protective layer (or inner spacer) in the channel area, removes the sacrificial layer to form a semiconductor layer and a gate electrode, and then exposes the channel of the parasitic transistor.
  • the channel of the device is protected by the protective layer, so that the channel of the parasitic transistor can be selectively removed, and finally the purpose of removing the parasitic transistor is achieved.
  • the solution provided in this embodiment can effectively eliminate the parasitic transistor, and there is no need to expose the channel of the device in the later stage, avoiding the risk of damage to the channel exposure, and ensuring the reliability and stability of the device channel material.
  • the manufacturing method of this embodiment can be implemented using existing mature manufacturing equipment, and can be well compatible with existing manufacturing processes. Therefore, the process is simple to implement, easy to implement, and has high production efficiency. It has the advantages of easy process implementation, low production cost, and high yield rate.
  • the present disclosure also provides an electronic device, including the 3D stacked semiconductor device described in any of the above embodiments.
  • the electronic device may be: a storage device, a smart phone, a computer, Tablet computer, artificial intelligence device, wearable device or mobile power supply, etc.
  • the storage device may include a memory in a computer, etc., which is not limited here.
  • FIG15 is a flow chart of a method for manufacturing a 3D stacked semiconductor device provided by an embodiment of the present disclosure.
  • this embodiment provides a method for manufacturing a 3D stacked semiconductor device, wherein the 3D stacked semiconductor device may include: a plurality of transistors distributed in different layers and stacked along a direction perpendicular to the substrate; a word line running through the transistors in the different layers; and a plurality of protective layers corresponding to the plurality of transistors respectively; the method for manufacturing the 3D stacked semiconductor device includes:
  • Step 1501 providing a substrate, and alternately depositing a first insulating film and a conductive film on the substrate in sequence, and patterning to form a stacked structure, wherein the stacked structure includes a stack of alternately arranged first insulating layers and conductive layers, wherein the conductive layer includes a preset electrode pattern, and the preset electrode pattern includes a first electrode and a second electrode of the transistor to be formed;
  • Step 1502 forming a through hole penetrating the stacked structure in a direction perpendicular to the substrate, wherein the sidewall of the through hole exposes each of the conductive layers, and an insulating film is filled in the through hole to form a sacrificial layer of a word line;
  • Step 1503 etching the conductive layer to expose a portion of the sidewall of the sacrificial layer, so that the first electrode and the second electrode in the preset electrode pattern are disconnected, and the first electrode contacts the sacrificial layer, and the second electrode contacts the sacrificial layer;
  • Step 1504 forming a plurality of protection layers corresponding to the plurality of transistors respectively, wherein the plurality of protection layers respectively cover the side walls of the sacrificial layer and the conductive layer, and two adjacent protection layers are disconnected;
  • Step 1505 removing the sacrificial layer, depositing a semiconductor film, a gate insulating film, and a gate electrode film filling the through hole in sequence on the sidewall of the through hole, so as to form a semiconductor layer, a gate insulating layer, and a word line of the transistor in multiple layers, wherein the semiconductor layer is in contact with the first electrode, the second electrode, and the protective layer; and the gate electrodes of the transistors in different layers are part of the word line;
  • Step 1506 etching and removing the semiconductor layer in a region of the through hole corresponding to the first insulating layer.
  • the manufacturing method of the semiconductor device provided in this embodiment protects the channel area by forming a sacrificial layer in the through hole and forming a protective layer covering the area corresponding to the sacrificial layer and the channel area, thereby facilitating the subsequent etching of the semiconductor layer between the layers, achieving the purpose of removing the parasitic transistor and improving the device performance and device stability.
  • the process before etching the conductive layer, the process further includes: etching from the top to the bottom of the stacked structure in a direction perpendicular to the substrate to expose the sidewalls of the conductive layer and the sidewalls of the first insulating layer;
  • the forming of a plurality of protection layers respectively corresponding to the plurality of transistors comprises:
  • a protective layer film is etched from the top to the bottom of the stacked structure in a direction perpendicular to the substrate to remove the protective layer film located on the side wall of the first insulating layer, thereby forming the protective layer covering the side wall of the conductive layer and the side wall of the sacrificial layer.
  • the method further includes: depositing a third insulating film to form a third insulating layer disposed on the sidewalls of the protection layer and the sidewalls of the first insulating layer;
  • the method further comprises:
  • the third insulating layer and the first insulating layer are etched to expose a sidewall of the protection layer and a sidewall of the semiconductor layer in a region of the through hole corresponding to the first insulating layer.

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Abstract

一种3D堆叠的半导体器件及其制造方法、电子设备，所述3D堆叠的半导体器件包括：多个晶体管，分布于不同层沿着垂直衬底方向堆叠；字线(40)，贯穿所述不同层的所述晶体管；与所述多个晶体管分别对应的多个保护层(82)；其中，晶体管包括环绕字线(40)侧壁的半导体层(23)，设置在字线(40)的侧壁和半导体层(23)之间的栅极绝缘层(24)；所述多个晶体管的多个半导体层(23)在所述字线(40)延伸的方向上间隔设置；每个所述保护层(82)分别环绕并覆盖对应的半导体层(23)的外侧壁，相邻两个保护层(82)之间断开。

Description

3D堆叠的半导体器件及其制造方法、电子设备
本申请要求于2023年1月30日提交中国专利局、申请号为2023101187601、发明名称为“一种3D堆叠的半导体器件及其制造方法、电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于半导体技术领域，尤指一种3D堆叠的半导体器件及其制造方法、电子设备。
背景技术
随着技术迭代的更新，动态随机存取存储器(Dynamic Random Access Memory，DRAM)想要获得更高的存储密度，三维(3D)DRAM是一个重要的发展方向。3D DRAM由于器件设计和工艺产生的寄生晶体管影响了DRAM工作时数据的正常写入和读取。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种3D堆叠的半导体器件，包括：
多个晶体管，分布于不同层沿着垂直衬底方向堆叠；
字线，贯穿所述不同层的所述晶体管；
与所述多个晶体管分别对应的多个保护层；
其中，所述晶体管包括环绕所述字线侧壁的半导体层，设置在所述字线的侧壁和所述半导体层之间的栅极绝缘层；
所述多个晶体管的多个半导体层在所述字线延伸的方向上间隔设置；
每个所述保护层分别环绕并覆盖对应的晶体管的半导体层的外侧壁，相邻两个保护层之间断开。
在一些实施例中，堆叠的所述多个晶体管还包括：
沿着垂直衬底的方向从下至上依次交替分布的绝缘层和导电层；
贯穿各所述绝缘层和各所述导电层的通孔，所述通孔中从内到外依次分布有所述字线、环绕所述字线侧壁的所述栅极绝缘层、环绕所述栅极绝缘层 的所述多个半导体层；环绕所述半导体层的所述保护层，所述保护层与所述半导体层接触；
其中，相邻两个所述半导体层之间露出所述栅极绝缘层，相邻两个所述半导体层之间填充有所述绝缘层且所述绝缘层与所述露出的栅极绝缘层接触；所述导电层包括相互独立的第一电极和第二电极，所述第一电极和所述第二电极其中之一为所述晶体管的源极，另一为所述晶体管的漏极。
在一些实施例中，所述通孔对应所述导电层的第一区域的口径等于所述通孔对应所述绝缘层的第二区域的口径；
所述导电层在所述通孔内仅露出侧壁，所述绝缘层在所述通孔内仅露出侧壁；
所述半导体层分布于所述导电层的侧壁。
在一些实施例中，所述多个保护层沿着垂直衬底的方向延伸且在所述绝缘层的上下两个表面断开。
在一些实施例中，所述保护层与对应的所述晶体管的半导体层接触，且所述保护层覆盖所述半导体层的侧壁中不与所述导电层接触的区域。
在一些实施例中，所述保护层还分布于所述导电层的侧壁且与所述导电层的侧壁接触。
在一些实施例中，所述保护层与所述绝缘层的材料不同。
在一些实施例中，所述多个晶体管还包括覆盖所述保护层的外侧壁的第五绝缘层。
本公开实施例提供一种电子设备，包括上述任一实施例所述的3D堆叠的半导体器件。
本公开实施例提供一种3D堆叠的半导体器件的制造方法，所述3D堆叠的半导体器件包括：多个晶体管，分布于不同层沿着垂直衬底方向堆叠；字线，贯穿所述不同层的所述晶体管；与所述多个晶体管分别对应的多个保护层；所述3D堆叠的半导体器件的制造方法包括：
提供衬底，在所述衬底上依次交替沉积第一绝缘薄膜和导电薄膜，进行构图形成堆叠结构，所述堆叠结构包括交替设置的第一绝缘层和导电层的堆叠，所述导电层包括预设电极图形，所述预设电极图形包含待形成的所述晶体管的第一电极和第二电极；
形成在垂直于所述衬底的方向上贯穿所述堆叠结构的通孔，所述通孔的侧壁露出每个所述导电层，在所述通孔内填充绝缘薄膜形成字线的牺牲层；刻蚀所述导电层，使得所述预设电极图形中的所述第一电极和第二电极断开，且，所述第一电极与所述牺牲层接触，所述第二电极与所述牺牲层接触；
形成与所述多个晶体管分别对应的多个保护层，所述多个保护层分别覆盖牺牲层和导电层的侧壁，相邻两个保护层之间断开；
去除所述牺牲层，在所述通孔的侧壁依次沉积半导体薄膜、栅绝缘薄膜，以及，沉积填充所述通孔的栅电极薄膜，以形成多层所述晶体管的半导体层、栅极绝缘层和所述字线，所述半导体层与所述第一电极、第二电极和所述保护层接触；不同层的所述晶体管的所述栅电极为所述字线的一部分；
刻蚀去除所述通孔内对应于所述第一绝缘层的区域内的所述半导体层。
在一些实施例中，所述刻蚀所述导电层之前还包括：沿垂直于衬底方向从所述堆叠结构的顶部至底部进行刻蚀，以暴露所述导电层的侧壁和所述第一绝缘层的侧壁；
所述形成与所述多个晶体管分别对应的多个保护层包括：
在所述导电层的侧壁、所述牺牲层的侧壁和所述第一绝缘层的侧壁沉积保护层薄膜，沿垂直于衬底方向从顶部至底部刻蚀所述保护层薄膜以去除位于所述第一绝缘层侧壁的保护层薄膜，形成覆盖所述导电层的侧壁、所述牺牲层的侧壁的所述保护层。
在一些实施例中，所述形成所述保护层之后，去除所述牺牲层之前，还包括：沉积第三绝缘薄膜，形成设置在所述保护层侧壁和所述第一绝缘层侧壁的第三绝缘层；
所述刻蚀去除所述通孔内对应于所述第一绝缘层的区域内的所述半导体层前还包括：
刻蚀所述第三绝缘层和第一绝缘层以暴露所述保护层的侧壁和所述通孔内对应于所述第一绝缘层的区域内的所述半导体层的侧壁。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和优点可通过在说明书以及附图中所特别指出的结构来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释技术方案，并不构成对技术方案的限制。
图1A为一示例性实施例提供的3D堆叠的半导体器件沿平行于衬底的C1方向的截面示意图；
图1B为图1A所示的3D堆叠的半导体器件沿垂直于衬底的C2方向的截面示意图；
图1C为图1A所示的3D堆叠的半导体器件沿垂直于衬底的C3方向的截面示意图；
图2A为一示例性实施例提供的3D堆叠的半导体器件形成导电薄膜和绝缘薄膜的堆叠结构后的立体示意图；
图2B为图2A所示的3D堆叠的半导体器件沿C1方向的截面示意图；
图2C为图2A所示的3D堆叠的半导体器件沿C2方向的截面示意图；
图2D为图2A所示的3D堆叠的半导体器件沿C3方向的截面示意图；
图3A为一示例性实施例提供的3D堆叠的半导体器件形成导电层后的立体示意图；
图3B为图3A所示的3D堆叠的半导体器件沿C1方向的截面示意图；
图3C为图3A所示的3D堆叠的半导体器件沿C2’方向的截面示意图；
图3D为图3A所示的3D堆叠的半导体器件沿C3方向的截面示意图；
图4A为一示例性实施例提供的3D堆叠的半导体器件形成电容后的立体示意图；
图4B为图4A所示的3D堆叠的半导体器件沿C1方向的截面示意图；
图4C为图4A所示的3D堆叠的半导体器件沿C2’方向的截面示意图；
图4D为图4A所示的3D堆叠的半导体器件沿C3方向的截面示意图；
图5A为一示例性实施例提供的3D堆叠的半导体器件形成牺牲层后的立体示意图；
图5B为图5A所示的3D堆叠的半导体器件沿C1方向的截面示意图；
图5C为图5A所示的3D堆叠的半导体器件沿C2方向的截面示意图；
图5D为图5A所示的3D堆叠的半导体器件沿C3方向的截面示意图；
图6A为一示例性实施例提供的3D堆叠的半导体器件刻蚀预设电极图形间的绝缘薄膜后的立体示意图；
图6B为图6A所示的3D堆叠的半导体器件沿C1方向的截面示意图；
图6C为图6A所示的3D堆叠的半导体器件沿C2方向的截面示意图；
图6D为图6A所示的3D堆叠的半导体器件沿C3方向的截面示意图；
图7A为一示例性实施例提供的3D堆叠的半导体器件形成第一电极和第二电极后的立体示意图；
图7B为图7A所示的3D堆叠的半导体器件沿C1方向的截面示意图；
图7C为图7A所示的3D堆叠的半导体器件沿C2方向的截面示意图；
图7D为图7A所示的3D堆叠的半导体器件沿C3方向的截面示意图；
图8A为一示例性实施例提供的3D堆叠的半导体器件形成保护层后的立体示意图；
图8B为图8A所示的3D堆叠的半导体器件沿C1方向的截面示意图；
图8C为图8A所示的3D堆叠的半导体器件沿C2方向的截面示意图；
图8D为图8A所示的3D堆叠的半导体器件沿C3方向的截面示意图；
图9A为一示例性实施例提供的3D堆叠的半导体器件去除牺牲层后的立体示意图；
图9B为图9A所示的3D堆叠的半导体器件沿C1方向的截面示意图；
图9C为图9A所示的3D堆叠的半导体器件沿C2方向的截面示意图；
图9D为图9A所示的3D堆叠的半导体器件沿C3方向的截面示意图；
图10A为一示例性实施例提供的3D堆叠的半导体器件形成半导体层和栅电极后的立体示意图；
图10B为图10A所示的3D堆叠的半导体器件沿C1方向的截面示意图；
图10C为图10A所示的3D堆叠的半导体器件沿C2方向的截面示意图；
图10D为图10A所示的3D堆叠的半导体器件沿C3方向的截面示意图；
图11A为一示例性实施例提供的3D堆叠的半导体器件暴露层间的半导体层后的立体示意图；
图11B为图11A所示的3D堆叠的半导体器件沿C1方向的截面示意图；
图11C为图11A所示的3D堆叠的半导体器件沿C2方向的截面示意图；
图11D为图11A所示的3D堆叠的半导体器件沿C3方向的截面示意图；
图12A为一示例性实施例提供的3D堆叠的半导体器件刻蚀层间的半导体层后的立体示意图；
图12B为图12A所示的3D堆叠的半导体器件沿C1方向的截面示意图；
图12C为图12A所示的3D堆叠的半导体器件沿C2方向的截面示意图；
图12D为图12A所示的3D堆叠的半导体器件沿C3方向的截面示意图；
图13A为一示例性实施例提供的3D堆叠的半导体器件形成第四绝缘层后的立体示意图；
图13B为图13A所示的3D堆叠的半导体器件沿C1方向的截面示意图；
图13C为图13A所示的3D堆叠的半导体器件沿C2方向的截面示意图；
图13D为图13A所示的3D堆叠的半导体器件沿C3方向的截面示意图；
图14为另一示例性实施例提供的预设电极图形示意图；
图15为一示例性实施例提供的3D堆叠的半导体器件的制造方法流程图。
具体实施方式
下文中将结合附图对本公开实施例进行详细说明。在不冲突的情况下，本公开实施例及实施例中的特征可以相互任意组合。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。
本公开的实施方式并不一定限定附图所示尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，并不表示任何顺序、数量或者重要性。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在公开中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，“平行”是指大约平行或几乎平行，比如，两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指大约垂直，比如，两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成。“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
本公开实施例中的“A和B为一体式结构”可以是指在微观结构上无明显的断层或间隙等明显的分界界面。一般地，在一个膜层上图案化形成连接的膜层为一体式。比如A和B使用相同的材料成一个膜层并通过同一次图案化工艺同时形成具有连接关系的结构。
本公开实施例中，通过刻蚀去除不同层存储单元层间的半导体层，可以消除相邻层之间相邻晶体管之间的寄生晶体管(简称寄生MOS)。
图1A为一示例性实施例提供的3D堆叠的半导体器件沿平行于衬底的C1方向的截面示意图；图1B为图1A所示3D堆叠的半导体器件沿垂直于衬底的C2方向的截面示意图，图1C为图1A所示3D堆叠的半导体器件沿垂直于衬底的C3方向的截面示意图。C2方向和C3方向垂直，如图1A、图1B和图1C所示，本实施例提供的3D堆叠的半导体器件可以包括：
多个晶体管，分布于不同层沿着垂直衬底1方向堆叠；
字线40，贯穿所述不同层的所述晶体管结构，所述字线40可以沿着垂直衬底1方向延伸；
与所述多个晶体管分别对应的多个保护层82；
其中，所述晶体管可以包括环绕所述字线40侧壁的半导体层23，设置在所述字线40的侧壁和所述半导体层23之间的栅极绝缘层24；
所述多个晶体管的多个半导体层23在所述字线40延伸的方向上间隔设置，即，所述多个半导体层23分布在所述字线40侧壁的不同区域；
每个所述保护层82分别环绕并覆盖对应的晶体管的半导体层23的外侧壁，相邻两个保护层82之间断开，即，所述多个晶体管分别对应的多个保护层82间隔设置。半导体层23的外侧壁为所述半导体层23远离所述栅电极26一侧的侧壁。
本实施例提供的3D堆叠的半导体器件，不同层的晶体管的半导体层间隔设置，可以消除寄生晶体管，另外，通过设置保护层，在制造3D堆叠的半导体器件时，可以避免暴露晶体管的半导体层，避免半导体层损坏，提高器件沟道材料的可靠性和稳定性。
一些实施例中，所述晶体管还可以包括栅电极26，所述栅电极26可以沿着垂直衬底1的方向延伸，每个所述晶体管的所述栅电极26为所述字线40的一部分。
一些实施例中，所述晶体管还可以包括第一电极51和第二电极52，所述第一电极51和所述第二电极52之间的沟道可以为水平沟道。水平沟道为沟道中载流子传输方向在平行于衬底的平面内，但是不限制载流子的传输方向必须是一个方向。实际应用中，载流子的传输方向整体上沿着一个方向延伸，但是在局部，与半导体层的形状有关。换句话说，水平沟道不代表在水 平面内必须沿着一个方向延伸，可能沿着不同的方向延伸，比如半导体层为环形时，环形半导体层上的源接触区和漏接触区为环形的一部分，此时，载流子从源接触区向漏接触区整体上沿着一个方向延伸，在局部可能不是一个方向。当然载流子传输方向在平行于衬底的平面内也是一个宏观上的概念，并不局限于绝对的平行于衬底，本申请保护第一电极和第二电极之间的沟道为非垂直于衬底的沟道。
一些实施例中，所述栅电极26可以仅沿垂直于所述衬底1的方向延伸。其中，该栅电极26包括侧表面和上下两端的端面，侧表面整体上与衬底垂直，或者说与半导体层23对应的起栅电极26控制作用的侧壁的部分区域，该区域的膜层与衬底1垂直。在实际制作产品过程中局部可能存在弯曲的区域也包含在本申请上述所述的情况中。
环绕所述栅电极26且与所述栅电极26相绝缘的半导体层23，其中的半导体层23可以理解为一个膜层，该膜层具有两个相对的主表面(称为半导体层23的两个侧壁)和两个端面。两个相对主表面为相比端面其表面积更大。比如，半导体层23沿着栅电极26的侧壁延伸，半导体层23的膜层厚度方向为平行衬底1的方向，膜层在栅电极26侧壁的上下延伸的长度为膜层的高度，环绕所述栅电极26的长度为膜层的宽度。
一些实施例中，所述半导体层23在所述栅电极26的侧壁上延伸形成沿着垂直于所述衬底1方向延伸的环形的半导体层。一些实施例中，所述半导体层23可以仅沿垂直于衬底1的方向延伸。另一些实施例中，所述半导体层23沿着栅电极26或字线40的侧壁延伸，半导体层23的形状与字线40或栅电极26的侧壁形状相适应。
其中，环绕可以理解为部分或全部环绕所述栅电极26或字线40。一些实施例中，所述环绕可以是整体上全部环绕，环绕后的半导体层23的横截面可以为闭合环形，且环形形状与栅电极26的横截面外轮廓形状相适应。示例性的，所述栅电极26的横截面比如为方形等结构。所述横截面的截取方向为沿着平行于衬底1的方向截取。一些实施例中，所述环绕可以是部分环绕，环绕后的横截面不是闭合的，但是呈现环形状。比如，半导体层23的横截面为具有开口的环形。
一些实施例中，沿着垂直所述衬底1的方向延伸的所述字线40不同区域的材料组分相同，可以理解为使用同一次膜层制作工艺形成，所述材料的组分相同可以理解为材料中测试出的主要元素相同，比如，都是通过金属或ITO等导电材料制作而成，但是不限制其不同区域的原子数比。
一些实施例中，不同层的晶体管可以共用一个沿着垂直所述衬底方向延伸的环状的栅极绝缘层24，即所述多个晶体管的栅极绝缘层24连接形成一体式结构。
一些实施例中，同一晶体管的所述第一电极51和第二电极52可以位于同一导电膜层。可以理解为第一电极51和第二电极52位于同一金属膜层，由一个导电膜层图案化形成，所述导电膜层与所述衬底1的上表面大约平行。第一电极51和第二电极52可以同层设置。即所述第一电极51和所述第二电极52可以通过同一次图案化工艺同时形成，但本公开实施例不限于此，可以通过不同图案化工艺分别制造所述第一电极51和所述第二电极52。
一些实施例中，所述间隔设置的所述半导体层23之间露出位于所述栅电极26和所述半导体层23之间的栅极绝缘层24。
一些实施例中，堆叠的所述多个晶体管还可以包括：
沿着垂直衬底1的方向从下至上(即从靠近衬底1至远离衬底1方向)依次交替分布的绝缘层16和导电层12；
贯穿每个所述绝缘层16和每个所述导电层12的通孔K1，所述通孔K1中从内到外依次分布有所述字线40、环绕所述字线40侧壁的所述栅极绝缘层24、环绕所述栅极绝缘层24的所述多个半导体层23，环绕所述半导体层23的所述保护层82，所述保护层82与所述半导体层23接触；
其中，相邻两个所述半导体层23之间露出所述栅极绝缘层24，相邻两个所述半导体层23之间填充有所述绝缘层16且所述绝缘层16与所述露出的栅极绝缘层24接触；
所述导电层12包括相互独立的第一电极51和第二电极52，所述第一电极51和所述第二电极52其中之一为所述晶体管的源极，另一为所述晶体管的漏极，每个所述半导体层23与对应层的所述导电层12的源极和漏极接触。
一些实施例中，所述通孔K1对应所述导电层12的第一区域的口径可以等于所述通孔K2对应所述绝缘层16的第二区域的口径；即，所述通孔K1沿平行于所述衬底1方向不同位置的截面的大小和形状可以相同，通孔K1可以通过一次刻蚀制造完成；
所述导电层12在所述通孔K1内仅露出侧壁，所述绝缘层16在所述通孔K1内仅露出侧壁；
所述半导体层23分布于所述导电层12的侧壁。本实施例中，半导体层23不延伸到所述导电层12的上下两个表面，其中，导电层12的上表面为远离衬底1的表面，导电层12的下表面为靠近衬底1的表面。
一些实施例中，所述多个保护层82可以沿着垂直衬底1的方向延伸且在所述绝缘层16的上下表面断开。绝缘层16可以包括位于朝向衬底1一侧的下表面和位于远离衬底1一侧的下表面，所述保护层82在所述绝缘层16的上下表面断开，即保护层82延伸到绝缘层16的上表面时断开，延伸到绝缘层16的下表面时断开，即，保护层82只分布在导电层12所在的膜层，在制 造3D堆叠的半导体器件时，保护层82在绝缘层16的上下表面断开，可以便于去除层间的半导体层。
一些实施例中，所述保护层82与对应的所述晶体管的半导体层23接触，且所述保护层82覆盖所述半导体层23的侧壁中不与所述导电层12接触的区域。如图1A所示，半导体层23的侧壁可以包括4个侧面，一个侧面与第一电极51接触，一个侧面与第二电极52接触，其余两个侧面与保护层82接触，被保护层82保护。
一些实施例中，所述保护层82还可以分布于所述导电层12的侧壁且与所述导电层12的侧壁接触。如图1A所示，所述保护层82与第一电极51的侧壁接触，与所述第二电极52的侧壁接触，保护层82可以对第一电极51和第二电极52进行保护，避免制造过程中损坏第一电极51和第二电极52。
一些实施例中，所述保护层82与所述绝缘层16的材料不同。在3D堆叠的半导体器件的制造过程中，导电层间通常填充有与绝缘层16材料相同的绝缘膜层，保护层82与绝缘层16的材料不同，便于在3D堆叠的半导体器件的制造过程中，实现对保护层82与绝缘膜层的分别刻蚀。
一些实施例中，所述多个晶体管的栅极绝缘层24可以连接形成一体式结构。但本公开实施例不限于此，一些实施例中，不同层晶体管的栅极绝缘层24在垂直于所述衬底1的方向上可以间隔设置。比如，多个晶体管的多个栅极绝缘层24可以在所述绝缘层16的侧壁断开。
一些实施例中，堆叠的所述多个晶体管还包括覆盖所述保护层82的外侧壁的第五绝缘层17。如图1B所示，所述保护层82远离所述半导体层23一侧的侧壁为外侧壁，所述保护层82的外侧壁覆盖有第五绝缘层17。
一些实施例中，沿垂直于衬底1方向相邻的晶体管的所述第一电极51在垂直衬底1的方向的投影重叠，所述第二电极52在垂直衬底1的方向的投影重叠，所述栅电极26在垂直衬底1的方向的投影重叠。本实施例提供的方案，在工艺过程中，可以通过导电层和绝缘层的相对堆叠再通过一个掩膜形成多层堆叠的第一电极和第二电极，实现工艺简单。另外，可以使得3D堆叠的半导体器件的结构更为紧凑。
一些实施例中，与所述多个晶体管对应的多个保护层82在垂直衬底1的方向的投影重叠。本实施例提供的方案，在工艺过程中，可以通过一次制造工艺形成多个保护层82，实现工艺简单。另外，可以使得3D堆叠的半导体器件的结构更为紧凑。
上述3D堆叠的半导体器件可以和电容器组成1T1C的存储结构，或者，和其他晶体管组成2T0C的存储结构，等等。
如图1A、图1B和图1C所示，本公开实施例提供一种3D存储器，包括：上述3D堆叠的半导体器件，还包括：数据存储元件。
一些实施例中，所述数据存储元件比如为电容，即形成1T1C的存储结构。但本公开实施例不限于此，可以和其他晶体管组成2T0C的存储结构，等等。一些实施例中，所述电容可以包括第一极板41和第二极板42，所述第一极板41与所述第一电极51连接。一些实施例中，所述第一极板41与所述第一电极51可以连接为一体式结构。一些实施例中，不同层的相同列的所述电容的所述第二极板42可以连接为一体式结构。如图1C所示，不同层的第一列的所述电容的所述第二极板42连接为一体式结构。不同层的第二列的所述电容的所述第二极板42连接为一体式结构，即，不同层的相同列的所述电容共用同一极板作为第二极板42。一些实施例中，所述电容还可以包括设置在所述第一极板41和第二极板42之间的第二绝缘层13。第二绝缘层13作为第一极板41和第二极板42之间的介质。
一些实施例中，不同层的相同列的所述电容的所述第二绝缘层13可以连接为一体式结构。如图1C所示，不同层的第一列的所述电容的所述第二绝缘层13连接为一体式结构。不同层的第二列的所述电容的所述第二绝缘层13连接为一体式结构，即，不同层的相同列的所述电容共用同一绝缘层作为极板间的介质。
一个晶体管和一个数据存储元件构成一个存储单元。一些实施例中，如图1B所示，同层的所述存储单元形成分别沿第一方向X和第二方向Y分布的阵列，每层所述存储单元还包括：位线30，所述位线30与同层同一列的晶体管的所述第二电极52连接。图1A中示出了每层包括三行两列存储单元，但本公开实施例不限于此，每层可以包括其他行数和列数的存储单元，比如，可以只包括一个存储单元。所述第一方向X可以平行于所述衬底，所述第二方向Y可以平行于所述衬底，第一方向X和第二方向Y交叉。在一些实施例中，所述第一方向X和第二方向Y可以垂直。
一些实施例中，相邻两列的存储单元的晶体管的第二电极52连接形成位线30。同层相邻两列的晶体管的所述第二电极52与所述位线30可以连接为一体式结构。
一些实施例中，所述位线30可以沿第二方向Y延伸。
一些实施例中，所述第一电极51可以沿第一方向X延伸。
在一示例性实施中，可以在形成导电层和绝缘层的堆叠结构后，刻蚀贯穿堆叠结构的通孔，在所述通孔内淀积牺牲层作为虚拟字线，形成保护层保护虚拟字线对应于沟道区域的区域，再去除牺牲层，在通孔内形成字线和半导体层，此时半导体层中晶体管的沟道区域被保护层保护，然后暴露出寄生晶体管的沟道并去除，达到去除寄生晶体管的效果。
下面通过本实施例3D堆叠的半导体器件的制造过程进一步说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、 掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制造工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，刻蚀可采用已知的方法，在此不做具体的限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺或光刻工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺或光刻工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺或光刻工艺后的“层”中包含至少一个“图案”。
一些实施例中，3D堆叠的半导体器件的制造过程可以包括：
1)在衬底1上依次交替沉积第一绝缘薄膜9和第一导电薄膜11形成叠层结构，如图2A、图2B、图2C、图2D所示，其中，图2A为3D堆叠的半导体器件的立体示意图，图2B为图2A所示3D堆叠的半导体器件沿C1方向的截面示意图，图2C为图2A所示3D堆叠的半导体器件沿C2方向的截面示意图，图2D为图2A所示3D堆叠的半导体器件沿C3方向的截面示意图。所述C1方向平行于所述衬底1，所述C2方向垂直于所述衬底1，所述C3方向垂直于所述衬底1，所述C2方向垂直于所述C3方向。
一些实施例中，所述衬底1可以为半导体衬底，比如可以是硅衬底。
一些实施例中，所述第一绝缘薄膜9可以是low-K介质层，即介电常数K<3.9的介质层，包括但不限于硅氧化物，比如二氧化硅(SiO2)等。
一些实施例中，所述第一导电薄膜11可以包括但不限于氮化钛(TiN)/钨(W)的多层结构。
图2A中示出的叠层结构包括5层第一绝缘薄膜9和4层第一导电薄膜11，仅为示例，在其他实施例中，所述叠层结构可以包括更多或更少层交替设置的第一绝缘薄膜9和第一导电薄膜11。图2A中示出的叠层结构还包括设置在顶部的硬掩膜，用于后续构图工艺，在构图后会去除。
2)对所述叠层结构进行构图形成包括交替堆叠的导电层12和第一绝缘层10的堆叠结构；如图3A、图3B、图3C、图3D所示，其中，图3A为3D堆叠的半导体器件的立体示意图，图3B为图3A所示3D堆叠的半导体器件沿C1方向的截面示意图，图3C为图3A所示3D堆叠的半导体器件沿C2’方向的截面示意图，图3D为图3A所示3D堆叠的半导体器件沿C3方向的截面示意图。所述C2’方向平行于所述C2方向。
所述对所述叠层结构进行构图形成包括导电层12和第一绝缘层10的堆叠结构可以包括：
利用干法刻蚀方法刻蚀所述叠层结构，构图形成所述导电层12后再在被刻蚀的区域填充第一绝缘薄膜，以隔离不同器件；所述导电层12包括预设电 极图形，所述预设电极图形包含待形成的位线和所述晶体管的第一电极、第二电极；如图3B所示。其中，图3B所示的预设电极图形仅为示例，所述预设电极图形可以是其他形状，比如预设电极图形可以为如图14所示的形状，本公开实施例对此不作限定。
对所述第一绝缘薄膜进行刻蚀(可以包括各向异性刻蚀和各向同性刻蚀)，去除位于电容区域100的第一绝缘薄膜，形成第一绝缘层10，此时，导电层12位于电容区域100的端面和部分侧壁暴露出来，暴露的区域可以作为电容的第一极板41。
图3A中器件的顶层为硬掩膜，在后续过程中会刻蚀掉。
3)形成第二绝缘层13和第二极板42；
所述形成第二绝缘层13和第二极板42可以包括：在所述电容区域100依次沉积第二绝缘薄膜和导体材料，分别形成第二绝缘层13和第二极板42，所述第二绝缘层13覆盖导电层12暴露出的区域，如图4A、图4B、图4C、图4D所示，其中，图4A为3D堆叠的半导体器件的立体示意图，图4B为图4A所示3D堆叠的半导体器件沿C1方向的截面示意图，图4C为图4A所示3D堆叠的半导体器件沿C2’方向的截面示意图，图4D为图4A所示3D堆叠的半导体器件沿C3方向的截面示意图。
其中，第二绝缘层13作为电容极板间的介质，第二极板42作为电容的一个电极。
一些实施例中，可以通过原子层沉积(Atomic Layer Deposition，ALD)方式沉积所述第二绝缘薄膜和导体材料。
一些实施例中，所述第二绝缘薄膜可以是High-K介质材料，即介电常数K≥3.9的介质材料。所述High-K介质材料可以包括但不限于以下至少之一：氧化硅，三氧化二铝(Al2O3)，氧化铪。
一些实施例中，所述导体材料包括但不限于以下至少之一：多晶硅，钨，氮化钛。
4)形成牺牲层81；
所述形成牺牲层81可以包括：通过干法刻蚀对所述堆叠结构进行刻蚀，形成贯穿所述多个堆叠结构的多个通孔K1，所述通孔K1的侧壁露出每个所述导电层12；所述通孔K1可以包括对应导电层12的区域和对应第一绝缘层10的区域，即通孔K1贯穿导电层12形成的区域为通孔K1对应导电层12的区域，通孔K1贯穿第一绝缘层10形成的区域为通孔K1对应第一绝缘层10的区域。
在所述多个通孔K1内沉积填充所述通孔K1的绝缘层薄膜，形成牺牲层 81，如图5A、图5B、图5C、图5D所示，其中，图5A为3D堆叠的半导体器件的立体示意图，图5B为图5A所示3D堆叠的半导体器件沿C1方向的截面示意图，图5C为图5A所示3D堆叠的半导体器件沿C2方向的截面示意图，图5D为图5A所示3D堆叠的半导体器件沿C3方向的截面示意图。
一些实施例中，所述通孔K1在平行于所述衬底1的平面上的正投影可以是方形等。
一些实施例中，所述通孔K1在平行于所述衬底1的平面上的正投影位于未形成通孔K1时所述导电层12的正投影内。
一些实施例中，所述绝缘层薄膜的材料不同于所述第一绝缘层10的材料，所述绝缘层薄膜比如为氮化硅(SiN)。
5)刻蚀填充在预设电极图形间的第一绝缘薄膜；
所述刻蚀填充在预设电极图形间的第一绝缘薄膜可以包括：沿垂直于衬底1方向从所述堆叠结构的顶部至底部刻蚀填充在预设电极图形间的第一绝缘薄膜，以暴露位于所述电容区域100外的导电层12的侧壁和第一绝缘层10的侧壁，如图6A、图6B、图6C、图6D所示，其中，图6A为3D堆叠的半导体器件的立体示意图，图6B为图6A所示3D堆叠的半导体器件沿C1方向的截面示意图，图6C为图6A所示3D堆叠的半导体器件沿C2方向的截面示意图，图6D为图6A所示3D堆叠的半导体器件沿C3方向的截面示意图。此时，位于电容区域100外的第一绝缘层10的图形与位于电容区域100外的导电层12的图形一致。
6)刻蚀所述导电层12，以暴露所述牺牲层81的部分侧壁，且使得所述预设电极图形形成至少一对彼此分离的第一电极51和第二电极52，所述第一电极51与所述牺牲层81接触，所述第二电极52与所述牺牲层81接触；如图7A、图7B、图7C、图7D所示，其中，图7A为3D堆叠的半导体器件的立体示意图，图7B为图7A所示3D堆叠的半导体器件沿C1方向的截面示意图，图7C为图7A所示3D堆叠的半导体器件沿C2方向的截面示意图，图7D为图7A所示3D堆叠的半导体器件沿C3方向的截面示意图。
所述第一电极51和第二电极52其中之一作为晶体管的源电极，另一作为晶体管的漏电极。
本步骤中，不刻蚀第一绝缘层10，即第一绝缘层10的图形保持不变，和未执行步骤6)时的导电层12的图形一致，即与图6B所示的导电层12的图形一致。
7)形成保护层82；
所述形成保护层82可以包括：在所述导电层12的侧壁、所述牺牲层81的侧壁(即步骤6中暴露出的牺牲层81的侧壁)和所述第一绝缘层10的侧 壁沉积保护层薄膜，各向异性刻蚀所述保护层薄膜，比如，沿垂直于衬底1方向从顶部至底部刻蚀所述保护层薄膜以去除位于所述第一绝缘层10侧壁的保护层薄膜，形成覆盖所述导电层12的侧壁，所述牺牲层81的侧壁的所述保护层82，所述保护层82填充步骤7)中对导电层12刻蚀的区域，即保护层82和导电层12二者共同形成的图形与导电层12未被刻蚀的图形一致，即与步骤5中的导电层12的图形一致，如图8A、图8B、图8C、图8D所示，其中，图8A为3D堆叠的半导体器件的立体示意图，图8B为图8A所示3D堆叠的半导体器件沿C1方向的截面示意图，图8C为图8A所示3D堆叠的半导体器件沿C2方向的截面示意图，图8D为图8A所示3D堆叠的半导体器件沿C3方向的截面示意图。
所述保护层82可以覆盖所述导电层12的侧壁，多个保护层82沿垂直于衬底1的方向延伸，多个保护层82沿垂直于衬底1的方向间隔设置，且在所述第一绝缘层10的侧壁断开。所述保护层82与牺牲层81的侧壁接触。所述保护层82可以包括第一部分和第二部分，所述第一部分设置在所述牺牲层81的第一侧，所述第二部分设置在所述牺牲层81的第二侧，所述第一侧和第二侧可以是相对的两侧。保护层82可以在后续刻蚀寄生晶体管的半导体层时保护作为晶体管的沟道区域的半导体层。
形成所述保护层82时，可以在导电层12和牺牲层81的侧壁上沉积保护层薄膜后对保护层薄膜进行刻蚀形成所述保护层82；或者，可以在衬底1上沉积保护层薄膜填充叠层结构中被刻蚀形成的空白区域后，再刻蚀所述保护层薄膜形成所述保护层82。
一些实施例中，所述保护层薄膜的材料与所述第一绝缘层10的材料不同，便于对保护层82和第一绝缘层10独立刻蚀。
一些实施例中，所述保护层薄膜可以和所述牺牲层薄膜材料一致，但不限于此。
一些实施例中，所述保护层薄膜可以包括但不限于SiN。
8)去除牺牲层81；
所述去除牺牲层81可以包括：
在形成前述图案的衬底上沉积第三绝缘薄膜；磨平所述第三绝缘薄膜，以形成第三绝缘层14，以及，暴露所述牺牲层81远离所述衬底1的表面；
通过各向异性刻蚀去除所述通孔K1中所述牺牲层81，比如，沿垂直于衬底的方向从所述通孔K1的顶部至底部进行刻蚀，去除所述牺牲层81，如图9A、图9B、图9C、图9D所示，其中，图9A为3D堆叠的半导体器件的立体示意图，图9B为图9A所示3D堆叠的半导体器件沿C1方向的截面示意图，图9C为图9A所示3D堆叠的半导体器件沿C2方向的截面示意图，图9D为图9A所示3D堆叠的半导体器件沿C3方向的截面示意图。
9)形成半导体层23、栅极绝缘层24和栅电极26；
所述形成半导体层23、栅极绝缘层24和栅电极26可以包括：在所述通孔K1的侧壁依次沉积半导体薄膜、栅绝缘薄膜，以及，沉积填充所述通孔K1的栅电极薄膜，依次形成半导体层23、栅极绝缘层24和栅电极26；如图10A、图10B、图10C、图10D所示，其中，图10A为3D堆叠的半导体器件的立体示意图，图10B为图10A所示3D堆叠的半导体器件沿C1方向的截面示意图，图10C为图10A所示3D堆叠的半导体器件沿C2方向的截面示意图，图10D为图10A所示3D堆叠的半导体器件沿C3方向的截面示意图。
一些实施例中，所述半导体薄膜包括但不限于以下至少之一：铟镓锌氧化物(InGaZnO)、氧化铟锌(InZnO)、氧化铟镓(InGaO)、氧化铟锡(InSnO)、氧化铟镓锡(InGaSnO)、氧化铟镓锌锡(InGaZnSnO)、氧化铟(InO)、氧化锡(SnO)、氧化锌锡(ZnSnO，ZTO)、氧化铟铝锌金(InAlZnO)、氧化锌(ZnO)、铟镓硅氧化物(InGaSiO)、氧化铟钨(InWO，IWO)、氧化钛(TiO)、氮氧化锌(ZnON)、氧化镁锌(MgZnO)、锆铟锌氧化物(ZrInZnO)、铪铟锌氧化物(HfInZnO)、锡铟锌氧化物(SnInZnO)、铝锡铟锌氧化物(AlSnInZnO)、硅铟锌氧化物(SiInZnO)、铝锌锡氧化物(AlZnSnO)、镓锌锡氧化物(GaZnSnO)、锆锌锡氧化物(ZrZnSnO)等材料，只要保证晶体管的漏电流能满足要求即可，具体可根据实际情况进行调整。
一些实施例中，所述栅绝缘薄膜可以是High-K介质材料，比如介电常数K≥3.9的介质材料。一些实施例中，可以包括铪、铝、镧、锆等一个或多个的氧化物。示例性的，比如，可以包括但不限于以下至少之一：氧化铪(HfO2)、氧化铝(Al2O3)，铪铝氧化物(HfAlO)，铪镧氧化物(HfLaO)、锆的氧化物(ZrO2)等高K材料。
一些实施例中，一些实施例中，栅极电极材料可以是如下不同类型材料中的一种或多种。
比如，含有钨、铝、钛、铜、镍、铂、钌、钼、金、铱、铑、钽、钴等金属；可以是含有前述提到的这些金属中的金属合金；还可以是金属氧化物、金属氮化物、金属硅化物、金属碳化物等，如掺锡的氧化铟ITO、掺铟的氧化锌IZO、铟的氧化物InO、掺铝氧化锌(Al-doped ZnO，AZO)、氧化铱(IrOx)、氧化钌(RuOx)等金属氧化物导电材料；比如，氮化钛(TiN)、氮化钽(TaN)、氮化钨(WN)、氮化钛铝(TiAlN)等金属氮化物材料。
10)刻蚀第一绝缘层10和第三绝缘层14以暴露所述通孔K1对应所述第一绝缘层10的区域内的半导体层23，以及，暴露所述保护层82的侧壁，如图11A、图11B、图11C、图11D所示，其中，图11A为3D堆叠的半导体器件的立体示意图，图11B为图11A所示3D堆叠的半导体器件沿C1方向的截面示意图，图11C为图11A所示3D堆叠的半导体器件沿C2方向的 截面示意图，图11D为图11A所示3D堆叠的半导体器件沿C3方向的截面示意图。其中，通孔K1对应所述导电层12的区域内的半导体层23未被暴露，该区域内的半导体层23的侧壁部分被导电层12覆盖，部分被保护层82覆盖，从而可以避免在后续步骤中被破坏。
所述刻蚀第一绝缘层10和第三绝缘层14可以包括：通过干法刻蚀去除所述第三绝缘层14，通过湿法刻蚀去除覆盖在所述半导体层23侧壁的所述第一绝缘层10。
11)刻蚀被暴露的半导体层23，即刻蚀所述通孔K1对应所述第一绝缘层10的区域内的半导体层23，如图12A至图12D所示，其中，图12A为3D堆叠的半导体器件的立体示意图，图12B为图12A所示3D堆叠的半导体器件沿C1方向的截面示意图，图12C为图12A所示3D堆叠的半导体器件沿C2方向的截面示意图，图12D为图12A所示3D堆叠的半导体器件沿C3方向的截面示意图。通过刻蚀所述通孔K1对应所述第一绝缘层10的区域内的半导体层23，可以去除寄生晶体管，提高器件性能。可以看到，半导体层23被刻蚀成间隔设置的多段，每段作为一个晶体管的半导体层。
12)形成第四绝缘层15；
所述形成第四绝缘层15可以包括：在形成前述图案的衬底上填充第四绝缘薄膜并磨平，形成所述第四绝缘层15，如图13A、图13B、图13C、图13D所示，其中，图13A为3D堆叠的半导体器件的立体示意图，图13B为图13A所示3D堆叠的半导体器件沿C1方向的截面示意图，图13C为图13A所示3D堆叠的半导体器件沿C2方向的截面示意图，图13D为图13A所示3D堆叠的半导体器件沿C3方向的截面示意图。第四绝缘层15可以包括两部分，一部分为位于相邻的导电层12间的绝缘层16，另一部分填充导电层12的电极间的区域，即第五绝缘层17。
本实施例提供的方案，形成通孔以后，形成牺牲层作为虚拟字线，将虚拟字线周边沟道区域的导电层去除，在沟道区域形成保护层(或称内侧墙，inner spacer)，再去除牺牲层形成半导体层和栅电极，然后暴露出寄生晶体管的沟道，此时器件的沟道被保护层保护，从而可以选择性去除寄生晶体管的沟道，最终达到去除寄生晶体管的目的，本实施例提供的本方案能够有效的消除寄生晶体管，且后期不需要暴露器件的沟道，避免了沟道暴露被破坏的风险，保证了器件沟道材料的可靠性和稳定性。另外，本实施例的制造方法利用现有成熟的制造设备即可实现，能够很好地与现有制造工艺兼容，因此工艺实现简单，易于实施，生产效率高，具有易于工艺实现、生产成本低和良品率高等优点。
本公开实施例还提供了一种电子设备，包括前述任一实施例所述的3D堆叠的半导体器件。所述电子设备可以为：存储装置、智能电话、计算机、 平板电脑、人工智能设备、可穿戴设备或移动电源等。存储装置可以包括计算机中的内存等，此处不作限定。
图15为本公开实施例提供的一种3D堆叠的半导体器件的制造方法流程图。如图15所示，本实施例提供一种3D堆叠的半导体器件的制造方法，所述3D堆叠的半导体器件可以包括：多个晶体管，分布于不同层沿着垂直衬底方向堆叠；字线，贯穿所述不同层的所述晶体管；与所述多个晶体管分别对应的多个保护层；所述3D堆叠的半导体器件的制造方法包括：
步骤1501，提供衬底，在所述衬底上依次交替沉积第一绝缘薄膜和导电薄膜，进行构图形成堆叠结构，所述堆叠结构包括交替设置的第一绝缘层和导电层的堆叠，所述导电层包括预设电极图形，所述预设电极图形包含待形成的所述晶体管的第一电极和第二电极；
步骤1502，形成在垂直于所述衬底的方向上贯穿所述堆叠结构的通孔，所述通孔的侧壁露出每个所述导电层在所述通孔内填充绝缘层薄膜形成字线的牺牲层；
步骤1503，刻蚀所述导电层，以暴露所述牺牲层的部分侧壁，使得所述预设电极图形中的所述第一电极和所述第二电极断开，且，所述第一电极与所述牺牲层接触，所述第二电极与所述牺牲层接触；
步骤1504，形成与所述多个晶体管分别对应的多个保护层，所述多个保护层分别覆盖牺牲层和导电层的侧壁，相邻两个保护层之间断开；
步骤1505，去除所述牺牲层，在所述通孔的侧壁依次沉积半导体薄膜、栅绝缘薄膜，以及，沉积填充所述通孔的栅电极薄膜，以形成多层所述晶体管的半导体层、栅极绝缘层和所述字线，所述半导体层与所述第一电极、第二电极和所述保护层接触；不同层的所述晶体管的所述栅电极为所述字线的一部分；
步骤1506，刻蚀去除所述通孔内对应于所述第一绝缘层的区域内的所述半导体层。
本实施例提供的半导体器件的制造方法，通过在通孔内形成牺牲层，以及，形成覆盖所述牺牲层与沟道区域对应的区域的保护层，实现对沟道区域的保护，便于后续刻蚀层间的半导体层，实现去除寄生晶体管的目的，提高器件性能和器件稳定性。
一些实施例中，所述刻蚀所述导电层之前还包括：沿垂直于衬底方向从所述堆叠结构的顶部至底部进行刻蚀，以暴露所述导电层的侧壁和所述第一绝缘层的侧壁；
所述形成与所述多个晶体管分别对应的多个保护层包括：
在所述导电层的侧壁、所述牺牲层的侧壁和所述第一绝缘层的侧壁沉积 保护层薄膜，沿垂直于衬底方向从所述堆叠结构的顶部至底部刻蚀所述保护层薄膜以去除位于所述第一绝缘层侧壁的保护层薄膜，形成覆盖所述导电层的侧壁、所述牺牲层的侧壁的所述保护层。
一些实施例中，所述形成所述保护层之后，去除所述牺牲层之前，还包括：沉积第三绝缘薄膜，形成设置在所述保护层侧壁和所述第一绝缘层侧壁的第三绝缘层；
所述刻蚀去除所述通孔内对应于所述第一绝缘层的区域内的所述半导体层前还包括：
刻蚀所述第三绝缘层和第一绝缘层以暴露所述保护层的侧壁和所述通孔内对应于所述第一绝缘层的区域内的所述半导体层的侧壁。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (12)

  1. 一种3D堆叠的半导体器件，包括：
    多个晶体管，分布于不同层沿着垂直衬底方向堆叠；
    字线，贯穿所述不同层的所述晶体管；
    与所述多个晶体管分别对应的多个保护层；
    其中，所述晶体管包括环绕所述字线侧壁的半导体层，设置在所述字线的侧壁和所述半导体层之间的栅极绝缘层；
    所述多个晶体管的多个半导体层在所述字线延伸的方向上间隔设置；
    每个所述保护层分别环绕并覆盖对应的半导体层的外侧壁，相邻两个保护层之间断开。
  2. 根据权利要求1所述的3D堆叠的半导体器件，其中，堆叠的所述多个晶体管包括：
    沿着垂直衬底的方向从下至上依次交替分布的绝缘层和导电层；
    贯穿各所述绝缘层和各所述导电层的通孔，所述通孔中从内到外依次分布有所述字线、环绕所述字线侧壁的所述栅极绝缘层、环绕所述栅极绝缘层的所述多个半导体层，环绕所述半导体层的所述保护层，所述保护层与所述半导体层接触；
    其中，相邻两个所述半导体层之间露出所述栅极绝缘层，相邻两个所述半导体层之间填充有所述绝缘层且所述绝缘层与所述露出的栅极绝缘层接触；
    所述导电层包括相互独立的第一电极和第二电极，所述第一电极和所述第二电极其中之一为所述晶体管的源极，另一为所述晶体管的漏极。
  3. 根据权利要求2所述的3D堆叠的半导体器件，其中，所述通孔对应所述导电层的第一区域的口径等于所述通孔对应所述绝缘层的第二区域的口径；
    所述导电层在所述通孔内仅露出侧壁，所述绝缘层在所述通孔内仅露出侧壁；
    所述半导体层分布于所述导电层的侧壁。
  4. 根据权利要求2所述的3D堆叠的半导体器件，其中，所述多个保护层沿着垂直衬底的方向延伸且在所述绝缘层的上下两个表面断开。
  5. 根据权利要求2所述的3D堆叠的半导体器件，其中，所述保护层与对应的所述晶体管的半导体层接触，且所述保护层覆盖所述半导体层的侧壁中不与所述导电层接触的区域。
  6. 根据权利要求2所述的3D堆叠的半导体器件，其中，所述保护层还 分布于所述导电层的侧壁且与所述导电层的侧壁接触。
  7. 根据权利要求2所述的3D堆叠的半导体器件，其中，所述保护层与所述绝缘层的材料不同。
  8. 根据权利要求2所述的3D堆叠的半导体器件，其中，堆叠的所述多个晶体管还包括覆盖所述保护层的外侧壁的第五绝缘层。
  9. 一种电子设备，包括如权利要求1至8任一所述的3D堆叠的半导体器件。
  10. 一种3D堆叠的半导体器件的制造方法，所述3D堆叠的半导体器件包括：多个晶体管，分布于不同层沿着垂直衬底方向堆叠；字线，贯穿所述不同层的所述晶体管；与所述多个晶体管分别对应的多个保护层；所述3D堆叠的半导体器件的制造方法包括：
    提供衬底，在所述衬底上依次交替沉积第一绝缘薄膜和导电薄膜，进行构图形成堆叠结构，所述堆叠结构包括交替设置的第一绝缘层和导电层的堆叠，所述导电层包括预设电极图形，所述预设电极图形包含待形成的所述晶体管的第一电极和第二电极；
    形成在垂直于所述衬底的方向上贯穿所述堆叠结构的通孔，所述通孔的侧壁露出每个所述导电层，在所述通孔内填充绝缘薄膜形成字线的牺牲层；
    刻蚀所述导电层，以暴露所述牺牲层的部分侧壁，使得所述预设电极图形中的所述第一电极和所述第二电极断开，且，所述第一电极与所述牺牲层接触，所述第二电极与所述牺牲层接触；
    形成与所述多个晶体管分别对应的多个保护层，所述多个保护层分别覆盖牺牲层和导电层的侧壁，相邻两个保护层之间断开；
    去除所述牺牲层，在所述通孔的侧壁依次沉积半导体薄膜、栅绝缘薄膜，以及，沉积填充所述通孔的栅电极薄膜，以形成多层所述晶体管的半导体层、栅极绝缘层和所述字线，所述半导体层与所述第一电极、第二电极和所述保护层接触；不同层的所述晶体管的所述栅电极为所述字线的一部分；
    刻蚀去除所述通孔内对应于所述第一绝缘层的区域内的所述半导体层。
  11. 根据权利要求10所述的3D堆叠的半导体器件的制造方法，其中，
    所述刻蚀所述导电层之前还包括：沿垂直于衬底方向从所述堆叠结构的顶部至底部进行刻蚀，以暴露所述导电层的侧壁和所述第一绝缘层的侧壁；
    所述形成与所述多个晶体管分别对应的多个保护层包括：
    在所述导电层的侧壁、所述牺牲层的侧壁和所述第一绝缘层的侧壁沉积保护层薄膜，沿垂直于衬底方向从顶部至底部刻蚀所述保护层薄膜以去除位于所述第一绝缘层侧壁的保护层薄膜，形成覆盖所述导电层的侧壁、所述牺 牲层的侧壁的所述保护层。
  12. 根据权利要求10所述的3D堆叠的半导体器件的制造方法，其中，
    所述形成所述保护层之后，去除所述牺牲层之前，还包括：沉积第三绝缘薄膜，形成设置在所述保护层侧壁和所述第一绝缘层侧壁的第三绝缘层；
    所述刻蚀去除所述通孔内对应于所述第一绝缘层的区域内的所述半导体层前还包括：
    刻蚀所述第三绝缘层和第一绝缘层以暴露所述保护层的侧壁和所述通孔内对应于所述第一绝缘层的区域内的所述半导体层的侧壁。
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CN115988875B (zh) * 2023-01-30 2023-09-05 北京超弦存储器研究院 一种3d堆叠的半导体器件及其制造方法、电子设备
CN118870825A (zh) * 2023-04-28 2024-10-29 北京超弦存储器研究院 三维堆叠存储器及其制造方法
CN118942494A (zh) * 2023-05-12 2024-11-12 北京超弦存储器研究院 存储器及其制备方法、电子设备
CN119012683B (zh) * 2023-05-15 2025-10-03 长鑫存储技术有限公司 半导体结构的制造方法及半导体结构
CN116709776B (zh) * 2023-08-08 2023-10-27 北京超弦存储器研究院 一种半导体器件及其制造方法、电子设备
US12238918B1 (en) 2023-08-10 2025-02-25 Beijing Superstring Academy Of Memory Technology Semiconductor device, manufacturing method therefor, and electronic device
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CN119835934B (zh) * 2023-10-12 2025-11-11 北京超弦存储器研究院 半导体器件结构及其制备方法
CN119922905B (zh) * 2023-10-31 2025-09-26 北京超弦存储器研究院 一种半导体器件及其制造方法、电子设备
CN119967803A (zh) * 2023-11-07 2025-05-09 北京超弦存储器研究院 半导体器件及其制造方法、电子设备
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112992902A (zh) * 2019-12-16 2021-06-18 三星电子株式会社 半导体存储器件及其制造方法
CN114975286A (zh) * 2022-05-24 2022-08-30 长鑫存储技术有限公司 半导体结构及其形成方法
CN115346988A (zh) * 2022-10-18 2022-11-15 北京超弦存储器研究院 一种晶体管、3d存储器及其制备方法、电子设备
CN115988875A (zh) * 2023-01-30 2023-04-18 北京超弦存储器研究院 一种3d堆叠的半导体器件及其制造方法、电子设备

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110102738A (ko) * 2010-03-11 2011-09-19 삼성전자주식회사 수직 채널 트랜지스터 및 그의 제조방법
CN104022121B (zh) * 2014-06-23 2017-05-03 中国科学院微电子研究所 三维半导体器件及其制造方法
CN113270405B (zh) * 2020-02-14 2024-08-02 长鑫存储技术有限公司 半导体器件及其制作方法
CN112466888B (zh) * 2020-11-18 2024-05-14 长江存储科技有限责任公司 半导体器件结构中多晶硅材料填充及3d nand存储器制备方法
CN115036290A (zh) * 2022-05-23 2022-09-09 长江存储科技有限责任公司 半导体器件及其制备方法和三维存储器系统

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112992902A (zh) * 2019-12-16 2021-06-18 三星电子株式会社 半导体存储器件及其制造方法
CN114975286A (zh) * 2022-05-24 2022-08-30 长鑫存储技术有限公司 半导体结构及其形成方法
CN115346988A (zh) * 2022-10-18 2022-11-15 北京超弦存储器研究院 一种晶体管、3d存储器及其制备方法、电子设备
CN115988875A (zh) * 2023-01-30 2023-04-18 北京超弦存储器研究院 一种3d堆叠的半导体器件及其制造方法、电子设备

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