WO2024159574A1 - 地址选择电路、地址选择方法、刷新控制电路和存储系统 - Google Patents

地址选择电路、地址选择方法、刷新控制电路和存储系统 Download PDF

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WO2024159574A1
WO2024159574A1 PCT/CN2023/079010 CN2023079010W WO2024159574A1 WO 2024159574 A1 WO2024159574 A1 WO 2024159574A1 CN 2023079010 W CN2023079010 W CN 2023079010W WO 2024159574 A1 WO2024159574 A1 WO 2024159574A1
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address
count value
row
output
value
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French (fr)
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刘勇
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Definitions

  • the present disclosure is based on Chinese patent application with application number 202310115031.0, application date February 2, 2023, and invention name “Address selection circuit, address selection method, refresh control circuit and storage system”, and claims the priority of the Chinese patent application.
  • the entire content of the Chinese patent application is hereby introduced into the present disclosure as a reference.
  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to an address selection circuit, an address selection method, a refresh control circuit and a storage system.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the charge in the memory cell can decay over time, so a refresh operation needs to be performed periodically, otherwise the stored data information will be lost.
  • the charge stored in the memory cell can be maintained by recharging. This recharging of the charge in the memory cell is called a refresh operation, and the refresh operation can be repeated before the charge is significantly lost to replenish the charge and avoid errors in the stored data.
  • the word line corresponding to a single row address in the memory cell is frequently turned on, it will cause the capacitors of the adjacent addresses to have unexpected charge interactions before the refresh operation arrives, causing data errors and data loss.
  • embodiments of the present disclosure provide an address selection circuit, an address selection method, a refresh control circuit, and a storage system.
  • an embodiment of the present disclosure provides an address selection circuit, comprising: a page table, each page table entry of the page table comprising a row address and a corresponding first count value; the first count value represents the number of accesses to the row address; a second count unit, configured to generate and output a second count value; the second count value serves as an index value corresponding to one of the page table entries; a comparison circuit, connected to the page table; the comparison circuit is used to output a maximum count value among multiple first count values through multiple comparison rounds; a row hammer address generation circuit, connecting the comparison circuit and the page table; the row hammer address generation circuit is used to output the row address corresponding to the maximum count value as a row hammer address after the last comparison round; a row hammer index generation circuit, connecting the comparison circuit and the second count unit; the row hammer index generation circuit is used to output the index value corresponding to the maximum count value as a row hammer index value after the last comparison round, and the row hammer index value is used
  • an embodiment of the present disclosure provides an address selection method, comprising: storing a plurality of row addresses in a page table, and counting the number of accesses to the row addresses to generate a corresponding first count value; each page table entry of the page table comprises a row address and a corresponding first count value; the first count value indicates the number of accesses to the row address; generating and outputting a second count value; The second count value is used as the index value corresponding to one of the page table entries; the maximum count value among the multiple first count values is output through multiple comparison rounds; after the last comparison round, the row address corresponding to the maximum count value is output as the row hammer address, and the index value corresponding to the maximum count value is output as the row hammer index value, and the row hammer index value is used to find the page table entry corresponding to the maximum count value.
  • an embodiment of the present disclosure provides a storage system, comprising: a memory, including a peripheral circuit and a storage cell array; wherein the peripheral circuit comprises the address selection circuit described in any one of the above embodiments; and a storage controller.
  • the comparison circuit outputs the maximum count value
  • the row hammer address generation circuit synchronously outputs the row hammer address corresponding to the maximum count value
  • the row hammer index generation circuit synchronously outputs the index value corresponding to the maximum count value as the row hammer index value.
  • FIG1 is a schematic diagram of an address selection circuit provided in an embodiment of the present disclosure.
  • FIG2 is a schematic diagram of another address selection circuit provided in an embodiment of the present disclosure.
  • FIG3 is a schematic diagram of another address selection circuit provided in an embodiment of the present disclosure.
  • FIG4 is a partial schematic diagram of another address selection circuit provided in an embodiment of the present disclosure.
  • FIG5 is a flowchart of a method for selecting an address provided by an embodiment of the present disclosure
  • FIG6 is a schematic diagram of a refresh control circuit provided in an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of a storage system provided by an embodiment of the present disclosure.
  • FIG8 is a partial schematic diagram of yet another address selection circuit provided in an embodiment of the present disclosure.
  • FIG. 9 is a working timing diagram of yet another address selection circuit provided in an embodiment of the present disclosure.
  • terms can be understood at least in part from their use in context.
  • the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense.
  • terms such as “one” or “the” can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context.
  • the term “based on” can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.
  • the capacitor size of the memory cell in the memory is small, so that the noise margin of the memory cell is small and it is easy to be interfered.
  • the memory cell is more susceptible to electromagnetic coupling and produces unexpected field effects.
  • the conventional refresh of the memory includes activation (Active, Act) and precharge (Precharge, Pre) operations.
  • activation activation
  • Precharge Precharge
  • a refresh window time when a word line (Word Line) in the memory is activated multiple times in succession, it may cause the capacitor of the adjacent address to flip data before the arrival of the conventional refresh signal, thereby generating erroneous storage. This phenomenon is generally called row hammer.
  • each word line corresponds to a row address
  • the row that is repeatedly accessed is called the aggressor row or the hammered row.
  • the address of the aggressor row is the row hammer address
  • the row adjacent to the aggressor row is called the victim row.
  • Row Hammer Refresh means refreshing the victim row after the memory has worked for a period of time to ensure that its data is correct.
  • the address of the victim row is the row hammer refresh address, and the number of accesses to the attacker row that causes data corruption is the row hammer threshold. It is worth noting that the row hammer attack behavior will cause data flipping in the victim row, including but not limited to flipping from "1" to "0" and from "0" to "1".
  • an embodiment of the present disclosure provides an address selection circuit 100, comprising: a page table 104, each page table entry of the page table 104 comprising a row address and a corresponding first count value; the first count value represents the number of accesses to the row address; a second counting unit 103, configured to generate and output a second count value; the second count value serves as an index value corresponding to one of the page table entries; a comparison circuit 110, connected to the page table 104; the comparison circuit is used to output a maximum count value among a plurality of the first count values through multiple comparison rounds; a row hammer address generation circuit 120, connected to the comparison circuit and the page table 104; the row hammer address generation circuit is used to output the row address corresponding to the maximum count value as a row hammer address after the last comparison round; a row hammer index generation circuit 130, connected to the comparison circuit and the second counting unit; the row hammer index generation circuit is used to output the index value corresponding to the
  • the address selection circuit 100 may have a page table 104, and the page table 104 may be located in the peripheral circuit area of the DRAM near the storage array area.
  • the page table 104 may store multiple row addresses, a first count value indicating the number of accesses to each row address, and the state of each page table entry, etc.
  • the page table 104 may include multiple address registers 101, and the address registers 101 are configured to store row addresses and output the row addresses stored in themselves.
  • Each row address here may physically correspond to a word line in the memory, and the row address for activation operation may enter the address register 101 by random sampling.
  • the random sampling method may be, for example: generating a pseudo-random number through a linear feedback shift register; or a random pulse generated by an oscillator, etc. It can be understood that each address register 101 here may be configured to store a row address.
  • the page table 104 may also include a plurality of first counting units 102, which may be connected to the plurality of address registers 101 in a one-to-one correspondence, and the first counting unit 102 may count the number of accesses to the row address stored in the corresponding address register 101, where the number of accesses may be the number of activation operations. Thus, each first counting unit 102 may generate a first count value corresponding to the number of accesses to a row address.
  • the first counting unit 102 may also be reset in response to an auto refresh (AR) command, thereby resetting the count value to 0.
  • the auto refresh here may set a refresh interval, thereby automatically performing a refresh operation on the storage unit according to the time of the refresh interval.
  • the second counting unit 103 can receive the pulse signal and count the pulse signal to generate a second count value, that is, the second count value can gradually increase as the number of pulses received by the second counting unit 103 increases.
  • the signal may be a clock signal provided by an oscillator (OSC), and the second counting unit may count the rising edge of the clock signal. It is worth noting that the second counting unit may count the rising edge of the pulse signal, may count the falling edge of the pulse signal, or may count both the rising edge and the falling edge of the pulse signal, without limitation here.
  • Each count of the second count value may be used as an index value corresponding to a first count value and a row address.
  • Table 1 shows a situation in which there are 9 page table entries in the page table, each page table entry includes an index value INDEX, a first count value CNT_VAL, a row address ADDR, and the state of the page table entry, that is, the page table includes 9 row addresses and corresponding 9 first count values, and the index value ranges from 1 to 9.
  • each index value here corresponds to a page table entry.
  • the OP state indicates that the page table entry is not occupied and does not store the row address; the LO state indicates that the page table entry is occupied and stores the row address.
  • the number of bits of the row address and the first count value is only for example.
  • the comparison circuit 110 is connected to the page table 104, and the comparison circuit 110 can compare the multiple first count values in pairs through multiple comparison rounds to determine the largest count value.
  • the comparison circuit 110 can compare the sizes of two of the first count values, where the two first count values compared here are respectively a larger first count value from the previous comparison round and another first count value that has not been compared. In this way, through multiple comparison rounds in a cycle, the comparison circuit 110 can output the maximum count value among the multiple first count values after the last comparison round. Since the multiple comparison rounds are performed in a cycle in sequence, each comparison round can be repeated through a comparator and a register, so that the comparison circuit 110 occupies a smaller area and has a faster processing speed.
  • the row hammer address generation circuit 120 is connected to the comparison circuit 110 and the page table 104. Specifically, in each comparison round, the row hammer address generation circuit 120 can select and store the row address corresponding to the larger first count value according to the comparison result of the two first count values in the comparison circuit 110. In this way, in each comparison round, the comparison circuit 110 and the row hammer address generation circuit 120 synchronously output the larger first count value and the corresponding row address. After the last comparison round, the comparison circuit 110 and the row hammer address generation circuit 120 can synchronously output the maximum count value and the corresponding row hammer address, where the row hammer address is the attacker row in the above embodiment.
  • the row hammer address generation circuit 120 synchronously outputs the row hammer address corresponding to the maximum count value, there is no need to set other circuits or units in the address selection circuit 100 to determine the row hammer address according to the maximum count value after the last comparison round, so the occupied area of the address selection circuit 100 is relatively small.
  • the address selection circuit 100 uses the row address with the largest number of accesses among the sampled multiple row addresses as the row hammer address, which can improve the accuracy of generating the row hammer address and reduce data errors caused by the row hammer effect.
  • the row hammer index generation circuit 130 is connected to the comparison circuit 110 and the second counting unit 103. Specifically, in each comparison round, the row hammer index generation circuit 130 can select and store the index value corresponding to the larger first count value according to the comparison result of the two first count values in the comparison circuit 110, where the index value is the count of the second count value corresponding to the larger first count value. In this way, in each comparison round, the comparison circuit 110, the row hammer address generation circuit 120 and the row hammer index generation circuit 130 synchronously output a larger first count value and the corresponding row address, as well as the corresponding index value.
  • the comparison circuit 110, the row hammer address generation circuit 120 and the row hammer index generation circuit 130 synchronously output the maximum count value, the row hammer address and the index value as the row hammer index value.
  • the page table entry corresponding to the row hammer address can be searched, so as to reset the first counting unit 102 and the address register unit 101 corresponding to the page table entry at a specific time, so as to dynamically update multiple row addresses, and further improve the accuracy of generating the row hammer address.
  • the comparison circuit can also be used to output the minimum count value among the multiple first count values.
  • the address selection circuit can implement a row hammer index value function, specifically including a maximum row hammer index value and a minimum row hammer index value.
  • the maximum row hammer index value is used to point to a page table entry corresponding to the maximum count value among the multiple first count values
  • the minimum row hammer index value is used to point to a page table entry corresponding to the minimum count value among the multiple first count values.
  • the address selection circuit 100 further includes: a control circuit 140 for resetting the row address stored in the corresponding address register unit 101 and the first count value generated by the corresponding first count unit 102 according to the row hammer index value.
  • the control circuit 140 can search the page table entry corresponding to the row hammer address through the row hammer index value, and control the corresponding address register unit 101 to replace the stored row address with another resampled row address. It can be understood that the row address stored in the corresponding address register unit 101 here is the row hammer address. In addition, the control circuit 140 can also reset the first count value generated by the corresponding first counting unit 102 to 0. It can be understood that the first count value generated by the corresponding first counting unit 102 here is the maximum count value. In this way, multiple row addresses and corresponding multiple first count values in the address selection circuit 100 can be dynamically updated, further improving the accuracy of generating the row hammer address.
  • the address selection circuit 100 further includes: a plurality of address register units 101, located in the page table 104; the plurality of address register units 101 are configured to output a plurality of parallel row addresses; a plurality of first counting units 102, located in the page table 104; the plurality of first counting units 102 are configured to output a plurality of parallel first counting values; a first conversion unit 151, the selection end of the first conversion unit 151 is connected to the second counting unit 103, the input end of the first conversion unit 151 is connected to the plurality of first counting units 102, and the output end of the first conversion unit 151 is connected to the comparison circuit 110; the first conversion unit 151 is configured to output a plurality of parallel first counting values based on the first counting unit 102; The second counting value is counted, and the multiple first counting values in parallel are outputted in sequence as the multiple first counting values in series, until the second counting value is equal to the preset value; the preset value is equal to the number of the
  • the plurality of first counting units 102 may output a plurality of first counting values in parallel, that is, the plurality of first counting values are outputted by the plurality of first counting units 102 in sequence without any particular order.
  • the address selection circuit 100 may further include a first conversion unit 151 for converting the plurality of first counting values in parallel into a plurality of first counting values in series.
  • the plurality of first counting values in series may be a plurality of first counting values sequentially transmitted according to the order of counting of the second counting value.
  • the first conversion unit 151 may be a data selector (Multiplexer, MUX), and the multi-channel parallel first counting values outputted by the plurality of first counting units 102 are converted into a channel of data arranged in the order of counting of the second counting value for output through the time-sharing selection of the first conversion unit 151, so as to perform round-by-round comparison in the comparison circuit 110 to output the maximum counting value therein.
  • Multiplexer MUX
  • MUX multi-channel parallel first counting values outputted by the plurality of first counting units 102 are converted into a channel of data arranged in the order of counting of the second counting value for output through the time-sharing selection of the first conversion unit 151, so as to perform round-by-round comparison in the comparison circuit 110 to output the maximum counting value therein.
  • the multiple address registers 101 can output multiple parallel row addresses, that is, the multiple row addresses are outputted by the multiple address registers 101 in sequence without any particular order.
  • the address selection circuit 100 may also include a second conversion unit 152 for converting the multiple parallel row addresses into multiple serial row addresses.
  • the multiple serial row addresses may be multiple row addresses transmitted sequentially according to the order of counting of the second count value.
  • the second conversion unit 152 may be a data selector, and the multiple parallel row addresses outputted by the multiple address registers 101 are converted into one data channel arranged in the order of counting of the second count value through the time-sharing selection of the second conversion unit 152. The output is performed, so that a selection is made in the row hammer address generating circuit 120 to synchronously output the row hammer address corresponding to the maximum count value.
  • the first conversion unit when the count of the second count value is 1, the first conversion unit outputs the corresponding first first count value, and the second conversion unit outputs the row address corresponding to the first first count value; when the count of the second count value is 2, the first conversion unit outputs the corresponding second first count value, and the second conversion unit outputs the row address corresponding to the second first count value...
  • the count of the second count value is n
  • the first conversion unit outputs the corresponding nth first count value
  • the second conversion unit outputs the row address corresponding to the nth first count value, where n is a positive integer.
  • the first conversion unit 151 and the second conversion unit 152 can end the conversion process, and the preset value here can be the total number of the first count values.
  • first count values and multiple row addresses are converted from parallel to serial through the first conversion unit 151 and the second conversion unit 152, so that the count of each second count value, that is, each index value, can correspond to a first count value and a row address.
  • a corresponding address storage unit 101 and a first counting unit 102 can be determined by the index value.
  • the comparison circuit 110 includes: a comparator 111, a first arbitration unit 112 and a first register unit 113; an input end of the comparator 111 is connected to an output end of the first register unit 113; an input end of the first arbitration unit 112 is connected to an output end of the first register unit 113 and an output end of the comparator 111; an input end of the first register unit 113 is connected to an output end of the first arbitration unit 112; the comparator 111 is used to compare the larger first count value in the previous comparison round outputted by the first register unit 113 with another first count value that has not been compared in each comparison round, and output a comparison result signal; the first arbitration unit 112 is configured to output the larger first count value between the first count value outputted by the first register unit 113 and another first count value that has not been compared to the first register unit 113 in each comparison round according to the comparison result signal; the first register unit 113 is configured to store the larger first count value outputted by the first arbitration unit 11
  • the first arbitration unit 112 may be a data selector, and the first register unit 113 may be a D flip-flop (Delay Flipflop, DFF) to store a larger first count value in the current comparison round and output a larger first count value in the previous comparison round.
  • the comparator 111 may compare a larger first count value in the previous comparison round with another first count value that has not been compared, and output a comparison result signal; and the first arbitration unit 112 selects a larger first count value to output according to the comparison result signal.
  • the comparison circuit can output the maximum count value among multiple first count values.
  • the comparison circuit may include only one comparator 111, one first arbitration unit 112 and one first register unit 113, and the above three are reused in multiple comparison rounds, the circuit occupies a smaller area and has a faster processing speed; in addition, the first register unit 113 only stores a larger first count value in each comparison round, that is, there is no need to process other useless intermediate process values, so the power consumption of the circuit is lower.
  • the first register unit 113 is a D flip-flop, and the D flip-flop can also update or maintain the first count value stored in itself according to the edge of the pulse signal.
  • the comparison circuit 110 also includes: a first output unit 114, connecting the first register unit 113 and the second counting unit 103; the first output unit 114 is configured to output the first count value stored in the first register unit 113 as the maximum count value when the second count value is greater than the preset value.
  • the first output unit 114 can output the first count value stored in the first register unit 113 as the maximum count value.
  • the second count value is greater than the preset value, indicating that the multiple first count values have been compared round by round, and the first output unit 114 can output the maximum count value, and the preset value here can be the total number of the first count values.
  • the first output unit 114 may be a data selector.
  • the first output unit 114 is also connected to a ground voltage VSS, where the ground voltage VSS enables the first output unit 114 to maintain the state when the second count value is not greater than a preset value. Keep outputting 0 until the last comparison round, then output the maximum count value.
  • the row hammer address generating circuit 120 includes: a second register unit 121, configured to store the row address corresponding to the larger first count value in each comparison round; a second arbitration unit 122, wherein the input end of the second arbitration unit 122 is connected to the output end of the second conversion unit 152 and the output end of the second register unit 121, and the selection end of the second arbitration unit 122 is connected to the output end of the comparator 111; the output end of the second arbitration unit 122 is connected to the input end of the second register unit 121; the second arbitration unit 122 is configured to select the row address corresponding to the larger first count value in each comparison round according to the comparison result signal, and output it to the second register unit 121.
  • the row hammer address generation circuit 120 may include a second register unit 121 and a second arbitration unit 122, wherein the second arbitration unit 122 may be a data selector, and the selection end of the second arbitration unit 122 is connected to the output end of the comparator 111 to receive the comparison result signal.
  • the second arbitration unit 122 may select a row address corresponding to a larger first count value from the row address corresponding to a larger first count value in the previous comparison round output by the second register unit 121 and a row address corresponding to a first count value that has not been compared output by the second conversion unit 152, and output it to the second register unit 121.
  • the first arbitration unit 112 and the second arbitration unit 122 may synchronously output a larger first count value and a corresponding row address, and the first register unit 113 and the second register unit 121 store them respectively. In this way, after the last comparison round, the first register unit 113 and the second register unit 121 store the maximum count value and the row address corresponding to the maximum count value, respectively.
  • the second register unit 121 is a D flip-flop, which can also update or maintain its own stored row address according to the edge of the pulse signal.
  • the second register unit 121 can also be configured to reset its own stored address before the first comparison round.
  • the row hammer address generating circuit 120 also includes: a second output unit 124, connecting the second register unit 121 and the second counting unit 103; the second output unit 124 is configured to output the row address stored in the second register unit 121 as the row hammer address when the second counting value is greater than the preset value.
  • the second output unit 124 can output the row address stored in the second register unit 121 as the row hammer address.
  • the second count value is greater than the preset value, indicating that multiple first count values have been compared round by round, and the second output unit 124 can output the row address corresponding to the maximum count value, where the preset value can be the total number of first count values. It can be understood that after the last comparison round, the first output unit 114 and the second output unit 124 can synchronously output the maximum count value and the row hammer address.
  • the second output unit 124 may be a data selector.
  • the second output unit 124 is also connected to a ground voltage VSS, where the ground voltage VSS enables the second output unit 124 to keep outputting an invalid address when the second count value is not greater than a preset value, and to output a row hammer address after the last comparison round.
  • the hammer index generating circuit 130 includes: a third register unit 131, configured to store the index value corresponding to the larger first count value in each comparison round; a third arbitration unit 132, the input end of the third arbitration unit 132 is connected to the output end of the second counting unit 103 and the output end of the third register unit 131, and the selection end of the third arbitration unit 132 is connected to the output end of the comparator 111; the output end of the third arbitration unit 132 is connected to the input end of the third register unit 131; the third arbitration unit 132 is configured to select the index value corresponding to the larger first count value in each comparison round according to the comparison result signal, and output it to the third register unit 131.
  • the hammer index generating circuit 130 may include a third register unit 131 and a third arbitration unit 132.
  • the third arbitration unit 132 may be a data selector, and the selection end of the third arbitration unit 132 is connected to the output end of the comparator 111 to receive the comparison result signal.
  • the third arbitration unit 132 may determine the comparison result signal. From the index value corresponding to the larger first count value in the previous comparison round output by the third register unit 131 and the index value corresponding to the first count value that has not been compared and output by the second counting unit 103 (i.e., the count of the current second count value), the index value corresponding to the larger first count value is selected and output to the third register unit 131.
  • the first arbitration unit 112 and the third arbitration unit 132 can synchronously output the larger first count value and the corresponding index value, and the first register unit 113 and the third register unit 131 respectively store them. In this way, after the last comparison round, the first register unit 113 and the third register unit 131 respectively store the maximum count value and the row hammer index value corresponding to the maximum count value.
  • the third register unit 131 is a D flip-flop, which can also update or maintain its own stored row address according to the edge of the pulse signal.
  • the third register unit 131 can also be configured to reset its own stored address before the first comparison round.
  • the first register unit 113 , the second register unit 121 , and the third register unit 131 may also reset the data stored in themselves to 0 before the first comparison round.
  • the row hammer index generating circuit 130 also includes: a third output unit 134, connecting the third register unit 131 and the second counting unit 103; the third output unit 134 is configured to output the index value stored in the third register unit 131 as the row hammer index value when the second counting value is greater than the preset value.
  • the third output unit 134 can output the index value stored in the third register unit 131 as the row hammer index value.
  • the second count value is greater than the preset value, indicating that multiple first count values have been compared round by round, and the third output unit 134 can output the row hammer index value corresponding to the maximum count value, where the preset value can be the total number of first count values. It can be understood that after the last comparison round, the first output unit 114 and the third output unit 134 can synchronously output the maximum count value and the row hammer index value.
  • the third output unit 134 may be a data selector.
  • the third output unit 134 is also connected to a ground voltage VSS, where the ground voltage VSS enables the third output unit 134 to keep outputting 0 when the second count value is not greater than a preset value, and to output the row hammer index value only after the last comparison round.
  • the address selection circuit 100 further includes: an oscillator connected to the second counting unit; the oscillator is used to provide a clock signal; the second counting unit is specifically configured to count pulses of the clock signal to generate and output the second count value.
  • the control circuit 140 further includes: a command decoding circuit 160, for generating and outputting an activation signal according to an external command issued by a storage controller; an address sampling circuit 170, connecting the command decoding circuit 160 and the page table; the address sampling circuit 170 is used to respond to the activation signal, sample the multiple row addresses corresponding to the activation signal and store them in the page table.
  • the command decoding circuit 160 can decode the external command sent by the memory controller (Memory Controller, MC), where the external command includes but is not limited to the refresh command (Refresh, REF), refresh management command (Refresh Management, RFM), automatic refresh command, activation command, etc.
  • the command decoding circuit 160 can generate and output an activation signal to activate multiple word lines corresponding to multiple row addresses.
  • the address sampling circuit 170 can respond to the above activation signal to randomly capture the row address corresponding to the activation signal and store the captured row address in the page table.
  • the address sampling circuit 170 in response to the automatic refresh command, can also resample multiple new row addresses to replace the original row addresses in the multiple address registers to ensure the dynamic update of the row address and improve the accuracy of generating the row hammer address.
  • the comparison circuit is further used to output a minimum count value based on a plurality of the first count values; the control circuit is further used to replace the row address stored in the address register unit corresponding to the minimum count value with a new row address.
  • the comparison circuit can also compare multiple first count values in pairs through multiple comparison rounds and output the minimum count value. In each comparison round, a smaller first count value in the previous comparison round is compared with another first count value that has not been compared, and the smaller first count value is output to the register unit.
  • the specific implementation method for obtaining the minimum count value is as follows: The formula refers to the above embodiment and will not be repeated here.
  • the control circuit can determine the address register unit where the row address corresponding to the minimum count value is located according to the index value corresponding to the minimum count value, and replace the row address stored in the address register unit corresponding to the minimum count value with the new row address to ensure the dynamic update of the row address and improve the accuracy of generating the row hammer address.
  • the control circuit can also connect multiple address register units to clear the row address stored in the address register unit corresponding to the minimum count value, and control the above address sampling circuit to output the new row address to the address register unit.
  • control circuit 140 further includes: an address operation circuit 180 for determining, according to the row hammer address, at least one row address adjacent to the row hammer address as a row hammer refresh address.
  • the control circuit 140 further includes an address operation circuit 180.
  • the address operation circuit 180 can use at least one row address adjacent to the row hammer address as a row hammer refresh address, where the row hammer refresh address is the victim row. In this way, performing a row hammer refresh operation on the word line corresponding to the victim row within a refresh window time can reduce data errors caused by the row hammer effect and improve the reliability of the memory operation.
  • a row address adjacent to the row hammer address can be selected as the row hammer refresh address for refresh to reduce power consumption; or multiple row addresses adjacent to the row hammer address can be selected for refresh to improve the accuracy of refreshing the victim row.
  • an embodiment of the present disclosure provides an address selection method, including:
  • Step S10 storing a plurality of row addresses in a page table, and counting the number of accesses to the row addresses to generate a corresponding first count value; each page table entry of the page table includes a row address and a corresponding first count value; the first count value indicates the number of accesses to the row address; generating and outputting a second count value; the second count value is used as an index value corresponding to the row address of one of the page table entries and the first count value;
  • Step S20 output the maximum count value among multiple first count values through multiple comparison rounds; after the last comparison round, output the row address corresponding to the maximum count value as the row hammer address, and output the index value corresponding to the maximum count value as the row hammer index value, and the row hammer index value is used to find the page table entry corresponding to the maximum count value.
  • a plurality of row addresses may be stored in a page table, and the number of accesses to each row address may be counted to generate a corresponding first count value.
  • Each row address may physically correspond to a word line in a memory.
  • the row address stored in the page table may be obtained from the row address for the activation operation by random sampling.
  • the number of accesses to each of the plurality of row addresses is counted respectively to generate a plurality of corresponding first count values, where the number of accesses may be the number of activation operations performed on the word line corresponding to the row address.
  • the plurality of first count values may also be reset to 0 in response to an automatic refresh command.
  • the automatic refresh may set a refresh interval, so that a refresh operation is automatically performed on the memory cell according to the refresh interval.
  • the pulse signal is counted to generate a second count value, that is, the second count value can gradually increase as the number of pulses received increases.
  • the pulse signal here can be a clock signal provided by an oscillator, and counting the rising edge of the clock signal can generate a second count value.
  • the falling edge of the pulse signal can also be counted here, and both the rising edge and the falling edge of the pulse signal can be counted, which is not limited in the embodiments of the present disclosure.
  • Each count of the second count value can be used as an index value corresponding to a first count value and a row address.
  • first count values are compared in pairs through multiple comparison rounds, and after the last comparison round, the maximum count value, the row hammer address corresponding to the maximum count value, and the index value corresponding to the maximum count value are synchronously output.
  • the maximum count value can be output after the last comparison round.
  • the row address and index value corresponding to the larger first count value can also be selected and stored according to the comparison result signal, so as to synchronously output the maximum count value, the row hammer address, and the index value as the row hammer index value after the last comparison round.
  • the row address with the most access times among the multiple sampled row addresses is used as the row hammer address, which can improve the accuracy of generating the row hammer address and reduce the data errors caused by the row hammer effect; in addition, the corresponding row address and the first count value can be reset by the row hammer index value to further improve the accuracy of generating the row hammer address.
  • the row address, the first count value, the row hammer address, and the index value corresponding to the larger first count value are output.
  • the comparison of the first count value and the second count value may be performed synchronously, so that in each comparison round, while comparing the sizes of the two first count values, a corresponding row address and an index value are selected according to the comparison result signal.
  • the method further includes: resetting the row address and the first count value in the corresponding page table entry according to the row hammer index value.
  • a corresponding stored row address can be replaced with another resampled row address according to the row hammer index value.
  • the corresponding stored row address here is the row hammer address.
  • a corresponding first count value can also be reset to 0 according to the row hammer index value. It can be understood that the corresponding first count value here is the maximum count value. In this way, multiple row addresses and corresponding multiple first count values can be dynamically updated to further improve the accuracy of generating the row hammer address.
  • the output of multiple first count values includes: the method also includes: outputting multiple parallel row addresses through the page table; outputting multiple parallel first count values through the page table; based on the counting of the second count value, outputting the multiple parallel first count values in sequence as multiple serial first count values until the second count value is equal to a preset value; the preset value is equal to the number of the first count values; based on the counting of the second count value, outputting the multiple parallel row addresses in sequence as multiple serial row addresses until the second count value is equal to the preset value.
  • the above method may further include: transmitting multiple first count values in sequence according to the order of counting of the second count value.
  • multiple first count values transmitted in parallel can be converted into one channel of data arranged in the order of counting of the second count value for output through time-sharing selection of a data selector, so as to perform round-by-round comparison in sequence to output the maximum count value therein.
  • the conversion of multiple row addresses from parallel transmission to serial transmission can be implemented by referring to the above method, which will not be described in detail here.
  • the corresponding first count value is output, and the row address corresponding to the first first count value is output synchronously; when the count of the second count value is 2, the corresponding second first count value is output, and the row address corresponding to the second first count value is output synchronously...
  • the count of the second count value is n
  • the corresponding nth first count value is output, and the row address corresponding to the nth first count value is output synchronously, where n is a positive integer.
  • the conversion process can be ended, and the preset value here can be the total number of the first count values.
  • outputting the maximum count value among multiple first count values through multiple comparison rounds includes: in each comparison round, comparing one of the first count values stored in the previous comparison round with another first count value that has not been compared, and outputting a comparison result signal; outputting a larger one of the first count values according to the comparison result signal; and storing the larger one of the first count values.
  • outputting the maximum count value among multiple first count values through multiple comparison rounds also includes: when the second count value is greater than the preset value, outputting one of the first count values stored in the last comparison round; wherein, one of the first count values stored in the last comparison round is the maximum count value.
  • outputting the row address corresponding to the maximum count value as a row hammer address includes: selecting and outputting the row address corresponding to the larger first count value from one of the row addresses stored in the previous comparison round and the row address corresponding to the other first count value that has not been compared, based on the comparison result signal; and storing the row address corresponding to the larger first count value in each comparison round.
  • a larger first count value and a corresponding row address can be synchronously output according to the comparison result signal and stored separately.
  • the maximum count value among the multiple first count values and the row hammer address corresponding to the maximum count value can be obtained.
  • outputting the row address corresponding to the maximum count value as a row hammer address also includes: when the second count value is greater than the preset value, outputting the row address corresponding to the larger first count value in the last round of the comparison as the row hammer address.
  • the maximum count value and the corresponding row hammer address can be output synchronously.
  • outputting the index value corresponding to the maximum count value as the row hammer index value includes: selecting and outputting the index value corresponding to the larger first count value from one of the index values stored in the previous comparison round and the index value corresponding to another first count value that has not been compared, based on the comparison result signal; and storing the index value corresponding to the larger first count value in each comparison round.
  • a larger first count value and a corresponding index value can be synchronously output and stored respectively.
  • the maximum count value among the multiple first count values and the index value corresponding to the maximum count value can be obtained, and the index value is used as the row hammer index value.
  • the outputting of the index value corresponding to the maximum count value as the row hammer index value also includes: when the second count value is greater than the preset value, outputting the index value corresponding to the larger first count value in the last round of the comparison as the row hammer index value.
  • the maximum count value and the corresponding index value may be output synchronously.
  • the method further includes: providing a clock signal; and generating and outputting the second count value includes: counting pulses of the clock signal to generate and output the second count value.
  • the method further includes: generating and outputting an activation signal according to an external command issued by a storage controller; storing multiple row addresses in a page table includes: in response to the activation signal, sampling the multiple row addresses corresponding to the activation signal and storing them in the page table.
  • the external commands issued by the host include, but are not limited to, refresh commands, refresh management commands, automatic refresh commands, activation commands, etc.
  • an activation signal can be generated and output to activate multiple word lines corresponding to multiple row addresses.
  • the row address corresponding to the activation signal can be randomly captured, and the captured multiple row addresses can be stored.
  • multiple new row addresses can also be resampled to replace the original row addresses.
  • multiple first count values may be compared to output a minimum count value.
  • the specific implementation of obtaining the minimum count value is referred to the above embodiment and will not be described here.
  • the row address corresponding to the minimum count value may be replaced with a new row address to ensure dynamic update of the row address and improve the accuracy of generating the row hammer address.
  • the method further includes: determining, according to the row hammer address, at least one row address adjacent to the row hammer address as a row hammer refresh address.
  • At a specific moment at least one row address adjacent to the row hammer address can be used as a row hammer refresh address, and the row address corresponding to the minimum count value can be replaced with a new row address.
  • the specific moment here can be the moment when the automatic refresh command sent by the host is received.
  • an embodiment of the present disclosure provides a refresh control circuit 200, including: the address selection circuit 100 described in any of the above embodiments; a refresh circuit 201, connected to the row hammer address generation circuit; the refresh circuit 201 is used to refresh at least one address line adjacent to the address line corresponding to the row hammer address.
  • the refresh control circuit 200 can be used to sample multiple row addresses, and determine that the row address with the most access times is the row hammer address, and then perform a refresh operation on at least one address line adjacent to the address line corresponding to the row hammer address to reduce data errors.
  • the refresh control circuit 200 includes an address selection circuit 100 and a refresh circuit 201.
  • the refresh circuit 201 can perform a refresh operation on at least one word line adjacent to the word line corresponding to the row hammer address according to the row hammer address output by the address selection circuit 100.
  • the refresh circuit 201 can be a row decoder (Row Decoder) circuit in a memory.
  • the address selection circuit 100 has an address operation circuit to determine the row hammer refresh address according to the row hammer address, so the refresh circuit 201 can directly refresh the word line corresponding to the row hammer refresh address.
  • an embodiment of the present disclosure provides a storage system 300, including: a memory 310, including a peripheral circuit 311 and a storage cell array 312; wherein the peripheral circuit 311 includes the address selection circuit 100 described in any of the above embodiments; and a storage controller 320.
  • the memory 310 may include, but is not limited to, DRAM, static random access memory (SRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.
  • the storage controller 320 may control the memory 310 to perform various operations according to the signal sent by the host. It is understandable that after the last round of comparison, the comparison circuit outputs the maximum count value, the row hammer address generation circuit synchronously outputs the row hammer address corresponding to the maximum count value, and the row hammer index generation circuit synchronously outputs the row hammer index value corresponding to the maximum count value.
  • the address register corresponding to the row hammer address and the first counting unit corresponding to the maximum count value can be determined according to the row hammer index value, which facilitates dynamic updating of the row addresses in multiple address registers and further improves the accuracy of generating row hammer addresses.
  • Some embodiments of the present disclosure further provide an address selection circuit 400, as shown in FIG8 , which is a partial schematic diagram of the address selection circuit 400.
  • the address selection circuit 400 may have a row hammer index value, which is used to point to the first counting unit and/or address register unit corresponding to the maximum count value before a certain automatic refresh command appears (the first counting unit and the address register unit are not shown in FIG8 ).
  • the address selection circuit 400 may also output a row hammer index value corresponding to the maximum count value, so that after the row hammer refresh is completed, the row hammer address stored in the corresponding address register unit is replaced with another resampled row address, and the maximum count value generated by the corresponding first counting unit is reset to 0.
  • the address selection circuit 400 may further include an oscillator OSC, a second counting unit 403, a first conversion unit 451, a comparator 411, a first arbitration unit 412, a first register unit 413, a first output unit 414, a second conversion unit 452, a second arbitration unit 422, a second register unit 421, a second output unit 424, a third arbitration unit 432, a third register unit 431, a third output unit 434, etc.
  • OSC oscillator OSC
  • second counting unit 403 a first conversion unit 451, a comparator 411, a first arbitration unit 412, a first register unit 413, a first output unit 414, a second conversion unit 452, a second arbitration unit 422, a second register unit 421, a second output unit 424, a third arbitration unit 432, a third register unit 431, a third output unit 434, etc.
  • the first conversion unit 451, the second conversion unit 452, the first arbitration unit 412, the second arbitration unit 422, the third arbitration unit 432, the first output unit 414, the second output unit 424 and the third output unit 434 may be data selectors
  • the first register unit 413, the second register unit 421 and the third register unit 431 may be D flip-flops.
  • the following describes the working process of the address selection circuit 400 by taking the row address with the most access times among the 9 row addresses as the row hammer address as an example.
  • the nine row addresses here are RA_DLUT1 ⁇ 15:0>, RA_DLUT2 ⁇ 15:0>, ... RA_DLUT9 ⁇ 15:0>, which are stored and output in parallel through nine address register units.
  • the 9 first counting units count the number of accesses to the row addresses stored in the 9 address registers to generate 9 first counting values CNT1 ⁇ 8:0>, CNT2 ⁇ 8:0>...CNT9 ⁇ 8:0> for parallel transmission.
  • the oscillator OSC generates a pulse signal CLK
  • the second counting unit 403 counts the rising edge of the pulse signal to generate a second counting value.
  • the first register unit 413, the second register unit 421, and the third register unit 431 can reset their own stored data to 0 before the first round of comparison.
  • the first conversion unit 451 converts the 9 first counting values for parallel transmission into serial transmission according to the count of the second counting value; the second conversion unit 452 converts the 9 row addresses for parallel transmission into serial transmission according to the count of the second counting value.
  • the second counting unit 403 when the second count value is equal to 1, the index value output by the second counting unit 403 is 1, that is, in the first comparison round, the first conversion unit 451 outputs the first first count value CNT1 ⁇ 8:0>, and the second conversion unit 452 outputs the corresponding first row address RA_DLUT1 ⁇ 15:0>;
  • the comparator 411 compares the first first count value CNT1 ⁇ 8:0> with 0 stored in the first register unit 413, and outputs a comparison result signal CNT_SEL;
  • the first arbitration unit 412 selects the first first count value CNT1 ⁇ 8:0> according to the comparison result signal CNT_SEL and outputs it to the first register unit 413;
  • the second arbitration unit 422 selects the first row address RA_DLUT1 ⁇ 15:0> according to the comparison result signal CNT_SEL and outputs it to the second register unit 421;
  • the third arbitration unit 432 selects the index value 1 according to the comparison result signal CNT_SEL and outputs it
  • the index value output by the second counting unit 403 is 2, that is, in the second comparison round, the first conversion unit 451 outputs the second first count value CNT2 ⁇ 8:0>, and the second conversion unit 452 outputs the corresponding second row address RA_DLUT2 ⁇ 15:0>; the comparator 411 compares the second first count value CNT2 ⁇ 8:0> with the first row address stored in the first register unit 413.
  • the first count values CNT1 ⁇ 8:0> are compared and a comparison result signal CNT_SEL is output; the first arbitration unit 412 selects a larger first count value CNT12 ⁇ 8:0> according to the comparison result signal CNT_SEL and outputs it to the first register unit 413; the second arbitration unit 422 selects a row address RA_DLUT12 ⁇ 15:0> corresponding to the larger first count value CNT12 ⁇ 8:0> according to the comparison result signal CNT_SEL and outputs it to the second register unit 421; the third arbitration unit 432 selects an index value INDEX12 ⁇ 3:0> corresponding to the larger first count value according to the comparison result signal CNT_SEL and outputs it to the third register unit 431.
  • the second conversion unit 451 outputs the 9th first count value CNT9 ⁇ 8:0>
  • the second conversion unit 452 outputs the corresponding 9th row address RA_DLUT9 ⁇ 15:0>
  • the comparator 411 compares the 9th first count value CNT9 ⁇ 8:0> with the larger first count value CNT18 ⁇ 8:0> in the 8th comparison round stored in the first register unit 413, and outputs the comparison result signal CNT_SE L
  • the first arbitration unit 412 selects a larger first count value CNT19 ⁇ 8:0> according to the comparison result signal CNT_SEL and outputs it to the first register unit 413
  • the second arbitration unit 422 selects a row address RA_DLUT19 ⁇ 15:0> corresponding to the larger first count value CNT19 ⁇ 8:0> according to the comparison result signal CNT_SEL and outputs it to the second register unit 421;
  • the first output unit 414 When the second count value is equal to 10, the first output unit 414 outputs the first count value CNT19 ⁇ 8:0> stored in the first register unit 413 as the maximum count value, the second output unit 424 synchronously outputs the row address RA_DLUT19 ⁇ 15:0> stored in the second register unit 421 as the row hammer address, and the third output unit 434 synchronously outputs the index value INDEX19 ⁇ 3:0> stored in the third register unit 431 as the row hammer index value. It can be understood that when the second count value is less than 10, the first output unit 451, the second output unit 452 and the third output unit 434 keep outputting 0.
  • the address selection circuit 400 uses a time-division multiplexing method to compare multiple first count values in pairs, wherein the comparison circuit, the row hammer address generation circuit, and the row hammer index generation circuit can be reused in multiple comparison rounds, and can synchronously output the maximum count value, the corresponding row hammer address, and the corresponding row hammer index value.
  • the address selection circuit 400 only needs a comparator that occupies an area of 49 standard cells (STD Cell), and the other parts are a small number of D flip-flops or latches, so compared with outputting the maximum count value through a combinational logic circuit, the address selection circuit 400 occupies a relatively small area.
  • each comparison round of the address selection circuit 400 only takes 2ns, that is, the address selection circuit 400 can complete the comparison of 9 first count values within 18ns to output the maximum count value therein.
  • the first register unit 411, the second register unit 421 and the third register unit 431 are D flip-flops, only the larger first count value, the corresponding row address and the corresponding index value in each comparison round are stored, that is, there is no need to process other useless intermediate process data, so the power consumption of the circuit is low. It can be understood that the more the number of row addresses, that is, the more the number of first count values that need to be counted and compared, the more prominent the above advantages of the address selection circuit 400 are.
  • the address selection circuit 400 may also be used to find the minimum count value among multiple first count values, which can be achieved by only storing a smaller first count value and the corresponding row address and index value in each comparison round.
  • the refresh operation on the row address adjacent to the row hammer address can also be completed within the refresh cycle time (Time for Refresh Cycle, tRFC), and the address register unit corresponding to the row hammer address and the first counting unit corresponding to the maximum count value can be cleared to wait for the next address to be refreshed that is resampled.
  • tRFC Time for Refresh Cycle
  • the comparison circuit outputs the maximum count value.
  • the row hammer address generation circuit synchronously outputs the row hammer address corresponding to the maximum count value
  • the row hammer index generation circuit synchronously outputs the index value corresponding to the maximum count value as the row hammer index value.

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Abstract

公开了一种地址选择电路、地址选择方法、刷新控制电路和存储系统，地址选择电路包括：页表，每一页表项包括一个行地址和一个表示行地址访问次数的第一计数值；第二计数单元，配置为生成第二计数值；第二计数值作为对应一个页表项的索引值；比较电路，用于通过多轮比较回合输出多个第一计数值中的最大计数值；行锤地址产生电路，用于输出最大计数值对应的行地址以作为行锤地址；行锤索引产生电路，用于输出最大计数值对应的索引值以作为行锤索引值，行锤索引值用于查找最大计数值对应的页表项。

Description

地址选择电路、地址选择方法、刷新控制电路和存储系统
相关申请的交叉引用
本公开基于申请号为202310115031.0、申请日为2023年02月02日、发明名称为“地址选择电路、地址选择方法、刷新控制电路和存储系统”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种地址选择电路、地址选择方法、刷新控制电路和存储系统。
背景技术
随着当今科学技术的不断发展，半导体存储装置的密度不断增加。高数据可靠性、高存取速度以及更小的芯片尺寸成为了半导体存储器发展的重要趋势。然而，存储器单元之间的电磁相互作用对存储器单元的影响增大，使得存储器单元数据丢失的可能性增加。
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是一种易失性存储器，其通过存储单元电容器中积累的电荷作为物理信号来存储信息。而存储单元中的电荷可随着时间的推移衰减，因此需要周期性地实行刷新操作，否则存储的数据信息将会丢失。在数据由于电荷的泄漏而丢失之前，可以通过再充电来维持在存储单元中存储的电荷。存储单元中电荷的这种再充电被称为刷新操作，并且在电荷显著丢失之前可以重复执行刷新操作，以重新补充电荷，避免存储数据发生错误。然而，当存储器单元中某一单行地址对应的字线被频繁开启时，会导致相邻地址的电容器在刷新操作到来之前发生不期望的电荷交互，造成数据错误和数据丢失。
发明内容
有鉴于此，本公开实施例提供了一种地址选择电路、地址选择方法、刷新控制电路和存储系统。
第一方面，本公开实施例提供了一种地址选择电路，包括：页表，所述页表的每一页表项包括一个行地址和对应的一个第一计数值；所述第一计数值表示所述行地址的访问次数；第二计数单元，配置为生成并输出第二计数值；所述第二计数值作为对应于一个所述页表项的索引值；比较电路，连接所述页表；所述比较电路用于通过多轮比较回合输出多个所述第一计数值中的最大计数值；行锤地址产生电路，连接所述比较电路和所述页表；所述行锤地址产生电路用于在最后一轮所述比较回合后，输出所述最大计数值对应的所述行地址以作为行锤地址；行锤索引产生电路，连接所述比较电路和所述第二计数单元；所述行锤索引产生电路用于在最后一轮所述比较回合后，输出所述最大计数值对应的所述索引值以作为行锤索引值，所述行锤索引值用于查找所述最大计数值对应的所述页表项。
第二方面，本公开实施例提供了一种地址选择方法，包括：在页表中存储多个行地址，并对所述行地址的访问次数进行计数以生成对应的第一计数值；所述页表的每一页表项包括一个行地址和对应的一个第一计数值；所述第一计数值表示所述行地址的访问次数；生成并输出第二计数值；所 述第二计数值作为对应于一个所述页表项的索引值；通过多轮比较回合输出多个所述第一计数值中的最大计数值；在最后一轮所述比较回合后，输出所述最大计数值对应的所述行地址以作为行锤地址，并输出所述最大计数值对应的所述索引值以作为行锤索引值，所述行锤索引值用于查找所述最大计数值对应的所述页表项。
第三方面，本公开实施例提供了一种存储系统，包括：存储器，包括外围电路和存储单元阵列；其中，所述外围电路包括上述实施例中任一所述的地址选择电路；存储控制器。
在本公开实施例提供的地址选择电路中，在最后一轮比较回合后，比较电路输出最大计数值，行锤地址产生电路同步地输出最大计数值对应的行锤地址，行锤索引产生电路同步地输出最大计数值对应的索引值以作为行锤索引值。如此，一方面，将访问次数最多的行地址作为行锤地址，可以减少行锤效应带来的数据错误；另一方面，可以通过行锤索引值，查找最大计数值对应的页表项，便于动态更新多个页表项中的行地址，进一步地提高生成行锤地址的准确性。
附图说明
图1为本公开实施例提供的一种地址选择电路的示意图；
图2为本公开实施例提供的另一种地址选择电路的示意图；
图3为本公开实施例提供的又一种地址选择电路的示意图；
图4为本公开实施例提供的又一种地址选择电路的局部示意图；
图5为本公开实施例提供的一种地址选择方法的步骤流程图；
图6为本公开实施例提供的一种刷新控制电路的示意图；
图7为本公开实施例提供的一种存储系统的示意图；
图8为本公开实施例提供的再一种地址选择电路的局部示意图；
图9为本公开实施例提供的再一种地址选择电路的工作时序图。
具体实施方式
为了便于理解本公开，下面将参照相关附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在一些实施例中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即这里可以不描述实际实施例的全部特征，不详细描述公知的功能和结构。
一般地，术语可以至少部分地从上下文中的使用来理解。例如，至少部分地取决于上下文，如本文中所用的术语“一个或多个”可以用于以单数意义描述任何特征、结构或特性，或者可以用于以复数意义描述特征、结构或特性的组合。类似地，诸如“一”或“所述”的术语同样可以被理解为传达单数用法或传达复数用法，这至少部分地取决于上下文。另外，属于“基于”可以被理解为不一定旨在传达排他的一组因素，并且可以替代地允许存在不一定明确地描述的附加因素，这同样至少部分地取决于上下文。
除非另有定义，本文所使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、 步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
在一些实施例中，存储器中存储单元的电容尺寸较小，使得存储单元的噪声裕度较小，容易受到干扰。此外，由于相邻存储单元之间的距离较小，存储单元更容易受到电磁耦合的影响而产生意想不到的场效应。具体地，存储器的常规刷新包括激活(Active，Act)和预充电(Precharge，Pre)操作。在一个刷新窗口时间内，当存储器中的某一根字线(Word Line)连续进行多次的激活操作时，可能会导致相邻地址的电容器在常规刷新信号到来之前发生数据翻转，进而产生错误的存储，这种现象一般称为行锤(Row Hammer)。其中，每条字线对应一个行地址，被重复进行存取访问的行被称为攻击者行(Aggressor Row)或者锤击行(Hammered Row)，攻击者行的地址即行锤地址，而与攻击者行相邻近的行则被称为受害者行(Victim Row)。行锤刷新(Row Hammer Refresh)即在存储器工作一段时间后，对受害者行进行刷新，保证其数据正确，其中，受害者行的地址即行锤刷新地址，而造成数据损坏的攻击者行的访问次数即行锤阈值。值得注意的是，行锤攻击行为会导致受害者行发生数据翻转，包括但不限于从“1”翻转到“0”，以及从“0”翻转到“1”。
第一方面，如图1所示，本公开实施例提供了一种地址选择电路100，包括：页表104，所述页表104的每一页表项包括一个行地址和对应的一个第一计数值；所述第一计数值表示所述行地址的访问次数；第二计数单元103，配置为生成并输出第二计数值；所述第二计数值作为对应于一个所述页表项的索引值；比较电路110，连接所述页表104；所述比较电路用于通过多轮比较回合输出多个所述第一计数值中的最大计数值；行锤地址产生电路120，连接所述比较电路和所述页表104；所述行锤地址产生电路用于在最后一轮所述比较回合后，输出所述最大计数值对应的所述行地址以作为行锤地址；行锤索引产生电路130，连接所述比较电路和所述第二计数单元；所述行锤索引产生电路用于在最后一轮所述比较回合后，输出所述最大计数值对应的所述索引值以作为行锤索引值，所述行锤索引值用于查找所述最大计数值对应的所述页表项。
应当理解的是，图中为了使得各个电路和单元均能被清晰示出，可能造成各电路和单元的尺寸比例、位置关系与实际结构不符。
在本公开实施例中，地址选择电路100中可以具有页表104，页表104可以位于DRAM的外围电路区域中靠近存储阵列区域的位置。页表104中可以存储多个行地址、表示每个行地址的访问次数的第一计数值，以及每个页表项的状态等。页表104可以包括多个地址寄存单元101，地址寄存单元101配置为存储行地址，以及输出自身存储的行地址。这里的每个行地址在物理上可以对应于存储器中的一条字线，进行激活操作的行地址可以通过随机采样的方式进入到地址寄存单元101中。随机采样方式例如可以为：通过线性反馈移位寄存器产生伪随机数；或者振荡器产生的随机脉冲的方式等方式。可以理解的是，这里每个地址寄存单元101可以配置为存储一个行地址。
页表104中还可以包括多个第一计数单元102，多个第一计数单元102可以与多个地址寄存单元101一一对应连接，第一计数单元102可以对相应地址寄存单元101中存储的行地址的访问次数进行计数，这里的访问次数可以是进行激活操作的次数。如此，每个第一计数单元102可以生成一个行地址的访问次数对应的第一计数值。在一些实施例中，第一计数单元102还可以响应于自动刷新(Auto Refresh，AR)命令复位，从而将计数值重置为0。这里的自动刷新可以设置刷新间隔，从而按照刷新间隔的时间自动对存储单元执行刷新操作。
第二计数单元103可以接收脉冲信号，并对脉冲信号计数以生成第二计数值，也就是说，第二计数值可以随着第二计数单元103接收到的脉冲数目的增加而逐渐增大。示例性地，这里的脉冲信 号可以为振荡器(Oscillator，OSC)提供的时钟信号，而第二计数单元则可以对时钟信号的上升沿进行计数。值得注意的是，第二计数单元可以对脉冲信号的上升沿进行计数，也可以对脉冲信号的下降沿进行计数，还可以对脉冲信号的上升沿和下降沿均进行计数，这里不做限制。第二计数值的每个计数可以作为对应于一个第一计数值和一个行地址的索引值，示例性地，表1示出了页表中具有9个页表项的情况，每个页表项包括索引值INDEX、第一计数值CNT_VAL、行地址ADDR和页表项的状态，即页表中包括9个行地址和对应的9个第一计数值，索引值的取值为1至9，可以理解的是，这里的每个索引值对应于一个页表项。如此，利用索引值作为行锤索引值，可以查找对应的一个页表项中存储的行地址和第一计数值，以便于对特定的第一计数单元102和地址寄存单元101进行操作。而状态OP表示该页表项未被占用，未存储行地址；状态LO表示该页表项被占用，存储了行地址。行地址和第一计数值的位数仅作示例。
表1
比较电路110连接页表104，比较电路110可以通过多轮比较回合对多个第一计数值进行两两比较，以确定其中最大的计数值。示例性地，在每轮比较回合中，比较电路110可以比较其中两个第一计数值的大小，这里进行比较的两个第一计数值分别为，来自于上一轮比较回合中较大的一个第一计数值，以及另一个未经比较的第一计数值。如此，通过循环的多轮比较回合，比较电路110可以在最后一轮比较回合后，输出多个第一计数值中的最大计数值。由于多轮比较回合是依次循环进行的，故可以通过一个比较器和一个寄存器重复进行每轮比较回合，如此比较电路110的占用面积较小，处理速度较快。
行锤地址产生电路120连接比较电路110和页表104。具体地，在每轮比较回合中，行锤地址产生电路120可以根据比较电路110中两个第一计数值的比较结果，选择并存储较大的一个第一计数值对应的行地址。如此，在每轮比较回合中，比较电路110和行锤地址产生电路120同步地输出较大的一个第一计数值和对应的行地址。而在最后一轮比较回合后，比较电路110和行锤地址产生电路120可以同步地输出最大计数值和对应的行锤地址，这里的行锤地址即上述实施例中的攻击者行。可以理解的是，由于行锤地址产生电路120同步地输出最大计数值对应的行锤地址，地址选择电路100中无需再设置其他电路或者单元，以在最后一轮比较回合后，再根据最大计数值，确定行锤地址，故地址选择电路100的占用面积相对较小。另外，地址选择电路100将采样到的多个行地址中访问次数最多的行地址作为行锤地址，可以提高生成行锤地址的准确性，以减少行锤效应带来的数据错误。
行锤索引产生电路130连接比较电路110和第二计数单元103。具体地，在每轮比较回合中，行锤索引产生电路130可以根据比较电路110中两个第一计数值的比较结果，选择并存储较大的一个第一计数值对应的索引值，这里的索引值即对应于较大的一个第一计数值的第二计数值的计数。 如此，在每轮比较回合中，比较电路110、行锤地址产生电路120和行锤索引产生电路130同步地输出较大的一个第一计数值和对应的行地址，以及对应的索引值。而在最后一轮比较回合后，比较电路110、行锤地址产生电路120和行锤索引产生电路130同步地输出最大计数值、行锤地址和作为行锤索引值的索引值。由此，通过行锤索引值，可以查找行锤地址对应的页表项，从而在特定的时刻重置该页表项对应的第一计数单元102和地址寄存单元101，以动态更新多个行地址，进一步地提高生成行锤地址的准确性。
在一些实施例中，比较电路还可以用于输出多个第一计数值中的最小计数值。而地址选择电路可以实现行锤索引值功能，具体包括最大行锤索引值和最小行锤索引值。其中，最大行锤索引值用于指向多个第一计数值中最大计数值对应的页表项，最小行锤索引值则用于指向多个第一计数值中最小计数值对应的页表项。
在一些实施例中，如图2所示，所述地址选择电路100还包括：控制电路140，用于根据所述行锤索引值，重置对应的所述地址寄存单元101中存储的所述行地址，和对应的所述第一计数单元102生成的所述第一计数值。
在本公开实施例中，在对行锤地址相邻的受害者行进行刷新操作之后，控制电路140可以通过行锤索引值查找行锤地址对应的页表项，并控制对应的地址寄存单元101将存储的行地址替换为另一个重新采样到的行地址，可以理解的是，这里对应的地址寄存单元101中存储的行地址即为行锤地址。另外，控制电路140还可以将对应的第一计数单元102生成的第一计数值重置为0，可以理解的是，这里对应的第一计数单元102生成的第一计数值即为最大计数值。如此，可以动态更新地址选择电路100中的多个行地址以及对应的多个第一计数值，进一步地提高生成行锤地址的准确性。
在一些实施例中，如图3所示，所述地址选择电路100还包括：多个地址寄存单元101，位于所述页表104中；多个所述地址寄存单元101配置为输出并行的多个所述行地址；多个第一计数单元102，位于所述页表104中；多个所述第一计数单元102配置为输出并行的多个所述第一计数值；第一转换单元151，所述第一转换单元151的选择端连接所述第二计数单元103，所述第一转换单元151的输入端连接多个所述第一计数单元102，所述第一转换单元的151输出端连接所述比较电路110；所述第一转换单元151配置为基于所述第二计数值的计数，将并行的多个所述第一计数值，依次输出为串行的多个所述第一计数值，直至所述第二计数值等于预设值；所述预设值与所述第一计数值的个数相等；第二转换单元152，所述第二转换单元152的选择端连接所述第二计数单元103，所述第二转换单元152的输入端连接多个所述地址寄存单元101，所述第二转换单元152的输出端连接所述行锤地址产生电路120；所述第二转换单元152配置为基于所述第二计数值的计数，将并行的多个所述行地址，依次输出为串行的多个所述行地址，直至所述第二计数值等于所述预设值。
在本公开实施例中，多个第一计数单元102可以输出并行的多个第一计数值，即多个第一计数值不分先后顺序地由多个第一计数单元102输出。地址选择电路100还可以包括用于将并行的多个第一计数值转换为串行的多个第一计数值的第一转换单元151。这里串行的多个第一计数值可以为根据第二计数值的计数的顺序依次传输的多个第一计数值。示例性地，第一转换单元151可以为数据选择器(Multiplexer，MUX)，多个第一计数单元102输出的多路并列的第一计数值通过第一转换单元151的分时选择，转换为按第二计数值的计数的顺序排列的一路数据进行输出，从而在比较电路110中进行逐轮比较，以输出其中的最大计数值。
多个地址寄存单元101可以输出并行的多个行地址，即多个行地址不分先后顺序地由多个地址寄存单元101输出。地址选择电路100还可以包括用于将并行的多个行地址转换为串行的多个行地址的第二转换单元152。这里串行的多个行地址可以为根据第二计数值的计数的顺序依次传输的多个行地址。示例性地，第二转换单元152可以为数据选择器，多个地址寄存单元101输出的多路并列的行地址通过第二转换单元152的分时选择，转换为按第二计数值的计数的顺序排列的一路数据 进行输出，从而在行锤地址产生电路120中进行选择，以同步输出最大计数值对应的行锤地址。
示例性地，在第二计数值的计数为1的情况下，第一转换单元输出对应的第一个第一计数值，第二转换单元输出第一个第一计数值对应的行地址；在第二计数值的计数为2的情况下，第一转换单元输出对应的第二个第一计数值，第二转换单元输出第二个第一计数值对应的行地址……在第二计数值的计数为n的情况下，第一转换单元输出对应的第n个第一计数值，第二转换单元输出第n个第一计数值对应的行地址，这里的n为正整数。此外，在第二计数值等于预设值的情况下，第一转换单元151和第二转换单元152可以结束转换过程，这里的预设值可以为第一计数值的总数量。
可以理解的是，通过第一转换单元151和第二转换单元152将多个第一计数值和多个行地址由并行转换为串行，使得每个第二计数值的计数，即每个索引值，可以对应于一个第一计数值和一个行地址，如此，通过索引值即可确定对应的一个地址寄存单元101和一个第一计数单元102。
在一些实施例中，如图3所示，所述比较电路110包括：比较器111、第一仲裁单元112和第一寄存单元113；所述比较器111的输入端连接所述第一寄存单元113的输出端；所述第一仲裁单元112的输入端连接所述第一寄存单元113的输出端和所述比较器111的输出端；所述第一寄存单元113的输入端连接所述第一仲裁单元112的输出端；所述比较器111用于在每轮所述比较回合中，比较所述第一寄存单元113输出的上一轮比较回合中较大的一个所述第一计数值，和另一个未经比较的所述第一计数值的大小，并输出比较结果信号；所述第一仲裁单元112配置为在每轮所述比较回合中，根据所述比较结果信号，将所述第一寄存单元113输出的一个所述第一计数值和另一个未经比较的所述第一计数值中较大的一个所述第一计数值输出至所述第一寄存单元113；所述第一寄存单元113配置为存储每轮所述比较回合中所述第一仲裁单元112输出的较大的一个所述第一计数值。
在本公开实施例中，示例性地，第一仲裁单元112可以为数据选择器，第一寄存单元113可以为D触发器(Delay Flipflop，DFF)，以存储当前比较回合中较大的一个第一计数值，并输出上一轮比较回合中较大的一个第一计数值。在一轮比较回合中，比较器111可以将上一轮比较回合中较大的一个第一计数值，与另一个未经比较的第一计数值进行比较，并输出比较结果信号；而第一仲裁单元112则根据比较结果信号，选择其中较大的一个第一计数值进行输出。可以理解的是，上述上一轮比较回合中较大的一个第一计数值，即本轮比较回合中第一寄存单元113输出的第一计数值，上述另一个未经比较的第一计数值，即本轮比较回合中第一转换单元151输出的第一计数值。如此，通过循环的多轮比较回合，比较电路可以输出多个第一计数值中的最大计数值。由于比较电路中可以只包括一个比较器111、一个第一仲裁单元112和一个第一寄存单元113，且上述三者在多轮比较回合中都是重复使用的，故电路的占用面积较小，处理速度较快；另外，第一寄存单元113仅存储每轮比较回合中较大的一个第一计数值，即不需要处理其他无用的中间过程数值，故电路的功耗较低。
在一些实施例中，第一寄存单元113为D触发器，D触发器还可以根据上述脉冲信号的边沿，更新或保持自身存储的第一计数值。
在一些实施例中，如图3所示，所述比较电路110还包括：第一输出单元114，连接所述第一寄存单元113和所述第二计数单元103；所述第一输出单元114配置为在所述第二计数值大于所述预设值的情况下，输出所述第一寄存单元113存储的所述第一计数值，以作为所述最大计数值。
在本公开实施例中，由于第一寄存单元113可以存储每轮比较回合中较大的一个第一计数值，故在最后一轮比较回合后，第一输出单元114可以输出第一寄存单元113中存储的第一计数值以作为最大计数值。也就是说，第二计数值大于预设值，标志着多个第一计数值已逐轮完成比较，第一输出单元114可以输出最大计数值，这里的预设值可以为第一计数值的总数量。
在一些实施例中，第一输出单元114可以为数据选择器。第一输出单元114还连接至接地电压VSS，这里的接地电压VSS可以使得第一输出单元114在第二计数值还未大于预设值的情况下，保 持输出0，直至最后一轮比较回合后，才输出最大计数值。
在一些实施例中，如图3所示，所述行锤地址产生电路120包括：第二寄存单元121，配置为存储每轮所述比较回合中，较大的一个所述第一计数值对应的所述行地址；第二仲裁单元122，所述第二仲裁单元122的输入端连接所述第二转换单元152的输出端和所述第二寄存单元121的输出端，所述第二仲裁单元122的选择端连接所述比较器111的输出端；所述第二仲裁单元122的输出端连接所述第二寄存单元121的输入端；所述第二仲裁单元122配置为根据所述比较结果信号，选择每轮所述比较回合中较大的一个所述第一计数值对应的所述行地址，并输出至所述第二寄存单元121。
在本公开实施例中，行锤地址产生电路120可以包括一个第二寄存单元121和一个第二仲裁单元122，这里的第二仲裁单元122可以为数据选择器，且第二仲裁单元122的选择端连接比较器111的输出端，以接收比较结果信号。在一轮比较回合中，第二仲裁单元122可以根据比较结果信号，从第二寄存单元121输出的上一轮比较回合中较大一个第一计数值对应的行地址，和第二转换单元152输出的一个未经比较的第一计数值对应的行地址中，选择出较大的一个第一计数值对应的行地址，并输出至第二寄存单元121。也就是说，在一轮比较回合中，根据比较结果信号，第一仲裁单元112和第二仲裁单元122可以同步地输出较大的一个第一计数值和对应的行地址，并由第一寄存单元113和第二寄存单元121分别存储。如此，在最后一轮比较回合后，第一寄存单元113和第二寄存单元121分别存储着最大计数值和最大计数值对应的行地址。
在一些实施例中，第二寄存单元121为D触发器，D触发器还可以根据上述脉冲信号的边沿，更新或保持自身存储的行地址。第二寄存单元121还可以配置为在第一轮比较回合之前，重置自身存储的地址。
在一些实施例中，如图3所示，所述行锤地址产生电路120还包括：第二输出单元124，连接所述第二寄存单元121和所述第二计数单元103；所述第二输出单元124配置为在所述第二计数值大于所述预设值的情况下，输出所述第二寄存单元121存储的所述行地址，以作为所述行锤地址。
在本公开实施例中，由于第二寄存单元121可以存储每轮比较回合中较大的一个第一计数值对应的行地址，故在最后一轮比较回合后，第二输出单元124可以输出第二寄存单元121中存储的行地址以作为行锤地址。也就是说，第二计数值大于预设值，标志着多个第一计数值已逐轮完成比较，第二输出单元124可以输出最大计数值对应的行地址，这里的预设值可以为第一计数值的总数量。可以理解的是，在最后一轮比较回合后，第一输出单元114和第二输出单元124可以同步地输出最大计数值和行锤地址。
在一些实施例中，第二输出单元124可以为数据选择器。第二输出单元124还连接至接地电压VSS，这里的接地电压VSS可以使得第二输出单元124在第二计数值还未大于预设值的情况下，保持输出无效地址，直至最后一轮比较回合后，才输出行锤地址。
在一些实施例中，如图3所示，所述行锤索引产生电路130包括：第三寄存单元131，配置为存储每轮所述比较回合中，较大的一个所述第一计数值对应的所述索引值；第三仲裁单元132，所述第三仲裁单元132的输入端连接所述第二计数单元103的输出端和所述第三寄存单元131的输出端，所述第三仲裁单元132的选择端连接所述比较器111的输出端；所述第三仲裁单元132的输出端连接所述第三寄存单元131的输入端；所述第三仲裁单元132配置为根据所述比较结果信号，选择每轮所述比较回合中较大的一个所述第一计数值对应的所述索引值，并输出至所述第三寄存单元131。
在本公开实施例中，行锤索引产生电路130可以包括一个第三寄存单元131和一个第三仲裁单元132，这里的第三仲裁单元132可以为数据选择器，且第三仲裁单元132的选择端连接比较器111的输出端，以接收比较结果信号。在一轮比较回合中，第三仲裁单元132可以根据比较结果信号， 从第三寄存单元131输出的上一轮比较回合中较大一个第一计数值对应的索引值，和第二计数单元103输出的未经比较的一个第一计数值对应的索引值中(即当前第二计数值的计数)，选择出较大的一个第一计数值对应的索引值，并输出至第三寄存单元131。也就是说，在一轮比较回合中，根据比较结果信号，第一仲裁单元112和第三仲裁单元132可以同步地输出较大的一个第一计数值和对应的索引值，并由第一寄存单元113和第三寄存单元131分别存储。如此，在最后一轮比较回合后，第一寄存单元113和第三寄存单元131分别存储着最大计数值和最大计数值对应的行锤索引值。
在一些实施例中，第三寄存单元131为D触发器，D触发器还可以根据上述脉冲信号的边沿，更新或保持自身存储的行地址。第三寄存单元131还可以配置为在第一轮比较回合之前，重置自身存储的地址。
在一些实施例中，第一寄存单元113、第二寄存单元121和第三寄存单元131还可以在第一轮比较回合前，将自身存储的数据重置为0。
在一些实施例中，如图3所示，所述行锤索引产生电路130还包括：第三输出单元134，连接所述第三寄存单元131和所述第二计数单元103；所述第三输出单元134配置为在所述第二计数值大于所述预设值的情况下，输出所述第三寄存单元131存储的所述索引值，以作为所述行锤索引值。
在本公开实施例中，由于第三寄存单元131可以存储每轮比较回合中较大的一个第一计数值对应的索引值，故在最后一轮比较回合后，第三输出单元134可以输出第三寄存单元131中存储的索引值以作为行锤索引值。也就是说，第二计数值大于预设值，标志着多个第一计数值已逐轮完成比较，第三输出单元134可以输出最大计数值对应的行锤索引值，这里的预设值可以为第一计数值的总数量。可以理解的是，在最后一轮比较回合后，第一输出单元114和第三输出单元134可以同步地输出最大计数值和行锤索引值。
在一些实施例中，第三输出单元134可以为数据选择器。第三输出单元134还连接至接地电压VSS，这里的接地电压VSS可以使得第三输出单元134在第二计数值还未大于预设值的情况下，保持输出0，直至最后一轮比较回合后，才输出行锤索引值。
在一些实施例中，所述地址选择电路100还包括：振荡器，连接所述第二计数单元；所述振荡器用于提供时钟信号；所述第二计数单元具体配置为对所述时钟信号的脉冲进行计数，以生成并输出所述第二计数值。
在一些实施例中，如图4所示为地址选择电路的局部示意图，所述控制电路140还包括：命令解码电路160，用于根据存储控制器发出的外部命令，生成并输出激活信号；地址采样电路170，连接所述命令解码电路160和所述页表；所述地址采样电路170用于响应于所述激活信号，采样所述激活信号对应的多个所述行地址并存储至所述页表中。
在本公开实施例中，命令解码电路160可以对存储控制器(Memory Controller，MC)发送的外部命令进行解码，这里的外部命令包括但不限于刷新命令(Refresh，REF)、刷新管理命令(Refresh Management，RFM)、自动刷新命令、激活命令等。根据存储控制器发送的激活命令，命令解码电路160可以生成并输出激活信号，以对多个行地址对应的多条字线进行激活操作。地址采样电路170可以响应于上述激活信号，对激活信号对应的行地址进行随机抓取，并将抓取到的行地址存储至页表中。在一些实施例中，响应于自动刷新命令，地址采样电路170还可以重新采样多个新的行地址，以替换多个地址寄存单元中原有的行地址，以保证行地址的动态更新，提高生成行锤地址的准确性。
在一些实施例中，所述比较电路还用于根据多个所述第一计数值，输出最小计数值；所述控制电路还用于将所述最小计数值对应的所述地址寄存单元中存储的所述行地址替换为新的行地址。
在本公开实施例中，比较电路还可以通过多轮比较回合，对多个第一计数值进行两两比较，输出最小计数值。每轮比较回合中，比较上一轮比较回合中较小的一个第一计数值，与另一个未经比较的第一计数值，并将其中较小的一个第一计数值输出至寄存单元。获取最小计数值的具体实现方 式参考上述实施例，这里不再赘述。控制电路可以根据最小计数值对应的索引值，确定最小计数值对应的行地址所在的地址寄存单元，并将最小计数值对应的地址寄存单元中存储的行地址替换为新的行地址，以保证行地址的动态更新，提高生成行锤地址的准确性。示例性地，控制电路还可以连接多个地址寄存单元，以将最小计数值对应的地址寄存单元中存储的行地址清除，并控制上述地址采样电路，将新的行地址输出至该地址寄存单元。
在一些实施例中，如图4所示，所述控制电路140还包括：地址运算电路180，用于根据所述行锤地址，确定所述行锤地址相邻的至少一条行地址为行锤刷新地址。
在本公开实施例中，控制电路140中还具有地址运算电路180。地址运算电路180可以将行锤地址相邻的至少一条行地址作为行锤刷新地址，这里的行锤刷新地址即为受害者行。如此，在一个刷新窗口时间内对受害者行对应的字线执行行锤刷新操作，可以减少行锤效应带来的数据错误，提高存储器工作的可靠性。在一些实施例中，根据存储器的性能和功耗要求，可以选择与行锤地址相邻的一条行地址作为行锤刷新地址进行刷新，以降低功耗；也可以选择与行锤地址相邻的多条行地址进行刷新，以提高刷新受害行的准确性。
第二方面，如图5所示，本公开实施例提供了一种地址选择方法，包括：
步骤S10：在页表中存储多个行地址，并对所述行地址的访问次数进行计数以生成对应的第一计数值；所述页表的每一页表项包括一个行地址和对应的一个第一计数值；所述第一计数值表示所述行地址的访问次数；生成并输出第二计数值；所述第二计数值作为对应于一个所述页表项所述行地址和所述第一计数值的索引值；
步骤S20：通过多轮比较回合输出多个所述第一计数值中的最大计数值；在最后一轮所述比较回合后，输出所述最大计数值对应的所述行地址以作为行锤地址，并输出所述最大计数值对应的所述索引值以作为行锤索引值，所述行锤索引值用于查找所述最大计数值对应的所述页表项。
在本公开实施例中，可以在页表中存储多个行地址，并对每个行地址的访问次数进行计数以生成对应的第一计数值。每个行地址在物理上可以对应于存储器中的一条字线。这里存储在页表中的行地址可以通过随机采样的方式从进行激活操作的行地址中获得。
分别对多个行地址中的每一个行地址的访问次数进行计数，以生成对应的多个第一计数值，这里的访问次数可以是行地址对应的字线进行激活操作的次数。在一些实施例中，还可以响应于自动刷新命令，将多个第一计数值重置为0。这里的自动刷新可以设置刷新间隔，从而按照刷新间隔的时间自动对存储单元执行刷新操作。
对脉冲信号计数以生成第二计数值，也就是说，第二计数值可以随着接收到的脉冲数目的增加而逐渐增大。示例性地，这里的脉冲信号可以为振荡器提供的时钟信号，对时钟信号的上升沿进行计数可以生成第二计数值。值得注意的是，这里也可以对脉冲信号的下降沿进行计数，还可以对脉冲信号的上升沿和下降沿均进行计数，本公开实施例中不做限制。第二计数值的每个计数可以作为对应于一个第一计数值和一个行地址的索引值。
通过多轮比较回合对多个第一计数值进行两两比较，并在最后一轮比较回合后，同步地输出最大计数值、最大计数值对应的行锤地址和最大计数值对应的索引值。示例性地，在每轮比较回合中，比较上一轮比较回合中较大的一个第一计数值，以及另一个未经比较的第一计数值，并输出其中较大的一个第一计数值，如此重复多轮比较回合，可以在最后一轮比较回合后，输出最大计数值。在每轮比较回合中，还可以根据比较结果信号，选择并存储较大的一个第一计数值对应的行地址和索引值，以在最后一轮比较回合后，同步地输出最大计数值、行锤地址和作为行锤索引值的索引值。如此，将采样到的多个行地址中访问次数最多的行地址作为行锤地址，可以提高生成行锤地址的准确性，以减少行锤效应带来的数据错误；此外，通过行锤索引值可以重置对应的行地址和第一计数值，以进一步地提高生成行锤地址的准确性。值得注意的是，上述步骤中，输出行地址、第一计数 值以及第二计数值可以是同步进行的，从而在每轮比较回合中，在比较两个第一计数值的大小的同时，根据比较结果信号选择对应的一个行地址和一个索引值。
在一些实施例中，所述方法还包括：根据所述行锤索引值，重置对应的所述页表项中的所述行地址和所述第一计数值。
在本公开实施例中，在对行锤地址相邻的受害者行进行刷新操作之后，可以根据行锤索引值，将对应存储的一个行地址替换为另一个重新采样到的行地址，可以理解的是，这里对应存储的一个行地址即为行锤地址。另外，还可以根据行锤索引值，将对应的一个第一计数值重置为0，可以理解的是，这里对应的一个第一计数值即为最大计数值。如此，可以动态更新多个行地址以及对应的多个第一计数值，进一步地提高生成行锤地址的准确性。
在一些实施例中，所述输出多个第一计数值包括：所述方法还包括：通过所述页表输出并行的多个所述行地址；通过所述页表输出并行的多个所述第一计数值；基于所述第二计数值的计数，将并行的多个所述第一计数值，依次输出为串行的多个所述第一计数值，直至所述第二计数值等于预设值；所述预设值与所述第一计数值的个数相等；基于所述第二计数值的计数，将并行的多个所述行地址，依次输出为串行的多个所述行地址，直至所述第二计数值等于所述预设值。
在本公开实施例中，可以不分先后顺序地输出多个第一计数值，即并行的多个第一计数值。因此，上述方法还可以包括：根据第二计数值的计数的顺序，依次传输多个第一计数值。示例性地，可以通过数据选择器的分时选择，将多路并列传输的多个第一计数值，转换为按第二计数值的计数的顺序排列的一路数据进行输出，从而依次进行逐轮比较，以输出其中的最大计数值。多个行地址由并行传输转换为串行传输可以参考上述方式实现，这里不再赘述。
示例性地，在第二计数值的计数为1的情况下，输出对应的第一个第一计数值，并同步输出第一个第一计数值对应的行地址；在第二计数值的计数为2的情况下，输出对应的第二个第一计数值，并同步输出第二个第一计数值对应的行地址……在第二计数值的计数为n的情况下，输出对应的第n个第一计数值，并同步输出第n个第一计数值对应的行地址，这里的n为正整数。此外，在第二计数值等于预设值的情况下，可以结束转换过程，这里的预设值可以为第一计数值的总数量。
在一些实施例中，所述通过多轮比较回合输出多个所述第一计数值中的最大计数值，包括：在每轮所述比较回合中，比较上一轮比较回合中存储的一个所述第一计数值，和另一个未经比较的所述第一计数值，并输出比较结果信号；根据所述比较结果信号，输出其中较大的一个所述第一计数值；存储较大的一个所述第一计数值。
在一些实施例中，所述通过多轮比较回合输出多个所述第一计数值中的最大计数值，还包括：在所述第二计数值大于所述预设值的情况下，输出最后一轮所述比较回合中存储的一个所述第一计数值；其中，所述最后一轮所述比较回合中存储的一个所述第一计数值为所述最大计数值。
在一些实施例中，所述输出所述最大计数值对应的所述行地址以作为行锤地址，包括：根据所述比较结果信号，从上一轮比较回合存储的一个所述行地址，和另一个未经比较的所述第一计数值对应的所述行地址中，选择并输出较大的一个所述第一计数值对应的所述行地址；存储每轮所述比较回合中，较大的一个所述第一计数值对应的所述行地址。
示例性地，在一轮比较回合中，根据比较结果信号，可以同步地输出较大的一个第一计数值和对应的行地址，并分别进行存储。如此，在最后一轮比较回合后，即可得到多个第一计数值中的最大计数值，以及最大计数值对应的行锤地址。
在一些实施例中，所述输出所述最大计数值对应的所述行地址以作为行锤地址，还包括：在所述第二计数值大于所述预设值的情况下，输出最后一轮所述比较回合中较大的一个所述第一计数值对应的所述行地址，以作为所述行锤地址。
可以理解的是，在最后一轮比较回合后，可以同步地输出最大计数值和对应的行锤地址。
在一些实施例中，所述输出所述最大计数值对应的所述索引值以作为行锤索引值，包括：根据所述比较结果信号，从上一轮比较回合存储的一个所述索引值，和另一个未经比较的所述第一计数值对应的所述索引值中，选择并输出较大的一个所述第一计数值对应的所述索引值；存储每轮所述比较回合中，较大的一个所述第一计数值对应的所述索引值。
示例性地，在一轮比较回合中，根据比较结果信号，可以同步地输出较大的一个第一计数值和对应的索引值，并分别进行存储。如此，在最后一轮比较回合后，即可得到多个第一计数值中的最大计数值，以及最大计数值对应的索引值，并将该索引值作为行锤索引值。
在一些实施例中，所述输出所述最大计数值对应的所述索引值以作为行锤索引值，还包括：在所述第二计数值大于所述预设值的情况下，输出最后一轮所述比较回合中较大的一个所述第一计数值对应的所述索引值，以作为所述行锤索引值。
可以理解的是，在最后一轮比较回合后，可以同步地输出最大计数值和对应的索引值。
在一些实施例中，所述方法还包括：提供时钟信号；所述生成并输出第二计数值，包括：对所述时钟信号的脉冲进行计数，以生成并输出所述第二计数值。
在一些实施例中，所述方法还包括：根据存储控制器发出的外部命令，生成并输出激活信号；所述在页表中存储多个行地址包括：响应于所述激活信号，采样所述激活信号对应的多个所述行地址并存储至所述页表中。
在本公开实施例中，主机端发出的外部命令包括但不限于刷新命令、刷新管理命令、自动刷新命令、激活命令等。根据激活命令，可以生成并输出激活信号，以对多个行地址对应的多条字线进行激活操作。而响应于上述激活信号，可以随机抓取激活信号对应的行地址，并将抓取到的多个行地址进行存储。在一些实施例中，响应于自动刷新命令，还可以重新采样多个新的行地址，以替换原有的行地址。
在本公开实施例中，还可以对多个第一计数值进行比较，输出最小计数值。获取最小计数值的具体实现方式参考上述实施例，这里不再赘述。而根据最小计数值，可以将最小计数值对应的行地址替换为新的行地址，以保证行地址的动态更新，提高生成行锤地址的准确性。
在一些实施例中，所述方法还包括：根据所述行锤地址，确定所述行锤地址相邻的至少一条行地址为行锤刷新地址。
在一些实施例中，可以在特定时刻，将行锤地址相邻的至少一条行地址作为行锤刷新地址，同时将最小计数值对应的行地址替换为新的行地址。这里的特定时刻可以为接收到主机端发送的自动刷新命令的时刻。
第三方面，如图6所示，本公开实施例提供了一种刷新控制电路200，包括：上述实施例中任一所述的地址选择电路100；刷新电路201，连接所述行锤地址产生电路；所述刷新电路201用于对与所述行锤地址对应的地址线相邻的至少一条地址线进行刷新操作。
在本公开实施例中，刷新控制电路200可以用于采样多个行地址，并确定其中访问次数最多的行地址为行锤地址，然后将行锤地址对应的地址线相邻的至少一条地址线进行刷新操作，以减少数据错误。刷新控制电路200包括地址选择电路100，以及刷新电路201，刷新电路201可以根据地址选择电路100输出的行锤地址，对行锤地址对应的字线相邻的至少一条字线进行刷新操作。示例性地，刷新电路201可以为存储器中的行解码器(Row Decoder)电路。在一些实施例中，地址选择电路100中具有地址运算电路，以根据行锤地址确定行锤刷新地址，故刷新电路201可以直接对行锤刷新地址对应的字线进行刷新。
第四方面，如图7所示，本公开实施例提供了一种存储系统300，包括：存储器310，包括外围电路311和存储单元阵列312；其中，所述外围电路311包括上述实施例中任一所述的地址选择电路100；存储控制器320。
在本公开实施例中，存储器310可以包括但不限于DRAM、静态随机存取存储器(Static Random Access Memory，SRAM)、铁电随机存取存储器(Ferroelectric Random Access Memory，FRAM)、磁性随机存取存储器(Magnetoresistive Random Access Memory，MRAM)、相变随机存取存储器(Phase Change Random Access Memory，PCRAM)、阻变随机存取存储器(Resistive Random Access Memory，RRAM)、纳米随机存取存储器(Nano Random Access Memory，NRAM)等。存储控制器320可以根据主机发出的信号，控制存储器310进行各项操作。可以理解的是，在最后一轮比较回合后，比较电路输出最大计数值，行锤地址产生电路同步地输出最大计数值对应的行锤地址，行锤索引产生电路同步地输出最大计数值对应的行锤索引值。如此，一方面，将访问次数最多的行地址作为行锤地址，可以减少行锤效应带来的数据错误；另一方面，可以根据行锤索引值，确定行锤地址对应的地址寄存单元，以及最大计数值对应的第一计数单元，便于动态更新多个地址寄存单元中的行地址，进一步地提高生成行锤地址的准确性。
本公开些实施例还提供了一种地址选择电路400，如图8所示为地址选择电路400的局部示意图。地址选择电路400可以具有行锤索引值，用于在某一自动刷新命令出现之前，指向最大计数值对应的第一计数单元和/或地址寄存单元(第一计数单元和地址寄存单元未在图8中示出)。地址选择电路400还可以输出最大计数值对应的行锤索引值，以在行锤刷新完成之后，将对应的地址寄存单元中存储的行锤地址替换为另一个重新采样的行地址，并将对应的第一计数单元生成的最大计数值重置为0。
地址选择电路400中还可以包括振荡器OSC、第二计数单元403、第一转换单元451、比较器411、第一仲裁单元412、第一寄存单元413、第一输出单元414、第二转换单元452、第二仲裁单元422、第二寄存单元421、第二输出单元424、第三仲裁单元432、第三寄存单元431、第三输出单元434等。其中，第一转换单元451、第二转换单元452、第一仲裁单元412、第二仲裁单元422、第三仲裁单元432、第一输出单元414、第二输出单元424和第三输出单元434可以为数据选择器，第一寄存单元413、第二寄存单元421和第三寄存单元431可以为D触发器。下面以将9个行地址中访问次数最多的行地址作为行锤地址为例，对地址选择电路400的工作过程进行说明。这里的9个行地址分别为RA_DLUT1<15:0>、RA_DLUT2<15:0>……RA_DLUT9<15:0>，通过9个地址寄存单元存储和并行输出。
首先，9个第一计数单元对存储在9个地址寄存单元中的行地址的访问次数分别进行计数，以生成并行传输的9个第一计数值CNT1<8:0>、CNT2<8:0>……CNT9<8:0>。振荡器OSC产生脉冲信号CLK，第二计数单元403对脉冲信号的上升沿计数以生成第二计数值。第一寄存单元413、第二寄存单元421和第三寄存单元431可以在第一轮比较回合前，将自身存储的数据重置为0。第一转换单元451根据第二计数值的计数，将并行传输的9个第一计数值转换为串行传输；第二转换单元452根据第二计数值的计数，将并行传输的9个行地址转换为串行传输。
具体地，参考图9示出的工作时序图，在第二计数值等于1的情况下，第二计数单元403输出的索引值为1，即第1轮比较回合中，第一转换单元451输出第1个第一计数值CNT1<8:0>，第二转换单元452输出对应的第1个行地址RA_DLUT1<15:0>；比较器411将第1个第一计数值CNT1<8:0>与第一寄存单元413中存储的0进行比较，并输出比较结果信号CNT_SEL；第一仲裁单元412根据比较结果信号CNT_SEL选择第1个第一计数值CNT1<8:0>输出至第一寄存单元413；第二仲裁单元422根据比较结果信号CNT_SEL选择第1个行地址RA_DLUT1<15:0>输出至第二寄存单元421；第三仲裁单元432根据比较结果信号CNT_SEL选择索引值1输出至第三寄存单元431。
在第二计数值等于2的情况下，第二计数单元403输出的索引值为2，即第2轮比较回合中，第一转换单元451输出第2个第一计数值CNT2<8:0>，第二转换单元452输出对应的第2个行地址RA_DLUT2<15:0>；比较器411将第2个第一计数值CNT2<8:0>与第一寄存单元413中存储的第1 个第一计数值CNT1<8:0>进行比较，并输出比较结果信号CNT_SEL；第一仲裁单元412根据比较结果信号CNT_SEL选择其中较大的一个第一计数值CNT12<8:0>输出至第一寄存单元413；第二仲裁单元422根据比较结果信号CNT_SEL选择较大的一个第一计数值CNT12<8:0>对应的行地址RA_DLUT12<15:0>输出至第二寄存单元421；第三仲裁单元432根据比较结果信号CNT_SEL选择较大的一个第一计数值对应的索引值INDEX12<3:0>输出至第三寄存单元431。
依次推类，在第二计数值等于9的情况下，第二计数单元403输出的索引值为9，即第9轮比较回合中，第一转换单元451输出第9个第一计数值CNT9<8:0>，第二转换单元452输出对应的第9个行地址RA_DLUT9<15:0>；比较器411将第9个第一计数值CNT9<8:0>与第一寄存单元413中存储的第8轮比较回合中较大的一个第一计数值CNT18<8:0>进行比较，并输出比较结果信号CNT_SEL；第一仲裁单元412根据比较结果信号CNT_SEL选择其中较大的一个第一计数值CNT19<8:0>输出至第一寄存单元413；第二仲裁单元422根据比较结果信号CNT_SEL选择较大的一个第一计数值CNT19<8:0>对应的行地址RA_DLUT19<15:0>输出至第二寄存单元421；第三仲裁单元432根据比较结果信号CNT_SEL选择索引值INDEX19<3:0>输出至第三寄存单元431。而在第二计数值等于10的情况下，第一输出单元414输出第一寄存单元413中存储的第一计数值CNT19<8:0>，以作为最大计数值，第二输出单元424同步地输出第二寄存单元421中存储的行地址RA_DLUT19<15:0>，以作为行锤地址，第三输出单元434同步地输出第三寄存单元431中存储的索引值INDEX19<3:0>，以作为行锤索引值。可以理解的是，第一输出单元451、第二输出单元452和第三输出单元434在第二计数值小于10的情况下，保持输出0。
如此，地址选择电路400采用分时复用的方法对多个第一计数值进行两两比较，其中比较电路、行锤地址产生电路和行锤索引产生电路可以在多轮比较回合中重复使用，并可以同步地输出最大计数值、对应的行锤地址和对应的行锤索引值。在一些实施例中，地址选择电路400只需要一个占用面积为49个标准单元(STD Cell)的比较器，其他部分为数量较少的D触发器或锁存器，故相较于通过组合逻辑电路输出最大计数值，地址选择电路400的占用面积相对较小。在一些实施例中，地址选择电路400的每轮比较回合仅需要2ns，也就是说，地址选择电路400可以在18ns内完成9个第一计数值的比较，以输出其中的最大计数值。在一些实施例中，由于第一寄存单元411、第二寄存单元421和第三寄存单元431为D触发器，仅存储每轮比较回合中较大的一个第一计数值、对应的行地址和对应的索引值，即不需要处理其他无用的中间过程数据，故电路的功耗较低。可以理解的是，行地址的数量越多，即需要进行统计和比较的第一计数值的数量越多，地址选择电路400的上述优势越突出。
在一些实施例中，地址选择电路400还可以用于寻找多个第一计数值中的最小计数值，此时仅需在每轮比较回合中存储较小的一个第一计数值，以及对应的行地址和索引值即可实现。
在一些实施例中，还可以在刷新周期时间(Time for Refresh Cycle，tRFC)内，完成对行锤地址相邻的行地址的刷新操作，并将该行锤地址对应的地址寄存单元和最大计数值对应的第一计数单元清空，以等待重新采样到的下一个待刷新的地址。
需要说明的是，本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
在本公开实施例提供的地址选择电路中，在最后一轮比较回合后，比较电路输出最大计数值， 行锤地址产生电路同步地输出最大计数值对应的行锤地址，行锤索引产生电路同步地输出最大计数值对应的索引值以作为行锤索引值。如此，一方面，将访问次数最多的行地址作为行锤地址，可以减少行锤效应带来的数据错误；另一方面，可以通过行锤索引值，查找最大计数值对应的页表项，便于动态更新多个页表项中的行地址，进一步地提高生成行锤地址的准确性。

Claims (24)

  1. 一种地址选择电路(100)，包括：
    页表(104)，所述页表(104)的每一页表项包括一个行地址和对应的一个第一计数值；所述第一计数值表示所述行地址的访问次数；
    第二计数单元(103)，配置为生成并输出第二计数值；所述第二计数值作为对应于一个所述页表项的索引值；
    比较电路(110)，连接所述页表(104)；所述比较电路(110)用于通过多轮比较回合输出多个所述第一计数值中的最大计数值；
    行锤地址产生电路(120)，连接所述比较电路(110)和所述页表(104)；所述行锤地址产生电路(120)用于在最后一轮所述比较回合后，输出所述最大计数值对应的所述行地址以作为行锤地址；
    行锤索引产生电路(130)，连接所述比较电路(110)和所述第二计数单元(103)；所述行锤索引产生电路(130)用于在最后一轮所述比较回合后，输出所述最大计数值对应的所述索引值以作为行锤索引值，所述行锤索引值用于查找所述最大计数值对应的所述页表项。
  2. 根据权利要求1所述的地址选择电路(100)，其中，所述比较电路(110)包括：
    比较器(111)、第一仲裁单元(112)和第一寄存单元(113)；所述比较器(111)的输入端连接所述第一寄存单元(113)的输出端；所述第一仲裁单元(112)的输入端连接所述第一寄存单元(113)的输出端和所述比较器(111)的输出端；所述第一寄存单元(113)的输入端连接所述第一仲裁单元(112)的输出端；
    所述比较器(111)用于在每轮所述比较回合中，比较所述第一寄存单元(113)输出的上一轮比较回合中较大的一个所述第一计数值，和另一个未经比较的所述第一计数值的大小，并输出比较结果信号；
    所述第一仲裁单元(112)配置为在每轮所述比较回合中，根据所述比较结果信号，将所述第一寄存单元(113)输出的一个所述第一计数值和另一个未经比较的所述第一计数值中较大的一个所述第一计数值输出至所述第一寄存单元(113)；
    所述第一寄存单元(113)配置为存储每轮所述比较回合中所述第一仲裁单元(112)输出的较大的一个所述第一计数值。
  3. 根据权利要求2所述的地址选择电路(100)，其中，所述比较电路(110)还包括：
    第一输出单元(114)，连接所述第一寄存单元(113)和所述第二计数单元(103)；所述第一输出单元(114)配置为在所述第二计数值大于预设值的情况下，输出所述第一寄存单元(113)存储的所述第一计数值，以作为所述最大计数值。
  4. 根据权利要求2或3所述的地址选择电路(100)，其中，还包括：
    多个地址寄存单元(101)，位于所述页表(104)中；多个所述地址寄存单元(101)配置为输出并行的多个所述行地址；
    多个第一计数单元(102)，位于所述页表(104)中；多个所述第一计数单元(102)配置为输出并行的多个所述第一计数值；
    第一转换单元(151)，所述第一转换单元(151)的选择端连接所述第二计数单元(103)，所述第一转换单元(151)的输入端连接多个所述第一计数单元(102)，所述第一转换单元(151)的输出端连接所述比较电路(110)；所述第一转换单元(151)配置为基于所述第二计数值的计数，将并行的多个所述第一计数值，依次输出为串行的多个所述第一计数值，直至所述第二计数值等于预设值；所述预设值与所述第一计数值的个数相等；
    第二转换单元(152)，所述第二转换单元(152)的选择端连接所述第二计数单元(103)，所述第二转换单元(152)的输入端连接多个所述地址寄存单元(101)，所述第二转换单元(152)的输 出端连接所述行锤地址产生电路(120)；所述第二转换单元(152)配置为基于所述第二计数值的计数，将并行的多个所述行地址，依次输出为串行的多个所述行地址，直至所述第二计数值等于所述预设值。
  5. 根据权利要求4所述的地址选择电路(100)，其中，所述行锤地址产生电路(120)包括：
    第二寄存单元(121)，配置为存储每轮所述比较回合中，较大的一个所述第一计数值对应的所述行地址；
    第二仲裁单元(122)，所述第二仲裁单元(122)的输入端连接所述第二转换单元(152)的输出端和所述第二寄存单元(121)的输出端，所述第二仲裁单元(122)的选择端连接所述比较器(111)的输出端；所述第二仲裁单元(122)的输出端连接所述第二寄存单元(121)的输入端；所述第二仲裁单元(122)配置为根据所述比较结果信号，选择每轮所述比较回合中较大的一个所述第一计数值对应的所述行地址，并输出至所述第二寄存单元(121)。
  6. 根据权利要求5所述的地址选择电路(100)，其中，所述行锤地址产生电路(120)还包括：
    第二输出单元(124)，连接所述第二寄存单元(121)和所述第二计数单元(103)；所述第二输出单元(124)配置为在所述第二计数值大于所述预设值的情况下，输出所述第二寄存单元(121)存储的所述行地址，以作为所述行锤地址。
  7. 根据权利要求4至6中任一所述的地址选择电路(100)，其中，所述行锤索引产生电路(130)包括：
    第三寄存单元(131)，配置为存储每轮所述比较回合中，较大的一个所述第一计数值对应的所述索引值；
    第三仲裁单元(132)，所述第三仲裁单元(132)的输入端连接所述第二计数单元(103)的输出端和所述第三寄存单元(131)的输出端，所述第三仲裁单元(132)的选择端连接所述比较器(111)的输出端；所述第三仲裁单元(132)的输出端连接所述第三寄存单元(131)的输入端；所述第三仲裁单元(132)配置为根据所述比较结果信号，选择每轮所述比较回合中较大的一个所述第一计数值对应的所述索引值，并输出至所述第三寄存单元(131)。
  8. 根据权利要求7所述的地址选择电路(100)，其中，所述行锤索引产生电路(130)还包括：
    第三输出单元(134)，连接所述第三寄存单元(131)和所述第二计数单元(103)；所述第三输出单元(134)配置为在所述第二计数值大于所述预设值的情况下，输出所述第三寄存单元(131)存储的所述索引值，以作为所述行锤索引值。
  9. 根据权利要求1至8中任一所述的地址选择电路(100)，其中，还包括：
    振荡器，连接所述第二计数单元(103)；所述振荡器用于提供时钟信号；所述第二计数单元(103)具体配置为对所述时钟信号的脉冲进行计数，以生成并输出所述第二计数值。
  10. 根据权利要求1至9中任一所述的地址选择电路(100)，其中，还包括：
    控制电路(140)，用于根据所述行锤索引值，重置对应的所述页表项中的所述行地址和所述第一计数值。
  11. 根据权利要求10所述的地址选择电路(100)，其中，所述控制电路(140)包括：
    命令解码电路(160)，用于根据存储控制器发出的外部命令，生成并输出激活信号；
    地址采样电路(170)，连接所述命令解码电路(160)和所述页表(104)；所述地址采样电路(170)用于响应于所述激活信号，采样所述激活信号对应的多个所述行地址并存储至所述页表(104)中。
  12. 一种地址选择方法，包括：
    在页表中存储多个行地址，并对所述行地址的访问次数进行计数以生成对应的第一计数值；所述页表的每一页表项包括一个行地址和对应的一个第一计数值；
    生成并输出第二计数值；所述第二计数值作为对应于一个所述页表项的索引值；
    通过多轮比较回合输出多个所述第一计数值中的最大计数值；
    在最后一轮所述比较回合后，输出所述最大计数值对应的所述行地址以作为行锤地址，并输出所述最大计数值对应的所述索引值以作为行锤索引值，所述行锤索引值用于查找所述最大计数值对应的所述页表项。
  13. 根据权利要求12所述的方法，其中，所述通过多轮比较回合输出多个所述第一计数值中的最大计数值，包括：
    在每轮所述比较回合中，比较上一轮比较回合中存储的一个所述第一计数值，和另一个未经比较的所述第一计数值，并输出比较结果信号；
    根据所述比较结果信号，输出其中较大的一个所述第一计数值；
    存储较大的一个所述第一计数值。
  14. 根据权利要求13所述的方法，其中，所述通过多轮比较回合输出多个所述第一计数值中的最大计数值，还包括：
    在所述第二计数值大于预设值的情况下，输出最后一轮所述比较回合中存储的一个所述第一计数值；其中，所述最后一轮所述比较回合中存储的一个所述第一计数值为所述最大计数值。
  15. 根据权利要求13或14所述的方法，其中，还包括：
    通过所述页表输出并行的多个所述行地址；
    通过所述页表输出并行的多个所述第一计数值；
    基于所述第二计数值的计数，将并行的多个所述第一计数值，依次输出为串行的多个所述第一计数值，直至所述第二计数值等于预设值；所述预设值与所述第一计数值的个数相等；
    基于所述第二计数值的计数，将并行的多个所述行地址，依次输出为串行的多个所述行地址，直至所述第二计数值等于所述预设值。
  16. 根据权利要求15所述的方法，其中，所述输出所述最大计数值对应的所述行地址以作为行锤地址，包括：
    根据所述比较结果信号，从上一轮比较回合存储的一个所述行地址，和另一个未经比较的所述第一计数值对应的所述行地址中，选择并输出较大的一个所述第一计数值对应的所述行地址；
    存储每轮所述比较回合中，较大的一个所述第一计数值对应的所述行地址。
  17. 根据权利要求16所述的方法，其中，所述输出所述最大计数值对应的所述行地址以作为行锤地址，还包括：
    在所述第二计数值大于所述预设值的情况下，输出最后一轮所述比较回合中较大的一个所述第一计数值对应的所述行地址，以作为所述行锤地址。
  18. 根据权利要求15至17所述的方法，其中，所述输出所述最大计数值对应的所述索引值以作为行锤索引值，包括：
    根据所述比较结果信号，从上一轮比较回合存储的一个所述索引值，和另一个未经比较的所述第一计数值对应的所述索引值中，选择并输出较大的一个所述第一计数值对应的所述索引值；
    存储每轮所述比较回合中，较大的一个所述第一计数值对应的所述索引值。
  19. 根据权利要求18所述的方法，其中，所述输出所述最大计数值对应的所述索引值以作为行锤索引值，还包括：
    在所述第二计数值大于所述预设值的情况下，输出最后一轮所述比较回合中较大的一个所述第一计数值对应的所述索引值，以作为所述行锤索引值。
  20. 根据权利要求12至19中任一所述的方法，其中，还包括：
    提供时钟信号；
    所述生成并输出第二计数值，包括：
    对所述时钟信号的脉冲进行计数，以生成并输出所述第二计数值。
  21. 根据权利要求12至20中任一所述的方法，其中，还包括：
    根据所述行锤索引值，重置对应的所述页表项中的所述行地址和所述第一计数值。
  22. 根据权利要求21所述的方法，其中，还包括：
    根据存储控制器发出的外部命令，生成并输出激活信号；
    所述在页表中存储多个行地址包括：
    响应于所述激活信号，采样所述激活信号对应的多个所述行地址并存储至所述页表中。
  23. 根据权利要求1至11中任一所述的地址选择电路(100)，其中，所述地址选择电路用于在刷新控制电路中提供所述行锤地址，所述刷新控制电路还包括：
    刷新电路(201)，连接所述行锤地址产生电路(120)；所述刷新电路(201)用于对与所述行锤地址对应的地址线相邻的至少一条地址线进行刷新操作。
  24. 一种存储系统(300)，包括：
    存储器(310)，包括外围电路(311)和存储单元阵列(312)；其中，所述外围电路(311)包括如权利要求1至11中任一所述的地址选择电路(100)；
    存储控制器(320)。
PCT/CN2023/079010 2023-02-02 2023-03-01 地址选择电路、地址选择方法、刷新控制电路和存储系统 Ceased WO2024159574A1 (zh)

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