WO2024147302A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024147302A1
WO2024147302A1 PCT/JP2023/046128 JP2023046128W WO2024147302A1 WO 2024147302 A1 WO2024147302 A1 WO 2024147302A1 JP 2023046128 W JP2023046128 W JP 2023046128W WO 2024147302 A1 WO2024147302 A1 WO 2024147302A1
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Prior art keywords
terminal
semiconductor device
wiring portion
semiconductor
wiring
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Ceased
Application number
PCT/JP2023/046128
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English (en)
French (fr)
Japanese (ja)
Inventor
優斗 坂井
裕太 大河内
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024568904A priority Critical patent/JPWO2024147302A1/ja
Publication of WO2024147302A1 publication Critical patent/WO2024147302A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • This disclosure relates to a semiconductor device.
  • the multiple first connection wirings are, for example, wires, and connect the gate terminals and the wiring layer of the multiple first semiconductor elements to each other.
  • the wiring layer is connected to a signal terminal.
  • the signal terminal is connected to the gate terminal of each first semiconductor element via the wiring layer and each first connection wiring.
  • the signal terminal supplies a drive signal for driving each first semiconductor element to the gate terminal of each first semiconductor element.
  • FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG.
  • FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG.
  • FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG.
  • FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG.
  • FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG.
  • FIG. 26 is an enlarged plan view of a main portion showing a first modified example of the semiconductor device according to the third embodiment.
  • FIG. 27 is a diagram showing an example of a circuit configuration of a first modified example of the semiconductor device according to the third embodiment.
  • Each of the first semiconductor elements 11 and the second semiconductor elements 12 may be, for example, a MOSFET.
  • Each of the first semiconductor elements 11 and the second semiconductor elements 12 may be other switching elements such as field effect transistors including MISFETs (Metal-Insulator-Semiconductor FETs) instead of MOSFETs.
  • Each of the first semiconductor elements 11 and the second semiconductor elements 12 may be made of SiC (silicon carbide).
  • the semiconductor material is not limited to SiC, and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or Ga 2 O 3 (gallium oxide).
  • Each of the multiple first semiconductor elements 11 can be bonded to the support substrate 2 (the power wiring section 31 described below) via a conductive bonding material.
  • the conductive bonding material can be, for example, solder, a metal paste material, or a sintered metal.
  • the multiple first semiconductor elements 11 can be arranged, for example, at equal intervals in the first direction x, as shown in Figures 2 and 3.
  • Each of the multiple first semiconductor elements 11 may have a first electrode 111, a second electrode 112, and a third electrode 113.
  • the first electrode 111 may be a drain electrode
  • the second electrode 112 may be a source electrode
  • the third electrode 113 may be a gate electrode.
  • the first electrode 111 may be disposed on the first element rear surface 11b
  • the second electrode 112 and the third electrode 113 may be disposed on the first element main surface 11a.
  • a first drive signal (e.g., gate voltage) can be input to the third electrode 113 (gate electrode 113) of each of the multiple first semiconductor elements 11.
  • Each of the multiple first semiconductor elements 11 can switch between an on state (conducting state) and an off state (blocking state) depending on the input first drive signal. This operation of switching between the on state and the off state is called a switching operation.
  • a forward current flows from the first electrode 111 (drain electrode 111) to the second electrode 112 (source electrode 112), and in the off state, this current does not flow.
  • each of the first semiconductor elements 11 the on/off between the first electrode 111 (drain electrode 111) and the second electrode 112 (source electrode 112) can be controlled by the first drive signal (e.g., gate voltage) input to the third electrode 113 (gate electrode 113).
  • the switching frequency of each first semiconductor element 11 can depend on the frequency of the first drive signal. The switching frequency is not limited in any way, but can be, for example, 10 kHz or more and several hundred kHz or less.
  • the multiple first semiconductor elements 11 may be electrically connected to each other in parallel.
  • the first electrodes 111 drain electrodes 111
  • the second electrodes 112 source electrodes 112
  • the semiconductor device A1 may input a common first drive signal to the multiple first semiconductor elements 11 connected in parallel in this manner, thereby operating the multiple first semiconductor elements 11 in parallel.
  • the third electrodes 113 gate electrodes 113) may be electrically connected to each other (FIG. 6), but the present disclosure is not limited to this.
  • Each of the multiple second semiconductor elements 12 can be bonded to the support substrate 2 (the power wiring section 33 described below) via a conductive bonding material.
  • the conductive bonding material can be, for example, solder, a metal paste material, or a sintered metal.
  • the multiple second semiconductor elements 12 can be arranged at equal intervals in the first direction x, as shown in Figures 2 and 4.
  • Each of the multiple second semiconductor elements 12 may have a second element main surface 12a and a second element back surface 12b. As shown in Figures 4 and 5, the second element main surface 12a and the second element back surface 12b may be spaced apart from each other in the thickness direction z. The second element main surface 12a may face one side (upward) of the thickness direction z, and the second element back surface 12b may face the other side (downward) of the thickness direction z. The second element back surface 12b may face the support substrate 2 (the power wiring section 33 described below).
  • Each of the multiple second semiconductor elements 12 may have a fourth electrode 121, a fifth electrode 122, and a sixth electrode 123.
  • the fourth electrode 121 may be a drain
  • the fifth electrode 122 may be a source
  • the sixth electrode 123 may be a gate.
  • the fourth electrode 121 may be disposed on the second element rear surface 12b
  • the fifth electrode 122 and the sixth electrode 123 may be disposed on the second element main surface 12a.
  • the insulating substrate 20 may have a substrate main surface 20a and a substrate rear surface 20b. As shown in Figures 3 to 5, the substrate main surface 20a and the substrate rear surface 20b may be spaced apart from each other in the thickness direction z. The substrate main surface 20a may face upward in the thickness direction z, and the substrate rear surface 20b may face downward in the thickness direction z.
  • the main surface metal layer 21 and the back surface metal layer 22 may each include, for example, copper or a copper alloy.
  • the main surface metal layer 21 and the back surface metal layer 22 may each include aluminum or an aluminum alloy.
  • the main surface metal layer 21 may be formed on the main surface 20a of the substrate, and the back surface metal layer 22 may be formed on the back surface 20b of the substrate.
  • the bottom surface of the back surface metal layer 22 (the surface facing downward in the thickness direction z) may be exposed from the sealing member 6. Unlike this configuration, the bottom surface of the back surface metal layer 22 may be covered by the sealing member 6.
  • the signal wiring section 35A is electrically connected to the second electrodes 112 (source electrodes 112) of the first semiconductor elements 11, and is hereinafter referred to as the voltage detection wiring section 35A.
  • the voltage detection wiring section 35A may be referred to as the source sense wiring section 35A.
  • the voltage detection wiring section 35A may transmit a first detection signal.
  • the first detection signal is a signal indicating the conductive state of each first semiconductor element 11, and may be, for example, a voltage signal corresponding to a current (source current) flowing through each second electrode 112 (source electrode 112).
  • a second terminal 45A which is a voltage detection terminal, may be joined to the voltage detection wiring section 35A (source sense wiring section 35A).
  • the second terminal 45A may be referred to as the source sense terminal 45A.
  • the signal wiring portion 38A can be electrically connected to each of the third electrodes 113 (gate electrodes 113) of the multiple first semiconductor elements 11.
  • the intermediate signal wiring portion 38A can be located between the third wiring portion 34A (gate wiring portion 34A) and the pad portion 311 in the second direction y.
  • the signal wiring portion 38A will be referred to as the intermediate signal wiring portion 38A.
  • the sealing member 6 can protect the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12.
  • the sealing member 6 can cover the multiple first semiconductor elements 11, the multiple second semiconductor elements 12, a portion of the support substrate 2, a portion of each of the multiple power terminals 41 to 43, a portion of each of the multiple signal terminals 44A, 44B, 45A, 45B, 49, and the multiple connection members 51A, 51B, 52A, 52B, 53A, 53B, 54A, 54B.
  • the sealing member 6 can include, for example, an insulating resin material.
  • the insulating material can be, for example, an epoxy resin.
  • the sealing member 6 can be, for example, black.
  • the sealing member 6 can be rectangular in plan view.
  • the sealing member 6 can have a resin main surface 61, a resin back surface 62, and multiple resin side surfaces 631 to 634.
  • the pair of resin side surfaces 633, 634 may face opposite each other in the second direction y.
  • Each of the signal terminals 44A, 45A may be configured to protrude from the resin side surface 634.
  • Each signal terminal 44B, 45B can be configured to protrude from the resin side surface 633.
  • the frequency of this oscillation may be, for example, several hundred MHz, higher than the frequency (for example, 10 Hz to several hundred Hz) of the gate signal applied to the third electrode 113 (gate electrode 113).
  • a capacitor element C1 may be provided that connects the third conduction path Jg1 (gate conduction path Jg1) and the second conduction path Js1 (source sense conduction path Js1) to each other.
  • the semiconductor device A1 may include a passive low-pass filter. By setting the cutoff frequency of this low-pass filter higher than the frequency of the gate signal and lower than the frequency of the possible oscillation, the gate signal may be appropriately passed while the oscillation may be reduced.
  • the semiconductor device A1 may include a resistor element R1.
  • the cutoff frequency of the low-pass filter for the multiple first semiconductor elements 11 may be set with high precision over a wide range.
  • the cutoff frequency of the low-pass filter for the multiple second semiconductor elements 12 may be set with high precision over a wider range.
  • the resistor element R1 may be arranged to straddle the first portion 381 and the second portion 382 of the intermediate signal wiring portion 38A.
  • the capacitor element C1 may be arranged to straddle the first portion 381 and the voltage detection wiring portion 35A (source sense wiring portion 35A).
  • the intermediate signal wiring portion 38A may be arranged between the pad portion 311 of the power wiring portion 31 and the voltage detection wiring portion 35A (source sense wiring portion 35A) in the second direction y.
  • the resistor elements R1 and the capacitor elements C1 may be arranged in a position close to the first semiconductor elements 11.
  • the third wiring portion 34A may be disposed between the intermediate signal wiring portion 38A and the voltage detection wiring portion 35A (source sense wiring portion 35A) in the second direction y.
  • the resistive element R1 may be disposed so as to straddle the first portion 381 and the third wiring portion 34A (gate wiring portion 34A).
  • the capacitor element C1 may be disposed so as to straddle the first portion 381 and the second portion 382.
  • the first intermediate connection member 53A may be connected to the second portion 382 and the voltage detection wiring portion 35A (source sense wiring portion 35A).
  • the sixth wiring portion 34B (gate wiring portion 34B), the voltage detection wiring portion 35B (source sense wiring portion 35B), the intermediate signal wiring portion 38B, the first intermediate connection member 53B, the multiple resistive elements R2, and the multiple capacitor elements C2 may be disposed in the same manner for the multiple second semiconductor elements 12.
  • Second Modification of First Embodiment shows a second modification of the semiconductor device A1.
  • the intermediate signal wiring portions 38A, 38B may include a first portion 381, a second portion 382, and a third portion 383.
  • the semiconductor device A12 may include a plurality of second intermediate connection members 55A, 55B.
  • the first portion 381, the second portion 382, and the third portion 383 may be aligned in the first direction x and spaced apart from each other.
  • the third portion 383 may be located between the first portion 381 and the second portion 382.
  • the resistive elements R1 and R2 may be connected to straddle the first portion 381 and the third portion 383.
  • the capacitor elements C1 and C2 may be connected to straddle the second portion 382 and the third portion 383.
  • the third connection member 52A (gate connection member 52A) and the sixth connection member 52B (gate connection member 52B) may be connected to the third portion 383.
  • the first intermediate connection members 53A and 53B may be connected to the signal wiring portion 391, the third wiring portion 34A (gate wiring portion 34A), and the sixth wiring portion 34B (gate wiring portion 34B).
  • the second intermediate connection members 55A and 55B can be connected to the second portion 382, the voltage detection wiring portion 35A (source sense wiring portion 35A), and the voltage detection wiring portion 35B (source sense wiring portion 35B).
  • the semiconductor device A12 may have a circuit configuration similar to the circuit configuration diagram of the semiconductor device A1 shown in FIG. 6.
  • This modified example can reduce the oscillation phenomenon that occurs when multiple first semiconductor elements 11 and multiple second semiconductor elements 12 are driven in parallel.
  • Third Modification of First Embodiment 9 shows a third modification of the semiconductor device A13.
  • the semiconductor device A13 of this modification may differ from the above-described examples in the configurations of the resistor element R1 and the intermediate signal wiring portions 38A and 38B.
  • the resistor elements R1 and R2 can be made of wire.
  • the wire that makes up the resistor element R1 can be made of a material with a high resistance value.
  • a material can be, for example, constantan, Ni-Cr (nickel-chromium alloy), alumel, chromel, etc.
  • FIG. 10 shows a fourth modification of the semiconductor device A14.
  • a semiconductor device A14 of this modification can differ from the above-described examples in that it includes a plurality of element packages P1 and P2.
  • FIG. 11 shows an example of the configuration of element packages P1 and P2.
  • the element packages P1 and P2 may include built-in resistor elements R1 and R2 and capacitor elements C1 and C2, and may include electrodes 81, 82, and 83 and a sealing resin 80.
  • the resistance elements R1 and R2 may be, for example, chip resistors.
  • the capacitor elements C1 and C2 may be, for example, ceramic capacitors.
  • the sealing resin 80 may cover the resistance elements R1 and R2 and the capacitor elements C1 and C2.
  • a wiring pattern that is conductive to the resistance elements R1 and R2 and the capacitor elements C1 and C2 may be formed in the sealing resin 80 by, for example, plating.
  • the resistance elements R1 and R2 may be electrically connected between the electrodes 81 and 82.
  • the capacitor elements C1 and C2 may be electrically connected between the electrodes 81 and 83.
  • the third connection member 52A (gate connection member 52A) and the sixth connection member 52B (gate connection member 52B) may be connected to the electrode 81, and the first intermediate connection members 53A and 53B may be connected to the electrode 82.
  • the electrode 83 can be conductively connected to the voltage detection wiring section 35A (source sense wiring section 35A) and the voltage detection wiring section 35B (source sense wiring section 35B).
  • This modified example can reduce the oscillation phenomenon that occurs when multiple first semiconductor elements 11 and multiple second semiconductor elements 12 are driven in parallel.
  • the multiple resistance elements R1, R2 and multiple capacitor elements C1, C2 are not limited to being configured as individual electronic elements, but can be configured as an integrated package such as element packages P1, P2. By adopting element packages P1, P2, the semiconductor device A14 can be made smaller.
  • FIG. 12 shows another example of element packages P1, P2.
  • the element packages P1, P2 may be configured so as not to incorporate chip resistors for forming resistance elements R1, R2 or ceramic capacitors for forming capacitor elements C1, C2.
  • the resistance elements R1, R2 may be formed by providing a material with a high resistance value, for example, using a technique for forming a rewiring layer on a semiconductor layer.
  • the capacitor elements C1, C2 may be formed by stacking dielectric layers and metal layers using the rewiring technique described above.
  • element packages P1 and P2 are not limited in any way.
  • the semiconductor device A2 may include a plurality of first semiconductor elements 11, a plurality of second semiconductor elements 12, a support substrate 2, a plurality of terminals, a plurality of resistor elements R1, a plurality of capacitor elements C1, a plurality of connecting members, and a sealing member 6.
  • the plurality of terminals may include a plurality of power terminals 41 to 43 and a plurality of signal terminals 44A, 44B, 45A, 45B, 46, 49.
  • the plurality of connecting members may include a plurality of connecting members 52A, 52B, 53A, 53B, 54A, 54B, 56, and a plurality of connecting members 58A, 58B.
  • the pair of main surface metal layers 21A, 21B may each be formed on the substrate main surface 20a of the insulating substrate 20, as shown in FIG. 18.
  • the pair of main surface metal layers 21A, 21B may be spaced apart in the first direction x.
  • a conductive substrate 23A may be bonded to the main surface metal layer 21A, and a conductive substrate 23B may be bonded to the main surface metal layer 21B.
  • Each of the pair of main surface metal layers 21A, 21B may be, for example, rectangular in plan view.
  • the conductive substrate 23A may be disposed on the main surface metal layer 21A as shown in FIG. 18.
  • the conductive substrate 23A may have a plurality of first semiconductor elements 11 mounted thereon as shown in FIG. 18.
  • the plurality of first semiconductor elements 11 of the semiconductor device A2 may be disposed on the conductive substrate 23A along the second direction y.
  • the conductive substrate 23A may face the first element rear surfaces 11b of the plurality of first semiconductor elements 11.
  • the conductive substrate 23A may be conductively bonded to the first electrodes 111 (drain electrodes 111) of the plurality of first semiconductor elements 11.
  • the first electrodes 111 (drain electrodes 111) of the plurality of first semiconductor elements 11 may be electrically connected to each other via the conductive substrate 23A.
  • the conductive substrate 23B may be disposed on the main surface metal layer 21B as shown in FIG. 18.
  • a plurality of second semiconductor elements 12 may be mounted on the conductive substrate 23B as shown in FIG. 18.
  • the plurality of second semiconductor elements 12 of the semiconductor device A2 may be disposed on the conductive substrate 23B along the second direction y.
  • the conductive substrate 23B may face the second element rear surfaces 12b of the plurality of second semiconductor elements 12.
  • the conductive substrate 23B may be conductively joined to the fourth electrodes 121 (drain electrodes 121) of the plurality of second semiconductor elements 12.
  • the fourth electrodes 121 of the plurality of second semiconductor elements 12 may be electrically connected to each other via the conductive substrate 23B.
  • the pair of signal boards 24A, 24B can support a plurality of signal terminals 44A, 44B, 45A, 45B, 46, 49. As shown in FIG. 18, the pair of signal boards 24A, 24B can be interposed between the pair of conductive boards 23A, 23B and the plurality of signal terminals 44A, 44B, 45A, 45B, 46, 49 in the thickness direction z.
  • Each of the pair of signal boards 24A, 24B can be formed, for example, by a DBC board.
  • each of the pair of signal boards 24A, 24B can be formed, for example, by a DBA board or an AMB board.
  • Each of the pair of signal boards 24A, 24B can be formed, for example, by a printed board, rather than a DBC board or a DBA board.
  • the insulating substrate 241 may be made of, for example, ceramic.
  • the ceramic may be, for example, AlN, SiN , or Al2O3 .
  • the insulating substrate 241 may be, for example, rectangular in plan view. As shown in FIG. 18, the insulating substrate 241 may have a main surface 241a and a back surface 241b.
  • the main surface 241a and the back surface 241b may be spaced apart in the thickness direction z.
  • the main surface 241a may face upward in the thickness direction z, and the back surface 241b may face downward in the thickness direction z.
  • the main surface 241a and the back surface 241b may be flat (or approximately flat).
  • the back metal layer 243 may be formed on the back surface 241b of the insulating substrate 241, as shown in FIG. 18.
  • the back metal layer 243 of the signal substrate 24A may be bonded to the conductive substrate 23A via a bonding material.
  • the back metal layer 243 of the signal substrate 24B may be bonded to the conductive substrate 23B via a bonding material.
  • the constituent material of the back metal layer 243 may be, for example, copper or a copper alloy.
  • the constituent material may be aluminum or an aluminum alloy, rather than copper or a copper alloy.
  • the main surface metal layer 242 may be formed on the main surface 241a of the insulating substrate 241, as shown in FIG. 18. Each of the multiple signal terminals 44A, 44B, 45A, 45B, 46, and 49 may be provided upright on the main surface metal layer 242 of one of the pair of signal substrates 24A and 24B.
  • the constituent material of the main surface metal layer 242 may be, for example, copper or a copper alloy.
  • the constituent material may be aluminum or an aluminum alloy, rather than copper or a copper alloy.
  • the main surface metal layer 242 of the signal board 24A may include a plurality of signal wiring portions 34A, 35A, 36, 38A, and 39, as shown in Figures 15 and 16.
  • the main surface metal layer 242 of the signal board 24B may include a plurality of signal wiring portions 34B, 35B, 38B, and 39, as shown in Figures 15 and 17.
  • the signal wiring portion 36 is joined to a connection member 56 and can be electrically connected to the conductive substrate 23A via the connection member 56.
  • the conductive substrate 23A can be electrically connected to the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11.
  • the signal wiring portion 36 can be electrically connected to the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11.
  • the power terminal 41 may be formed integrally with the conductive substrate 23A. Alternatively, the power terminal 41 may be joined to the conductive substrate 23A. The power terminal 41 may have a smaller dimension in the thickness direction z than the conductive substrate 23A. The power terminal 41 may be configured to extend from the conductive substrate 23A to one side in the first direction x. The one side in the first direction x may be the side of the conductive substrate 23A opposite to the side on which the conductive substrate 23B is located. The power terminal 41 may be configured to protrude from the resin side surface 632. The power terminal 41 may be electrically connected to the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11 via the conductive substrate 23A.
  • the signal terminals 44A, 44B, 45A, 45B, 46, and 49 may each be configured to protrude from the resin main surface 61 as shown in FIG. 13.
  • the signal terminals 44A, 44B, 45A, 45B, 46, and 49 may each be, for example, a press-fit terminal.
  • the signal terminals 44A, 44B, 45A, 45B, 46, and 49 may each include a holder and a metal pin.
  • the holder may be a cylindrical member made of a conductive material.
  • the holder may be joined to the main surface metal layer 242 of the signal board 24A or the signal board 24B.
  • the metal pin may be configured to be pressed into the holder and extend in the thickness direction z.
  • the signal terminal 46 can be provided upright on the signal wiring portion 36.
  • the signal terminal 46 can be electrically connected to the signal wiring portion 36.
  • the signal wiring portion 36 can be electrically connected to the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11.
  • the signal terminal 46 can be electrically connected to the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11.
  • the multiple signal terminals 49 can be provided upright on the signal wiring portion 39.
  • the multiple signal terminals 49 can be non-conductive to the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12.
  • Each of the multiple signal terminals 49 can be a non-connect terminal.
  • connection member 56 may be, for example, a bonding wire.
  • the material of the bonding wire may be any of gold, copper, or aluminum.
  • the connection member 56 may be joined to the signal wiring portion 36 and the conductive substrate 23A, and may provide electrical conductivity between them.
  • the multiple connection members 58A, 58B together with the support substrate 2, can form a path for a main circuit current that is switched by the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12.
  • the multiple connection members 58A, 58B can be formed of a metal plate-shaped member.
  • the metal can be, for example, copper or a copper alloy.
  • the multiple connection members 58A, 58B can have a partially bent shape.
  • the multiple connection members 58A can be bonded to the second electrodes 112 (source electrodes 112) of the multiple first semiconductor elements 11 and the conductive substrate 23B.
  • the second electrodes 112 (source electrodes 112) of the multiple first semiconductor elements 11 and the conductive substrate 23B can be mutually conductive.
  • the connection members 58A and the second electrodes 112 (source electrodes 112) of the multiple first semiconductor elements 11 can be bonded by a conductive bonding material (for example, solder, metal paste material, sintered metal, etc.).
  • the connection members 58A and the conductive substrate 23B can be bonded by a conductive bonding material (for example, solder, metal paste material, sintered metal, etc.).
  • Each connection member 58A can be a strip extending in the first direction x in a plan view, as shown in FIG. 15.
  • connection members 58A may be the same as the number of first semiconductor elements 11. In the example shown in the figure, the number of connection members 58A is three, but the present disclosure is not limited to this. In a variation from this configuration, the number of connection members 58A may be different from the number of first semiconductor elements 11. As an example, for example, one connection member 58A may be used for multiple first semiconductor elements 11.
  • connection member 58B can mutually connect the fifth electrodes 122 (source electrodes 122) of the multiple second semiconductor elements 12 and the power terminals 42. As shown in FIG. 14, the connection member 58B can include a pair of first wiring portions 581B, a second wiring portion 582B, a third wiring portion 583B, and multiple fourth wiring portions 584B.
  • the second wiring portion 582B may be connected to both of the pair of first wiring portions 581B as shown in FIG. 14.
  • the second wiring portion 582B may be in the shape of a strip extending in the second direction y in a planar view. As can be understood from FIG. 14 and FIG. 18, the second wiring portion 582B may overlap with a plurality of second semiconductor elements 12 in a planar view.
  • the second wiring portion 582B may be connected to each second semiconductor element 12 (fifth electrode 122) as shown in FIG. 18.
  • the second wiring portion 582B may have a portion that overlaps with each second semiconductor element 12 in a planar view. This overlapping portion may have a configuration that protrudes downward in the thickness direction z more than other portions.
  • each of the multiple fourth wiring parts 584B may be connected to both the second wiring part 582B and the third wiring part 583B.
  • Each of the multiple fourth wiring parts 584B may be in the shape of a strip extending in the first direction x in a plan view.
  • the multiple fourth wiring parts 584B may be spaced apart in the second direction y and arranged parallel (or approximately parallel) in a plan view.
  • Each of the multiple fourth wiring parts 584B may have one end and the other end in the first direction x.
  • the one end may be connected to a portion of the third wiring part 583B that overlaps between two first semiconductor elements 11 adjacent to each other in the second direction y in a plan view.
  • the other end may be connected to a portion of the second wiring part 582B that overlaps between two second semiconductor elements 12 adjacent to each other in the second direction y in a plan view.
  • the semiconductor device A2 may have the same configuration as the semiconductor device A1 in terms of the multiple resistor elements R2, multiple capacitor elements C2, multiple sixth connection members 52B (gate connection members 52B), multiple voltage detection connection members 54B (source sense connection members 54B), multiple first intermediate connection members 53B, sixth wiring portion 34B (gate wiring portion 34B), voltage detection wiring portion 35B (source sense wiring portion 35B) and intermediate signal wiring portion 38B.
  • the semiconductor device A2 may have the sixth conduction path Jg2 (gate conduction path Jg2) and the fifth conduction path Js2 (source sense conduction path Js2) shown in FIG. 6.
  • the semiconductor device A2 can reduce the oscillation phenomenon that occurs when multiple first semiconductor elements 11 and multiple second semiconductor elements 12 are operated in parallel.
  • the configurations of the above-mentioned semiconductor devices A11 to A14 can be appropriately adopted.
  • the semiconductor device A3 may include a plurality of first semiconductor elements 11, a plurality of second semiconductor elements 12, a support substrate 2, a plurality of terminals, a plurality of connection members, a plurality of resistor elements R1, a plurality of capacitor elements C1, a heat sink 70, a case 71, and a resin member 75.
  • the plurality of terminals may include a plurality of power terminals 41 to 43 and a plurality of signal terminals 44A, 44B, 45A, 45B, 46, and 47.
  • the plurality of connection members may include a plurality of connection members 51A, 51B, 52A, 52B, 53A, 53B, 54A, 54B, 551A, 551B, 552A, 552B, 56, and 57.
  • the semiconductor device A3 can be a case type module structure in which a plurality of first semiconductor elements 11 and a plurality of second semiconductor elements 12 are housed in a case 71.
  • the case 71 may be, for example, a rectangular parallelepiped.
  • the case 71 is made of a synthetic resin that has electrical insulation properties and excellent heat resistance, for example, PPS (polyphenylene sulfide).
  • the case 71 may be rectangular and have the same (or approximately the same) size as the heat sink 70 in a plan view.
  • the case 71 may include a frame portion 72, a top plate 73, and a plurality of terminal blocks 741 to 744.
  • the frame 72 may be fixed to the upper surface of the heat sink 70 in the thickness direction z.
  • the top plate 73 may be fixed to the frame 72. As shown in Figures 19, 21, 22, and 25, the top plate 73 may close the opening of the frame 72 on the upper side in the thickness direction z. As shown in Figures 21, 22, and 25, the top plate 73 may face the heat sink 70 that closes the lower side of the frame 72 in the thickness direction z.
  • the top plate 73, the heat sink 70, and the frame 72 may partition a circuit accommodating space inside the case 71.
  • the circuit accommodating space may accommodate a plurality of first semiconductor elements 11, a plurality of second semiconductor elements 12, and the like. Hereinafter, this circuit accommodating space may be referred to as the inside of the case 71.
  • the two terminal blocks 741, 742 may be arranged on one side of the frame portion 72 in the first direction x and may be formed integrally with the frame portion 72.
  • the two terminal blocks 743, 744 may be arranged on the other side of the frame portion 72 in the first direction x and may be formed integrally with the frame portion 72.
  • the two terminal blocks 741, 742 may be arranged along the second direction y against the side wall of the frame portion 72 on one side in the first direction x.
  • the terminal block 741 may cover a portion of the power terminal 41. As shown in FIG. 19, the terminal block 741 may have a portion of the power terminal 41 arranged on the upper surface of the terminal block 741 in the thickness direction z.
  • the terminal block 742 may cover a portion of the power terminal 42.
  • the terminal block 742 may have a portion of the power terminal 42 arranged on the upper surface of the terminal block 742 in the thickness direction z.
  • the two terminal blocks 743, 744 may be arranged along the second direction y on the side wall of the frame portion 72 on the other side in the first direction x.
  • the terminal block 743 may cover a portion of one of the two power terminals 43.
  • a portion of this power terminal 43 may be arranged on the upper surface of the terminal block 743 in the thickness direction z.
  • the terminal block 744 may cover a portion of the other of the two power terminals 43.
  • a portion of this power terminal 43 may be arranged on the upper surface of the terminal block 744 in the thickness direction z.
  • the resin member 75 may be filled into the area surrounded by the top plate 73, the heat sink 70 and the frame portion 72. This area may be the circuit accommodating space.
  • the resin member 75 may cover the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12.
  • the resin member 75 may be made of, for example, black epoxy resin.
  • the material of the resin member 75 may not be epoxy resin, but may be other insulating materials such as silicone gel.
  • the semiconductor device A3 is not limited to a configuration that includes the resin member 75, and may be configured without the resin member 75. In a configuration that includes the resin member 75, the case 71 may be configured without including the top plate 73.
  • the support substrate 2 of the semiconductor device A3 can be bonded to the heat sink 70.
  • the support substrate 2 of the semiconductor device A3 can include an insulating substrate 20 and a main surface metal layer 21.
  • the support substrate 2 can include a back surface metal layer 22.
  • connection member 56 is joined to the extension 313 and the signal terminal 46, and can electrically connect the power wiring portion 31 and the signal terminal 46 to each other.
  • the signal terminal 46 can be electrically connected to each of the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11 via the connection member 56 and the power wiring portion 31.
  • three resistive elements R1 are provided for one first semiconductor element 11.
  • One resistive element R1 may be connected to straddle the first portion 381 and the third portion 383.
  • Another resistive element R1 may be connected to straddle the third portion 383 and the fourth portion 384.
  • the remaining resistive element R1 may be connected to straddle the fourth portion 384 and the second portion 382.
  • the three resistive elements R1 may be connected in series with each other in the third conduction path Jg1 (gate conduction path Jg1).
  • capacitor elements C1 are provided for one first semiconductor element 11.
  • One capacitor element C1 can be connected to straddle the third portion 383 and the voltage detection wiring portion 35A (source sense wiring portion 35A).
  • Another capacitor element C1 can be connected to straddle the fourth portion 384 and the voltage detection wiring portion 35A (source sense wiring portion 35A).
  • the remaining capacitor element C1 can be connected to straddle the second portion 382 and the voltage detection wiring portion 35A (source sense wiring portion 35A).
  • the semiconductor device according to the present disclosure is not limited to the above-described embodiment.
  • the specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways.
  • the present disclosure includes the embodiments described in the following appendices.
  • Appendix 1 a plurality of semiconductor elements each having a first electrode, a second electrode, and a third electrode to which a drive signal for controlling a conduction state of the first electrode and the second electrode is input, the semiconductor elements being connected in parallel with each other; A second terminal; A third terminal; a second conductive path that electrically connects the second electrode and the second terminal of each semiconductor element to each other; a third conductive path that electrically connects the third electrode and the third terminal of each semiconductor element to each other; at least one capacitor element connecting the second conduction path and the third conduction path to each other;
  • a semiconductor device comprising: Appendix 2.
  • the semiconductor device further comprising a first intermediate connection member connected to the second portion and the voltage detection wiring portion.
  • Appendix 13 a first intermediate connection member connected to the second portion and the voltage detection wiring portion; a second intermediate connection member connected to the first portion and the third wiring portion, the intermediate signal wiring portion includes a third portion, the third connection member is connected to the third portion, the resistive element is connected to the first portion and the third portion; 6.
  • the semiconductor device according to claim 5, wherein the capacitor element is connected to the second portion and the third portion.
  • Appendix 14 Further comprising a support substrate supporting the plurality of semiconductor elements; the support substrate includes an insulating substrate and a main surface metal layer; 14.

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PCT/JP2023/046128 2023-01-05 2023-12-22 半導体装置 Ceased WO2024147302A1 (ja)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026023458A1 (ja) * 2024-07-22 2026-01-29 ローム株式会社 半導体装置の製造方法および半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000340738A (ja) * 1999-05-25 2000-12-08 Toshiba Corp Ｍｏｓゲート入力型電力用半導体素子
JP2003125574A (ja) * 2001-10-11 2003-04-25 Fuji Electric Co Ltd 絶縁ゲートトランジスタの駆動回路および電力変換装置と電力用半導体モジュール
WO2021038724A1 (ja) * 2019-08-27 2021-03-04 三菱電機株式会社 電力用半導体モジュール及び電力変換装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000340738A (ja) * 1999-05-25 2000-12-08 Toshiba Corp Ｍｏｓゲート入力型電力用半導体素子
JP2003125574A (ja) * 2001-10-11 2003-04-25 Fuji Electric Co Ltd 絶縁ゲートトランジスタの駆動回路および電力変換装置と電力用半導体モジュール
WO2021038724A1 (ja) * 2019-08-27 2021-03-04 三菱電機株式会社 電力用半導体モジュール及び電力変換装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026023458A1 (ja) * 2024-07-22 2026-01-29 ローム株式会社 半導体装置の製造方法および半導体装置

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