WO2024147302A1 - Semiconductor device - Google Patents

Abstract

In the present invention, a semiconductor device comprises a plurality of parallel-connected semiconductor elements, a second terminal, a third terminal, a second continuity path, a third continuity path, and a capacitor element. Each semiconductor element has a first electrode, a second electrode, and a third electrode into which is inputted a drive signal that controls the state of continuity of the first electrode and the second electrode. The second electrode and second terminal of each of the semiconductor elements are caused to have continuity with each other on the second continuity path. The third electrode and third terminal of each of the semiconductor elements are caused to have continuity with each other on the third continuity path. The second continuity path and the third continuity path are interconnected by the capacitor element.

Description

Semiconductor Device

This disclosure relates to a semiconductor device.

Conventionally, semiconductor devices including power semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are known. In such semiconductor devices, a configuration in which multiple power semiconductor elements are connected in parallel to ensure the allowable current of the semiconductor device is known (for example, Patent Document 1). The power module described in Patent Document 1 includes multiple first semiconductor elements, multiple first connection wirings, a wiring layer, and a signal terminal. The multiple first semiconductor elements are, for example, MOSFETs. Each first semiconductor element is turned on and off in response to a drive signal input to the gate terminal. The multiple first semiconductor elements are connected in parallel. The multiple first connection wirings are, for example, wires, and connect the gate terminals and the wiring layer of the multiple first semiconductor elements to each other. The wiring layer is connected to a signal terminal. The signal terminal is connected to the gate terminal of each first semiconductor element via the wiring layer and each first connection wiring. The signal terminal supplies a drive signal for driving each first semiconductor element to the gate terminal of each first semiconductor element.

JP 2016-225493 A

When multiple semiconductor elements are connected in parallel for use, as in the device disclosed in Patent Document 1, an oscillation phenomenon may occur when each semiconductor element is switched (when driven on and off). This oscillation phenomenon may cause the drive signals of the multiple semiconductor elements to vibrate, which may cause each semiconductor element to malfunction or be destroyed.

An object of the present disclosure is to provide a semiconductor device that is an improvement over conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can reduce the oscillation phenomenon that occurs when multiple semiconductor elements are operated in parallel.

The semiconductor device provided by the first aspect of the present disclosure comprises a plurality of semiconductor elements each having a first electrode, a second electrode, and a third electrode to which a drive signal is input that controls the conductive state of the first electrode and the second electrode, and connected in parallel with each other, a second terminal, a third terminal, a second conductive path that connects the second electrode and the second terminal of each semiconductor element to each other, a third conductive path that connects the third electrode and the third terminal of each semiconductor element to each other, and at least one capacitor element that connects the second conductive path and the third conductive path to each other.

The above configuration can reduce the oscillation phenomenon that occurs when multiple semiconductor elements are operated in parallel in a semiconductor device.

FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment. FIG. 2 is a plan view showing the semiconductor device according to the first embodiment, in which a sealing member is shown by imaginary lines. FIG. 3 is a cross-sectional view taken along line III-III in FIG. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. FIG. 5 is a cross-sectional view taken along line VV in FIG. FIG. 6 is a diagram illustrating an example of a circuit configuration of the semiconductor device according to the first embodiment. FIG. 7 is a plan view showing a first modification of the semiconductor device according to the first embodiment, in which a sealing member is shown by imaginary lines. FIG. 8 is a plan view showing a second modification of the semiconductor device according to the first embodiment, in which a sealing member is shown by imaginary lines. FIG. 9 is a plan view showing a third modified example of the semiconductor device according to the first embodiment, in which a sealing member is shown by imaginary lines. FIG. 10 is a plan view showing a fourth modification of the semiconductor device according to the first embodiment, in which a sealing member is shown by imaginary lines. FIG. 11 is a cross-sectional view showing an element package of a fourth modified example of the semiconductor device according to the first embodiment. FIG. 12 is a cross-sectional view showing another example of an element package of the fourth modified example of the semiconductor device according to the first embodiment. FIG. 13 is a perspective view showing a semiconductor device according to the second embodiment. FIG. 14 is a plan view showing the semiconductor device according to the second embodiment, in which the sealing member is shown by imaginary lines. FIG. 15 is a plan view of FIG. 14 in which some of the connecting members and sealing members are omitted. FIG. 16 is an enlarged plan view of a main portion of FIG. FIG. 17 is an enlarged plan view of a main portion of FIG. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. FIG. 19 is a perspective view showing a semiconductor device according to the third embodiment. FIG. 20 is a plan view showing the semiconductor device according to the third embodiment, in which a part of the case (top plate) and a resin member are omitted. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. FIG. 26 is an enlarged plan view of a main portion showing a first modified example of the semiconductor device according to the third embodiment. FIG. 27 is a diagram showing an example of a circuit configuration of a first modified example of the semiconductor device according to the third embodiment.

A preferred embodiment of the present disclosure will be described below with reference to the drawings. In the following, identical or similar components will be given the same reference numerals, and duplicated descriptions will be omitted. The configurations of each part in each embodiment and each modified example described below can be combined with each other to the extent that no technical contradictions arise. Terms such as "first," "second," and "third" in this disclosure are used merely as labels, and are not necessarily intended to assign an order to the objects they refer to.

In this disclosure, "an object A is formed on an object B" and "an object A is formed on (an object B)" may include "an object A is formed directly on an object B" and "an object A is formed on an object B with another object interposed between the object A and the object B" unless otherwise specified. Similarly, "an object A is disposed on an object B" and "an object A is disposed on (an object B)" may include "an object A is disposed directly on an object B" and "an object A is disposed on (an object B) with another object interposed between the object A and the object B" unless otherwise specified. Similarly, "an object A is located on (an object B)" may include "an object A is in contact with an object B and is located on (an object B)" and "an object A is located on (an object B) with another object interposed between the object A and the object B". "When viewed in a certain direction, an object A overlaps an object B" can include "an object A overlaps the entire object B" and "an object A overlaps a part of an object B" unless otherwise specified. "An object A (its constituent material) contains a certain material C" can include "an object A (its constituent material) is made of a certain material C" and "an object A (its constituent material) mainly consists of a certain material C."

First embodiment:
1 to 6 show a semiconductor device A1 according to a first embodiment. The semiconductor device A1 may include a plurality of first semiconductor elements 11, a plurality of second semiconductor elements 12, a support substrate 2, a plurality of terminals, a plurality of connection members, a plurality of resistor elements R1, R2, a plurality of capacitor elements C1, C2, and a sealing member 6. The plurality of terminals may include a plurality of power terminals 41 to 43 and a plurality of signal terminals 44A, 44B, 45A, 45B, 49. The plurality of connection members may include a plurality of connection members 51A, 51B, 52A, 52B, 53A, 53B, 54A, 54B.

For ease of explanation, the thickness direction of the semiconductor device A1 is referred to as the "thickness direction z". In the following explanation, the terms "top", "bottom", "upper", "lower", "top surface" and "bottom surface" indicate the relative positional relationship of each component in the thickness direction z, and do not necessarily define the relationship with the direction of gravity. "Planar view" refers to the view in the thickness direction z. A direction perpendicular to the thickness direction z is referred to as the "first direction x". As an example, the first direction x is the left-right direction in the plan view of the semiconductor device A1 (see FIG. 2). A direction perpendicular to the thickness direction z and the first direction x is referred to as the "second direction y". As an example, the second direction y is the up-down direction in the plan view of the semiconductor device A1 (see FIG. 2).

Each of the first semiconductor elements 11 and the second semiconductor elements 12 may be, for example, a MOSFET. Each of the first semiconductor elements 11 and the second semiconductor elements 12 may be other switching elements such as field effect transistors including MISFETs (Metal-Insulator-Semiconductor FETs) instead of MOSFETs. Each of the first semiconductor elements 11 and the second semiconductor elements 12 may be made of SiC (silicon carbide). The semiconductor material is not limited to SiC, and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or Ga ₂ O ₃ (gallium oxide).

Each of the multiple first semiconductor elements 11 can be bonded to the support substrate 2 (the power wiring section 31 described below) via a conductive bonding material. The conductive bonding material can be, for example, solder, a metal paste material, or a sintered metal. The multiple first semiconductor elements 11 can be arranged, for example, at equal intervals in the first direction x, as shown in Figures 2 and 3.

Each of the multiple first semiconductor elements 11 may have a first element main surface 11a and a first element back surface 11b. As shown in Figures 3 and 5, the first element main surface 11a and the first element back surface 11b may be spaced apart from each other in the thickness direction z. The first element main surface 11a may face one side (upward) of the thickness direction z, and the first element back surface 11b may face the other side (downward) of the thickness direction z. The first element back surface 11b may face the support substrate 2 (the power wiring section 31 described below).

Each of the multiple first semiconductor elements 11 may have a first electrode 111, a second electrode 112, and a third electrode 113. In an example in which each first semiconductor element 11 is a MOSFET, the first electrode 111 may be a drain electrode, the second electrode 112 may be a source electrode, and the third electrode 113 may be a gate electrode. As can be seen from Figures 2, 3, and 5, in each first semiconductor element 11, the first electrode 111 may be disposed on the first element rear surface 11b, and the second electrode 112 and the third electrode 113 may be disposed on the first element main surface 11a.

A first drive signal (e.g., gate voltage) can be input to the third electrode 113 (gate electrode 113) of each of the multiple first semiconductor elements 11. Each of the multiple first semiconductor elements 11 can switch between an on state (conducting state) and an off state (blocking state) depending on the input first drive signal. This operation of switching between the on state and the off state is called a switching operation. As an example, in the on state, a forward current flows from the first electrode 111 (drain electrode 111) to the second electrode 112 (source electrode 112), and in the off state, this current does not flow. In each of the first semiconductor elements 11, the on/off between the first electrode 111 (drain electrode 111) and the second electrode 112 (source electrode 112) can be controlled by the first drive signal (e.g., gate voltage) input to the third electrode 113 (gate electrode 113). The switching frequency of each first semiconductor element 11 can depend on the frequency of the first drive signal. The switching frequency is not limited in any way, but can be, for example, 10 kHz or more and several hundred kHz or less.

The multiple first semiconductor elements 11 may be electrically connected to each other in parallel. Specifically, for example, as shown in FIG. 6, the first electrodes 111 (drain electrodes 111) may be electrically connected to each other, and the second electrodes 112 (source electrodes 112) may be electrically connected to each other. The semiconductor device A1 may input a common first drive signal to the multiple first semiconductor elements 11 connected in parallel in this manner, thereby operating the multiple first semiconductor elements 11 in parallel. In this case, the third electrodes 113 (gate electrodes 113) may be electrically connected to each other (FIG. 6), but the present disclosure is not limited to this.

Each of the multiple second semiconductor elements 12 can be bonded to the support substrate 2 (the power wiring section 33 described below) via a conductive bonding material. The conductive bonding material can be, for example, solder, a metal paste material, or a sintered metal. The multiple second semiconductor elements 12 can be arranged at equal intervals in the first direction x, as shown in Figures 2 and 4.

Each of the multiple second semiconductor elements 12 may have a second element main surface 12a and a second element back surface 12b. As shown in Figures 4 and 5, the second element main surface 12a and the second element back surface 12b may be spaced apart from each other in the thickness direction z. The second element main surface 12a may face one side (upward) of the thickness direction z, and the second element back surface 12b may face the other side (downward) of the thickness direction z. The second element back surface 12b may face the support substrate 2 (the power wiring section 33 described below).

Each of the multiple second semiconductor elements 12 may have a fourth electrode 121, a fifth electrode 122, and a sixth electrode 123. In an example in which each second semiconductor element 12 is a MOSFET, the fourth electrode 121 may be a drain, the fifth electrode 122 may be a source, and the sixth electrode 123 may be a gate. As can be seen from Figures 2, 4, and 5, in each second semiconductor element 12, the fourth electrode 121 may be disposed on the second element rear surface 12b, and the fifth electrode 122 and the sixth electrode 123 may be disposed on the second element main surface 12a.

A second drive signal (e.g., gate voltage) can be input to the sixth electrode 123 (gate electrode 123) of each of the multiple second semiconductor elements 12. Each of the multiple second semiconductor elements 12 can be switched between an on state and an off state depending on the input second drive signal. In the on state, a forward current flows from the fourth electrode 121 (drain electrode 121) to the fifth electrode 122 (source electrode 122), and in the off state, this current does not flow. In each second semiconductor element 12, the on/off control between the fourth electrode 121 (drain electrode 121) and the fifth electrode 122 (source electrode 122) can be performed by the second drive signal (e.g., gate voltage) input to the sixth electrode 123 (gate electrode 123). The switching frequency of each second semiconductor element 12 can depend on the frequency of the second drive signal. The switching frequency is not limited in any way, but can be, for example, 10 kHz or more and several hundred kHz or less.

The second semiconductor elements 12 may be electrically connected to each other in parallel. Specifically, for example, as shown in FIG. 6, the fourth electrodes 121 (drain electrodes 121) may be electrically connected to each other, and the fifth electrodes 122 (source electrodes 122) may be electrically connected to each other. The semiconductor device A1 may input a common second drive signal to the second semiconductor elements 12 connected in parallel in this manner, thereby operating the second semiconductor elements 12 in parallel. In this case, the sixth electrodes 123 (gate electrodes 123) may be electrically connected to each other (FIG. 6), but the present disclosure is not limited to this.

The support substrate 2 can support the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12, and can provide electrical conductivity between the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12 and multiple terminals. In the semiconductor device A1, the support substrate 2 can be, for example, a DBC (Direct Bonded Copper) substrate or an AMB (Active Material Brazing) substrate. Alternatively to this configuration, the support substrate 2 can be, for example, a DBA (Direct Bonded Aluminum) substrate. The support substrate 2 can include an insulating substrate 20, a main surface metal layer 21, and a back surface metal layer 22.

The insulating substrate 20 may be made of, for example, ceramic having excellent thermal conductivity. Examples of such ceramics _that may be used include AlN (aluminum nitride), SiN (silicon nitride), and _Al2O3 (aluminum oxide). The insulating substrate 20 may be, for example, a flat plate. As shown in Fig. 2, the insulating substrate 20 may be, for example, rectangular in plan view.

The insulating substrate 20 may have a substrate main surface 20a and a substrate rear surface 20b. As shown in Figures 3 to 5, the substrate main surface 20a and the substrate rear surface 20b may be spaced apart from each other in the thickness direction z. The substrate main surface 20a may face upward in the thickness direction z, and the substrate rear surface 20b may face downward in the thickness direction z.

The main surface metal layer 21 and the back surface metal layer 22 may each include, for example, copper or a copper alloy. The main surface metal layer 21 and the back surface metal layer 22 may each include aluminum or an aluminum alloy. As shown in Figures 3 to 5, the main surface metal layer 21 may be formed on the main surface 20a of the substrate, and the back surface metal layer 22 may be formed on the back surface 20b of the substrate. The bottom surface of the back surface metal layer 22 (the surface facing downward in the thickness direction z) may be exposed from the sealing member 6. Unlike this configuration, the bottom surface of the back surface metal layer 22 may be covered by the sealing member 6.

As shown in FIG. 2, the main surface metal layer 21 may include a plurality of power wiring sections 31-33 and a plurality of signal wiring sections 34A, 34B, 35A, 35B, 38A, 38B, and 39. The plurality of power wiring sections 31-33 and the plurality of signal wiring sections 34B, 34B, 35A, 35B, 38A, 38B, and 39 may be separated from one another.

The multiple power wiring sections 31, 32, 33 may form a conduction path for the main circuit current in the semiconductor device A1. The main circuit current may include a first main circuit current and a second main circuit current. The first main circuit current may be a current flowing between the power terminal 41 and the power terminal 43. The second main circuit current may be a current flowing between the power terminal 43 and the power terminal 42.

The power wiring section 31 may be electrically connected to each of the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11. The power wiring section 31 may be electrically connected to the power terminal 41. As shown in FIG. 2, the power wiring section 31 may include two pad sections 311, 312. The two pad sections 311, 312 are connected to each other and may be formed integrally.

The pad portion 311 can have multiple first semiconductor elements 11 mounted thereon. The pad portion 311 can have each of the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11 bonded thereto. In the illustrated example, the pad portion 311 can have a rectangular shape in a plan view with the first direction x as its longitudinal direction. The pad portion 311 can extend from the pad portion 312 along the first direction x.

As shown in Figures 2 to 4, the power terminal 41 can be joined to the pad portion 312. In the illustrated example, the pad portion 312 can be strip-shaped in plan view with the second direction y as the longitudinal direction. The pad portion 312 can be connected to the edge of the pad portion 311 on one side in the first direction x (the side where the power terminal 41 is located).

The power wiring section 32 may be electrically connected to each of the fifth electrodes 122 (source electrodes 122) of the multiple second semiconductor elements 12. The power wiring section 32 may be electrically connected to the power terminal 42. The power wiring section 32 may include two pad sections 321, 322. The two pad sections 321, 322 are connected to each other and may be formed integrally.

As shown in Figures 2 and 6, the pad portion 321 may have a plurality of connection members 51B bonded thereto, and may be electrically connected to each of the fifth electrodes 122 (source electrodes 122) of the plurality of second semiconductor elements 12 via the plurality of connection members 51B. As shown in Figures 2 and 3, the pad portion 321 may extend from the pad portion 322 along the first direction x. In the illustrated example, the pad portion 321 may be in the shape of a band with the first direction x as the longitudinal direction in a plan view. The pad portion 321 may be located on one side of the pad portion 311 in the second direction y (the lower side in Figure 2).

The pad portion 322 may be joined to the power terminal 42 as shown in Figures 2, 3, and 5. As shown in Figures 2 and 3, the pad portion 322 may be strip-shaped in plan view with the second direction y as its longitudinal direction. The pad portion 322 may be connected to an edge of the pad portion 321 on one side in the first direction x (the side on which the power terminal 42 is located). The pad portion 322 may be located on one side in the second direction y (the lower side in Figure 2) relative to the pad portion 321.

The power wiring section 33 may be electrically connected to each of the second electrodes 112 (source electrodes 112) of the multiple first semiconductor elements 11, and may also be electrically connected to each of the fourth electrodes 121 (drain electrodes 121) of the multiple second semiconductor elements 12. The power wiring section 33 may be electrically connected to two power terminals 43. The power wiring section 33 may include two pad sections 331, 332. The two pad sections 331, 332 are connected to each other and may be formed integrally.

As shown in Figures 2 and 3, the pad portion 331 can have multiple second semiconductor elements 12 mounted thereon. The pad portion 331 can be bonded to the fourth electrodes 121 (drain electrodes 121) of the multiple second semiconductor elements 12. In the illustrated example, the pad portion 331 can be rectangular in plan view with the first direction x as its longitudinal direction. The pad portion 331 can extend from the pad portion 332 along the first direction x. The pad portion 331 can be located between the pad portion 311 and the pad portion 321 in the second direction y.

As shown in Figures 2 and 3, the power terminal 43 can be joined to the pad portion 332. In a plan view, the pad portion 332 can be strip-shaped with the second direction y as the longitudinal direction. The pad portion 332 can be connected to an edge of the pad portion 331 on one side in the first direction x (the side where the power terminal 43 is located).

The multiple signal wiring sections 34A, 34B, 35A, 35B, 38A, and 38B can form conduction paths for the electrical signals that control the semiconductor device A1.

The signal wiring portion 34A is electrically connected to each of the third electrodes 113 (gate electrodes 113) of the multiple first semiconductor elements 11, and is hereinafter referred to as the third wiring portion 34A. When the third electrodes 113 are gate electrodes, the third wiring portion 34A may be referred to as the gate wiring portion 34A. The third wiring portion 34A (gate wiring portion 34A) may transmit a first drive signal. A signal terminal 44A may be joined to the third wiring portion 34A (gate wiring portion 34A). Hereinafter, the signal terminal 44A will be referred to as the third terminal 44A. When the third electrodes 113 are gate electrodes, the third terminal 44A may be referred to as the gate terminal 44A.

The signal wiring portion 34B is electrically connected to each sixth electrode 123 (gate electrode 123) of the multiple second semiconductor elements 12, and is hereinafter referred to as the sixth wiring portion 34B. When the sixth electrode 123 is a gate electrode, the sixth wiring portion 34B may be referred to as the gate wiring portion 34B. The sixth wiring portion 34B (gate wiring portion 34B) may transmit a second drive signal. A signal terminal 44B may be joined to the sixth wiring portion 34B (gate wiring portion 34B). Hereinafter, the signal terminal 44B will be referred to as the sixth terminal 44B. When the sixth electrode 123 is a gate electrode, the sixth terminal 44B may be referred to as the gate terminal 44B.

As shown in FIG. 2, the third wiring portion 34A (gate wiring portion 34A) and the sixth wiring portion 34B (gate wiring portion 34B) may be located on opposite sides of the pad portions 311, 321, and 331 in the second direction y. The third wiring portion 34A (gate wiring portion 34A) may be located on the opposite side of the pad portion 331 from the pad portion 311 in the second direction y. The sixth wiring portion 34B (gate wiring portion 34B) may be located on the opposite side of the pad portion 331 from the pad portion 321 in the second direction y.

The signal wiring section 35A is electrically connected to the second electrodes 112 (source electrodes 112) of the first semiconductor elements 11, and is hereinafter referred to as the voltage detection wiring section 35A. When the second electrodes 112 are source electrodes, the voltage detection wiring section 35A may be referred to as the source sense wiring section 35A. The voltage detection wiring section 35A (source sense wiring section 35A) may transmit a first detection signal. The first detection signal is a signal indicating the conductive state of each first semiconductor element 11, and may be, for example, a voltage signal corresponding to a current (source current) flowing through each second electrode 112 (source electrode 112). A second terminal 45A, which is a voltage detection terminal, may be joined to the voltage detection wiring section 35A (source sense wiring section 35A). When the second electrodes 112 are source electrodes, the second terminal 45A may be referred to as the source sense terminal 45A.

The signal wiring section 35B is electrically connected to the fifth electrodes 122 (source electrodes 122) of the second semiconductor elements 12, and is hereinafter referred to as the voltage detection wiring section 35B. When the fifth electrodes 122 are source electrodes, the voltage detection wiring section 35B may be referred to as the source sense wiring section 35B. The voltage detection wiring section 35B (source sense wiring section 35B) may transmit a second detection signal. The second detection signal is an electrical signal indicating the conductive state of each second semiconductor element 12, and may be, for example, a voltage signal corresponding to a current (source current) flowing through each fifth electrode 122 (source electrode 122). A fifth terminal 45B, which is a voltage detection terminal, may be joined to the voltage detection wiring section 35B (source sense wiring section 35B). When the fifth electrodes 122 are source electrodes, the fifth terminal 45B may be referred to as the source sense terminal 45B.

As shown in FIG. 2, the voltage detection wiring unit 35A (source sense wiring unit 35A) and the voltage detection wiring unit 35B (source sense wiring unit 35B) may be located on opposite sides of the pad units 311, 321, and 331 in the second direction y. The voltage detection wiring unit 35A (source sense wiring unit 35A) may be located on the same side as the third wiring unit 34A (gate wiring unit 34A) with respect to the pad unit 311 in the second direction y. The voltage detection wiring unit 35B (source sense wiring unit 35B) may be located on the same side as the sixth wiring unit 34B (gate wiring unit 34B) with respect to the pad unit 321 in the second direction y.

The signal wiring portion 38A can be electrically connected to each of the third electrodes 113 (gate electrodes 113) of the multiple first semiconductor elements 11. In the illustrated example, the intermediate signal wiring portion 38A can be located between the third wiring portion 34A (gate wiring portion 34A) and the pad portion 311 in the second direction y. Hereinafter, the signal wiring portion 38A will be referred to as the intermediate signal wiring portion 38A.

The signal wiring portion 38B can be electrically connected to each of the sixth electrodes 123 (gate electrodes 123) of the multiple second semiconductor elements 12. In the illustrated example, the intermediate signal wiring portion 38B can be located between the sixth wiring portion 34B (gate wiring portion 34B) and the pad portion 321 in the second direction y. Hereinafter, the signal wiring portion 38B will be referred to as the intermediate signal wiring portion 38B.

Each intermediate signal wiring portion 38A, 38B is divided into multiple portions, and in this embodiment, each may include multiple first portions 381 and multiple second portions 382. The following description of the multiple first portions 381 may be common to each intermediate signal wiring portion 38A, 38B unless otherwise specified. The multiple first portions 381 and the multiple second portions 382 may be arranged along the first direction x. The first portions 381 and the second portions 382 may be adjacent to each other in the first direction x and spaced apart from each other.

In the intermediate signal wiring section 38A, the first portion 381 and the second portion 382 adjacent in the first direction x may be connected to each other so that the resistive element R1 straddles them. In the intermediate signal wiring section 38A, the first portion 381 and the second portion 382 adjacent in the first direction x may be electrically connected via the resistive element R1. In the intermediate signal wiring section 38B, the first portion 381 and the second portion 382 adjacent in the first direction x may be connected to each other so that the resistive element R2 straddles them. In the intermediate signal wiring section 38B, the first portion 381 and the second portion 382 adjacent in the first direction x may be electrically connected via the resistive element R2. The specific configuration of the resistive elements R1 and R2 is not limited in any way, and in the illustrated example, for example, a chip resistor may be used. The resistance value of the resistive elements R1 and R2 may be, for example, 0.1 Ω or more and 1 Ω or less.

The multiple signal wiring sections 39 may be non-conductive to the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12. The multiple signal wiring sections 39 may be configured so that no main circuit current or electrical signals flow.

As shown in Figs. 1 and 2, each of the multiple power terminals 41-43 and the multiple signal terminals 44A, 44B, 45A, 45B, 49 may be partially exposed from the sealing member 6. The constituent materials of each of the multiple power terminals 41-43 and the multiple signal terminals 44A, 44B, 45A, 45B, 49 may be, for example, copper or a copper alloy, but may also be other metals (including metal composites). Each of the multiple power terminals 41-43 and the multiple signal terminals 44A, 44B, 45A, 45B, 49 may be made of a metal plate. As an example, these signal terminals may be appropriately bent.

The pair of power terminals 41, 42 are connected to a power source, and a power source voltage (e.g., DC voltage) can be applied to them. In this embodiment, the power terminal 41 is a positive power input terminal (P terminal), and the power terminal 42 is a negative power input terminal (N terminal), but they may be of opposite polarity. The power terminal 43 can output a voltage (e.g., AC voltage) that is power converted by the switching operations of the multiple first semiconductor elements 11 and the switching operations of the multiple second semiconductor elements 12. The power terminal 43 can be a power output terminal (OUT terminal). The main circuit current (first main circuit current and second main surface current) in the semiconductor device A1 can be generated by the power source voltage and the converted voltage.

The power terminal 41 may be electrically connected to each of the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11 via the power wiring portion 31. The power terminal 41 may include a joint portion 411 and a terminal portion 412.

The joint 411 may be covered with a sealing member 6 as shown in FIG. 2. The joint 411 may be joined to the pad portion 312 of the power wiring portion 31 as shown in FIG. 2. This allows the power terminal 41 and the power wiring portion 31 to be electrically connected to each other. The joint between the joint 411 and the pad portion 312 may be joined using a method such as joining using a conductive joining material (such as solder or sintered metal), laser joining, or ultrasonic joining.

As shown in FIG. 2, the terminal portion 412 may be exposed from the sealing member 6. As shown in FIG. 2, the terminal portion 412 may extend from the sealing member 6 to one side in the first direction x in a plan view. The surface of the terminal portion 412 may be plated with silver, for example.

The power terminal 42 may be electrically connected to each of the fifth electrodes 122 (source electrodes 122) of the multiple second semiconductor elements 12 via the power wiring portion 32. The power terminal 42 may include a joint portion 421 and a terminal portion 422.

The joint 421 may be covered with a sealing member 6 as shown in FIG. 2. The joint 421 may be joined to the pad portion 322 of the power wiring portion 32 as shown in FIG. 2. This may allow electrical continuity between the power terminal 42 and the power wiring portion 32. The joint between the joint 421 and the pad portion 322 may be joined using a method such as joining using a conductive joining material (such as solder or sintered metal), laser joining, or ultrasonic joining.

As shown in FIG. 2, the terminal portion 422 may be exposed from the sealing member 6. As shown in FIG. 2, the terminal portion 422 may extend from the sealing member 6 to one side in the first direction x in a plan view. The surface of the terminal portion 422 may be plated with silver, for example.

The power terminal 43 may be electrically connected to each of the second electrodes 112 (source electrodes 112) of the multiple first semiconductor elements 11 via the power wiring portion 33, while also being electrically connected to each of the fourth electrodes 121 (drain electrodes 121) of the multiple second semiconductor elements 12. The power terminal 43 may include a joint portion 431 and a terminal portion 432.

The joint 431 may be covered with a sealing member 6 as shown in FIG. 2. The joint 431 may be joined to the pad portion 332 of the power wiring portion 33 as shown in FIG. 2. This may allow electrical continuity between the power terminal 43 and the power wiring portion 33. The joint between the joint 431 and the pad portion 332 may be joined using a method such as joining using a conductive joining material (such as solder or sintered metal), laser joining, or ultrasonic joining.

As shown in FIG. 2, the terminal portion 432 may be exposed from the sealing member 6. As shown in FIG. 2, the terminal portion 432 may extend from the sealing member 6 to the other side in the first direction x in a plan view. The surface of the terminal portion 432 may be plated with silver, for example.

The power terminals 41 and 42 may be spaced apart from each other and arranged along the second direction y. The power terminals 41 and 42 may be arranged on opposite sides of the support substrate 2 in the first direction x from the power terminals 43. In a configuration different from the semiconductor device A1, the number of power terminals 43 may be two or more instead of one. In this configuration, the multiple power terminals 43 may each be joined to the power wiring portion 33 (pad portion 332) and arranged along the second direction y.

The multiple signal terminals 44A, 44B, 45A, and 45B may be input or output terminals for electrical signals to control the semiconductor device A1. Each of the multiple signal terminals 44A, 44B, 45A, 45B, and 49 may include a portion covered by the sealing member 6 and a portion exposed from the sealing member 6. The multiple signal terminals 44A, 44B, 45A, 45B, and 49 may be pin-shaped metal members. The metal members may include, for example, copper or a copper alloy.

As shown in FIG. 2, the portion of the third terminal 44A (gate terminal 44A) covered by the sealing member 6 may be joined to the third wiring portion 34A (gate wiring portion 34A). Since the third wiring portion 34A (gate wiring portion 34A) is conductive to each of the third electrodes 113 (gate electrodes 113) of the multiple first semiconductor elements 11, the third terminal 44A (gate terminal 44A) may be conductive to each of the third electrodes 113 (gate electrodes 113). The third terminal 44A (gate terminal 44A) may be an input terminal for the first drive signal.

As shown in FIG. 2, the portion of the sixth terminal 44B (gate terminal 44B) that is covered by the sealing member 6 can be joined to the sixth wiring portion 34B (gate wiring portion 34B). Since the sixth wiring portion 34B (gate wiring portion 34B) is conductive to each of the sixth electrodes 123 (gate electrodes 123) of the multiple second semiconductor elements 12, the signal terminal 44B can be conductive to each of the sixth electrodes 123. The sixth terminal 44B (gate terminal 44B) can be an input terminal for the second drive signal.

As shown in FIG. 2, the portion of the second terminal 45A (source sense terminal 45A) covered by the sealing member 6 may be joined to the voltage detection wiring portion 35A (source sense wiring portion 35A). Since the voltage detection wiring portion 35A (source sense wiring portion 35A) is conductive to each of the second electrodes 112 (source electrodes 112) of the multiple first semiconductor elements 11, the second terminal 45A (source sense terminal 45A) may be conductive to each of the second electrodes 112 (source electrodes 112). The second terminal 45A may be an output terminal for the first detection signal.

2, the portion of the fifth terminal 45B (source sense terminal 45B) covered by the sealing member 6 may be joined to the voltage detection wiring portion 35B (source sense wiring portion 35B). Since the voltage detection wiring portion 35B (source sense wiring portion 35B) is conductive to each of the fifth electrodes 122 (source electrodes 122) of the multiple second semiconductor elements 12, the fifth terminal 45B (source sense terminal 45B) may be conductive to each of the fifth electrodes 122. The fifth terminal 45B (source sense terminal 45B) may be an output terminal for the second detection signal.

As shown in FIG. 2, the portions of the multiple signal terminals 49 that are covered by the sealing member 6 can be joined to the multiple signal wiring portions 39, respectively. The multiple signal terminals 49 can be non-conductive to the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12. The multiple signal terminals 49 can be non-connect terminals. The semiconductor device A1 can be configured without including the multiple signal terminals 49.

The multiple connection members 51A, 51B, 52A, 52B, 53A, 53B, 54A, and 54B can each electrically connect two parts that are separated from each other. In the semiconductor device A1, the multiple connection members 51A, 51B, 52A, 52B, 53A, 53B, 54A, and 54B can be bonding wires. The constituent material of each of the multiple connection members 51A, 51B, 52A, 52B, 53A, 53B, 54A, and 54B can include any of gold, copper, and aluminum.

The multiple connection members 51A, as shown in FIG. 2 and FIG. 5, are respectively bonded to the second electrodes 112 (source electrodes 112) and pad portions 331 of the multiple first semiconductor elements 11, and can electrically connect each second electrode 112 (source electrode 112) and the power wiring portion 33. In the semiconductor device A1, as shown in FIG. 2, multiple connection members 51A can be bonded to each second electrode 112 (source electrode 112). A main circuit current (first main circuit current) in the semiconductor device A1 can flow through the multiple connection members 51A. The connection members 51A bonded to each second electrode 112 (source electrode 112) do not have to be bonding wires. As an example, one metal (e.g., copper) plate-shaped member can be bonded to each second electrode 112.

The multiple connection members 51B may be bonded to the fifth electrodes 122 (source electrodes 122) and pad portions 321 of the multiple second semiconductor elements 12, respectively, as shown in FIG. 2 and FIG. 5, and may provide electrical continuity between each of the fifth electrodes 122 and the power wiring portion 32. In the semiconductor device A1, multiple connection members 51B may be bonded to each of the fifth electrodes 122, as shown in FIG. 2. A main circuit current (second main circuit current) in the semiconductor device A1 may flow through the multiple connection members 51B. The multiple connection members 51A bonded to each of the fifth electrodes 122 may not be bonding wires. As an example, a single metal (e.g., copper) plate-shaped member may be bonded to each of the fifth electrodes 122.

2, the multiple connection members 52A are respectively bonded to the third electrodes 113 (gate electrodes 113) of the multiple first semiconductor elements 11 and the multiple first portions 381 of the intermediate signal wiring portion 38A, and can mutually conduct the third electrodes 113 (gate electrodes 113) and the first portions 381 of the intermediate signal wiring portion 38A. As a result, each first portion 381 of the intermediate signal wiring portion 38A can be conductive to the third electrodes 113 (gate electrodes 113) of any of the multiple first semiconductor elements 11 via the connection members 52A. Hereinafter, the connection members 52A are referred to as third connection members 52A. When the third electrodes 113 are gate electrodes, the third connection members 52A may be referred to as gate connection members 52A.

2, the multiple connection members 52B are respectively joined to the sixth electrodes 123 (gate electrodes 123) of the multiple second semiconductor elements 12 and the multiple first portions 381 of the intermediate signal wiring portion 38B, and can mutually conduct the sixth electrodes 123 and the first portions 381 of the intermediate signal wiring portion 38B. As a result, each first portion 381 of the intermediate signal wiring portion 38B can be electrically connected to the sixth electrodes 123 of any of the multiple second semiconductor elements 12 via the connection members 52B. Hereinafter, the connection members 52B are referred to as sixth connection members 52B. When the sixth electrodes 123 are gate electrodes, the sixth connection members 52B may be referred to as gate connection members 52B.

2, the multiple connection members 53A are respectively joined to the multiple second parts 382 in the intermediate signal wiring portion 38A and the third wiring portion 34A (gate wiring portion 34A), and can mutually conduct the second part 382 of the intermediate signal wiring portion 38A and the third wiring portion 34A (gate wiring portion 34A). As a result, the third wiring portion 34A (gate wiring portion 34A) can be conductive to any of the second parts 382 of the intermediate signal wiring portion 38A via the connection members 53A. Hereinafter, the connection members 53A are referred to as first intermediate connection members 53A. The third wiring portion 34A (gate wiring portion 34A) can be conductive to the multiple third electrodes 113 (gate electrodes 113) via the multiple third connection members 52A (gate connection members 52A), the multiple first parts 381, the multiple resistance elements R1, the multiple second parts 382, and the multiple first intermediate connection members 53A. In FIG. 6, this conduction path is shown as a third conduction path Jg1 for the multiple first semiconductor elements 11. The third conduction path Jg1 may be a gate conduction path.

2, the multiple connection members 53B are respectively joined to the multiple second parts 382 in the intermediate signal wiring portion 38B and the sixth wiring portion 34B (gate wiring portion 34B), and can conduct the second part 382 of the intermediate signal wiring portion 38B and the sixth wiring portion 34B (gate wiring portion 34B). The sixth wiring portion 34B (gate wiring portion 34B) can be conducted to any of the second parts 382 of the intermediate signal wiring portion 38B via the connection members 53B. Hereinafter, the connection members 53B are referred to as first intermediate connection members 53B. The sixth wiring portion 34B (gate wiring portion 34B) can be conducted to the multiple sixth electrodes 123 via the multiple sixth connection members 52B (gate connection members 52B), the multiple first parts 381, the multiple resistance elements R2, the multiple second parts 382, and the multiple first intermediate connection members 53B. In FIG. 6, this conduction path is shown as a sixth conduction path Jg2 for the multiple second semiconductor elements 12. The sixth conduction path Jg2 may be a gate conduction path.

2, the multiple connection members 54A are respectively joined to the second electrodes 112 (source electrodes 112) and voltage detection wiring portion 35A (source sense wiring portion 35A) of the multiple first semiconductor elements 11, and can mutually conduct the second electrodes 112 (source electrodes 112) and the voltage detection wiring portion 35A (source sense wiring portion 35A). The voltage detection wiring portion 35A (source sense wiring portion 35A) can be electrically connected to the multiple second electrodes 112 (source electrodes 112) via the connection members 54A. Hereinafter, the connection members 54A are referred to as voltage detection connection members 54A. When the second electrodes 112 are source electrodes, the voltage detection connection members 54A may be referred to as source sense connection members 54A. The second terminal 45A (source sense terminal 45A) can be electrically connected to the multiple second electrodes 112 (source electrodes 112) via the voltage detection wiring section 35A (source sense wiring section 35A) and multiple voltage detection connection members 54A (source sense connection members 54A). In FIG. 6, this conductive path is shown as a second conductive path Js1 for the multiple first semiconductor elements 11. The second conductive path Js1 can be a source sense conductive path.

2, the multiple connection members 54B are respectively joined to the fifth electrodes 122 (source electrodes 122) and the voltage detection wiring portion 35B (source sense wiring portion 35B) of the multiple second semiconductor elements 12, and may mutually conduct the fifth electrodes 122 and the voltage detection wiring portion 35B (source sense wiring portion 35B). The voltage detection wiring portion 35B (source sense wiring portion 35B) may be conductive to the multiple fifth electrodes 122 via the connection members 54B. Hereinafter, the connection members 54B are referred to as voltage detection connection members 54B. When the fifth electrode 122 is a source electrode, the voltage detection connection member 54B may be referred to as source sense connection members 54B. The fifth terminal 45B (source sense terminal 45B) may be conductive to the multiple fifth electrodes 122 via the voltage detection wiring portion 35B (source sense wiring portion 35B) and the multiple voltage detection connection members 54B (source sense connection members 54B). In FIG. 6, this conduction path is shown as a fifth conduction path Js2 for the multiple second semiconductor elements 12. The fifth conduction path Js2 may be a source sense conduction path.

The capacitor element C1 can be connected across the multiple first parts 381 of the intermediate signal wiring section 38A and the voltage detection wiring section 35A (source sense wiring section 35A). The gate conduction paths and source sense conduction paths for the multiple first semiconductor elements 11 can be connected to each other by the capacitor element C1.

The capacitor element C2 can be connected across the multiple first parts 381 of the intermediate signal wiring section 38B and the voltage detection wiring section 35B (source sense wiring section 35B). The gate conduction paths and source sense conduction paths for the multiple second semiconductor elements 12 can be connected to each other by the capacitor element C2.

The specific configuration of the capacitor elements C1 and C2 is not limited in any way, and in the illustrated example, for example, a ceramic capacitor, an aluminum electrolytic capacitor, a tantalum electrolytic capacitor, etc. may be used. The capacitance of the capacitor elements C1 and C2 may be, for example, 0.1 nF or more and 10 nF or less.

The sealing member 6 can protect the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12. The sealing member 6 can cover the multiple first semiconductor elements 11, the multiple second semiconductor elements 12, a portion of the support substrate 2, a portion of each of the multiple power terminals 41 to 43, a portion of each of the multiple signal terminals 44A, 44B, 45A, 45B, 49, and the multiple connection members 51A, 51B, 52A, 52B, 53A, 53B, 54A, 54B. The sealing member 6 can include, for example, an insulating resin material. The insulating material can be, for example, an epoxy resin. The sealing member 6 can be, for example, black. The sealing member 6 can be rectangular in plan view. The sealing member 6 can have a resin main surface 61, a resin back surface 62, and multiple resin side surfaces 631 to 634.

The resin main surface 61 and the resin back surface 62 may be spaced apart from each other in the thickness direction z, as shown in Figures 3 to 5. The resin main surface 61 may face upward in the thickness direction z, and the resin back surface 62 may face downward in the thickness direction z. Each of the multiple resin side surfaces 631 to 634 may be sandwiched between the resin main surface 61 and the resin back surface 62 in the thickness direction z and connected to them. As shown in Figures 4 and 5, the pair of resin side surfaces 631, 632 may face opposite each other in the first direction x. Each of the power terminals 41, 42 may be configured to protrude from the resin side surface 632. The power terminal 43 may be configured to protrude from the resin side surface 631. As shown in Figure 5, the pair of resin side surfaces 633, 634 may face opposite each other in the second direction y. Each of the signal terminals 44A, 45A may be configured to protrude from the resin side surface 634. Each signal terminal 44B, 45B can be configured to protrude from the resin side surface 633.

The semiconductor device A1 can have the following functions and effects:

When multiple first semiconductor elements 11 are driven in parallel, electrical oscillation may occur in the conduction path connecting the multiple first semiconductor elements 11. The frequency of this oscillation may be, for example, several hundred MHz, higher than the frequency (for example, 10 Hz to several hundred Hz) of the gate signal applied to the third electrode 113 (gate electrode 113). In the semiconductor device A1, as shown in FIG. 6, a capacitor element C1 may be provided that connects the third conduction path Jg1 (gate conduction path Jg1) and the second conduction path Js1 (source sense conduction path Js1) to each other. As a result, the semiconductor device A1 may include a passive low-pass filter. By setting the cutoff frequency of this low-pass filter higher than the frequency of the gate signal and lower than the frequency of the possible oscillation, the gate signal may be appropriately passed while the oscillation may be reduced.

A capacitor element C2 may be provided to connect the sixth conduction path Jg2 (gate conduction path Jg2) and the fifth conduction path Js2 (source sense conduction path Js2) of the multiple second semiconductor elements 12 to each other. This allows the gate signal of the second semiconductor elements 12 to pass through appropriately while reducing the oscillation phenomenon.

The semiconductor device A1 may include a resistor element R1. By including the resistor element R1 and the capacitor element C1, the cutoff frequency of the low-pass filter for the multiple first semiconductor elements 11 may be set with high precision over a wide range. By including the semiconductor device A2 with the resistor element R2, the cutoff frequency of the low-pass filter for the multiple second semiconductor elements 12 may be set with high precision over a wider range.

2, in this embodiment, the resistor element R1 may be arranged to straddle the first portion 381 and the second portion 382 of the intermediate signal wiring portion 38A. The capacitor element C1 may be arranged to straddle the first portion 381 and the voltage detection wiring portion 35A (source sense wiring portion 35A). The intermediate signal wiring portion 38A may be arranged between the pad portion 311 of the power wiring portion 31 and the voltage detection wiring portion 35A (source sense wiring portion 35A) in the second direction y. The resistor elements R1 and the capacitor elements C1 may be arranged in a position close to the first semiconductor elements 11. For example, the length of the conductive path from the first semiconductor elements 11 to the resistor elements R1 and the capacitor elements C1 may be shorter than the length of the conductive path from the resistor elements R1 and the capacitor elements C1 to the third terminal 44A (gate terminal 44A) and the second terminal 45A (source sense terminal 45A). This may reduce the oscillation phenomenon.

By arranging the multiple resistance elements R2 and multiple capacitor elements C2 between the pad portion 321 of the power wiring portion 32 and the voltage detection wiring portion 35B (source sense wiring portion 35B), the multiple resistance elements R2 and multiple capacitor elements C2 can be arranged in a position close to the multiple second semiconductor elements 12. For example, the length of the conductive path from the multiple second semiconductor elements 12 to the multiple resistance elements R2 and multiple capacitor elements C2 can be made shorter than the length of the conductive path from the multiple resistance elements R2 and multiple capacitor elements C2 to the sixth terminal 44B (gate terminal 44B) and the fifth terminal 45B (source sense terminal 45B). This can more reliably reduce the oscillation phenomenon.

FIGS. 7 to 27 show modified examples and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals as in the above-described embodiment. The configurations of the various parts in each modified example and each embodiment can be combined with each other to the extent that no technical contradictions arise.

First Modification of First Embodiment:
7 shows a first modified example of the semiconductor device A1. In the semiconductor device A11 of this modification, the arrangement of the third wiring portion 34A (gate wiring portion 34A), the voltage detection wiring portion 35A (source sense wiring portion 35A), the intermediate signal wiring portion 38A, the first intermediate connection member 53A, the multiple resistor elements R1, and the multiple capacitor elements C1 for the multiple first semiconductor elements 11 may be different from that of the above-mentioned example.

The third wiring portion 34A (gate wiring portion 34A) may be disposed between the intermediate signal wiring portion 38A and the voltage detection wiring portion 35A (source sense wiring portion 35A) in the second direction y. The resistive element R1 may be disposed so as to straddle the first portion 381 and the third wiring portion 34A (gate wiring portion 34A). The capacitor element C1 may be disposed so as to straddle the first portion 381 and the second portion 382. The first intermediate connection member 53A may be connected to the second portion 382 and the voltage detection wiring portion 35A (source sense wiring portion 35A). The sixth wiring portion 34B (gate wiring portion 34B), the voltage detection wiring portion 35B (source sense wiring portion 35B), the intermediate signal wiring portion 38B, the first intermediate connection member 53B, the multiple resistive elements R2, and the multiple capacitor elements C2 may be disposed in the same manner for the multiple second semiconductor elements 12.

The semiconductor device A11 has a circuit configuration similar to that of the semiconductor device A1 shown in FIG. 6.

This modified example can reduce the oscillation phenomenon that occurs when multiple first semiconductor elements 11 and multiple second semiconductor elements 12 are driven in parallel. The arrangement of the multiple resistive elements R1, R2 and the multiple resistive elements C1, C2 is not limited in any way.

Second Modification of First Embodiment:
8 shows a second modification of the semiconductor device A1. In the semiconductor device A12 of this modification, the intermediate signal wiring portions 38A, 38B may include a first portion 381, a second portion 382, and a third portion 383. The semiconductor device A12 may include a plurality of second intermediate connection members 55A, 55B.

The first portion 381, the second portion 382, and the third portion 383 may be aligned in the first direction x and spaced apart from each other. The third portion 383 may be located between the first portion 381 and the second portion 382. The resistive elements R1 and R2 may be connected to straddle the first portion 381 and the third portion 383. The capacitor elements C1 and C2 may be connected to straddle the second portion 382 and the third portion 383. The third connection member 52A (gate connection member 52A) and the sixth connection member 52B (gate connection member 52B) may be connected to the third portion 383. The first intermediate connection members 53A and 53B may be connected to the signal wiring portion 391, the third wiring portion 34A (gate wiring portion 34A), and the sixth wiring portion 34B (gate wiring portion 34B). The second intermediate connection members 55A and 55B can be connected to the second portion 382, the voltage detection wiring portion 35A (source sense wiring portion 35A), and the voltage detection wiring portion 35B (source sense wiring portion 35B).

The semiconductor device A12 may have a circuit configuration similar to the circuit configuration diagram of the semiconductor device A1 shown in FIG. 6.

This modified example can reduce the oscillation phenomenon that occurs when multiple first semiconductor elements 11 and multiple second semiconductor elements 12 are driven in parallel. There are no limitations on the arrangement of the multiple resistive elements R1, R2 and multiple resistive elements C1, C2, or the configuration of the intermediate signal wiring sections 38A, 38B.

Third Modification of First Embodiment:
9 shows a third modification of the semiconductor device A13. The semiconductor device A13 of this modification may differ from the above-described examples in the configurations of the resistor element R1 and the intermediate signal wiring portions 38A and 38B.

The resistor elements R1 and R2 can be made of wire. The wire that makes up the resistor element R1 can be made of a material with a high resistance value. Such a material can be, for example, constantan, Ni-Cr (nickel-chromium alloy), alumel, chromel, etc.

The semiconductor device A13 may have a circuit configuration similar to the circuit configuration diagram of the semiconductor device A1 shown in FIG. 6.

This modified example can reduce the oscillation phenomenon that occurs when multiple first semiconductor elements 11 and multiple second semiconductor elements 12 are driven in parallel. The specific configuration of the multiple resistance elements R1 and R2 is not limited in any way.

Fourth Modification of First Embodiment:
10 shows a fourth modification of the semiconductor device A14. A semiconductor device A14 of this modification can differ from the above-described examples in that it includes a plurality of element packages P1 and P2.

FIG. 11 shows an example of the configuration of element packages P1 and P2. The element packages P1 and P2 may include built-in resistor elements R1 and R2 and capacitor elements C1 and C2, and may include electrodes 81, 82, and 83 and a sealing resin 80.

The resistance elements R1 and R2 may be, for example, chip resistors. The capacitor elements C1 and C2 may be, for example, ceramic capacitors. The sealing resin 80 may cover the resistance elements R1 and R2 and the capacitor elements C1 and C2. A wiring pattern that is conductive to the resistance elements R1 and R2 and the capacitor elements C1 and C2 may be formed in the sealing resin 80 by, for example, plating. The resistance elements R1 and R2 may be electrically connected between the electrodes 81 and 82. The capacitor elements C1 and C2 may be electrically connected between the electrodes 81 and 83. The third connection member 52A (gate connection member 52A) and the sixth connection member 52B (gate connection member 52B) may be connected to the electrode 81, and the first intermediate connection members 53A and 53B may be connected to the electrode 82. The electrode 83 can be conductively connected to the voltage detection wiring section 35A (source sense wiring section 35A) and the voltage detection wiring section 35B (source sense wiring section 35B).

The semiconductor device A14 may have a circuit configuration similar to that of the semiconductor device A1 shown in FIG. 6.

This modified example can reduce the oscillation phenomenon that occurs when multiple first semiconductor elements 11 and multiple second semiconductor elements 12 are driven in parallel. The multiple resistance elements R1, R2 and multiple capacitor elements C1, C2 are not limited to being configured as individual electronic elements, but can be configured as an integrated package such as element packages P1, P2. By adopting element packages P1, P2, the semiconductor device A14 can be made smaller.

FIG. 12 shows another example of element packages P1, P2. In this example, the element packages P1, P2 may be configured so as not to incorporate chip resistors for forming resistance elements R1, R2 or ceramic capacitors for forming capacitor elements C1, C2. The resistance elements R1, R2 may be formed by providing a material with a high resistance value, for example, using a technique for forming a rewiring layer on a semiconductor layer. The capacitor elements C1, C2 may be formed by stacking dielectric layers and metal layers using the rewiring technique described above.

The specific configuration of element packages P1 and P2 is not limited in any way.

Second embodiment:
13 to 18 show a semiconductor device A2 according to a second embodiment. As shown in the figures, the semiconductor device A2 may include a plurality of first semiconductor elements 11, a plurality of second semiconductor elements 12, a support substrate 2, a plurality of terminals, a plurality of resistor elements R1, a plurality of capacitor elements C1, a plurality of connecting members, and a sealing member 6. The plurality of terminals may include a plurality of power terminals 41 to 43 and a plurality of signal terminals 44A, 44B, 45A, 45B, 46, 49. The plurality of connecting members may include a plurality of connecting members 52A, 52B, 53A, 53B, 54A, 54B, 56, and a plurality of connecting members 58A, 58B.

In semiconductor device A2, the support substrate 2 may include an insulating substrate 20, a main surface metal layer 21, a back surface metal layer 22, a pair of conductive substrates 23A, 23B, and a pair of signal substrates 24A, 24B. The support substrate 2 may be configured such that the pair of conductive substrates 23A, 23B and the pair of signal substrates 24A, 24B are disposed on a DBC substrate (or a DBA substrate, an AMB substrate). The DBC substrate (or DBA substrate) may be configured, like semiconductor device A1, with an insulating substrate 20, a pair of main surface metal layers 21A, 21B, and a back surface metal layer 22.

The pair of main surface metal layers 21A, 21B may each be formed on the substrate main surface 20a of the insulating substrate 20, as shown in FIG. 18. The pair of main surface metal layers 21A, 21B may be spaced apart in the first direction x. A conductive substrate 23A may be bonded to the main surface metal layer 21A, and a conductive substrate 23B may be bonded to the main surface metal layer 21B. Each of the pair of main surface metal layers 21A, 21B may be, for example, rectangular in plan view.

Each of the pair of conductive substrates 23A, 23B may be made of a metal. The metal may be copper or a copper alloy, or aluminum or an aluminum alloy, etc.

The conductive substrate 23A may be disposed on the main surface metal layer 21A as shown in FIG. 18. The conductive substrate 23A may have a plurality of first semiconductor elements 11 mounted thereon as shown in FIG. 18. As shown in FIG. 15, the plurality of first semiconductor elements 11 of the semiconductor device A2 may be disposed on the conductive substrate 23A along the second direction y. The conductive substrate 23A may face the first element rear surfaces 11b of the plurality of first semiconductor elements 11. The conductive substrate 23A may be conductively bonded to the first electrodes 111 (drain electrodes 111) of the plurality of first semiconductor elements 11. The first electrodes 111 (drain electrodes 111) of the plurality of first semiconductor elements 11 may be electrically connected to each other via the conductive substrate 23A.

The conductive substrate 23B may be disposed on the main surface metal layer 21B as shown in FIG. 18. A plurality of second semiconductor elements 12 may be mounted on the conductive substrate 23B as shown in FIG. 18. As shown in FIG. 15, the plurality of second semiconductor elements 12 of the semiconductor device A2 may be disposed on the conductive substrate 23B along the second direction y. The conductive substrate 23B may face the second element rear surfaces 12b of the plurality of second semiconductor elements 12. The conductive substrate 23B may be conductively joined to the fourth electrodes 121 (drain electrodes 121) of the plurality of second semiconductor elements 12. The fourth electrodes 121 of the plurality of second semiconductor elements 12 may be electrically connected to each other via the conductive substrate 23B.

The pair of signal boards 24A, 24B can support a plurality of signal terminals 44A, 44B, 45A, 45B, 46, 49. As shown in FIG. 18, the pair of signal boards 24A, 24B can be interposed between the pair of conductive boards 23A, 23B and the plurality of signal terminals 44A, 44B, 45A, 45B, 46, 49 in the thickness direction z. Each of the pair of signal boards 24A, 24B can be formed, for example, by a DBC board. In contrast to this configuration, each of the pair of signal boards 24A, 24B can be formed, for example, by a DBA board or an AMB board. Each of the pair of signal boards 24A, 24B can be formed, for example, by a printed board, rather than a DBC board or a DBA board.

The signal board 24A may be disposed on the conductive board 23A as shown in FIG. 18. The signal board 24A may support a plurality of signal terminals 44A, 45A, 46, and 49. The signal board 24A may be bonded to the conductive board 23A via a bonding material. The bonding material may be conductive or insulating. As an example, the bonding material may be solder. The signal board 24B may be disposed on the conductive board 23B as shown in FIG. 18. The signal board 24B may support a plurality of signal terminals 44B, 45B, and 49. The signal board 24B may be bonded to the conductive board 23B via a bonding material. The bonding material may be conductive or insulating. As an example, the bonding material may be solder.

As shown in FIG. 18, each of the pair of signal boards 24A, 24B may include an insulating substrate 241, a main surface metal layer 242, and a back surface metal layer 243. Unless otherwise specified, the following description of the insulating substrate 241, the main surface metal layer 242, and the back surface metal layer 243 may be common to the pair of signal boards 24A, 24B.

The insulating substrate 241 may be made of, for example, ceramic. The ceramic may be, for example, AlN, _SiN , or _Al2O3 . The insulating substrate 241 may be, for example, rectangular in plan view. As shown in FIG. 18, the insulating substrate 241 may have a main surface 241a and a back surface 241b. The main surface 241a and the back surface 241b may be spaced apart in the thickness direction z. The main surface 241a may face upward in the thickness direction z, and the back surface 241b may face downward in the thickness direction z. The main surface 241a and the back surface 241b may be flat (or approximately flat).

The back metal layer 243 may be formed on the back surface 241b of the insulating substrate 241, as shown in FIG. 18. The back metal layer 243 of the signal substrate 24A may be bonded to the conductive substrate 23A via a bonding material. The back metal layer 243 of the signal substrate 24B may be bonded to the conductive substrate 23B via a bonding material. The constituent material of the back metal layer 243 may be, for example, copper or a copper alloy. The constituent material may be aluminum or an aluminum alloy, rather than copper or a copper alloy.

The main surface metal layer 242 may be formed on the main surface 241a of the insulating substrate 241, as shown in FIG. 18. Each of the multiple signal terminals 44A, 44B, 45A, 45B, 46, and 49 may be provided upright on the main surface metal layer 242 of one of the pair of signal substrates 24A and 24B. The constituent material of the main surface metal layer 242 may be, for example, copper or a copper alloy. The constituent material may be aluminum or an aluminum alloy, rather than copper or a copper alloy.

The main surface metal layer 242 of the signal board 24A may include a plurality of signal wiring portions 34A, 35A, 36, 38A, and 39, as shown in Figures 15 and 16. The main surface metal layer 242 of the signal board 24B may include a plurality of signal wiring portions 34B, 35B, 38B, and 39, as shown in Figures 15 and 17.

The signal wiring portion 36 is joined to a connection member 56 and can be electrically connected to the conductive substrate 23A via the connection member 56. The conductive substrate 23A can be electrically connected to the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11. The signal wiring portion 36 can be electrically connected to the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11.

The power terminal 41 may be formed integrally with the conductive substrate 23A. Alternatively, the power terminal 41 may be joined to the conductive substrate 23A. The power terminal 41 may have a smaller dimension in the thickness direction z than the conductive substrate 23A. The power terminal 41 may be configured to extend from the conductive substrate 23A to one side in the first direction x. The one side in the first direction x may be the side of the conductive substrate 23A opposite to the side on which the conductive substrate 23B is located. The power terminal 41 may be configured to protrude from the resin side surface 632. The power terminal 41 may be electrically connected to the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11 via the conductive substrate 23A.

The two power terminals 42 may be spaced apart from the conductive substrate 23A. The two power terminals 42 may be arranged on opposite sides of the power terminal 41 in the second direction y. The two power terminals 42 may be arranged on one side of the conductive substrate 23A in the first direction x. The one side of the first direction x may be the side on which the power terminal 41 is located with respect to the conductive substrate 23A. The two power terminals 42 may be configured to protrude from the resin side surface 632. A connection member 58B may be joined to each of the two power terminals 42. The two power terminals 42 may be electrically connected to the fifth electrodes 122 (source electrodes 122) of the multiple second semiconductor elements 12 via the connection member 58B.

The two power terminals 43 may each be formed integrally with the conductive substrate 23B. Alternatively, the two power terminals 43 may each be joined to the conductive substrate 23B. The two power terminals 43 may each have a smaller dimension in the thickness direction z than the conductive substrate 23B. The two power terminals 43 may each be configured to extend from the conductive substrate 23B to the other side in the first direction x. The other side in the first direction x may be the opposite side of the conductive substrate 23B to the side on which the conductive substrate 23A is located. The two power terminals 43 may each be configured to protrude from the resin side surface 631. The two power terminals 43 may each be electrically connected to the second electrodes 112 (source electrodes 112) of the multiple first semiconductor elements 11 and the fourth electrodes 121 (drain electrodes 121) of the multiple second semiconductor elements 12 via the conductive substrate 23B.

The signal terminals 44A, 44B, 45A, 45B, 46, and 49 may each be configured to protrude from the resin main surface 61 as shown in FIG. 13. The signal terminals 44A, 44B, 45A, 45B, 46, and 49 may each be, for example, a press-fit terminal. The signal terminals 44A, 44B, 45A, 45B, 46, and 49 may each include a holder and a metal pin. The holder may be a cylindrical member made of a conductive material. The holder may be joined to the main surface metal layer 242 of the signal board 24A or the signal board 24B. The metal pin may be configured to be pressed into the holder and extend in the thickness direction z.

The signal terminal 46 can be provided upright on the signal wiring portion 36. The signal terminal 46 can be electrically connected to the signal wiring portion 36. The signal wiring portion 36 can be electrically connected to the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11. The signal terminal 46 can be electrically connected to the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11.

The multiple signal terminals 49 can be provided upright on the signal wiring portion 39. The multiple signal terminals 49 can be non-conductive to the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12. Each of the multiple signal terminals 49 can be a non-connect terminal.

The connection member 56 may be, for example, a bonding wire. The material of the bonding wire may be any of gold, copper, or aluminum. As shown in FIG. 15, the connection member 56 may be joined to the signal wiring portion 36 and the conductive substrate 23A, and may provide electrical conductivity between them.

The multiple connection members 58A, 58B, together with the support substrate 2, can form a path for a main circuit current that is switched by the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12. The multiple connection members 58A, 58B can be formed of a metal plate-shaped member. The metal can be, for example, copper or a copper alloy. The multiple connection members 58A, 58B can have a partially bent shape.

The multiple connection members 58A can be bonded to the second electrodes 112 (source electrodes 112) of the multiple first semiconductor elements 11 and the conductive substrate 23B. The second electrodes 112 (source electrodes 112) of the multiple first semiconductor elements 11 and the conductive substrate 23B can be mutually conductive. The connection members 58A and the second electrodes 112 (source electrodes 112) of the multiple first semiconductor elements 11 can be bonded by a conductive bonding material (for example, solder, metal paste material, sintered metal, etc.). The connection members 58A and the conductive substrate 23B can be bonded by a conductive bonding material (for example, solder, metal paste material, sintered metal, etc.). Each connection member 58A can be a strip extending in the first direction x in a plan view, as shown in FIG. 15.

The number of connection members 58A may be the same as the number of first semiconductor elements 11. In the example shown in the figure, the number of connection members 58A is three, but the present disclosure is not limited to this. In a variation from this configuration, the number of connection members 58A may be different from the number of first semiconductor elements 11. As an example, for example, one connection member 58A may be used for multiple first semiconductor elements 11.

The connection member 58B can mutually connect the fifth electrodes 122 (source electrodes 122) of the multiple second semiconductor elements 12 and the power terminals 42. As shown in FIG. 14, the connection member 58B can include a pair of first wiring portions 581B, a second wiring portion 582B, a third wiring portion 583B, and multiple fourth wiring portions 584B.

One of the pair of first wiring portions 581B may be connected to one of the pair of power terminals 42, and the other of the pair of first wiring portions 581B may be connected to the other of the pair of power terminals 42. Each of the first wiring portions 581B and each of the power terminals 42 may be joined by a conductive bonding material (e.g., solder, a metal paste material, or a sintered metal). As shown in FIG. 14, each of the pair of first wiring portions 581B may be in the shape of a strip extending in the first direction x in a plan view. The pair of first wiring portions 581B may be spaced apart from each other in the second direction y and arranged parallel to each other (or approximately parallel to each other).

The second wiring portion 582B may be connected to both of the pair of first wiring portions 581B as shown in FIG. 14. The second wiring portion 582B may be in the shape of a strip extending in the second direction y in a planar view. As can be understood from FIG. 14 and FIG. 18, the second wiring portion 582B may overlap with a plurality of second semiconductor elements 12 in a planar view. The second wiring portion 582B may be connected to each second semiconductor element 12 (fifth electrode 122) as shown in FIG. 18. The second wiring portion 582B may have a portion that overlaps with each second semiconductor element 12 in a planar view. This overlapping portion may have a configuration that protrudes downward in the thickness direction z more than other portions. The downward protruding portion of the second wiring portion 582B may be joined to each fifth electrode 122 of the plurality of second semiconductor elements 12. The second wiring portion 582B and each of the fifth electrodes 122 can be joined to each other, for example, by a conductive bonding material (for example, solder, a metal paste material, or a sintered metal).

The third wiring portion 583B may be connected to both of the pair of first wiring portions 581B, as shown in FIG. 14. The third wiring portion 583B may be in the shape of a band extending in the second direction y in a planar view. The third wiring portion 583B may be separated from the second wiring portion 582B in the first direction x. The third wiring portion 583B may be positioned parallel to (or approximately parallel to) the second wiring portion 582B. As can be understood from FIG. 14 and FIG. 18, the third wiring portion 583B may overlap a plurality of first semiconductor elements 11 in a planar view. The third wiring portion 583B may be configured such that the portions overlapping each first semiconductor element 11 in a planar view protrude upward in the thickness direction z from the other portions. This portion protruding upward in the thickness direction z forms an area on each first semiconductor element 11 where each connection member 58A is bonded, which can reduce contact between the third wiring portion 583B and each connection member 58A.

As shown in FIG. 14, each of the multiple fourth wiring parts 584B may be connected to both the second wiring part 582B and the third wiring part 583B. Each of the multiple fourth wiring parts 584B may be in the shape of a strip extending in the first direction x in a plan view. The multiple fourth wiring parts 584B may be spaced apart in the second direction y and arranged parallel (or approximately parallel) in a plan view. Each of the multiple fourth wiring parts 584B may have one end and the other end in the first direction x. The one end may be connected to a portion of the third wiring part 583B that overlaps between two first semiconductor elements 11 adjacent to each other in the second direction y in a plan view. The other end may be connected to a portion of the second wiring part 582B that overlaps between two second semiconductor elements 12 adjacent to each other in the second direction y in a plan view.

As shown in FIG. 16, the semiconductor device A2 may have the same configuration as the semiconductor device A1 in terms of the multiple resistor elements R1, multiple capacitor elements C1, multiple third connection members 52A (gate connection members 52A), multiple voltage detection connection members 54A (source sense connection members 54A), multiple first intermediate connection members 53A, third wiring portion 34A (gate wiring portion 34A), voltage detection wiring portion 35A (source sense wiring portion 35A) and intermediate signal wiring portion 38A. As a result, the semiconductor device A2 may have the third conduction path Jg1 (gate conduction path Jg1) and the second conduction path Js1 (source sense conduction path Js1) shown in FIG. 6.

As shown in FIG. 17, the semiconductor device A2 may have the same configuration as the semiconductor device A1 in terms of the multiple resistor elements R2, multiple capacitor elements C2, multiple sixth connection members 52B (gate connection members 52B), multiple voltage detection connection members 54B (source sense connection members 54B), multiple first intermediate connection members 53B, sixth wiring portion 34B (gate wiring portion 34B), voltage detection wiring portion 35B (source sense wiring portion 35B) and intermediate signal wiring portion 38B. As a result, the semiconductor device A2 may have the sixth conduction path Jg2 (gate conduction path Jg2) and the fifth conduction path Js2 (source sense conduction path Js2) shown in FIG. 6.

The semiconductor device A2 can reduce the oscillation phenomenon that occurs when multiple first semiconductor elements 11 and multiple second semiconductor elements 12 are operated in parallel. As a modified example of the semiconductor device A2, the configurations of the above-mentioned semiconductor devices A11 to A14 can be appropriately adopted.

Third embodiment:
19 to 25 show a semiconductor device A3 according to a third embodiment. As shown in the figures, the semiconductor device A3 may include a plurality of first semiconductor elements 11, a plurality of second semiconductor elements 12, a support substrate 2, a plurality of terminals, a plurality of connection members, a plurality of resistor elements R1, a plurality of capacitor elements C1, a heat sink 70, a case 71, and a resin member 75. The plurality of terminals may include a plurality of power terminals 41 to 43 and a plurality of signal terminals 44A, 44B, 45A, 45B, 46, and 47. The plurality of connection members may include a plurality of connection members 51A, 51B, 52A, 52B, 53A, 53B, 54A, 54B, 551A, 551B, 552A, 552B, 56, and 57.

In the first and second embodiments, an example was shown in which a resin mold type module structure was used in which a plurality of first semiconductor elements 11 and a plurality of second semiconductor elements 12 were covered with a sealing member 6. In contrast, the semiconductor device A3 can be a case type module structure in which a plurality of first semiconductor elements 11 and a plurality of second semiconductor elements 12 are housed in a case 71.

As can be seen from Figs. 19 to 25, the case 71 may be, for example, a rectangular parallelepiped. The case 71 is made of a synthetic resin that has electrical insulation properties and excellent heat resistance, for example, PPS (polyphenylene sulfide). The case 71 may be rectangular and have the same (or approximately the same) size as the heat sink 70 in a plan view. The case 71 may include a frame portion 72, a top plate 73, and a plurality of terminal blocks 741 to 744.

The frame 72 may be fixed to the upper surface of the heat sink 70 in the thickness direction z. The top plate 73 may be fixed to the frame 72. As shown in Figures 19, 21, 22, and 25, the top plate 73 may close the opening of the frame 72 on the upper side in the thickness direction z. As shown in Figures 21, 22, and 25, the top plate 73 may face the heat sink 70 that closes the lower side of the frame 72 in the thickness direction z. The top plate 73, the heat sink 70, and the frame 72 may partition a circuit accommodating space inside the case 71. The circuit accommodating space may accommodate a plurality of first semiconductor elements 11, a plurality of second semiconductor elements 12, and the like. Hereinafter, this circuit accommodating space may be referred to as the inside of the case 71.

The two terminal blocks 741, 742 may be arranged on one side of the frame portion 72 in the first direction x and may be formed integrally with the frame portion 72. The two terminal blocks 743, 744 may be arranged on the other side of the frame portion 72 in the first direction x and may be formed integrally with the frame portion 72. The two terminal blocks 741, 742 may be arranged along the second direction y against the side wall of the frame portion 72 on one side in the first direction x. The terminal block 741 may cover a portion of the power terminal 41. As shown in FIG. 19, the terminal block 741 may have a portion of the power terminal 41 arranged on the upper surface of the terminal block 741 in the thickness direction z. The terminal block 742 may cover a portion of the power terminal 42. As shown in FIG. 19, the terminal block 742 may have a portion of the power terminal 42 arranged on the upper surface of the terminal block 742 in the thickness direction z. The two terminal blocks 743, 744 may be arranged along the second direction y on the side wall of the frame portion 72 on the other side in the first direction x. The terminal block 743 may cover a portion of one of the two power terminals 43. As shown in FIG. 19 , a portion of this power terminal 43 may be arranged on the upper surface of the terminal block 743 in the thickness direction z. The terminal block 744 may cover a portion of the other of the two power terminals 43. As shown in FIG. 19 , a portion of this power terminal 43 may be arranged on the upper surface of the terminal block 744 in the thickness direction z.

As shown in Figures 21, 22 and 25, the resin member 75 may be filled into the area surrounded by the top plate 73, the heat sink 70 and the frame portion 72. This area may be the circuit accommodating space. The resin member 75 may cover the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12. The resin member 75 may be made of, for example, black epoxy resin. The material of the resin member 75 may not be epoxy resin, but may be other insulating materials such as silicone gel. The semiconductor device A3 is not limited to a configuration that includes the resin member 75, and may be configured without the resin member 75. In a configuration that includes the resin member 75, the case 71 may be configured without including the top plate 73.

The support substrate 2 of the semiconductor device A3 can be bonded to the heat sink 70. The support substrate 2 of the semiconductor device A3 can include an insulating substrate 20 and a main surface metal layer 21. Alternatively, the support substrate 2 can include a back surface metal layer 22.

The main surface metal layer 21 may include a plurality of power wiring sections 31-33 and a plurality of signal wiring sections 34A, 34B, 35A, 35B, 37, 38A, 38B. Compared to the main surface metal layer 21 of the semiconductor device A1, the main surface metal layer 21 of the semiconductor device A3 may further include a signal wiring section 37.

The pair of signal wiring portions 37 may be spaced apart from each other in the second direction y, as shown in FIG. 20. A thermistor 91 may be bonded to each of the pair of signal wiring portions 37, for example. The thermistor 91 may be disposed across the pair of signal wiring portions 37. In an example different from the semiconductor device A3, the thermistor 91 may not be bonded to the pair of signal wiring portions 37. As shown in FIG. 20, the pair of signal wiring portions 37 may be located near the corners of the insulating substrate 20. The pair of signal wiring portions 37 may be located between the pad portion 311 and the two signal wiring portions 34A, 35A in the first direction x.

The power wiring section 31 of the semiconductor device A3 includes two pad sections 311, 312, similar to the power wiring section 31 of the semiconductor device A1, and may include an extension section 313, unlike the power wiring section 31 of the semiconductor device A1. As shown in FIG. 20, the extension section 313 may be configured to extend in the second direction y from the end of the pad section 311 on the other side in the first direction x (the side opposite to the side where the power terminal 41 is located). In the example shown in FIG. 20, the extension section 313 may be located between the pad section 332 (power wiring section 33) and each of the signal wiring sections 34A, 35A, 38A in a plan view.

As shown in FIG. 20, a slit 321s may be formed in the pad portion 321 of the power wiring portion 32. In a plan view, the slit 321s may extend along the first direction x from an edge of the pad portion 321 on one side in the first direction x (the side on which the pad portion 322 is located) as a base end. The tip of the slit 321s may be located in the center of the pad portion 321 in the first direction x.

20, the signal terminal 46 may be joined to a connection member 56. The signal terminal 47 may be electrically connected to the power wiring section 31 via the connection member 56. The signal terminal 46 may be electrically connected to each of the first electrodes 111 (drain electrodes 111) of the first semiconductor elements 11. The signal terminal 46 may be an output terminal for a third detection signal. The third detection signal may be a voltage signal corresponding to a current flowing through the power wiring section 31. As an example, the current may be a drain current flowing through each of the first electrodes 111 (drain electrodes 111) of the first semiconductor elements 11. The signal terminal 46 may be a press-fit terminal. Alternatively, the signal terminal 46 may be a pin-shaped metal member, similar to the other signal terminals 44A, 44B, 45A, 45B, etc.

As shown in FIG. 20, each of the pair of signal terminals 47 may be joined to a pair of connecting members 57. The pair of signal terminals 47 may be electrically connected to a pair of signal wiring portions 37 via the pair of connecting members 57. The pair of signal terminals 47 may be electrically connected to a thermistor 91. The pair of signal terminals 47 may be terminals for detecting the temperature inside the case 71. When the thermistor 91 is not joined to the pair of signal wiring portions 37, the pair of signal terminals 47 may be non-connect terminals.

As shown in Figures 20 and 25, the connection member 551A can be joined to the third wiring portion 34A (gate wiring portion 34A) and the third terminal 44A (gate terminal 44A) to provide electrical continuity between them. The third wiring portion 34A (gate wiring portion 34A) and the third terminal 44A (gate terminal 44A) can be connected to each other via the connection member 551A.

As shown in Figures 20 and 25, the connection member 551B is joined to the sixth wiring portion 34B (gate wiring portion 34B) and the sixth terminal 44B (gate terminal 44B), and can provide electrical conductivity between them. The sixth wiring portion 34B (gate wiring portion 34B) and the sixth terminal 44B (gate terminal 44B) can be connected to each other via the connection member 551B.

As shown in FIG. 20, the connection member 552A can be joined to the voltage detection wiring portion 35A (source sense wiring portion 35A) and the second terminal 45A (source sense terminal 45A) to make them conductive to each other. The voltage detection wiring portion 35A (source sense wiring portion 35A) and the second terminal 45A (source sense terminal 45A) can be connected to each other via the connection member 552A.

As shown in FIG. 20, the connection member 552B is joined to the voltage detection wiring portion 35B (source sense wiring portion 35B) and the fifth terminal 45B (source sense terminal 45B), and can make them conductive to each other. The voltage detection wiring portion 35B (source sense wiring portion 35B) and the fifth terminal 45B (source sense terminal 45B) can be connected to each other via the connection member 552B.

20, the connection member 56 is joined to the extension 313 and the signal terminal 46, and can electrically connect the power wiring portion 31 and the signal terminal 46 to each other. The signal terminal 46 can be electrically connected to each of the first electrodes 111 (drain electrodes 111) of the multiple first semiconductor elements 11 via the connection member 56 and the power wiring portion 31.

As shown in FIG. 20, the pair of connection members 57 are respectively joined to the pair of signal wiring portions 37 and the pair of signal terminals 47, and can provide electrical conductivity between them. The pair of signal terminals 47 can be electrically connected to the thermistor 91 via the pair of connection members 57 and the pair of signal wiring portions 37. If the thermistor 91 is not joined to the pair of signal wiring portions 37, the pair of connection members 57 may not be necessary.

As shown in FIG. 20, the semiconductor device A3 may have the same configuration as the semiconductor device A1 in terms of the multiple resistor elements R1, multiple capacitor elements C1, multiple third connection members 52A (gate connection members 52A), multiple voltage detection connection members 54A (source sense connection members 54A), multiple first intermediate connection members 53A, third wiring portion 34A (gate wiring portion 34A), voltage detection wiring portion 35A (source sense wiring portion 35A) and intermediate signal wiring portion 38A. The semiconductor device A3 may have the third conduction path Jg1 (gate conduction path Jg1) and the second conduction path Js1 (source sense conduction path Js1) shown in FIG. 6.

As shown in FIG. 20, the semiconductor device A3 may have the same configuration as the semiconductor device A1 in terms of the multiple resistor elements R2, multiple capacitor elements C2, multiple sixth connection members 52B (gate connection members 52B), multiple voltage detection connection members 54B (source sense connection members 54B), multiple first intermediate connection members 53B, sixth wiring portion 34B (gate wiring portion 34B), voltage detection wiring portion 35B (source sense wiring portion 35B) and intermediate signal wiring portion 38B. The semiconductor device A3 may have the sixth conduction path Jg2 (gate conduction path Jg2) and the fifth conduction path Js2 (source sense conduction path Js2) shown in FIG. 6.

The semiconductor device A3 can reduce the oscillation phenomenon that occurs when multiple first semiconductor elements 11 and multiple second semiconductor elements 12 are operated in parallel. As a modified example of the semiconductor device A3, the configurations of the above-mentioned semiconductor devices A11 to A14 can be appropriately adopted.

Third embodiment, first modification:
26 and 27 show a first modified example of the semiconductor device A3. In the semiconductor device A31 of this modification, the numbers of the resistor elements R1, R2 and the capacitor elements C1, C2 provided for one first semiconductor element 11 and one second semiconductor element 12 may be different from those in the above-described example.

FIG. 26 shows a plurality of resistor elements R1 and a plurality of capacitor elements C1 provided for one first semiconductor element 11. In this modified example, the intermediate signal wiring portion 38A may include a first portion 381, a second portion 382, a third portion 383, and a fourth portion 384. The first portion 381, the second portion 382, the third portion 383, and the fourth portion 384 may be aligned in the first direction x and spaced apart from one another. The third portion 383 may be located between the first portion 381 and the second portion 382, and the fourth portion 384 may be located between the third portion 383 and the second portion 382.

In the illustrated example, three resistive elements R1 are provided for one first semiconductor element 11. One resistive element R1 may be connected to straddle the first portion 381 and the third portion 383. Another resistive element R1 may be connected to straddle the third portion 383 and the fourth portion 384. The remaining resistive element R1 may be connected to straddle the fourth portion 384 and the second portion 382. The three resistive elements R1 may be connected in series with each other in the third conduction path Jg1 (gate conduction path Jg1).

In the illustrated example, three capacitor elements C1 are provided for one first semiconductor element 11. One capacitor element C1 can be connected to straddle the third portion 383 and the voltage detection wiring portion 35A (source sense wiring portion 35A). Another capacitor element C1 can be connected to straddle the fourth portion 384 and the voltage detection wiring portion 35A (source sense wiring portion 35A). The remaining capacitor element C1 can be connected to straddle the second portion 382 and the voltage detection wiring portion 35A (source sense wiring portion 35A).

The configuration shown in FIG. 26 may be adopted for each of the multiple first semiconductor elements 11 and the multiple second semiconductor elements 12. The semiconductor device A31 may have a circuit configuration shown in FIG. 27. As shown in the figure, multiple resistor elements R1, R2 and multiple capacitor elements C1, C2 may be provided in multiple stages for one first semiconductor element 11 and one second semiconductor element 12. In this way, the order of the low-pass filter of the semiconductor device A31 may be increased.

This modified example can also reduce the oscillation phenomenon that occurs when multiple first semiconductor elements 11 and multiple second semiconductor elements 12 are operated in parallel. By increasing the order of the low-pass filter, signals in a frequency band below the cutoff frequency can be passed efficiently (e.g., with reduced attenuation). In a frequency band above the cutoff frequency, the passage of signals can be reduced with a high attenuation rate.

The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. The present disclosure includes the embodiments described in the following appendices.
Appendix 1.
a plurality of semiconductor elements each having a first electrode, a second electrode, and a third electrode to which a drive signal for controlling a conduction state of the first electrode and the second electrode is input, the semiconductor elements being connected in parallel with each other;
A second terminal;
A third terminal;
a second conductive path that electrically connects the second electrode and the second terminal of each semiconductor element to each other;
a third conductive path that electrically connects the third electrode and the third terminal of each semiconductor element to each other;
at least one capacitor element connecting the second conduction path and the third conduction path to each other;
A semiconductor device comprising:
Appendix 2.
2. The semiconductor device according to claim 1, wherein the second terminal is a voltage detection terminal.
Appendix 3.
2. The semiconductor device according to claim 1, further comprising a resistive element included in at least one of the second conductive path and the third conductive path.
Appendix 4.
4. The semiconductor device according to claim 3, wherein the resistive element is included in the third conductive path.
Appendix 5.
a third connection member connected to the third electrode of each semiconductor element;
a voltage detection connection member connected to the second electrode of each semiconductor element;
a third wiring portion connected to the third terminal;
A voltage detection wiring portion connected to the second terminal;
5. The semiconductor device of claim 4, further comprising: an intermediate signal wiring portion including a first portion and a second portion.
Appendix 6.
the third connection member is connected to the first portion,
6. The semiconductor device according to claim 5, wherein the voltage detection connection member is connected to the voltage detection wiring portion.
Appendix 7.
7. The semiconductor device according to claim 6, wherein the resistive element is connected to the first portion and the second portion.
Appendix 8.
7. The semiconductor device according to claim 6, further comprising a first intermediate connection member connected to the second portion and the third wiring portion.
Appendix 9.
9. The semiconductor device according to claim 8, wherein the capacitor element is connected to the second portion and the voltage detection wiring portion.
Appendix 10.
7. The semiconductor device according to claim 6, wherein the resistive element is connected to the first portion and the third wiring portion.
Appendix 11.
11. The semiconductor device according to claim 10, wherein the capacitor element is connected to the first portion and the second portion.
Appendix 12.
12. The semiconductor device according to claim 11, further comprising a first intermediate connection member connected to the second portion and the voltage detection wiring portion.
Appendix 13.
a first intermediate connection member connected to the second portion and the voltage detection wiring portion;
a second intermediate connection member connected to the first portion and the third wiring portion,
the intermediate signal wiring portion includes a third portion,
the third connection member is connected to the third portion,
the resistive element is connected to the first portion and the third portion;
6. The semiconductor device according to claim 5, wherein the capacitor element is connected to the second portion and the third portion.
Appendix 14.
Further comprising a support substrate supporting the plurality of semiconductor elements;
the support substrate includes an insulating substrate and a main surface metal layer;
14. The semiconductor device according to claim 5, wherein the main surface metal layer includes the third wiring portion, the voltage detection wiring portion, and the intermediate signal wiring portion.
Appendix 15.
6. The semiconductor device according to claim 5, wherein the resistive element is formed of a connection member having a resistance value higher than that of the third connection member.
Appendix 16.
4. The semiconductor device according to claim 3, further comprising an element package including the capacitor element and the resistor element.
Appendix 17.
2. The semiconductor device according to claim 1, wherein the at least one capacitor element includes a plurality of capacitor elements corresponding to one of the plurality of semiconductor elements.
Appendix 18.
18. The semiconductor device according to any one of claims 1 to 17, wherein the first electrodes of the respective semiconductor elements are electrically connected to each other, and the second electrodes of the respective semiconductor elements are electrically connected to each other.
Appendix 19.
19. The semiconductor device according to claim 1, wherein the third electrodes of the respective semiconductor elements are electrically connected to each other.

A1, A11, A12, A13, A14, A2, A3, A31: semiconductor device 2: supporting substrate 6: sealing member 11: first semiconductor element 11a: first element main surface 11b: first element back surface 12: second semiconductor element 12a: second element main surface 12b: second element back surface 20: insulating substrate 20a: substrate main surface 20b: substrate back surface 21, 21A, 21B, 22: back surface metal layer 23A, 23B: conductive substrate 24A, 24B: signal substrate 31, 32, 33: power wiring section 34A: signal wiring section (third wiring section, gate wiring section)
34B: Signal wiring section (sixth wiring section, gate wiring section)
35A, 35B: Signal wiring section (voltage detection wiring section)
36, 37, 39: signal wiring section 38A, 38B: signal wiring section (intermediate signal wiring section)
41, 42, 43: Power terminals 44A: Signal terminal (third terminal, gate terminal)
44B: Signal terminal (sixth terminal, gate terminal)
45A: Signal terminal (second terminal, voltage detection terminal, source sense terminal)
45B: Signal terminal (5th terminal, voltage detection terminal, source sense terminal)
46, 47, 49: signal terminals 51A, 51B: connecting members 52A: connecting members (third connecting members)
52B: Connection member (sixth connection member)
53A, 53B: Connection member (first intermediate connection member)
54A, 54B: Connection members (voltage detection connection member, source sense connection member)
55A, 55B: Connection member (second intermediate connection member)
56, 57, 58A, 58B: Connection member 61: Resin main surface 62: Resin back surface 70: Heat sink 71: Case 72: Frame 73: Top plate 75: Resin member 80: Sealing resin 81, 82, 83: Electrode 91: Thermistor 111: First electrode (drain electrode)
112: second electrode (source electrode) 113: third electrode (gate electrode)
121: Fourth electrode (drain electrode)
122: Fifth electrode (source electrode)
123: Sixth electrode (gate electrode) 241: Insulating substrate 241a: Main surface 241b: Back surface 242: Main surface metal layer 243: Back surface metal layer 311: Pad portion 312: Pad portion 313: Extension portion 321: Pad portion 321s: Slit 322, 331, 332: Pad portion 381: First portion 382: Second portion 383: Third portion 384: Fourth portion 391: Signal wiring portion 411: Bonding portion 412: Terminal portion 421: Bonding portion 422: Terminal portion 431: Bonding portion 432: Terminal portion
551A, 551B, 552A, 552B: Connection member 581B: First wiring portion 582B: Second wiring portion 583B: Third wiring portion 584B: Fourth wiring portion 631, 632, 633, 634: Resin side surface 741, 742, 743, 744: Terminal block C1, C2: Capacitor element Jg1: Third conduction path Jg2: Sixth conduction path Js1: Second conduction path Js2: Fifth conduction path P1, P2: Element package R1, R2: Resistive element x: First direction y: Second direction z: Thickness direction

Claims (19)

1. a plurality of semiconductor elements each having a first electrode, a second electrode, and a third electrode to which a drive signal for controlling a conduction state of the first electrode and the second electrode is input, the semiconductor elements being connected in parallel with each other;
   A second terminal;
   A third terminal;
   a second conductive path that electrically connects the second electrode and the second terminal of each semiconductor element to each other;
   a third conductive path that electrically connects the third electrode and the third terminal of each semiconductor element to each other;
   at least one capacitor element connecting the second conductive path and the third conductive path to each other.
2. The semiconductor device according to claim 1, wherein the second terminal is a voltage detection terminal.
3. The semiconductor device of claim 1, further comprising a resistive element included in at least one of the second conductive path and the third conductive path.
4. The semiconductor device according to claim 3, wherein the resistive element is included in the third conductive path.
5. a third connection member connected to the third electrode of each semiconductor element;
   a voltage detection connection member connected to the second electrode of each semiconductor element;
   a third wiring portion connected to the third terminal;
   A voltage detection wiring portion connected to the second terminal;
   The semiconductor device according to claim 4 , further comprising: an intermediate signal wiring portion including a first portion and a second portion.
6. the third connection member is connected to the first portion,
   The semiconductor device according to claim 5 , wherein the voltage detection connection member is connected to the voltage detection wiring portion.
7. The semiconductor device of claim 6, wherein the resistive element is connected to the first portion and the second portion.
8. The semiconductor device of claim 6, further comprising a first intermediate connection member connected to the second portion and the third wiring portion.
9. The semiconductor device according to claim 8, wherein the capacitor element is connected to the second part and the voltage detection wiring part.
10. The semiconductor device according to claim 6, wherein the resistive element is connected to the first portion and the third wiring portion.
11. The semiconductor device of claim 10, wherein the capacitor element is connected to the first part and the second part.
12. The semiconductor device according to claim 11, further comprising a first intermediate connection member connected to the second portion and the voltage detection wiring portion.
13. a first intermediate connection member connected to the second portion and the voltage detection wiring portion;
    a second intermediate connection member connected to the first portion and the third wiring portion,
    the intermediate signal wiring portion includes a third portion,
    the third connection member is connected to the third portion,
    the resistive element is connected to the first portion and the third portion;
    The semiconductor device according to claim 5 , wherein the capacitor element is connected to the second portion and the third portion.
14. Further comprising a support substrate supporting the plurality of semiconductor elements;
    the support substrate includes an insulating substrate and a main surface metal layer;
    14. The semiconductor device according to claim 5, wherein said main surface metal layer includes said third wiring portion, said voltage detection wiring portion, and said intermediate signal wiring portion.
15. The semiconductor device according to claim 5, wherein the resistive element is formed of a connection member having a resistance value higher than that of the third connection member.
16. The semiconductor device according to claim 3, further comprising an element package including the capacitor element and the resistor element.
17. The semiconductor device according to claim 1, wherein the at least one capacitor element includes a plurality of capacitor elements corresponding to one of the plurality of semiconductor elements.
18. The semiconductor device according to any one of claims 1 to 17, wherein the first electrodes of the plurality of semiconductor elements are electrically connected to each other, and the second electrodes of the plurality of semiconductor elements are electrically connected to each other.
19. The semiconductor device according to any one of claims 1 to 18, wherein the third electrodes of the plurality of semiconductor elements are electrically connected to each other.

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