WO2024143456A1 - 薄膜キャパシタ及びその製造方法、並びに、薄膜キャパシタを備える電子回路基板 - Google Patents

薄膜キャパシタ及びその製造方法、並びに、薄膜キャパシタを備える電子回路基板 Download PDF

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Publication number
WO2024143456A1
WO2024143456A1 PCT/JP2023/046882 JP2023046882W WO2024143456A1 WO 2024143456 A1 WO2024143456 A1 WO 2024143456A1 JP 2023046882 W JP2023046882 W JP 2023046882W WO 2024143456 A1 WO2024143456 A1 WO 2024143456A1
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WO
WIPO (PCT)
Prior art keywords
metal foil
region
film capacitor
electrode
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/046882
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English (en)
French (fr)
Japanese (ja)
Inventor
光勇 長谷川
大基 石井
悟 川合
満広 冨川
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TDK Corp
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TDK Corp
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Publication date
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Priority to JP2024567922A priority Critical patent/JPWO2024143456A1/ja
Publication of WO2024143456A1 publication Critical patent/WO2024143456A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors (thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G9/00—Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
    • H01G9/004—Details
    • H01G9/04—Electrodes or formation of dielectric layers thereon
    • H01G9/048—Electrodes or formation of dielectric layers thereon characterised by their structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G9/00—Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
    • H01G9/004—Details
    • H01G9/04—Electrodes or formation of dielectric layers thereon
    • H01G9/048—Electrodes or formation of dielectric layers thereon characterised by their structure
    • H01G9/052—Sintered electrodes

Definitions

  • This disclosure relates to a thin-film capacitor and a method for manufacturing the same, and in particular to a thin-film capacitor using metal foil and a method for manufacturing the same.
  • This disclosure also relates to an electronic circuit board equipped with such a thin-film capacitor.
  • Circuit boards on which ICs are mounted usually have decoupling capacitors to stabilize the potential of the power supply supplied to the IC.
  • Multilayer ceramic chip capacitors are generally used as decoupling capacitors, and the necessary decoupling capacitance is ensured by mounting a large number of multilayer ceramic chip capacitors on the surface of the circuit board.
  • the thin-film capacitors described in Patent Documents 1 to 4 use a metal substrate with a roughened surface, and are configured so that the surface of the metal substrate is covered with an upper electrode via a dielectric film.
  • the lower electrode In this type of thin-film capacitor, the lower electrode must be in contact with the metal substrate. If peeling occurs at the interface between the lower electrode and the metal substrate, a poor connection will result.
  • a thin film capacitor comprises a metal foil having a roughened main surface including a first and second region, a dielectric film covering the second region without covering the first region, a first electrode in contact with the metal foil exposed in the first region, and a second electrode covering the metal foil via a dielectric film provided in the second region, and the metal material constituting the first electrode is in contact with the metal foil exposed in the first region.
  • a method for manufacturing a thin film capacitor according to one aspect of the present disclosure includes roughening a main surface of a metal foil including first and second regions, forming a dielectric film on the first and second regions, and removing the dielectric film covering the first region to expose the metal foil located in the first region, forming a first electrode on the first region by electrolytic plating using the metal foil exposed in the first region as a power source, and forming a second electrode on the second region via the dielectric film.
  • the metal material constituting the first electrode is in contact with the roughened surface of the metal foil, making it possible to improve adhesion between the two.
  • FIG. 1 is a schematic cross-sectional view for explaining the structure of a thin-film capacitor 1 according to an embodiment of the technology disclosed herein.
  • FIG. 2 is a partial enlarged view of the electrode E1.
  • 3A to 3C are process diagrams for explaining a method for manufacturing the thin film capacitor 1.
  • FIG. 4A to 4C are process diagrams for explaining a method for manufacturing the thin film capacitor 1.
  • FIG. 5A to 5C are process diagrams for explaining a method for manufacturing the thin film capacitor 1.
  • FIG. 6A to 6C are process diagrams for explaining a method for manufacturing the thin film capacitor 1.
  • FIG. 7A to 7C are process diagrams for explaining a method for manufacturing the thin film capacitor 1.
  • FIG. 8A to 8C are process diagrams for explaining a method for manufacturing the thin film capacitor 1.
  • FIG. 9A to 9C are process diagrams for explaining a method for manufacturing the thin film capacitor 1.
  • FIG. 10A to 10C are process diagrams for explaining a method for manufacturing the thin film capacitor 1.
  • FIG. 11A to 11C are process diagrams for explaining a method for manufacturing the thin film capacitor 1.
  • FIG. 12A to 12C are process diagrams for explaining a method for manufacturing the thin film capacitor 1.
  • FIG. 13 is a schematic cross-sectional view showing an electronic circuit board having a configuration in which a thin film capacitor 1 is embedded in a multilayer substrate 100.
  • FIG. 14 is a schematic cross-sectional view showing an electronic circuit board having a configuration in which a thin film capacitor 1 is mounted on the surface of a multi-layer substrate 300.
  • the thin-film capacitor 1 includes a metal foil 10 and electrodes E1 and E2 formed on a main surface 11, which is the upper surface of the metal foil 10.
  • the metal foil 10 is made of, for example, Al (aluminum).
  • the main surface 11 of the metal foil 10 is roughened.
  • a main surface 12 of the metal foil 10 located opposite the main surface 11 may also be roughened.
  • the central portion of the metal foil 10 in the thickness direction is not roughened.
  • a dielectric film 13 is formed on the roughened main surface 11 of the metal foil 10.
  • a dielectric film 13 may also be formed on the main surface 12, which is the lower surface of the metal foil 10.
  • the dielectric film 13 may be made of, for example, aluminum oxide.
  • a ring-shaped or polygonal annular insulating resin 21 and an insulating resin 22 extending along the outer periphery of the main surface 11 are provided.
  • the dielectric film 13 is removed. That is, in the area A1, the roughened main surface 11 of the metal foil 10 is exposed without being covered by the dielectric film 13. In the other area A2, the roughened main surface 11 of the metal foil 10 is covered by the dielectric film 13 without being exposed.
  • the insulating resin 21 is provided along the boundary between the area A1 and the area A2.
  • the surface roughness of the metal foil 10 in the area A1 may be equal to the surface roughness of the metal foil 10 in the area A2.
  • the electrode E1 is formed in the area A1 surrounded by the insulating resin 21.
  • the dielectric film 13 may be removed from the entire area A1 surrounded by the insulating resin 21.
  • the electrode E2 is formed outside the area surrounded by the insulating resin 21, in an area surrounded by the insulating resin 22.
  • the electrode E1 is in contact with the metal foil 10, while the electrode E2 is insulated from the metal foil 10 by the dielectric film 13.
  • the electrodes E1 and E2 are also insulated by the insulating resin 21.
  • the electrodes E1 and E2 function as a pair of capacitive electrodes facing each other via the dielectric film 13.
  • the electrode E1 constitutes a lower electrode
  • the electrode E2 constitutes an upper electrode.
  • the electrode E1 may protrude from the upper surface 21A of the insulating resin 21 without contacting the upper surface 21A of the insulating resin 21, which is parallel to the main surface 11 of the metal foil 10. This allows the planar size of the electrode E1 to be reduced and makes it easier to connect the electrode E1 to an external terminal. Reducing the size of the electrode E1 also makes it possible to arrange multiple electrodes E1 at high density. In addition, because the electrode E1 does not cover the upper surface 21A of the insulating resin 21, the size of the insulating resin 21 can be reduced accordingly, making it possible to obtain a larger capacitance.
  • the surface E1A which is the exposed surface of the electrode E1 may be a convex surface that increases in height toward the center. This makes it possible to increase the bonding area between the electrode E1 and the external terminal while reducing the planar size of the electrode E1. In addition, the stress generated at the interface between the electrode E1 and the external terminal is effectively dispersed, improving the bonding strength between the two. To achieve these effects, the difference in height between the peripheral portion and the central portion of the surface E1A of the electrode E1 may be 2 ⁇ m or more.
  • Figure 2 is a partially enlarged view of electrode E1.
  • the electrode E1 is in direct contact with the main surface 11 of the roughened metal foil 10.
  • the main surface 11 of the metal foil 10 in the region A1 has a convex portion 11A and a concave portion 11B. Neither the convex portion 11A nor the concave portion 11B is covered with the dielectric film 13, and the metal foil 10 is exposed.
  • the difference in height between the convex portion 11A and the concave portion 11B, i.e., the depth D of the concave portion 11B may be 2 ⁇ m or more. If the depth D is not constant, it may be defined by an average value.
  • the width WA of the convex portion 11A and the width WB of the concave portion 11B may be in the range of 0.1 to 2 ⁇ m. If the width WA of the convex portion 11A and the width WB of the concave portion 11B are not constant, they may be defined by an average value. If the width WA of the convex portion 11A and the width WB of the concave portion 11B are in the range of 0.1 to 2 ⁇ m, sufficient adhesion between the electrode E1 and the metal foil 10 is ensured.
  • the electrode E1 includes a main body 31 made of a good conductor such as Cu (copper) and an interface portion 32 made of, for example, Zn (zinc) that contacts the metal foil 10.
  • the interface portion 32 is in direct contact with the roughened main surface 11 of the metal foil 10.
  • the interface portion 32 is formed not only on the surface of the convex portion 11A but also on the surface of the concave portion 11B.
  • the electrode E2 may be composed of a conductive polymer layer 41 that contacts the dielectric film 13 without contacting the metal foil 10, a seed layer 42 provided on the conductive polymer layer 41, and a metal layer 43 provided on the seed layer 42.
  • Metal materials such as copper, nickel, and gold, and alloys thereof, can be used as the material for the metal layer 43.
  • the metal layer 43 may have a structure in which these metal materials are laminated. It is preferable to use a material for the seed layer 42 that has a barrier function to prevent the diffusion of copper and other materials contained in the metal layer 43, has high adhesion to the metal foil 10 and the conductive polymer layer 41, and does not damage the conductive polymer layer 41.
  • the thin film capacitor 1 according to this embodiment can be used as a decoupling capacitor by embedding it in a multilayer substrate.
  • Figures 3 to 12 are process diagrams for explaining the manufacturing method of the thin-film capacitor 1.
  • a metal foil 10 made of aluminum or the like with a thickness of about 50 ⁇ m is prepared, and its main surfaces 11 and 12 are roughened by etching (FIG. 3).
  • the metal foil 10 may be formed by sintering metal powder.
  • the metal foil 10 is formed with a porous layer 11a located on the main surface 11 side and a porous layer 12a located on the main surface 12 side. Between the porous layer 11a and the porous layer 12a is a non-porous layer 10a that is not roughened.
  • the main surface 11 located on the upper side it is sufficient to roughen at least the main surface 11 located on the upper side, and it is not necessary to roughen the main surface 12 located on the lower side, but by roughening both sides, warping of the metal foil 10 can be prevented.
  • the main surface 12 may be etched under conditions that maximize adhesion to the multilayer substrate.
  • a dielectric film 13 is formed on the surface of the metal foil 10 (FIG. 4).
  • the dielectric film 13 may be formed by oxidizing the metal foil 10, or may be formed using a film forming method with excellent coverage, such as an ALD method, a CVD method, or a mist CVD method.
  • the material of the dielectric film 13 may be Al 2 O 3 , TiO 2 , Ta 2 O 5 , or SiNx.
  • the material of the dielectric film 13 may be amorphous. In this case, the composition ratio of the dielectric film 13 is not necessarily the above-mentioned composition ratio.
  • the dielectric film 13 at least on the main surface 11, and it is not necessary to form the dielectric film 13 on the main surface 12, but by forming the dielectric film 13 on the main surface 12 as well, the insulation of the main surface 12 can be ensured.
  • a support substrate 60 is attached to the main surface 12 side of the metal foil 10, and then insulating resins 21, 22 are formed on the main surface 11 of the metal foil 10 (Figure 5).
  • the insulating resins 21, 22 can be formed by photolithographic patterning, screen printing, gravure printing, inkjet printing, or the like.
  • the portion of the main surface 11 of the metal foil 10 that is surrounded by the insulating resin 21 in a plan view constitutes the region A1.
  • a photosensitive resist is formed, and a patterned resist 61 is formed by exposure and development ( Figure 6).
  • the resist 61 has an opening 62 that exposes the dielectric film 13 on the region A1.
  • the resist may be either positive or negative.
  • the dielectric film may be removed from the entire area surrounded by the insulating resin. This reduces the contact resistance between the first electrode and the metal foil.
  • the first electrode may include a main body portion made of a first metal material and an interface portion made of a second metal material that is in contact with the metal foil. This makes it possible to prevent the formation of a natural oxide film on the surface of the metal foil.
  • the metal foil may contain Al (aluminum), the first metal material may contain Cu (copper), and the second metal material may contain Zn (zinc). This makes it possible to form an interface by zincate treatment.
  • the metal foil may contain Al (aluminum), and the step of exposing the metal foil may be performed by zincate treatment. This makes it possible to remove the dielectric film covering the first region while maintaining the roughened state of the metal foil in the first region.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
PCT/JP2023/046882 2022-12-29 2023-12-27 薄膜キャパシタ及びその製造方法、並びに、薄膜キャパシタを備える電子回路基板 Ceased WO2024143456A1 (ja)

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US63/477,674 2022-12-29

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149730A (ja) * 2005-11-24 2007-06-14 Shinko Electric Ind Co Ltd 薄膜キャパシタ、実装基板、実装基板の製造方法、半導体装置、および半導体装置の製造方法
JP2008078299A (ja) * 2006-09-20 2008-04-03 Fujitsu Ltd キャパシタ、その製造方法、および電子基板
WO2021066091A1 (ja) * 2019-10-04 2021-04-08 株式会社村田製作所 電解コンデンサ及び電解コンデンサの製造方法
WO2022004020A1 (ja) * 2020-06-29 2022-01-06 Tdk株式会社 薄膜キャパシタ及びこれを備える電子回路基板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149730A (ja) * 2005-11-24 2007-06-14 Shinko Electric Ind Co Ltd 薄膜キャパシタ、実装基板、実装基板の製造方法、半導体装置、および半導体装置の製造方法
JP2008078299A (ja) * 2006-09-20 2008-04-03 Fujitsu Ltd キャパシタ、その製造方法、および電子基板
WO2021066091A1 (ja) * 2019-10-04 2021-04-08 株式会社村田製作所 電解コンデンサ及び電解コンデンサの製造方法
WO2022004020A1 (ja) * 2020-06-29 2022-01-06 Tdk株式会社 薄膜キャパシタ及びこれを備える電子回路基板

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